High-speed data transmission system based on TLK2711 interface

Abstract

The present invention relates to a high-speed data transmission system, and in particular to a high-speed data transmission system based on TLK2711. The system solves the problem that the existing high-speed data transmission system based on the TLK2711 interface is prone to bit errors due to the clock network design. Two crystal oscillators are used, one of which drives two TLK2711 transceivers at the same time and is connected to the clock input pin of an FPGA unit at the same time, as the input clock of the FPGA unit, and is used as the output main clock of the process unit for sending data to the first TLK2711 transceiver and the second TLK2711 transceiver inside the FPGA unit; the other crystal oscillator is directly connected only to the working clock pin of the FPGA unit, as the main clock for the operation of the FPGA unit itself; the problem of bit errors in transmission caused by directly using the clock directly generated by the internal phase-locked loop of the FPGA unit as the TLK2711 clock is avoided.

Description

Technical Field

[0001] The invention relates to a high-speed data transmission system, in particular to a high-speed data transmission system based on TLK2711. Background Art

[0002] With the development of modern electronic technology, the continuous improvement of high-speed photography technology, and the increasing market demand for high-speed motion analysis, the application of high-speed photography is becoming more and more extensive. High-speed photography has become an indispensable technical testing method in fields that require high-speed motion analysis, such as space remote sensing, automobile collision tests, scientific research experiments, industrial production process monitoring, and sports.

[0003] In particular, with the development of space remote sensing technology, satellite remote sensing is increasingly showing a trend of high temporal resolution, high spatial resolution and high spectral resolution. The types of payload data are becoming more and more diverse, and the amount of data is increasing, resulting in higher data rates and bandwidths. The increase in data volume has brought new challenges to the transmission scheme, making some traditional transmission interfaces that were relied on in the past unable to meet the needs, or requiring multiple interfaces to transmit in parallel, which increases the complexity of the system. Therefore, in recent years, a new type of high-speed serial / deserialization transceiver TLK2711 has opened up new ideas for high-speed data transmission and has been widely used in payload equipment or ground test equipment. Its single-channel transmission rate is as high as 2.7Gbps. At the same time, the TLK2711 interface chip itself has a self-synchronous communication mode, using clock and data recovery technology instead of synchronous transmission of data and clock, which effectively solves the problem of signal and clock offset; in addition, the use of serial communication technology makes equipment and cable wiring simpler and the system has stronger anti-interference ability.

[0004] Compared with LVDS interface, TLK2711 interface has advantages such as high bandwidth and simple system; compared with USB interface, it has advantages such as long transmission distance and high reliability. However, in the design of high-speed data transmission system based on TLK2711 interface, special attention should be paid to the design of clock network, which will affect the system transmission error. In some fields, data transmission requires error-free transmission for a period of time, otherwise it will affect the judgment of the origin of the material. For example, in the field of spectral application, if there is a bit error, it will affect the spectral inversion and fail to accurately obtain the target spectrum information.

[0005] Therefore, it is particularly important to provide a high-speed data transmission system based on the TLK2711 interface that is error-free, universal, and portable. Summary of the invention

[0006] The purpose of the present invention is to provide a high-speed data transmission system based on the TLK2711 interface that is error-free, universal and portable, so as to solve the problem that the existing high-speed data transmission system based on the TLK2711 interface is prone to error due to the clock network design.

[0007] The technical solution of the present invention is:

[0008] A high-speed data transmission system based on a TLK2711 interface, which is special in that it includes an FPGA unit, a FLASH storage unit, a crystal oscillator unit, a data output unit and a power supply and distribution unit;

[0009] The crystal oscillator unit includes a first crystal oscillator and a second crystal oscillator; the data output unit includes a first TLK2711 transceiver, a second TLK2711 transceiver and an external connector; the output ends of the first TLK2711 transceiver and the second TLK2711 transceiver are both connected to the external connector;

[0010] The FLASH storage unit, the first TLK2711 transceiver and the second TLK2711 transceiver are all connected to the FPGA unit;

[0011] The first crystal oscillator is connected to the first TLK2711 transceiver, the second TLK2711 transceiver and the input clock pin of the FPGA unit at the same time; the second crystal oscillator is connected to the working clock pin of the FPGA unit;

[0012] The FPGA unit is used to receive external data or generate data, and to exchange data with the first TLK2711 transceiver and the second TLK2711 transceiver, and to send the processed data to the first TLK2711 transceiver and the second TLK2711 transceiver according to the transmission protocol;

[0013] The first TLK2711 transceiver and the second TLK2711 transceiver are used to receive data output by the FPGA unit and encode and output through an external connector;

[0014] The FLASH storage unit is used to provide program loading for the FPGA unit startup;

[0015] The second crystal oscillator is used to provide a working clock for the FPGA unit; the working clock refers to the source power of the internal clock when the FPGA unit is running;

[0016] The first crystal oscillator is used to drive the first TLK2711 transceiver and the second TLK2711 transceiver at the same time, and serves as the input clock of the FPGA unit, and serves as the output master clock of the process unit that sends data to the first TLK2711 transceiver and the second TLK2711 transceiver inside the FPGA unit;

[0017] The power supply and distribution unit is used to provide required power.

[0018] Furthermore, the models of the first crystal oscillator and the second crystal oscillator are ZA715CB3-100MHz.

[0019] Furthermore, the model of the FPGA unit is XC2V3000-4BG728I.

[0020] Furthermore, the model of the FLASH storage unit is XC32PV048.

[0021] Furthermore, the external connector is a HSMHK connector produced by Guizhou Aerospace Electronics Company.

[0022] The beneficial effects of the present invention are:

[0023] 1. The present invention designs two crystal oscillators, one of which drives two TLK2711 transceivers at the same time, and is connected to the clock input pin of the FPGA unit at the same time, as the input clock of the FPGA unit, which is used as the output master clock of the process unit that sends data to the first TLK2711 transceiver and the second TLK2711 transceiver inside the FPGA unit; the other crystal oscillator is only directly connected to the working clock pin of the FPGA unit, as the main clock of the FPGA unit itself; it avoids the problem of directly using the clock directly generated by the internal phase-locked loop of the FPGA unit as the TLK2711 clock, which causes transmission errors. The present invention makes full use of the advantages of the high-speed serial TLK2711 interface, and provides an effective technical means for reliable and error-free transmission of a large number of high-speed devices;

[0024] 2. The high-speed data transmission system based on the TLK2711 interface of the present invention can realize continuous transmission without error and has high reliability.

[0025] 3. The high-speed data transmission system based on the TLK2711 interface of the present invention has a simple structure and has many advantages such as universality, portability, stable working performance, etc. The system has a wide range of application prospects and can also be used in many imaging or non-imaging data transmission devices such as high-speed photography, high-resolution imaging spectrometers, stereo mapping cameras, and high-bandwidth data compression transmission systems.

[0026] 4. The present invention is economical and practical, can be used in applications where various FPGA devices are connected to TLK2711, and has universal applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A block diagram of a high-speed data transmission system based on a TLK2711 interface in an embodiment of the present invention;

[0028] Figure 2 The figure is a connection diagram of an FPGA unit, a crystal oscillator unit and a data output unit in a high-speed data transmission system based on a TLK2711 interface in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0030] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0031] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0032] Furthermore, the terms “first or second” are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0033] like Figure 1 As shown, the high-speed data transmission system based on the TLK2711 interface in this embodiment is mainly composed of an FPGA unit, a FLASH storage unit, a crystal oscillator unit, a data output unit, and a power supply and distribution unit.

[0034] The crystal oscillator unit includes a first crystal oscillator and a second crystal oscillator; the data output unit includes a first TLK2711 transceiver, a second TLK2711 transceiver and an external connector; the output ends of the first TLK2711 transceiver and the second TLK2711 transceiver are both connected to the external connector; the FLASH storage unit, the first TLK2711 transceiver and the second TLK2711 transceiver are all connected to the FPGA unit; the first crystal oscillator is simultaneously connected to the first TLK2711 transceiver, the second TLK2711 transceiver and the input clock pin of the FPGA unit; the second crystal oscillator is directly connected to the working clock pin of the FPGA unit.

[0035] Figure 1 The external data input unit in the main inputs data to the FPGA unit. The external data input unit can be adaptively designed according to external requirements, or can be designed to generate a regular image data stream for internal coding of the FPGA. Specifically in this embodiment, a satellite-borne high-resolution camera is used as a data source, and multiple LVDS chips are used to transmit image data.

[0036] The FPGA unit is a core device for high-speed data transmission, which is used to receive data input, and call its internal logic unit through internal running software to store valid data into its internal cache, and then encode and send the data according to the TLK2711 transmission protocol. In this embodiment, the Xilinx FPGA model XC2V3000-4BG728I is selected.

[0037] The FLASH storage unit is a non-volatile, electrically erasable programmable read-only memory, which is mainly used to provide program loading for FPGA startup. In this embodiment, the dedicated XC32PV048 device of Xilinx Company is used.

[0038] The first TLK2711 transceiver and the second TLK2711 transceiver encode the parallel data output by the FPGA unit, thereby realizing the serialization of the parallel data and outputting it through the external connector. In this embodiment, the working clock of the first TLK2711 transceiver and the second TLK2711 transceiver is 100Mhz; the first TLK2711 transceiver and the second TLK2711 transceiver respectively encode the input parallel 16-bit data, 1 clock, and 2 K / D coding control signals into serial data, and send them to the lower computer through the external connector. The external connector is connected to the interface of the onboard imaging device. In this embodiment, the HSMHK connector produced by Guizhou Aerospace Electronics Company is used.

[0039] The crystal oscillator unit provides the working clock for the FPGA unit and the TLK2711 device. In this embodiment, the ZA715CB3-100MHz device of Hitron Electronics is used. It is the source clock for the entire board. Figure 2 As shown, in order to prevent a crystal oscillator from fanning out too much and affecting the internal logic layout and wiring of the FPGA unit, this embodiment designs two crystal oscillators. One of them is a dedicated FPGA unit for internal timing and logic generation. The other crystal oscillator is connected to the FPGA unit and two TLK2711 transceivers respectively. Since the data sent by the FPGA unit enters the TLK2711, in order to ensure the consistency of the relative phase of the clock on the data transmission link, the data needs to be sent to the TLK2711 entry clock as the same source clock. The advantage of this design is that it can effectively avoid bit errors in the transmission process.

[0040] The power supply and distribution unit provides power supply and distribution for the entire circuit design, and is mainly composed of several power conversion chips. In this embodiment, an LDO power supply is used, which has the characteristics of high performance and low noise, which is conducive to ensuring the reliability of data transmission.

Claims

1. A high-speed data transmission system based on TLK2711 interface, characterized in that: It includes FPGA unit, FLASH storage unit, crystal oscillator unit, data output unit and power supply and distribution unit; The crystal oscillator unit includes a first crystal oscillator and a second crystal oscillator; The data output unit includes a first TLK2711 transceiver, a second TLK2711 transceiver and an external connector; the output ends of the first TLK2711 transceiver and the second TLK2711 transceiver are both connected to the external connector; The FLASH storage unit, the first TLK2711 transceiver and the second TLK2711 transceiver are all connected to the FPGA unit; The first crystal oscillator is connected to the first TLK2711 transceiver, the second TLK2711 transceiver and the input clock pin of the FPGA unit at the same time; the second crystal oscillator is connected to the working clock pin of the FPGA unit; The FPGA unit is used to receive external data or generate data, and to exchange data with the first TLK2711 transceiver and the second TLK2711 transceiver, and to send the processed data to the first TLK2711 transceiver and the second TLK2711 transceiver according to the transmission protocol; The first TLK2711 transceiver and the second TLK2711 transceiver are used to receive data output by the FPGA unit and encode and output through an external connector; The FLASH storage unit is used to provide program loading for the FPGA unit startup; The second crystal oscillator is used to provide a working clock for the FPGA unit; the first crystal oscillator is used to drive the first TLK2711 transceiver and the second TLK2711 transceiver at the same time, and serves as the input clock of the FPGA unit, and serves as the output master clock of the process unit that sends data to the first TLK2711 transceiver and the second TLK2711 transceiver inside the FPGA unit; The power supply and distribution unit is used to provide required power.

2. The high-speed data transmission system based on the TLK2711 interface according to claim 1, characterized in that: The models of the first crystal oscillator and the second crystal oscillator are both ZA715CB3-100MHz.

3. The high-speed data transmission system based on the TLK2711 interface according to claim 2, characterized in that: The model of the FPGA unit is XC2V3000-4BG728I.

4. The high-speed data transmission system based on the TLK2711 interface according to claim 3, characterized in that: The model of the FLASH storage unit is XC32PV048.

5. The high-speed data transmission system based on the TLK2711 interface according to claim 4, characterized in that: The external connector is a HSMHK connector produced by Guizhou Aerospace Electronics Company.

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