Screening of memory circuits

Abstract

Examples include systems and methods for screening memory cells of a memory array (401) by modulating bit line and / or word line voltages. A built-in self-test (BIST) system (400) for screening a memory array (401) has bit line margin control and word line margin control (402, 403) to modulate bit line and word line voltages in the memory array (401), respectively. In a read operation, the word line margin control (403) can overdrive or underdrive the word line compared to a nominal operating voltage on the word line. In a write operation, the bit line margin control and the word line margin control (402, 403) can overdrive or underdrive one or both of the bit line and the word line compared to a nominal operating voltage of each of the bit line and the word line.

Description

Background Technology

[0001] Screening memory devices can help ensure their reliable operation. Screening may involve testing the memory device in a less unstable state, where it is assumed that if the device operates normally in the less unstable state, it will also operate normally in the stable state. A less unstable state can be a state susceptible to disturbances. This less unstable state can be achieved, for example, by subjecting the memory device to stress through temperature variations. Screening provides an operational margin by identifying the portions that operate normally in the less unstable state.

[0002] For memory devices that include planar transistors—that is, transistors with active drain and source portions coplanar with the oxide or insulating layer—screening may involve modulating the N-well to place the memory device in a less stable state. As used herein, modulation means applying a voltage higher or lower than the nominal operating voltage. However, this approach may not be suitable for memory devices using FinFET transistors, which have active drain and source portions that protrude above the oxide or insulating layer in a fin-like manner. The active drain and source portions of a FinFET transistor may not be affected by changes to the N-well due to the distance between the active drain and source portions and the N-well in the FinFET transistor architecture. Summary of the Invention

[0003] The illustrative example described herein includes a method for filtering memory cells. The illustrative method includes overdriving or underdriving the word line compared to a nominal operating voltage on the word line. The method also includes reading the memory cell to obtain a cell value and comparing the cell value with a desired value.

[0004] The illustrative examples described herein also include a method for filtering memory cells having a first bit line, a second bit line, and a word line. The illustrative method includes writing a write value to the memory cell by overdriving or underdriving one of the first and second bit lines compared to their nominal operating voltages. The method also includes reading the memory cell to obtain a cell value and comparing the cell value with a desired value.

[0005] The illustrative example described herein also includes a built-in self-test (BIST) system for screening memory arrays. The illustrative BIST system includes an external interface configured to receive a test program with multiple instructions. These multiple instructions include read instructions, write instructions, or a combination of read and write instructions. The BIST system further includes: a control engine configured to control the operation of the BIST system to screen the memory array based on the multiple instructions; and an address / data generator configured to be controlled by the control engine to generate addresses for read and write instructions, and test data to be written to the memory array for the write instructions, based on the multiple instructions. The BIST system also includes a write / read control generator configured to be controlled by the control engine to generate write / read memory instructions based on the multiple instructions and provide them to the memory array, wherein the write / read instructions are selected from memory read instructions and memory write instructions. The BIST system further includes: a word line margin control configured to be controlled by the control engine to modulate the word line voltage of the word lines in the memory array based on the plurality of instructions; a bit line margin control configured to be controlled by the control engine to modulate the bit line voltage of the bit lines in the memory array based on the plurality of instructions; and an output comparator configured to receive read data from the memory array and compare the read data with an expected value to obtain a test result. Attached Figure Description

[0006] Figure 1 A schematic memory cell is shown;

[0007] Figure 2 This demonstrates how to filter using read commands. Figure 1 A schematic method for the memory cell;

[0008] Figure 3 This illustrates how to filter using write commands. Figure 1 A schematic method for the memory cell;

[0009] Figure 4 An illustrative built-in self-test system is shown; and

[0010] Figure 5 The operation is shown Figure 4 An illustrative method for a built-in self-test system. Detailed Implementation

[0011] In this specification, the term "coupled" means an indirect or direct wired or wireless connection. Therefore, if a first device is coupled to a second device, the connection can be either a direct connection or an indirect connection via other devices and connections.

[0012] Figure 1 A schematic 6-transistor static random access memory (SRAM) cell 1 with transistors M1, M2, M3, M4, M5, and M6 is shown. Access transistor M1 couples bit line BL 7 to node A, and access transistor M6 couples bit line BB 8 to node B. The drain terminals of transistors M2 and M3 are coupled together at node A. The source terminal of transistor M2 is coupled to a power supply (e.g., VCC), and the source terminal of transistor M3 is coupled to VSS (e.g., ground). The drain terminals of transistors M4 and M5 are coupled together at node B. The source terminal of transistor M4 is coupled to a power supply (e.g., VCC), and the source terminal of transistor M5 is coupled to VSS (e.g., ground). The gate terminals of transistors M2 and M3 are coupled together and to node B. The gate terminals of transistors M4 and M5 are coupled together and to node A. Transistors M2 and M4 have N-wells 5 and 6, respectively. The gate terminals of access transistors M1 and M6 are coupled to word line WL2. Figure 1 In this configuration, transistors M2 and M4 are p-type metal-oxide-semiconductor field-effect transistors (PMOS transistors), and transistors M1, M3, M5, and M6 are n-type metal-oxide-semiconductor field-effect transistors (NMOS transistors). Other architectures for memory cells can also be implemented.

[0013] If transistors M1, M2, M3, M4, M5, and M6 are planar transistors, memory cell 1 can be screened to generate margin by modulating the voltage on N-wells 5 and 6. However, if transistors M1, M2, M3, M4, M5, and M6 are FinFET transistors, this screening method is not applicable. The N-well region can be on the side of the transistor opposite to the active portion, and in a FinFET transistor, the active portion extends away from the surface of the transistor opposite to the N-well, and therefore farther from the N-well. Thus, the distance between the N-well region and the active drain and source portions in a FinFET transistor is greater than the distance in a planar transistor. Therefore, biasing the N-well in a FinFET transistor may not affect the active drain and source portions of the transistor because electrons are too far away to travel.

[0014] Figure 2 A schematic method is shown for filtering memory cell 1 during a read operation by modulating the voltage on word line WL 2 instead of the voltage on N-wells 5 and / or 6. Therefore, Figure 2This method can be used to screen FinFET memory cells or planar memory cells. Figure 2 Screening methods, for example, are performed in the factory as a quality check before the chips are used in the field.

[0015] At step 201, word line WL2 is driven to a voltage higher or lower than its nominal operating voltage. For example, word line WL2 may be driven to + / - 5% of its nominal operating voltage. At step 202, bit lines BL7 and BB8 are read (e.g., by a comparator) and the cell value is calculated. For example, the cell value can be determined by calculating the difference between the voltage on bit line BL7 and the voltage on bit line BB8. At step 203, the calculated cell value is compared with the desired cell value. If the values ​​are the same, the cell passes the selection process, thus having sufficient margin.

[0016] Figure 3 A schematic method is shown for filtering memory cell 1 during a write operation by modulating the voltage on bit line BL 7 or BB 8 and / or word line WL 2 instead of the voltage on N-well 5 and / or 6. Therefore, Figure 3 This method can be used to screen FinFET memory cells or planar memory cells. Figure 3 Screening methods, for example, are performed in the factory as a quality check before the chips are used in the field.

[0017] At step 301, bit lines BL 7 and BB 8 are precharged high, for example, to their nominal operating voltages. At step 302, the bit line BL 7 or BB 8 corresponding to the value to be written is driven to a voltage higher or lower than the voltage used for the write operation in the field. During the write operation, bit line BL 7 may be driven low to write "0", and bit line BB 8 may be driven low to write "1", or vice versa. Bit lines BL 7 or BB 8 should be driven low enough to ensure that the corresponding access transistor M1 or M6 can turn on the corresponding PMOS transistor M4 or M2. For example, if bit lines BL 7 or BB 8 can be pulled down to 0 volts for a write operation, they can instead be driven to + / - 100mV. At step 303, word line WL 2 is driven to a voltage higher or lower than its nominal voltage. For example, word line WL 2 can be driven to + / - 5% of the nominal operating voltage.

[0018] At step 304, memory cell 1 is read. For example... Figure 2As described in step 201, during step 304, the word line WL2 may optionally be overdriven or underdriven. At step 305, the value read at step 304 is compared with the value written in steps 301-303. If the values ​​are the same, the cell passes the filter, thus having sufficient margin. When Figure 3 The method illustrates that when bit line BL 7 or BB 8 and word line WL 2 are both overdriven or underdriven to place the cell in a less stable state, the method may alternatively involve only overdriving or underdriving bit line BL 7 or BB 8 or only overdriving or underdriving word line WL 2.

[0019] Figure 4 A schematic diagram of a built-in self-test (BIST) system 400 is shown, which can be used in the factory before chip shipment to perform tests on memory cells in memory array 401. Figure 2 and / or Figure 3 The method. Memory array 401 may, for example, include multiple memory cells (such as... Figure 1 The BIST system 400 includes an SRAM memory array (memory cell 1). The BIST system 400 includes a control engine 406 coupled to a bit line margin control 402, a word line margin control 403, a write / read control generator 404, and an address / data generator 405. The control engine 406 may be, for example, a processor or a computer, and controls the operation of other components of the BIST 400 based on software, for example, stored in memory 409. As described in more detail below, the software may include a test program that instructs the control engine 406 to test the memory array 401 by writing to and / or reading from individual cells of the memory array 401 using voltages varying from the nominal operating voltage.

[0020] For this purpose, bit line margin control 402 can be a voltage biasing circuit and can provide a modulation voltage specified by a test procedure on the bit lines (e.g., bit lines BL 7 and / or BB 8) in the memory array 401. Word line margin control 403 can be a voltage biasing circuit and can provide a modulation voltage specified by a test procedure to the word lines (e.g., word line WL 2) in the memory array 401. Bit line margin control 402 and word line margin control 403 can also be circuits that provide control data to the memory array 401 to allow the memory array 401 to adjust the voltage on the bit lines or word lines respectively based on the control data.

[0021] The BIST system 400 also includes an output comparator 408 for receiving read data from the memory array 401 and comparing the read data with the written data to determine whether the memory cell being tested has the expected value. If the values ​​match, it may indicate that the corresponding cell has sufficient operating margin. The BIST system 400 also includes an external interface 407 for receiving test programs and / or for outputting the results of the test programs to, for example, an external computer.

[0022] Figure 5 An exemplary method for using the BIST system 400 to filter one or more cells in a memory array 401 is shown. Figure 5 The screening method is performed, for example, at the factory as a quality check before the memory array chips are used in the field. At step 501, a test program is received from, for example, an external computer at an external interface 407. The external interface 407 can store the program, for example, in memory 409. For example, the test program could be based on… Figure 2 and Figure 3 A series of write and / or read instructions for a method. For example, a write instruction may have the following format:

[0023] Write BL1 WL2 A0,D0

[0024] The `Write` directive identifies the instruction as a write command, `D0` is the data to be written, and `A0` is the address where the data should be written. `BL1` is the bit line voltage modulation value, which specifies the voltage to be applied to the bit line during the write operation. The bit line modulation value can be specified by directly indicating the voltage, by indicating an offset from a nominal voltage specified elsewhere, or by other appropriate means. Similarly, `WL2` is the word line voltage modulation value, and can also be specified by directly indicating the voltage, by indicating an offset from a nominal voltage specified elsewhere, or by other appropriate means, to specify the voltage to be applied to the word line during the write operation.

[0025] The sampling and reading command can be:

[0026] Read WL2 A0

[0027] In this instruction, Read identifies it as a read instruction, A0 is the address from which data should be read, and WL2 is the word line modulation value specifying the voltage to be applied to the word line during the read operation. The word line modulation value can be specified by directly indicating the voltage, by indicating an offset from a nominal voltage specified elsewhere, or by other appropriate means. The test program may contain instructions with voltage modulation values, such as those described above, interspersed with instructions for reading and / or writing at the nominal voltage.

[0028] At step 502, control engine 406 retrieves the test program from memory 409. At step 503, control engine 406 retrieves or reads the next instruction from the test program, which may be a read instruction or a write instruction with or without a voltage modulation value. If no other instructions have been processed, control engine 406 may retrieve the first instruction.

[0029] At step 504, control engine 406 prepares instructions and data to be sent to memory array 401 to execute instructions from the test program. This preparation may involve causing address / data generator 405 to generate a sequence of addresses to be read from or written to, for example, based on the value A0 in the instructions from the test program. The addresses may correspond to some or all of the memory cells in the memory array 401 under test. Since performance can have spatial components, the addresses may correspond to a physical pattern distributed across the memory cells of memory array 401, such as a checkerboard pattern, row stripe pattern, or column stripe pattern.

[0030] For a write instruction, control engine 406 may cause address / data generator 405 to generate test data to be written, for example, based on the value D0 from the instruction from the test program. For example, the generated test data may be a series of 1s and 0s as the binary representation of the value D0.

[0031] The control engine 406 may also cause the write / read control generator 404 to generate signals that cause the memory array 401 to execute corresponding write or read instructions for each address based on instructions, for example, from a test program. These signals may include write enable signals or read enable signals provided to the write enable input or read enable input of the memory array 401, respectively. A read enable signal sent to the read enable input or a write enable signal sent to the write enable input may instruct the memory array to read from or write to the memory array at the address provided to the memory array 401, for example, via an address input in the memory array 401. The form of the instructions and data sent to the memory array 401 typically depends on the requirements of the memory array 401.

[0032] The control engine 406 can also instruct the bit line margin control 402 and / or the word line margin control 403 to modulate the voltages on the bit lines and / or word lines based on, for example, the BL1 and WL2 values ​​from instructions from a test program. In an example where the bit line margin control 402 and word line margin control 403 are biasing circuits, they will generate voltages based on the BL1 and WL2 values, respectively. In an example where the bit line margin control 402 and word line margin control 403 are circuits generating modulation control values, they can generate modulation control values ​​corresponding to BL1 and / or WL2, respectively, based on the requirements of the memory array 401. For example, word line margin control 403 can provide memory array 401 with a modulation control value "0" to indicate a word line voltage offset of 0mV from the nominal voltage, a modulation control value "1" to indicate a word line voltage offset of 300mV from the nominal voltage, and a modulation control value "2" to indicate a word line voltage offset of -300mV from the nominal voltage. In another example, where word line margin control 403 directly specifies the word line voltage, word line margin control 403 can provide memory array 401 with a modulation control value "0" to indicate a read or write operation performed at a word line voltage of 0mV, a modulation control value "1" to indicate a read or write operation performed at a word line voltage of 300mV, and a modulation control value "2" to indicate a read or write operation performed at a word line voltage of -300mV.

[0033] At step 505, the BIST system 400 sends the read and / or write instructions generated in step 504 to the memory array 401. The instructions and / or data generated in step 504 may be sent to the BIST system 400 by components that generate the corresponding instructions and / or data (e.g., bit line margin control 402, word line margin control 403, write / read control generator 404, and / or address / data generator 405). In the case of a write instruction, the data generated in step 504 is written to the appropriate memory location in the memory array 401. In the case of a read instruction, the cell at the specified address is read.

[0034] At step 506, if the instruction is a read instruction, memory array 401 outputs the read data to output comparator 408. Output comparator 408 compares the result of the read instruction with the expected result that can be stored in memory 409 to test whether the read data matches the expected result. Comparator 408 provides the comparison result to control engine 406. At step 507, control engine 406 determines whether any instructions that have not yet been executed remain in the test program. If so, control engine 406 reads the next read or write instruction at step 503 and processes the instruction in steps 504-506. If no instructions remain in the test program, at step 508, control engine 406 outputs the result of the test program to external interface 407. Alternatively, the result of the test program may be output to external interface 407 when the result is generated, and / or may be stored in memory 409.

[0035] Within the scope of the claims, modifications are possible in the described embodiments, and other embodiments are possible.

Claims

1. A built-in self-test system, or BIST system, for screening memory arrays, the BIST system comprising: An external interface is configured to receive a test program having multiple instructions, including a read instruction pointing to a memory cell of the memory array, wherein the memory cell has a nominal word line voltage associated with access to the memory cell and the read instruction specifies a modulated word line voltage different from the nominal word line voltage. A processor coupled to the external interface to receive the plurality of instructions; An address / data generator, configured to be controlled by the processor, generates a set of addresses and a set of test data including desired values ​​for the memory cells based on the plurality of instructions. A word line margin control, the word line margin control being configured to be controlled by the processor to provide the modulated word line voltage to the memory cell based on the read instruction; A write / read control generator, configured to be controlled by the processor to read read values ​​from the memory cell using the modulated word line voltage; as well as An output comparator is configured to compare the read value with the expected value.

2. The BIST system according to claim 1 further includes a memory for receiving the test program from the external interface.

3. The BIST system according to claim 1, wherein: The modulation word line voltage is the first modulation word line voltage; The plurality of instructions includes write instructions pointing to the memory cell; The write instruction specifies a second modulated word line voltage that is different from the nominal word line voltage; The word line margin control is configured to be controlled by the processor to provide the second modulated word line voltage to the memory cell based on the write instruction; and The write / read control generator is configured to be controlled by the processor to write the write value to the memory cell using the second modulated word line voltage.

4. The BIST system of claim 2, wherein the memory is configured to store the result of the comparison operation.

5. The BIST system of claim 1, wherein the external interface is further configured to output the result of the comparison operation to an external computer.

6. The BIST system according to claim 3, wherein: The memory cell has a nominal bit line voltage associated with the access of the memory cell; The write instruction specifies a modulation bit line voltage that is different from the nominal bit line voltage; The BIST system includes a bit line margin control configured to be controlled by the processor to provide the modulated bit line voltage to the memory cell based on the write instruction; as well as The write / read control generator is configured to be controlled by the processor to write the write value to the memory cell using the modulated bit line voltage.

7. The BIST system according to claim 1, wherein: The plurality of instructions includes write instructions pointing to the memory cell; The memory cell has a nominal bit line voltage associated with the access of the memory cell; The write instruction specifies a modulation bit line voltage that is different from the nominal bit line voltage; The BIST system includes a bit line margin control configured to be controlled by the processor to provide the modulated bit line voltage to the memory cell based on the write instruction; The write / read control generator is configured to be controlled by the processor to write the write value to the memory cell using the modulated bit line voltage.

8. The BIST system of claim 1, wherein the memory array comprises a plurality of memory cells containing the memory cells and having fin field-effect transistors.

9. A method for screening memory cells, the method comprising: Receive a read instruction to the memory cell, wherein the memory cell has a nominal word line voltage and the read instruction specifies a modulated word line voltage different from the nominal word line voltage; Provide the modulated word line voltage to the word line coupled to the memory cell; The memory cell is read using the modulated word line voltage to obtain the cell value; as well as The cell value is compared with the expected value.

10. The method of claim 9, wherein the modulated word line voltage is within + / - 5% of the nominal word line voltage.

11. The method of claim 9, wherein the memory cell comprises a fin field-effect transistor.

12. The method according to claim 9, further comprising: Receive a write instruction to the memory cell, wherein the modulation word line voltage is a first modulation word line voltage and the write instruction specifies a second modulation word line voltage that is different from the nominal word line voltage; The second modulation word line voltage is provided to the word line; as well as The write value is written to the memory cell using the second modulated word line voltage.

13. The method according to claim 12, wherein: The memory cell has a nominal bit line voltage; The write instruction specifies a modulation bit line voltage that is different from the nominal bit line voltage; The method includes providing the modulated bit line voltage to a bit line coupled to the memory cell; and The writing of the write value also uses the modulated bit line voltage.

14. The method of claim 9, further comprising: Receive a write instruction to the memory cell, wherein the memory cell has a nominal bit line voltage and the write instruction specifies a modulated bit line voltage different from the nominal bit line voltage; Provide the modulated bit line voltage to the bit line coupled to the memory cell; as well as The write value is written to the memory cell using the modulated bit line voltage.

15. A method for screening memory cells coupled to a first bit line, a second bit line, and a word line, the method comprising: A modulation bit line voltage is provided to at least one of the first bit line and the second bit line, wherein the modulation bit line voltage is different from the nominal bit line voltage of the memory cell; A modulated word line voltage is provided to the word line, the modulated word line voltage being different from the nominal word line voltage of the memory cell; The write value is written to the memory cell using the modulation bit line voltage and the modulation word line voltage; Read the memory cell to obtain the read value; as well as The read value is compared with the write value.

16. The method of claim 15, wherein reading the memory cell includes providing a modulated word line voltage to the word line, the modulated word line voltage being different from the nominal word line voltage of the memory cell.

17. The method of claim 15, wherein writing the write value to the memory cell further comprises precharging the first bit line and the second bit line before providing the modulated bit line voltage to at least one of the first bit line and the second bit line.

18. The method of claim 15, wherein the memory cell comprises a fin field-effect transistor.

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