Processor system

Abstract

The present invention provides a processor system, comprising a processor unit, a random access memory unit, a memory control unit, a flash memory unit and an internal bus, wherein the processor unit is connected to the random access memory unit via the internal bus, the random access memory unit is connected to the flash memory unit via the memory control unit, and the flash memory unit is mapped via the memory control unit. The present invention maps the storage data of the flash memory unit to the random access memory unit via the memory control unit, so that the processor unit can quickly obtain execution data without interacting with the flash memory unit, so that the processor unit can always be in an efficient operation state, greatly improving the operation efficiency of the computer system.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more particularly, to a processor system. Background Art

[0002] At present, DRAM (Dynamic Random Access Memory) technology has achieved great development, and the main applications include synchronous dynamic random access memory (SDRAM), double data rate (DDR) SDRAM, second generation double data rate (DDR2) SDRAM, third generation double data rate (DDR3) SDRAM and fourth generation double data rate (DDR4) SDRAM and other types. For the above types of DRAM, it is mainly composed of a memory control unit and a DRAM chip (i.e., memory particles). The CPU (central processing unit) sends control commands to the DRAM chip via the memory control unit, including clock signals, command control signals, and address signals, and controls the reading and writing operations of data signals on the DRAM chip through the above control commands.

[0003] When the computer system is executing a program, the relevant program and data executed by the CPU must be placed in DRAM first. When executing the program, the CPU fetches instructions from DRAM and executes them according to the content of the current program pointer register, and then fetches the next instruction and executes it, and so on until the program ends. The working process is the process of continuously fetching and executing instructions, and finally putting the calculation result into the memory address specified by the instruction.

[0004] However, due to the high cost of DRAM, its storage capacity is usually limited, so most programs are stored in relatively low-cost large-capacity storage devices, such as hard disks, solid-state drives, etc. When the computer is running, the CPU needs to move the data in the large-capacity storage device to DRAM, and write the data in DRAM to the large-capacity storage device. In addition, because the interaction speed between the large-capacity storage device and the central processing unit is much lower than the interaction speed between the central processing unit and DRAM, the overall operating efficiency of the computer system is greatly affected. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a processor system to address the problem of high DRAM cost in the above-mentioned computer system.

[0006] The technical solution of the present invention to solve the above technical problems is to provide a processor system, including a processor unit, a random access memory unit, a memory control unit, a flash memory unit and an internal bus, wherein the processor unit is connected to the random access memory unit through the internal bus, the random access memory unit is connected to the flash memory unit through the memory control unit, and the flash memory unit is mapped through the memory control unit, the processor unit reads the data instruction set of the random access memory unit through the internal bus, the memory control unit is used to read and feedback the corresponding data instructions from the random access memory unit, and when the data instruction set in the random access memory unit meets the preset conditions, obtains the subsequent instruction set of the data instruction set from the flash memory unit and writes it into the random access memory unit.

[0007] As a further improvement of the present invention, the processor unit includes a first processor unit and a second processor unit, the data instruction set includes a first instruction set and a second instruction set, the preset condition includes a first preset condition and a second preset condition, the first instruction set is an instruction set waiting to be processed by the first processor unit, and the second instruction set is an instruction set waiting to be processed by the second processor unit;

[0008] The memory control unit is used to read and feed back corresponding instructions from the random access memory unit according to requests from the first processor unit and the second processor unit, and when a first instruction set in the random access memory unit meets a first preset condition, obtain a subsequent instruction set of the first instruction set from the flash memory unit and write it into the random access memory unit, and when a second instruction set in the random access memory unit meets a second preset condition, obtain a subsequent instruction set of the second instruction set from the flash memory unit and write it into the random access memory unit.

[0009] As a further improvement of the present invention, the first processor unit is further configured to read a subsequent instruction set of the second instruction set from the random access memory unit.

[0010] As a further improvement of the present invention, the first processor unit is further used to cache the processed first instruction set to the random access memory unit, and the second processor unit is used to read the processed first instruction set from the random access memory unit.

[0011] As a further improvement of the present invention, the random access memory unit includes a first mapping area and a second mapping area, the first mapping area is used to cache the first instruction set and its subsequent instruction set, and the second mapping area is used to cache the second instruction set and its subsequent instruction set.

[0012] As a further improvement of the present invention, the random access memory unit includes a first mapping area, a second mapping area, a third mapping area and a fourth mapping area, the first mapping area is used to cache the first instruction set, the third mapping area is used to cache the subsequent instruction set of the first instruction set; the second mapping area is used to cache the second instruction set, and the fourth mapping area is used to cache the subsequent instruction set of the second instruction set.

[0013] As a further improvement of the present invention, the first mapping area and the third mapping area are used to cache the data instruction set and switch with each other; the second mapping area and the fourth mapping area are used to cache the data instruction set and switch with each other.

[0014] As a further improvement of the present invention, the preset condition is that the number of data instruction sets in the random access memory unit waiting to be read by the processor unit is less than a preset value, or the estimated execution time of the data instruction sets in the random access memory unit waiting to be read in the processor is less than a preset time.

[0015] As a further improvement of the present invention, the internal bus further comprises an arbitrator unit, which is used to determine the execution order of the requests of the processor units and / or to determine the processing order of the same data instruction set between different processor units.

[0016] As a further improvement of the present invention, the processor unit, random access memory unit, memory control unit, flash memory unit and internal bus are integrated into the same processor chip.

[0017] As a further improvement of the present invention, the processor unit is integrated into a first chip, the random access memory unit, the memory control unit, the flash memory unit, and the internal bus are integrated into a second chip, and the first chip is electrically connected to the second chip.

[0018] As a further improvement of the present invention, the processor unit and the internal bus are integrated into a first chip, the random access memory unit, the memory control unit and the flash memory unit are integrated into a second chip, and the first chip is electrically connected to the second chip.

[0019] The processor system of the present invention maps the storage data of the flash memory unit to the random access memory unit through the memory control unit, so that the processor unit can quickly obtain execution data without interacting with the flash memory unit, so that the processor unit can always be in an efficient operating state, greatly improving the operating efficiency of the computer system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a block diagram of a processor system provided by an embodiment of the present invention;

[0021] Figure 2 is a schematic diagram (I) of the working principle of a processor system provided by another embodiment of the present invention;

[0022] Figure 3 is a schematic diagram (II) of the working principle of a processor system provided by another embodiment of the present invention;

[0023] Figure 4 It is a schematic diagram (III) of the working principle of a processor system provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0025] like Figure 1 , is a block diagram of a processor system provided by the present invention, and the processor system can be applied to electronic devices, such as personal computers, servers, mobile phones, tablets, etc., and implements instruction storage and processing. The processor system of this embodiment includes a processor unit 12, a memory control unit 13, an internal bus 14, a random access memory unit 15, and a flash memory unit 16, and the processor unit 12 and the random access memory unit 15 are respectively connected to the internal bus 14, the random access memory unit 15 is electrically connected to the memory control unit 13, the memory control unit 13 is electrically connected to the flash memory unit, and the random access memory unit 15 maps the flash memory unit 16 through the memory control unit 13. During the operation of the above-mentioned processor system, the data instruction set currently being executed or about to be executed by the processor unit 12 is stored through the random access memory unit 15, and the flash memory unit 16 is used to store the data instruction set that needs to be stored for a long time.

[0026] In one embodiment of the present invention, the processor unit 12, the random access memory unit 15, the memory control unit 13, the flash memory unit 16 and the internal bus 14 can be integrated into the same processor chip, which includes a unified external interface and is installed on a circuit board (such as a motherboard of a computer system) through the external interface, so that it can communicate with external devices and realize signal input and output operations.

[0027] In practical applications, the processor unit 12, the random access memory unit 15, the memory control unit 13, the flash memory unit 16 and the internal bus 14 can also be integrated into multiple chips, for example, the processor unit 12 is integrated into the first chip, the random access memory unit 15, the memory control unit 13, the flash memory unit 16, and the internal bus 14 are integrated into the second chip, and the first chip is electrically connected to the second chip. Alternatively, the processor unit 12 and the internal bus 14 are integrated into the first chip, the random access memory unit 15, the memory control unit 13, and the flash memory unit 16 are integrated into the second chip, and the first chip is electrically connected to the second chip. The above-mentioned first chip and the second chip can be packaged into one body using a system-level packaging process, and a unified external interface is provided, so that they can be installed on devices such as circuit boards. In addition, the above units can also be integrated into different processor chips, DRAM chips, memory control chips, flash memory chips and internal buses, then the processor system can be packaged into one body using a system-level packaging process, and a unified external interface is provided, so that it can be installed on devices such as circuit boards.

[0028] In one embodiment of the present invention, the internal bus 14 may include a memory bus (e.g., a DRAM bus, etc.), a peripheral bus (e.g., a PCIE bus, etc.), and a bridge. The processor unit 12 and the random access memory unit 15 are electrically connected to the memory bus, respectively, the memory control unit 13 is electrically connected to the random access memory unit 15 via the DRAM bus, and the flash memory unit 16 is electrically connected to the memory control unit 13 via the peripheral bus.

[0029] In one embodiment of the present invention, the flash memory unit 16 may specifically use a NAND memory chip with a relatively large storage capacity, relatively low cost, and relatively slow data access speed, which can save data in a power-off state; the random access memory unit 15 may specifically use a DDR, DDR2, DDR3, DDR4, DDR5 or phase change memory memory chip with a relatively small storage capacity, relatively high cost, and relatively fast data access speed, that is, the data storage capacity of the random access memory unit 15 is smaller than the data storage capacity of the flash memory unit 16. Considering the cost factor, the random access memory unit 15 preferably uses a memory chip that cannot retain the stored data when the power is off.

[0030] The memory control unit 13 maps the storage data of the flash memory unit 16 with a larger storage capacity and a lower cost to the random access memory unit 15 with a smaller storage capacity and a higher cost, and the above-mentioned mapping operation does not occupy the clock cycle of the processor unit 12, and the memory bus between the processor unit 12 and the random access memory unit 15. High-speed data processing can be achieved when the storage capacity of the random access memory unit 15 is small, so that the processor unit 12 can always be in an efficient operating state, greatly improving the operating efficiency of electronic devices such as computer systems.

[0031] In one embodiment of the present invention, the memory control unit 13 can read and feed back corresponding data instructions from the random access memory unit 15 according to the request of the processor unit 12, that is, when the memory control unit 13 receives the read / write request of the processor unit 12, it obtains the data instruction corresponding to the read / write request from the random access memory unit 15 and sends the data instruction corresponding to the read / write request to the processor unit 12 through the memory bus, and writes the execution result of the processor unit 12 to the random access memory unit 15. The above operation process is the same as the data interaction process between the existing processor and the internal memory (such as DRAM), which will not be repeated here.

[0032] Furthermore, the memory control unit 13 can realize the mapping between the random access memory unit 15 and the flash memory unit 16 in the following manner: when the data instruction set in the random access memory unit 15 meets the preset condition, the memory control unit 13 obtains the subsequent instruction set of the data instruction set from the flash memory unit 16 and writes it into the random access memory unit 15. Specifically, the preset condition can be (that is, the memory control unit 13 can map the content in the flash memory unit 16 to the random access memory unit 15 in the following manner): when the number of instruction sets in the random access memory unit 15 waiting to be read by the processor unit 12 is less than a preset value, or when the estimated execution time of the instruction set in the random access memory unit 15 waiting to be read in the processor unit 12 is less than a preset time, the memory control unit 13 obtains the subsequent instruction set of the instruction set from the flash memory unit 16, and updates and stores the subsequent instruction set of the instruction set in the random access memory unit 15. Therefore, the data instruction in the random access memory unit 15 can be updated in time, so as not to affect the instruction execution of the processor unit 12.

[0033] Since the memory control unit 13 can directly predict the subsequent instruction set that the processor unit 12 needs to execute based on the instruction set that it is executing, and update the content in the random access memory unit 15 based on the prediction result, the processor unit 12 does not need to interact with the flash memory unit 16, and will not occupy the memory bus. That is, for the processor unit 12, the operation of the above-mentioned memory control unit 13 is transparent, and the data movement operation of the random access memory unit 15 does not require the participation of the processor unit 12, and does not need to allocate time for management. The processor unit 12 only uses the random access memory unit 15 and the flash memory unit 16 as a super large DRAM, and the data is permanently and automatically solidified. As a result, the processor unit 12 can always be in an efficient operating state, which is suitable for fields with high requirements for computing resources such as cloud computing, and can greatly improve the operating efficiency of the system.

[0034] Combination Figure 2 As shown, in one embodiment of the present invention, the processor unit 12 includes a first processor unit 121 and a second processor unit 122. The first processor unit 121 and the second processor unit 122 may be processors of different types, for example, the first processor unit 121 is a main processor, for example, an embedded processor including multiple cores, etc., and the second processor unit 122 may be an auxiliary processor, for example, a graphics processor, a neural network processor or other similar processors. Accordingly, the data instruction set in the random access memory unit 15 includes a first instruction set and a second instruction set, wherein the first instruction set is an instruction set waiting for processing by the first processor unit 121, and the second instruction set is an instruction set waiting for processing by the second processor unit 122. The preset condition includes a first preset condition and a second preset condition.

[0035] The memory control unit 13 reads and feeds back corresponding data instructions from the random access memory unit 15 according to the requests of the first processor unit 121 and the second processor unit 122 respectively, and when the first instruction set in the random access memory unit 15 meets the first preset condition, obtains the subsequent instruction set of the first instruction set from the flash memory unit 16 and writes it into the random access memory unit 15, and when the second instruction set in the random access memory unit meets the second preset condition, obtains the subsequent instruction set of the second instruction set from the flash memory unit 16 and writes it into the random access memory unit 15.

[0036] The first preset condition may specifically be: when the number of first instruction sets in the random access memory unit 15 waiting to be read by the first processor unit 121 is less than a preset value, or the estimated time for the first instruction sets in the random access memory unit 15 waiting to be read to be executed in the first processor unit 121 is less than a preset time; the second preset condition may specifically be: when the number of second instruction sets in the random access memory unit 15 waiting to be read by the second processor unit 122 is less than a preset value, or the estimated time for the second instruction sets in the random access memory unit 15 waiting to be read to be executed in the second processor unit 122 is less than a preset time. The above preset value and preset time may be adjusted according to the storage capacity of the random access memory unit 15, the main frequency of the first processor unit 121 and the second processor unit 122, etc.

[0037] In one embodiment of the present invention, the first processor unit 121 can also be used to read subsequent instruction sets of the second instruction set from the random access memory unit 15. That is, all instruction sets cached in the random access memory unit 15 can be read by different processor units such as the first processor unit 121 or the second processor unit 122, thereby accelerating the processing speed of data instruction sets between multiple processor units, reducing the frequency of the same data instruction set being transferred from the flash memory unit 16 to the random access memory unit 15, and thereby accelerating the speed at which multiple processor units process the same or similar data instruction sets.

[0038] In one embodiment of the present invention, the first processor unit 121 is also used to cache the processed first instruction set to the random access memory unit 15, and the second processor unit 122 is used to read the processed first instruction set from the random access memory unit 15. After the first processor unit 121 reads and processes the first instruction set, the first processor unit 121 is also responsible for caching the processed first instruction set to the random access memory unit 15. At this time, the first instruction set processed by the first processor unit 121 in the random access memory unit 15 can also be read by the second processor 122 and processed again. In this embodiment, after being processed by one processor unit, the same data instruction set is cached to the random access memory unit, and other processors can continue to read and process the instruction set. In this case, the data instruction set can be continuously transferred from the flash memory unit to the random access memory unit through the memory control unit, and the data instruction set can also be processed by different processing units according to the processing order, and then stored in the flash memory unit, which greatly improves the processing speed and efficiency of the data instruction set, reduces the number of times the data instruction set is transferred, and improves the processing efficiency of the processor.

[0039] Combination Figure 4As shown, in one embodiment of the present invention, the random access memory unit 15 includes a first mapping area 151 and a second mapping area 152, both of which are a section of storage space in the random access memory unit 15, wherein the first mapping area 151 is used to cache the first instruction set and its subsequent instruction set, and the second mapping area 152 is used to cache the second instruction set and its subsequent instruction set. That is, the first mapping area 151 is used by the first processor unit 121, and the second mapping area 152 is used by the second processor unit 122.

[0040] The first instruction set and the second instruction set in the first mapping area 151 and the second mapping area 152 correspond to a certain instruction program 161 and 162 in the flash memory unit 16, respectively, that is, the first mapping area 151 and the second mapping area 152 are equivalent to two "windows" of the flash memory unit 16, and the first processor unit 121 and the second processor unit 122 can obtain the instruction program stored in the flash memory unit 16 through the two "windows". The content displayed in the "window" is controlled by the memory control unit 13.

[0041] Specifically, when the first instruction set in the first mapping area 151 meets the first preset condition, the memory control unit 13 obtains the subsequent instruction set of the first instruction set from the flash memory unit 16 and writes it to the first mapping area 151; when the second instruction set in the second mapping area 152 meets the second preset condition, the memory control unit 13 obtains the subsequent instruction set of the second instruction set from the flash memory unit 16 and writes it to the second mapping area 152.

[0042] In another embodiment of the present invention, the random access memory unit 15 includes a first mapping area, a second mapping area, a third mapping area and a fourth mapping area, wherein the first mapping area is used to cache a first instruction set, and the third mapping area is used to cache a subsequent instruction set of the first instruction set; the second mapping area is used to cache a second instruction set, and the fourth mapping area is used to cache a subsequent instruction set of the second instruction set. In this way, the process of establishing a mapping is separated from the process of the processor unit reading instructions, so that the process of establishing a mapping does not affect the instruction execution operation of the processor unit, and the efficiency of the processor unit in executing instructions is further improved.

[0043] In particular, one of the first mapping area and the third mapping area is used as the main mapping area, and the other is used as the backup mapping area, wherein the main mapping area stores the data instructions currently being executed and to be executed by the first processor unit 121, and the memory control unit 13 stores the subsequent instruction set of the first instruction set in the main mapping area in the backup mapping area, and when the conditions are met, the main mapping area and the backup mapping area are interchanged, that is, the main and backup states of the first mapping area and the third mapping area are switched with each other. For example, the first mapping area and the third mapping area can switch the main mapping area and the backup mapping area according to the jump instruction executed by the first processor unit 121 (that is, the jump instruction in the main mapping area). For example, when the first mapping area is the main mapping area, the first processor unit 121 obtains the data instruction from the first mapping area through the memory control unit 13 according to the program address specified by the program counter. Under normal circumstances, each time the program counter executes a data instruction, it automatically increases the original address by 1 as the program address of the next data instruction, so that the first processor unit 121 obtains the next data instruction from the first mapping area according to the updated program address; if the data instruction executed by the first processor unit 121 is a jump instruction, the program counter increases the original address by n or -n according to the jump value n as the program address of the next data instruction, and the first processor unit 121 obtains the next data instruction from the first mapping area according to the updated program address; when the program address specified by the program counter is located in the third mapping area (i.e., the backup mapping area), the main mapping area and the backup mapping area are switched.

[0044] Similarly, one of the second mapping area and the fourth mapping area is used as a main mapping area, and the other is used as a backup mapping area for switching when caching the data instruction set.

[0045] Combination Figure 3 , Figure 4As shown, in one embodiment of the present invention, the internal bus 14 may also include an arbiter unit 141, which is used to determine the execution order of the requests of the processor unit 12. Specifically, when the arbiter unit 141 receives multiple requests from the processor unit 12 at the same time, the arbiter unit 141 may determine the priority of these requests and respond to the request with a higher priority first, that is, return the data instructions corresponding to the request with a higher priority to the processor unit 12 in advance, so that the parallel processing of the program can be achieved without affecting the execution of the main program. When there are multiple processor units in the processor system, for example: the first processor unit 121, the second processor unit 122, etc., the arbiter unit 141 of the internal bus 14 is also used to determine the priority of the requests from different processor units, and respond to the request with a higher priority first, that is, return the data instructions corresponding to the request with a higher priority to the processor unit 12 in advance, so that the parallel processing of the program can be achieved without affecting the execution of the main program. In some embodiments, the arbiter unit 141 can also be used to coordinate or determine the processing order of the same data instruction set between different processor units. For example, according to the processing order of the data, the first processor unit first processes the data, and then caches the processed data to the random access memory unit 15, and then the second processor unit reads the processed data instruction gold for secondary processing, thereby improving the data processing efficiency. In this way, if there are more processor units, the data can also be processed by processor units with different functions according to the type of data instruction set.

[0046] The present invention also provides a processor system, including a processor chip, a random access memory chip, a memory control chip, a flash memory chip and an internal bus. The processor chip is connected to the random access memory chip through the internal bus, and the random access memory chip maps the flash memory chip through the memory control chip; and the memory control chip is used to read and feedback corresponding instructions from the random access memory chip according to the request of the processor chip, and when the data instruction set in the random access memory chip meets the preset conditions, obtain the subsequent instruction set of the data instruction set from the flash memory chip and write it into the random access memory chip. The processor chip, random access memory chip, memory control chip, flash memory chip and internal bus are packaged together using a system-level packaging process, and provide a unified external interface, so that they can be installed on devices such as circuit boards.

[0047] The processor system in this embodiment is similar to the above Figure 1-2 The processor systems in the corresponding embodiments belong to the same concept, and their specific implementation processes are detailed in the corresponding embodiments, and Figure 1-2 The technical features in the embodiments are applicable to the present embodiment and will not be described in detail here.

[0048] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0049] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in the relevant technical field without departing from the purpose of the present invention. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

Claims

1. A processor system, characterized in that: The invention comprises a processor unit, a random access memory unit, a memory control unit, a flash memory unit and an internal bus, wherein the processor unit is connected to the random access memory unit through the internal bus, the random access memory unit is connected to the flash memory unit through the memory control unit, and the flash memory unit is mapped through the memory control unit, the processor unit reads a data instruction set of the random access memory unit through the internal bus, the memory control unit is used to read and feed back corresponding data instructions from the random access memory unit, and when the data instruction set in the random access memory unit meets a preset condition, obtains a subsequent instruction set of the data instruction set from the flash memory unit and writes it into the random access memory unit; The processor unit includes a first processor unit and a second processor unit, the data instruction set includes a first instruction set and a second instruction set, the preset condition includes a first preset condition and a second preset condition, the first instruction set is an instruction set waiting to be processed by the first processor unit, and the second instruction set is an instruction set waiting to be processed by the second processor unit; The memory control unit is used to read and feed back corresponding instructions from the random access memory unit according to requests of the first processor unit and the second processor unit, and when a first instruction set in the random access memory unit meets a first preset condition, obtain a subsequent instruction set of the first instruction set from the flash memory unit and write it into the random access memory unit, and when a second instruction set in the random access memory unit meets a second preset condition, obtain a subsequent instruction set of the second instruction set from the flash memory unit and write it into the random access memory unit; The first processor unit is used to read a subsequent instruction set of the second instruction set from the random access memory unit; The first processor unit is used to cache the processed first instruction set and / or processing result to the random access memory unit, and the second processor unit is used to continue processing the processed first instruction set and / or processing result.

2. The processor system according to claim 1, characterized in that The random access memory unit includes a first mapping area and a second mapping area, the first mapping area is used to cache the first instruction set and subsequent instruction sets, and the second mapping area is used to cache the second instruction set and subsequent instruction sets.

3. The processor system according to claim 1, characterized in that The random access memory unit includes a first mapping area, a second mapping area, a third mapping area and a fourth mapping area. The first mapping area is used to cache the first instruction set, and the third mapping area is used to cache the subsequent instruction set of the first instruction set; the second mapping area is used to cache the second instruction set, and the fourth mapping area is used to cache the subsequent instruction set of the second instruction set.

4. The processor system according to claim 3, characterized in that The first mapping area and the third mapping area are used to cache the data instruction set and switch between them; the second mapping area and the fourth mapping area are used to cache the data instruction set and switch between them.

5. The processor system according to claim 1, characterized in that The preset condition is that the number of data instruction sets in the random access memory unit waiting to be read by the processor unit is less than a preset value, or the estimated execution time of the data instruction sets in the random access memory unit waiting to be read in the processor is less than a preset time.

6. The processor system according to claim 1, characterized in that The internal bus further comprises an arbiter unit, which is used to determine the execution order of the requests of the processor units and / or to determine the processing order of the same data instruction set between different processor units.

7. The processor system according to claim 1, characterized in that The processor unit, random access memory unit, memory control unit, flash memory unit and internal bus are integrated into the same processor chip.

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