Semiconductor nanowire device with cavity spacer and method of manufacturing cavity spacer of semiconductor nanowire device

Abstract

Semiconductor nanowire devices with cavity spacers and methods of making cavity spacers for semiconductor nanowire devices are described. For example, the semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires including a discrete channel region. A common gate electrode stack surrounds each of the discrete channel regions of the plurality of vertically stacked nanowires. A pair of dielectric spacers are on either side of the common gate electrode stack, each of the pair of dielectric spacers including a continuous material disposed along a sidewall of the common gate electrode and surrounding a discrete portion of each of the vertically stacked nanowires. A pair of source and drain regions are on either side of the pair of dielectric spacers.

Description

Technical Field

[0001] Embodiments of the present invention are in the field of semiconductor devices, and in particular, in the field of semiconductor nanowire devices having cavity spacers and methods of fabricating cavity spacers of semiconductor nanowire devices. Background Art

[0002] Over the past several decades, the scaling of features in integrated circuits has become the driving force behind the growing semiconductor industry. Scaling to smaller and smaller features enables an increased density of functional units on the limited substrate area of ​​a semiconductor chip. For example, shrinking transistor size allows an increased number of memory devices to be incorporated on a chip, resulting in the manufacture of products with increased capacity. However, the push for greater capacity is not without problems. The necessity to optimize the performance of each device becomes increasingly important.

[0003] In the fabrication of integrated circuit devices, multi-gate transistors (e.g., tri-gate transistors or gate-all-around devices (e.g., nanowires) have become more common as device dimensions continue to scale down. Many different techniques have attempted to reduce the parasitic capacitance of such transistors. However, significant improvements are still needed in the field of parasitic capacitance suppression. Many different techniques have also attempted to fabricate devices with non-Si channel materials (e.g., SiGe, Ge, and III-V materials). However, significant process improvements are still needed to integrate these materials onto Si wafers. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1A A three-dimensional cross-sectional view of a nanowire-based semiconductor structure with a cavity spacer is illustrated in accordance with an embodiment of the present invention.

[0005] Figure 1B The diagram shows a diagram of an embodiment of the present invention, as taken along the a-a' axis. Figure 1A Cross-sectional channel diagram of a nanowire-based semiconductor structure.

[0006] Figure 1C The diagram shows a diagram of an embodiment of the present invention, as taken along the bb' axis. Figure 1A Figure 2. Cross-sectional spacer diagram of a nanowire-based semiconductor structure.

[0007] Figure 1C 'Illustration of a cross-sectional spacer diagram of a conventional nanowire-based semiconductor structure.

[0008] Figures 2A-2J illustrates a three-dimensional cross-sectional view representing various operations in a method of fabricating a semiconductor nanowire structure with a cavity spacer, in accordance with an embodiment of the present invention, wherein:

[0009] Figure 2AFIG. 1 shows a starting structure including a fin formed above a semiconductor substrate;

[0010] Figure 2B Image after sacrificial gate stack material deposition and gate patterning Figure 2A structure;

[0011] Figure 2C Figure 2 shows the first and second sacrificial release layers after removing the exposed portions of the source and drain regions of the protruding portion of the fin. Figure 2B structure.

[0012] Figure 2D Figure 1. After deposition of the spacer forming material layer. Figure 2C structure.

[0013] Figure 2E Figure 1. After etching the spacer forming material layer to form the cavity spacer. Figure 2D structure;

[0014] Figure 2F Figure 2. Source and drain structures after growth between cavity spacers. Figure 2E structure;

[0015] Figure 2G After forming the planarization oxide and removing the three sacrificial gates Figure 2F structure;

[0016] Figure 2H Figure 2 shows the process after removing the portions of the first and second sacrificial release layers exposed in the channel region of the protruding portion of the fin. Figure 2G structure;

[0017] Fig.2I After forming a gate dielectric layer on a portion of the active line formation layer and in the channel region Figure 2H structure; and

[0018] Figure 2J After forming the permanent gate electrode Fig.2I structure.

[0019] Figure 3 A computing device according to one implementation of the invention is illustrated.

[0020] Figure 4 is an interposer that implements one or more embodiments of the present invention. DETAILED DESCRIPTION

[0021] Semiconductor nanowire devices with cavity spacers and methods of manufacturing cavity spacers for semiconductor nanowire devices are described. In the following description, many specific details are set forth, such as specific integration and material regimes, in order to provide a comprehensive understanding of embodiments of the invention. It will be apparent to those skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, well-known features (e.g., integrated circuit design layouts) are not described in detail so as not to unnecessarily obscure embodiments of the invention. In addition, it is to be appreciated that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0022] One or more embodiments described herein are directed to nanowire-based field effect transistor (FET) MOS transistors. Certain embodiments are directed to cavity spacers for such nanowire devices.

[0023] To provide context, reducing parasitic capacitance in nanowires and also reducing dopant contamination in active wires can greatly improve the performance of such devices. According to embodiments of the present invention, parasitic capacitance is reduced by forming cavity spacers by removing a sacrificial layer subsequent to gate patterning. The process can involve isotropic deposition of the spacer material followed by a spacer etch process performed in the source and drain regions of the device. In addition to reducing parasitic capacitance, the embodiments described herein can also be useful for limiting the entry of source and drain dopant materials into the active channel region (which might otherwise occur through a sacrificial semiconductor layer).

[0024] More particularly, one or more embodiments described herein are directed to methods for forming non-planar architectures containing silicon (Si). For example, in embodiments, one or more devices described herein may be characterized as Si-based devices, nanoribbon-based devices, nanowire-based devices, non-planar transistors, or multi-gate devices. More particularly, one or more embodiments are directed to performing full or partial release of Si-containing features from a SiGe / Si multilayer stack.

[0025] Advantages of the described embodiments include low parasitic capacitance and improved short channel effects for nanowire-based semiconductor devices. Such improvements can enable scaling of next generation devices by making nanowires feasible via parasitic capacitance reduction and improved short channel effects. Additional advantages may include the ability to restrict source and drain dopants from entering the channel region of a nanowire device.

[0026] As examples of some of the structural ramifications that implement cavity spacers, Figure 1A A three-dimensional cross-sectional view of a nanowire-based semiconductor structure with a cavity spacer is illustrated in accordance with an embodiment of the present invention. Figure 1B The diagram shows a diagram of an embodiment of the present invention, as taken along the a-a' axis. Figure 1A Cross-sectional channel diagram of a nanowire-based semiconductor structure. Figure 1C The diagram shows a diagram of an embodiment of the present invention, as taken along the bb' axis. Figure 1A Figure 2. Cross-sectional spacer diagram of a nanowire-based semiconductor structure.

[0027] refer to Figure 1A , semiconductor device 100 includes one or more vertically stacked nanowires (set 104) disposed above substrate 102. Embodiments herein target both single-wire devices and multi-wire devices. As an example, three nanowire-based devices having nanowires 104A, 104B, and 104C are shown for illustration purposes. For ease of description, nanowire 104A is used as an example, wherein the description focuses on only one of the nanowires. It is to be appreciated that where properties of one nanowire are described, embodiments based on multiple nanowires may have the same properties for each of the nanowires. For ease of illustration, in Figure 1A For example, the cavity spacer 116 and the gate electrode stack 108 are shown in FIG. Figure 1A are shown as being substantially coplanar; however, as with Figures 2A-2J As described in more detail in conjunction with FIG. 1 , the cavity spacer 116 may be recessed below the gate electrode stack 108. Additionally, the source and drain regions 110 and 112 and the cavity spacer 116 may be recessed below the gate electrode stack 108. Figure 1A are shown as being substantially coplanar; however, as with Figures 2A-2J As described in more detail in conjunction with , the source and drain regions 110 and 112 may be recessed below the cavity spacer 116. Alternatively, in another embodiment, the source and drain regions 110 and 112 are raised above the cavity spacer 116.

[0028] refer to Figure 1A and 1B In both cases, each of the nanowires 104 (e.g., as 104A, 104B, and 104C) includes a channel region 106 disposed in the nanowire. The channel region 106 has a length (L). A gate electrode stack 108 surrounds the entire perimeter of each of the channel regions 106. The gate electrode stack 108 includes a gate electrode together with a gate dielectric layer (not shown here but described below) disposed between the channel region 106 and the gate electrode. Figures 2A-2J104B and 104C). The channel region 106 is discrete in that it is completely surrounded by the gate electrode stack 108 without any intervening materials such as base substrate material or overlying channel fabrication materials. Thus, in embodiments having a plurality of nanowires 104 (e.g., nanowires 104A, 104B, and 104C), the channel regions 106 of the nanowires are also discrete relative to each other. However, it is to be appreciated that in some embodiments, the lowest wire or wires are not completely discrete and may have a tri-gate-like architecture at the bottom portion of the wire stack.

[0029] refer to Figure 1A , each of the nanowires 104 is coupled to common source and drain regions 110 and 112 disposed on either side of the channel region 106. In an embodiment, the common source and drain regions 110 and 112 are semiconductor regions. Although not depicted, a pair of conductive contacts may be formed on the common source / drain regions 110 / 112.

[0030] refer to Figure 1A and 1C In an embodiment, the semiconductor device 100 further includes a pair of spacers 116. The spacers 116 are disposed between the gate electrode stack 108 and the common source and drain regions 110 and 112. Figures 2A-2J For reasons that will become apparent in the description of , the spacers 116 may be referred to as cavity spacers. In an embodiment, each of the pair of cavity spacers 116 is a continuous spacer, as opposed to having distinct outer and inner spacers. In one such embodiment, each of the pair of spacers 116 comprises a continuous material disposed along a sidewall of the gate electrode stack 108 and surrounding a discrete portion of each of the vertically stacked nanowires 104.

[0031] As briefly mentioned above, embodiments described herein may also be useful for limiting entry of source and drain dopant materials into the active channel region that might otherwise occur via a sacrificial semiconductor layer. Figure 1C 'Illustration of a cross-sectional spacer diagram of a conventional nanowire-based semiconductor structure. Reference Figure 1C ',and Figure 1C In contrast, the spacers 116 do not surround discrete portions of the nanowires 104. Instead, intervening sacrificial material portions 199 remain after conventional nanowire processing (e.g., where removal of the sacrificial material portions 199 is hindered by etch limitations or by the nature of the process integration scheme used). Such intervening sacrificial material portions 199 can provide undesirable entry pathways for dopants to enter the channel region 106 of the nanowires 104.

[0032] The substrate 102 may be composed of a material suitable for semiconductor device fabrication. In one embodiment, the substrate 102 includes a lower bulk substrate composed of a single crystal material, which may include but is not limited to silicon, germanium, silicon-germanium, or a III-V compound semiconductor material. In an embodiment, an upper insulator layer 103 composed of a material that may include but is not limited to silicon dioxide, silicon nitride, or silicon oxynitride is disposed on the lower bulk substrate. Thus, the substrate 100 may be fabricated from an initial semiconductor-on-insulator substrate. Alternatively, the structure 100 is formed directly from a bulk substrate and local oxidation is used to form an electrically insulating portion to replace the upper insulator layer described above. In another alternative embodiment, the structure 100 is formed directly from a bulk substrate and doping may be used to form electrically isolated active regions, such as nanowires, thereon.

[0033] In an embodiment, the nanowire 104 may be sized as a wire or a ribbon and may have squared or more rounded corners. In an embodiment, the nanowire 104 is composed of a material such as, but not limited to, silicon, germanium, silicon germanium, or a III-V material. In one such embodiment, the nanowire is single crystalline. For example, for silicon nanowire 104, the single crystalline nanowire may be based on a (100) global orientation, such as having a <100> Plane. It is to be appreciated that other orientations may also be considered. In an embodiment, the dimensions of the nanowires 104 are on the nanometer scale from an end-on cross-section perspective. For example, in a particular embodiment, the smallest dimension of each of the nanowires 104 is less than approximately 20 nanometers.

[0034] In an embodiment, the nanowire 104 is composed of strained material, particularly in the channel region 106. In an embodiment, the nanowires 104A-104C are uniaxially strained nanowires. The uniaxially strained nanowire or multiple nanowires, for example, can be uniaxially strained using tensile strain or using compressive strain for NMOS or PMOS, respectively. The width and height of each of the nanowires 104A-104C are shown as being approximately the same, however, they do not have to be so. For example, in another embodiment (not shown), the width of the nanowires 104A-104C is much larger than the height. In a specific embodiment, the width is approximately 2-10 times the height. Nanowires with such a geometric shape can be referred to as nanobelts. In an alternative embodiment (also not shown), the nanobelts are vertically oriented. That is, each of the nanowires 104A-104C has a certain width and a certain height, and the width is much smaller than the height.

[0035] In an embodiment, the gate electrode of the gate electrode stack 108 is composed of a metal gate and the gate dielectric layer is composed of a high-K material. For example, in one embodiment, the gate dielectric layer is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer may include a layer of native oxide formed by the top layers of the nanowires 104. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion (composed of an oxide of a semiconductor material). In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride.

[0036] In one embodiment, the gate electrode is composed of a metal layer (such as but not limited to metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or a conductive metal oxide). In a specific embodiment, the gate electrode is composed of a non-work function setting fill material formed above the metal work function setting layer.

[0037] In an embodiment, the source and drain regions 110 / 112 are embedded source and drain regions, for example, at least a portion of the nanowires are removed and replaced with source / drain material regions, as in Figure 1A In an embodiment, the common source and drain regions 110 and 112 are semiconductor regions. In one such embodiment, the semiconductor regions are epitaxially grown from the ends of the nanowires 104 and / or from exposed portions of the underlying bulk semiconductor substrate (hereinafter referred to as Figures 2A-2J In one embodiment, the common source and drain regions 110 and 112 are composed of a material such as, but not limited to, silicon, germanium, silicon germanium, or a III-V material. In one embodiment, the common source and drain regions 110 and 112 are doped with impurity atoms. In an embodiment, the common source and drain regions 110 and 112 are composed of a material different from the channel material. For example, in an embodiment, for PMOS, a silicon channel is used together with silicon germanium source and drain regions. In an embodiment, for NMOS, a silicon channel is used together with InAs source and drain regions. Alternatively, the common source and drain regions 110 and 112 are composed of a material that is the same or similar to the channel material.

[0038] In an embodiment, the cavity spacer 116 is composed of an insulating dielectric material (such as, but not limited to, silicon dioxide, silicon oxynitride, or silicon nitride). The overlying source / drain contacts (not shown) are made of a metal species in an embodiment. The metal species may be a pure metal, such as nickel or cobalt, or may be an alloy, such as a metal-metal alloy or a metal semiconductor alloy (e.g., such as a silicide material).

[0039] In an embodiment, semiconductor device 100 is a MOS-FET. In an embodiment, semiconductor device is a three-dimensional MOS-FET and is either an isolated device or one of a plurality of nested devices. As will be appreciated for a typical integrated circuit, both N- and P-channel transistors can be fabricated on a single substrate to form a CMOS integrated circuit. In addition, additional interconnect wiring can be fabricated to enable such a device to be integrated into an integrated circuit.

[0040] In another aspect, a sacrificial or replacement gate process can be used to first access the source and drain regions and then access the channel region to form a nanowire device with low parasitic capacitance. As an example, Figures 2A-2J Illustration is of three-dimensional cross-sectional views representing various operations in a method of fabricating a semiconductor nanowire structure with a cavity spacer, in accordance with an embodiment of the present invention.

[0041] refer to Figure 2A , the initial structure 200 includes a fin 211 formed above a semiconductor substrate 202. The fin 211 includes a buried portion 213 and a protruding portion 212. The protruding portion 212 includes active line forming layers 204 and 208, such as silicon line forming layers. A first sacrificial release layer 206 (e.g., a first silicon germanium sacrificial release layer) is disposed between the active line forming layers 204 and 208. A second sacrificial release layer 210 (e.g., a second silicon germanium sacrificial release layer) is disposed between the active line forming layer 204 and the buried portion 213 of the fin 211. In an embodiment, an isolation material region 214 (e.g., a silicon oxide region) is formed on either side of the buried portion 213 of the fin 211, but the protruding portion 212 is still electrically coupled to the substrate 202, as in Figure 2A However, in other embodiments, it is to be appreciated that in the case of manufacturing a bulk device, the subsequently formed permanent gate stack may be isolated from the semiconductor substrate 202 by a shallow trench isolation (STI) region formed after fin patterning. Alternatively, the subsequently formed permanent gate stack may be isolated from the semiconductor substrate 202 by a bottom gate isolation (BGI) structure (which may be fabricated during the permanent gate stack fabrication).

[0042] Reference again Figure 2AIn an embodiment, the nanowires can then be ultimately formed by first stacking the active and sacrificial materials and then etching the desired fin stack, followed by isolation material deposition, planarization, and etching. In the specific example described, the formation of two silicon nanowires is considered. It is to be appreciated that in another embodiment, two silicon germanium nanowires may ultimately be formed.

[0043] Figure 2B Image after sacrificial gate stack material deposition and gate patterning Figure 2A In a specific example showing the formation of three gate structures, Figure 2B The protruding portion 212 of the fin 211 is shown with three sacrificial gates 216A, 216B, and 216C disposed thereon. In one such embodiment, the three sacrificial gates 216A, 216B, and 216C are composed of a sacrificial gate oxide layer and a sacrificial polysilicon gate layer, which are, for example, blanket deposited and patterned using a plasma etching process. It is to be appreciated that the patterning of the three sacrificial gates 216A, 216B, and 216C exposes the source and drain regions 218 of the protruding portion 212 of the fin 211.

[0044] Figure 2C The diagram is shown after removing the portions of the first 206 and second 210 sacrificial release layers exposed in the source and drain regions 218 of the protruding portion 212 of the fin 211. Figure 2B This removal forms a space 220 between the active line forming layers 204 and 208 and between the active line forming layer 204 and the buried portion 213 of the fin 211. However, in an embodiment, portions of the first 206 and second 210 sacrificial release layers under the three sacrificial gates 216A, 216B, and 216C are retained, as shown in Figure 2C Depicted in.

[0045] In an embodiment, etching chemistries such as carboxylic acid / nitric acid / HF chemistry and citric acid / nitric acid / HF, for example, may be used to selectively etch portions of the first and second silicon germanium sacrificial release layers (selective to silicon active lines) exposed in the source and drain regions 218 of the protruding portion 212 of the fin 211. Alternatively, an isotropic dry etch may be used. In another embodiment, etching chemistries such as aqueous hydroxide chemistry (which contains ammonium hydroxide and potassium hydroxide), for example, may be used to selectively etch portions of the first and second silicon sacrificial release layers (selective to silicon germanium or germanium active lines) exposed in the source and drain regions 218 of the protruding portion 212 of the fin 211. Alternatively, an isotropic dry etch may be used. Thus, the silicon germanium layer may be removed from the silicon active region or the silicon layer may be removed from the silicon germanium active region.

[0046] Figure 2DAfter depositing the spacer forming material layer 222 Figure 2C In an embodiment, the spacer-forming material layer 222 is an insulating dielectric layer, such as but not limited to silicon dioxide, silicon oxynitride, or silicon nitride. In an embodiment, the spacer-forming material layer 222 is formed by atomic layer deposition (ALD).

[0047] Figure 2E After etching the spacer forming material layer 222 to form the cavity spacer 224 Figure 2D The cavity spacer is formed along the sidewalls of the three sacrificial gates 216A, 216B, and 216C. In an embodiment, an anisotropic plasma etching process is used to form the cavity spacer 224. In an embodiment, the etching process also removes the portions of the active line forming layers 204 and 208 exposed in the source and drain regions 218, such as in Figure 2E However, portions of the active line forming layers 204 and 208 below the cavity spacer 224 are retained. In other embodiments, the etching process recesses a portion of the buried portion 213 of the fin 211 to form a recessed portion 226, as also shown in FIG. Figure 2E In an embodiment, cavity spacer 224 is formed to a height lower than the height of three sacrificial gates 216A, 216B, and 216C, as shown in Figure 2E Depicted in.

[0048] Figure 2F The source and drain structures 228 are shown after being grown between the cavity spacers 224. Figure 2E In an embodiment, the growth of the source and drain structures 228 is performed by epitaxial deposition of semiconductor material in the source and drain regions 218. In one embodiment, the epitaxial growth is initiated on the exposed ends of the portions of the active line-forming layers 204 and 208 below the cavity spacer 224. In another embodiment, the epitaxial growth is initiated on the exposed surfaces of the recessed portions 226 of the buried portions 213 of the fins 211. In yet another embodiment, the epitaxial growth is initiated on the exposed ends of the portions of the active line-forming layers 204 and 208 below the cavity spacer 224 and on the exposed surfaces of the recessed portions 226 of the buried portions 213 of the fins 211. In an embodiment, the source and drain structures 228 are formed to a height lower than the height of the cavity spacer 224, such as in Figure 2F In an embodiment, doping of the source and drain structures 228 may be performed in situ or after epitaxial growth.

[0049] Figure 2G After forming the planarization oxide 230 and removing the three sacrificial gates 216A, 216B, and 216C Figure 2FFor example, in an embodiment, oxide is deposited and planarized before removing the three sacrificial gates 216A, 216B, and 216C. Such planarized oxide 230 covers the source and drain structures 228. The removal of the sacrificial gates 216A, 216B, and 216C is then performed without damaging adjacent structures, thereby exposing the channel region 232.

[0050] Figure 2H The diagram shows the portion of the first 206 and second 210 sacrificial release layers after removing the portions of the first 206 and second 210 sacrificial release layers exposed in the channel region 232 of the protruding portion 212 of the fin 211. Figure 2G This removal forms a space 234 between the active line-forming layers 204 and 208 and between the active line-forming layer 204 and the buried portion 213 of the fin 211 .

[0051] In an embodiment, an etching chemistry such as carboxylic acid / nitric acid / HF chemistry and citric acid / nitric acid / HF, for example, may be used to selectively etch portions of the first and second silicon germanium sacrificial release layers (selective to silicon active lines) exposed in the channel region 232 of the protruding portion 212 of the fin 211. Alternatively, an isotropic dry etch may be used. In another embodiment, an etching chemistry such as an aqueous hydroxide chemistry (which contains ammonium hydroxide and potassium hydroxide), for example, may be used to selectively etch portions of the first and second silicon sacrificial release layers (selective to silicon germanium or germanium active lines) exposed in the channel region 232 of the protruding portion 212 of the fin 211. Alternatively, an isotropic dry etch may be used. Thus, the silicon germanium layer may be removed from the silicon active region or the silicon layer may be removed from the silicon germanium active region.

[0052] The discrete portions of active wire-forming layers 204 and 208 formed in channel region 232 will eventually become channel regions in a nanowire-based device in one embodiment. Figure 2H At the process stages depicted in , channel engineering or tuning may be performed. For example, in one embodiment, Figure 2H The discrete portions of the active line-forming layers 204 and 208 shown in FIG. 1 are then thinned using oxidation and etching processes.

[0053] Fig.2I After forming a gate dielectric layer 236 on portions of the active line formation layers 204 and 208 in the channel region 232, Figure 2H In an embodiment, the gate dielectric layer 236 is a high-k gate dielectric layer. In an embodiment, the gate dielectric layer 236 is formed by atomic layer deposition (ALD). In an embodiment, the gate dielectric layer 236 is selectively formed on portions of the active line forming layers 204 and 208 in the channel region 232. However, in another embodiment, the gate dielectric layer 236 is formed on the active line forming layers 204 and 208 in the channel region 232. Figure 2H The structure is formed conformally.

[0054] Figure 2J After forming the permanent gate electrode 238 Fig.2I Each of the permanent gate electrodes 238 completely surrounds the portion of the active line-forming layers 204 and 208 in the channel region 232. The permanent gate electrodes 238 may be formed by depositing a metal (or metal-containing material) or a metal stack (or a stacked metal-containing material) in the channel region 232. It is to be appreciated that additional fabrication may involve forming conductive contacts to the source and drain structures 228 and / or to the gate electrodes 238. In an embodiment, Figure 2J The complete device exhibits reduced parasitic capacitance due to the presence of cavity spacer 224.

[0055] It is to be appreciated that different material stacks may be preferred for PMOS or NMOS fabricated on a common substrate or as part of a common circuit. In such an embodiment, the semiconductor structure includes an NMOS semiconductor device. The NMOS semiconductor device includes a plurality of vertically stacked silicon nanowires disposed above a substrate, each of the silicon nanowires including a discrete channel region, a common NMOS gate electrode stack surrounding each of the discrete channel regions of the plurality of vertically stacked silicon nanowires, a first pair of dielectric spacers on either side of the common NMOS gate electrode stack (each of the first pair of dielectric spacers includes a continuous material disposed along the sidewalls of the common NMOS gate electrode and surrounding a discrete portion of each of the vertically stacked silicon nanowires) and a pair of NMOS source and drain regions on either side of the first pair of dielectric spacers. The semiconductor structure also includes a PMOS semiconductor device. The PMOS semiconductor device includes a plurality of vertically stacked silicon germanium or germanium nanowires disposed above a substrate, each of the silicon germanium or germanium nanowires including a discrete channel region, a common PMOS gate electrode stack surrounding each of the discrete channel regions of the plurality of vertically stacked silicon germanium or germanium nanowires, a second pair of dielectric spacers on either side of the common PMOS gate electrode stack (each of the second pair of dielectric spacers includes a continuous material disposed along the sidewall of the common PMOS gate electrode and surrounding discrete portions of each of the vertically stacked silicon germanium or germanium nanowires), and a pair of PMOS source and drain regions on either side of the second pair of dielectric spacers.

[0056] However, other PMOS / NMOS arrangements can be considered. For example, in addition to or in place of the materials listed above, the NMOS channel region can be composed of germanium or III-V materials such as InAs, InGaAs (various compositions ranging from 0.5 to 1.0 In), GaAs, GaN. In addition to or in place of the materials listed above, the PMOS channel material can be based on silicon.

[0057] Figure 3A computing device 300 is illustrated in accordance with one implementation of the present invention. The computing device 300 houses a board 302. The board 302 may contain a number of components, including but not limited to a processor 304 and at least one communication chip 306. The processor 304 is physically and electrically coupled to the board 302. In some implementations, the at least one communication chip 306 is also physically and electrically coupled to the board 302. In other implementations, the communication chip 306 is part of the processor 304.

[0058] The computing device 300 may include other components, depending on its application, which may or may not be physically and electrically coupled to the board 302. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0059] The communication chip 306 implements wireless communication for the transfer of data to and from the computing device 300. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can convey data by using modulated electromagnetic radiation through a non-solid medium. The term does not mean that the associated device does not contain any wires, but in some embodiments they may not contain any wires. The communication chip 306 can implement any of many wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and later. The computing device 300 may include multiple communication chips 306. For example, the first communication chip 306A may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 306 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0060] The processor 304 of the computing device 300 may include an integrated circuit die packaged within the processor 304. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors, constructed in accordance with implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory.

[0061] The communication chip 306 also includes an integrated circuit die packaged within the communication chip 306. According to another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FETs, constructed according to implementations of the invention.

[0062] In further implementations, another component housed within computing device 300 may include an integrated circuit die that includes one or more devices, such as MOS-FET transistors, constructed in accordance with implementations of the present invention.

[0063] In various implementations, computing device 300 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In other implementations, computing device 300 may be any other electronic device that processes data.

[0064] Figure 4 An interposer 400 is shown, which includes one or more embodiments of the present invention. Interposer 400 is an intervening substrate used to bridge a first substrate 402 to a second substrate 404. The first substrate 402 can be, for example, an integrated circuit die. The second substrate 404 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of interposer 400 is to extend the connection to a wider spacing or to reroute the connection to a different connection. For example, interposer 400 can couple an integrated circuit die to a ball grid array (BGA) 406, which can then be coupled to a second substrate 404. In some embodiments, the first and second substrates 402 / 404 are attached to opposite sides of interposer 400. In other embodiments, the first and second substrates 402 / 404 are attached to the same side of interposer 400. And in other embodiments, three or more substrates are interconnected through interposer 400.

[0065] Interposer 400 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In other implementations, the interposer may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0066] The interposer may include metal interconnects 408 and vias 410, including but not limited to through silicon vias (TSVs) 412. The interposer 400 may further include embedded devices 414, including passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 400. According to embodiments of the present invention, the apparatus or process disclosed herein may be used in the manufacture of the interposer 400.

[0067] Thus, embodiments of the present invention include semiconductor nanowire devices having cavity spacers and methods of making cavity spacers for semiconductor nanowire devices.

[0068] In an embodiment, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires including a discrete channel region. A common gate electrode stack surrounds each of the discrete channel regions of the plurality of vertically stacked nanowires. A pair of dielectric spacers are on either side of the common gate electrode stack, each of the pair of dielectric spacers including a continuous material disposed along a sidewall of the common gate electrode and surrounding a discrete portion of each of the vertically stacked nanowires. A pair of source and drain regions are on either side of the pair of dielectric spacers.

[0069] In one embodiment, an uppermost surface of the pair of dielectric spacers is below an uppermost surface of the common gate electrode stack.

[0070] In one embodiment, the pair of source and drain regions have uppermost surfaces below uppermost surfaces of the pair of dielectric spacers.

[0071] In one embodiment, the pair of source and drain regions is a pair of common source and drain regions coupled to a plurality of vertically stacked nanowires.

[0072] In one embodiment, the substrate is a single crystalline semiconductor substrate, and the pair of common source and drain regions are a pair of epitaxial semiconductor regions further coupled to exposed portions of the single crystalline semiconductor substrate.

[0073] In one embodiment, the semiconductor device further includes a pair of conductive contacts disposed on the pair of common source and drain regions.

[0074] In one embodiment, the common gate electrode stack includes a high-k gate dielectric layer disposed over and surrounding each of the discrete channel regions of the plurality of vertically stacked nanowires.

[0075] In one embodiment, the common gate electrode stack further includes a metal gate disposed on the high-k gate electrode dielectric layer.

[0076] In one embodiment, the substrate is a polycrystalline silicon substrate and the plurality of vertically stacked nanowires is a plurality of vertically stacked single crystal silicon nanowires.

[0077] In one embodiment, the substrate is a polycrystalline silicon substrate and the plurality of vertically stacked nanowires are a plurality of vertically stacked single crystal silicon germanium or single crystal germanium nanowires.

[0078] In an embodiment, a semiconductor structure includes an NMOS semiconductor device. The NMOS semiconductor device includes a plurality of vertically stacked silicon nanowires disposed above a substrate, each of the silicon nanowires including a discrete channel region, a common NMOS gate electrode stack surrounding each of the discrete channel regions of the plurality of vertically stacked silicon nanowires, a first pair of dielectric spacers on either side of the common NMOS gate electrode stack (each of the first pair of dielectric spacers includes a continuous material disposed along the sidewall of the common NMOS gate electrode and surrounding a discrete portion of each of the vertically stacked silicon nanowires), and a pair of NMOS source and drain regions on either side of the first pair of dielectric spacers. The semiconductor structure also includes a PMOS semiconductor device. The PMOS semiconductor device includes a plurality of vertically stacked silicon germanium or germanium nanowires disposed above a substrate, each of the silicon germanium or germanium nanowires including a discrete channel region, a common PMOS gate electrode stack surrounding each of the discrete channel regions of the plurality of vertically stacked silicon germanium or germanium nanowires, a second pair of dielectric spacers on either side of the common PMOS gate electrode stack (each of the second pair of dielectric spacers includes a continuous material disposed along a sidewall of the common PMOS gate electrode and surrounding discrete portions of each of the vertically stacked silicon germanium or germanium nanowires), and a pair of PMOS source and drain regions on either side of the second pair of dielectric spacers.

[0079] In one embodiment, an uppermost surface of the first pair of dielectric spacers is below an uppermost surface of the common NMOS gate electrode stack, and an uppermost surface of the second pair of dielectric spacers is below an uppermost surface of the common PMOS gate electrode stack.

[0080] In one embodiment, the pair of NMOS source and drain regions have uppermost surfaces below uppermost surfaces of a first pair of dielectric spacers, and the pair of NMOS source and drain regions have uppermost surfaces below uppermost surfaces of a second pair of dielectric spacers.

[0081] In one embodiment, the pair of NMOS source and drain regions is a pair of common source and drain regions coupled to a plurality of vertically stacked silicon nanowires, and the pair of PMOS source and drain regions is a pair of common source and drain regions coupled to a plurality of vertically stacked silicon germanium or germanium nanowires.

[0082] In one embodiment, the substrate is a single crystal semiconductor substrate, and the pair of common NMOS source and drain regions are a pair of epitaxial semiconductor regions further coupled to the exposed portion of the single crystal semiconductor substrate, and the pair of common PMOS source and drain regions are a pair of epitaxial semiconductor regions further coupled to the exposed portion of the single crystal semiconductor substrate.

[0083] In one embodiment, the semiconductor substrate further includes a first pair of conductive contacts disposed on the pair of common NMOS source and drain regions, and a second pair of conductive contacts disposed on the pair of common PMOS source and drain regions.

[0084] In one embodiment, a common NMOS gate electrode stack includes a first high-k gate dielectric layer disposed on and surrounding each of the discrete channel regions of a plurality of vertically stacked silicon nanowires, and a common PMOS gate electrode stack includes a second high-k gate dielectric layer disposed on and surrounding each of the discrete channel regions of a plurality of vertically stacked silicon germanium or germanium nanowires.

[0085] In one embodiment, the common NMOS gate electrode stack further includes a first metal gate disposed on the first high-k gate dielectric layer, and the common PMOS gate electrode stack further includes a second metal gate disposed on the second high-k gate dielectric layer.

[0086] In an embodiment, a method for manufacturing a semiconductor device includes forming a fin structure above a substrate, the fin structure including alternating active layers and sacrificial layers. The method also includes forming a sacrificial gate stack on the fin structure, thereby exposing the source and drain regions of the fin structure. The method also includes removing a portion of the sacrificial layer of the fin structure in the source and drain regions. The method also includes, subsequent to removing a portion of the sacrificial layer of the fin structure in the source and drain regions, forming a conformal dielectric material layer in the source and drain regions and above the sacrificial gate stack. The method also includes etching the conformal dielectric material layer to form a pair of dielectric spacers on either side of the common gate electrode stack, each of the pair of dielectric spacers including a continuous material disposed along the sidewalls of the sacrificial gate stack and surrounding a discrete portion of each of the active layers in the source and drain regions. The method also includes, subsequent to etching the conformal dielectric material layer to form the pair of dielectric spacers, forming source and drain structures in the source and drain regions. The method also includes removing the sacrificial gate stack to expose the channel region of the fin structure after forming the source and drain structures. The method also includes removing a portion of the sacrificial layer of the fin structure in the channel region.The method also includes forming a permanent gate electrode stack between the pair of dielectric spacers and around discrete portions of each of the active layers in the channel region.

[0087] In one embodiment, forming the conformal dielectric material layer includes depositing the conformal dielectric material layer by atomic layer deposition (ALD).

[0088] In one embodiment, removing portions of the sacrificial layer of the fin structure in the source and drain regions and removing portions of the sacrificial layer of the fin structure in the channel region includes removing the sacrificial silicon germanium using a wet etching process employing a composition selected from the group consisting of: an aqueous carboxylic acid / nitric acid / HF solution and an aqueous citric acid / nitric acid / HF solution.

[0089] In one embodiment, removing portions of the sacrificial layer of the fin structure in the source and drain regions and removing portions of the sacrificial layer of the fin structure in the channel region includes removing sacrificial silicon using an aqueous hydroxide chemistry selected from the group consisting of: aqueous ammonium hydroxide and aqueous potassium hydroxide.

[0090] In one embodiment, forming source and drain structures in the source and drain regions includes epitaxially growing semiconductor material in the source and drain regions.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a fin structure over a substrate, the fin structure comprising alternating active layers and sacrificial layers; forming a sacrificial gate stack on the fin structure, thereby exposing source and drain regions of the fin structure; removing portions of the sacrificial layer of the fin structure in the source and drain regions; subsequent to removing portions of the sacrificial layer of the fin structure in the source and drain regions, forming a conformal dielectric material layer in the source and drain regions and over the sacrificial gate stack; etching the conformal dielectric material layer to form a pair of dielectric spacers on both sides of a common gate electrode stack, each of the pair of dielectric spacers comprising a continuous material disposed along a sidewall of the sacrificial gate stack and surrounding discrete portions of each of the active layers in the source and drain regions; forming source and drain structures in the source and drain regions subsequent to etching the conformal dielectric material layer to form the pair of dielectric spacers; After forming the source and drain structures, removing the sacrificial gate stack to expose the channel region of the fin structure; removing a portion of the sacrificial layer of the fin structure in the channel region; as well as A permanent gate electrode stack is formed between the pair of dielectric spacers and around discrete portions of each of the active layers in the channel region. 2 . The method of claim 1 , wherein forming the conformal dielectric material layer comprises depositing the conformal dielectric material layer by atomic layer deposition (ALD).

3. The method of claim 1 , wherein removing portions of the sacrificial layer of the fin structure in the source and drain regions and removing portions of the sacrificial layer of the fin structure in the channel region comprises removing sacrificial silicon germanium using a wet etching process employing a composition selected from the group consisting of: an aqueous carboxylic acid / nitric acid / HF solution and an aqueous citric acid / nitric acid / HF solution.

4. The method of claim 1 , wherein removing portions of the sacrificial layer of the fin structure in the source and drain regions and removing portions of the sacrificial layer of the fin structure in the channel region comprises removing sacrificial silicon using an aqueous hydroxide chemistry selected from the group consisting of: aqueous ammonium hydroxide and aqueous potassium hydroxide. 5 . The method of claim 1 , wherein forming source and drain structures in the source and drain regions comprises epitaxially growing semiconductor material in the source and drain regions.

6. A method for manufacturing a semiconductor device, comprising: forming a plurality of vertically stacked nanowires over a substrate, each of the nanowires comprising a discrete channel region; forming a common gate electrode stack surrounding each of the discrete channel regions of the plurality of vertically stacked nanowires; forming a pair of dielectric spacers on both sides of the common gate electrode stack, each of the pair of dielectric spacers comprising a continuous material along a sidewall of the common gate electrode and surrounding a discrete portion of each of the vertically stacked nanowires, the continuous material between adjacent ones of the vertically stacked nanowires, wherein uppermost surfaces of the pair of dielectric spacers are below an uppermost surface of the common gate electrode stack; as well as A pair of source and drain regions are formed on both sides of the pair of dielectric spacers.

7. The method of claim 6, wherein the pair of source and drain regions have uppermost surfaces below the uppermost surfaces of the pair of dielectric spacers.

8. The method of claim 6, wherein the pair of source and drain regions are a pair of common source and drain regions coupled to the plurality of vertically stacked nanowires.

9. The method of claim 8, wherein the substrate is a single crystalline semiconductor substrate, and the pair of common source and drain regions are a pair of epitaxial semiconductor regions further coupled to exposed portions of the single crystalline semiconductor substrate.

10. The method of claim 8, further comprising: A pair of conductive contacts are formed on the pair of common source and drain regions.

11. The method of claim 6, wherein the common gate electrode stack comprises a high-k gate dielectric layer on and surrounding each of the discrete channel regions of the plurality of vertically stacked nanowires. 12 . The method of claim 11 , wherein the common gate electrode stack further comprises a metal gate on the high-k gate dielectric layer.

13. The method of claim 6, wherein the substrate is a polycrystalline silicon substrate, and the plurality of vertically stacked nanowires are a plurality of vertically stacked single crystalline silicon nanowires.

14. The method of claim 6, wherein the substrate is a polycrystalline silicon substrate, and the plurality of vertically stacked nanowires are a plurality of vertically stacked single crystal silicon germanium or single crystal germanium nanowires.

15. A method for manufacturing a semiconductor device, comprising: Forming an NMOS semiconductor device, the forming comprising: forming a plurality of vertically stacked silicon nanowires over a substrate, each of the silicon nanowires comprising a discrete channel region; forming a common NMOS gate electrode stack surrounding each of the discrete channel regions of the plurality of vertically stacked silicon nanowires; forming a first pair of dielectric spacers on both sides of the common NMOS gate electrode stack, each of the first pair of dielectric spacers comprising a continuous material along a sidewall of the common NMOS gate electrode and surrounding a discrete portion of each of the vertically stacked silicon nanowires, the continuous material being between adjacent ones of the vertically stacked silicon nanowires, wherein uppermost surfaces of the first pair of dielectric spacers are below an uppermost surface of the common NMOS gate electrode stack; and forming a pair of NMOS source and drain regions on both sides of the first pair of dielectric spacers; and Forming a PMOS semiconductor device, the forming comprising: forming a plurality of vertically stacked silicon germanium or germanium nanowires over a substrate, each of the silicon germanium or germanium nanowires comprising a discrete channel region; forming a common PMOS gate electrode stack surrounding each of the discrete channel regions of the plurality of vertically stacked silicon germanium or germanium nanowires; forming a second pair of dielectric spacers on both sides of the common PMOS gate electrode stack, each of the second pair of dielectric spacers comprising a continuous material along a sidewall of the common PMOS gate electrode and surrounding a discrete portion of each of the vertically stacked silicon germanium or germanium nanowires, the continuous material between adjacent ones of the vertically stacked silicon germanium or germanium nanowires, wherein an uppermost surface of the second pair of dielectric spacers is below an uppermost surface of the common PMOS gate electrode stack; and A pair of PMOS source and drain regions are formed on both sides of the second pair of dielectric spacers.

16. The method of claim 15, wherein the pair of NMOS source and drain regions have uppermost surfaces below the uppermost surfaces of the first pair of dielectric spacers, and the pair of NMOS source and drain regions have uppermost surfaces below the uppermost surfaces of the second pair of dielectric spacers.

17. The method of claim 15, wherein the pair of NMOS source and drain regions are a pair of common source and drain regions coupled to the plurality of vertically stacked silicon nanowires, and the pair of PMOS source and drain regions are a pair of common source and drain regions coupled to the plurality of vertically stacked silicon germanium or germanium nanowires.

18. The method of claim 17, wherein the substrate is a single crystal semiconductor substrate, and the pair of common NMOS source and drain regions are a pair of epitaxial semiconductor regions further coupled to an exposed portion of the single crystal semiconductor substrate, and the pair of common PMOS source and drain regions are a pair of epitaxial semiconductor regions further coupled to an exposed portion of the single crystal semiconductor substrate.

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