Power semiconductor devices

Abstract

The present invention provides a power semiconductor device and a manufacturing method thereof, the power semiconductor device comprising: a first submodule having a first power semiconductor element; a second submodule having a second power semiconductor element; a positive side conductor portion and a negative side conductor portion; an intermediate substrate forming a negative side opposite portion sandwiching the first submodule and opposite to the negative side conductor portion, and a positive side opposite portion sandwiching the second submodule and opposite to the positive side conductor portion; a plurality of signal terminals of the first power semiconductor element or the second power semiconductor element are controlled by transmitting signals, the second submodule is configured in such a way that the electrode surface of the second power semiconductor element is reversed in direction to the electrode surface of the first power semiconductor element, a signal relay conductor portion is configured in a space sandwiched between a part of the second submodule and the intermediate substrate in the height direction of the second submodule, and the intermediate substrate has wiring connected to the signal relay conductor portion and electrically connected to the signal terminal. Thus, while suppressing the increase of the main circuit inductance, the productivity of the power semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to a power semiconductor device, and in particular to a power semiconductor device for controlling a vehicle-mounted drive motor. Background Art

[0002] In recent years, high output density has been required for power conversion devices used in vehicles. To achieve high output density, it is necessary to reduce losses and heat generation. One way to reduce losses is to reduce switching losses by increasing the switching speed, but as the switching speed increases, the surge voltage increases.

[0003] Therefore, it is necessary to reduce the parasitic inductance of the main circuit that causes the surge voltage. Patent document 1 discloses a structure in which a power semiconductor element is cooled from both sides in order to improve heat dissipation. Patent document 2 discloses a structure in which a power semiconductor element of one of the upper and lower arms is reversed in order to reduce inductance and improve cooling performance.

[0004] However, when the structure of inverting a single-arm power semiconductor element as in Patent Document 2 is applied to the double-sided cooling structure of Patent Document 1, it is necessary to further improve the productivity of the power semiconductor device including the upper and lower arms.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Laid-Open No. 2014-23327 Patent Document 2: Japanese Patent Laid-Open No. 2017-183430 Summary of the invention

[0008] Technical problem to be solved by the invention

[0009] The technical problem of the present invention is to improve the productivity of power semiconductor devices while suppressing the increase of main circuit inductance.

[0010] Technical solutions adopted to solve technical problems

[0011] The power semiconductor device involved in the present invention includes: a first submodule having a first power semiconductor element; a second submodule having a second power semiconductor element; a positive side conductor portion and a negative side conductor portion; an intermediate substrate forming a negative side opposite portion that sandwiches the first submodule and is opposite to the negative side conductor portion, and a positive side opposite portion that sandwiches the second submodule and is opposite to the positive side conductor portion; and a plurality of signal terminals for transmitting signals for controlling the first power semiconductor element or the second power semiconductor element, the second submodule being arranged in such a manner that the electrode surface of the second power semiconductor element is oriented in the opposite direction to the electrode surface of the first power semiconductor element, a signal relay conductor portion being arranged in a space sandwiched in the height direction of the second submodule and between a portion of the second submodule and the intermediate substrate, and the intermediate substrate having wiring connected to the signal relay conductor portion and electrically connected to the signal terminal.

[0012] Effects of the Invention

[0013] According to the present invention, it is possible to improve the productivity of power semiconductor devices while suppressing an increase in main circuit inductance. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a front view of the appearance of a power semiconductor device 100 according to the present embodiment.

[0015] Figure 2 is from Figure 1 The internal structure of the power semiconductor device 100 shown is a diagram in which the molding material 206 , the cooling metal portion 207 , the insulating layer 306 , the soldering pattern 307 , and the soldering material 602 are removed.

[0016] Figure 3 is from Figure 2 The power semiconductor device 100 shown is an internal structure diagram in which the high potential side wiring 301 and the low potential side wiring 302 are removed.

[0017] Figure 4 is from Figure 3 The internal structure of the power semiconductor device 100 is shown with the first submodule 401 and the second submodule 402 removed.

[0018] Figure 5 It is a front view of the appearance of the submodule 400 involved in this embodiment.

[0019] Figure 6 is from Figure 5 The submodule 400 shown is an internal structure diagram after the low-potential side conductor part 403 in the submodule is removed.

[0020] Figure 7 Observe from the direction of the arrow Figure 5A cross-sectional view of a submodule 400 is shown in section through the dash-dotted line DD′.

[0021] Figure 8 Observe from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a section taken along the dashed line AA′.

[0022] Fig. 9 Observe from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a section passing through the dashed line BB′.

[0023] Fig.10 Observe from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a cross section passing through a dashed line CC′.

[0024] Fig.11 Implementation Example 2 is viewed from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a section taken along the dashed line AA′.

[0025] Fig.12 Implementation Example 2 is viewed from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a section passing through the dashed line BB′.

[0026] Fig.13 Implementation Example 3 is viewed from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a section taken along the dashed line AA′.

[0027] Fig.14 Implementation Example 3 is viewed from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a section passing through the dashed line BB′.

[0028] Fig.15 Implementation Example 4 is observed from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a section taken along the dashed line AA′.

[0029] FIG. 16( a - 1 ) is a cross-sectional view of a first submodule and a second submodule, showing a manufacturing process of a power semiconductor device according to the second embodiment.

[0030] FIG. 16( a - 2 ) is a plan view of a first submodule and a second submodule, illustrating a manufacturing process of a power semiconductor device according to the second embodiment.

[0031] 16( b - 1 ) is a cross-sectional view showing a manufacturing process of the power semiconductor device according to the second embodiment, in which a first submodule and a second submodule are mounted on an AC output-side substrate 801 and a DC input-side substrate 802 .

[0032] 16( b - 2 ) is a plan view showing a manufacturing process of the power semiconductor device according to the second embodiment, in which the first submodule and the second submodule are mounted on the AC output-side substrate 801 and the DC input-side substrate 802 .

[0033] FIG16(c-1) is a cross-sectional view showing a manufacturing process of the power semiconductor device according to the second embodiment, in which a wire bond 601 is connected to the structure shown in FIG16(b-1).

[0034] FIG16(c-2) is a plan view showing a manufacturing process of the power semiconductor device according to the second embodiment, in which a wire bond 601 is connected to the structure shown in FIG16(b-2).

[0035] FIG16(d-1) is a cross-sectional view showing a manufacturing process of the power semiconductor device according to the second embodiment, in which a cooling metal portion 207 is attached to the structure shown in FIG16(c-1).

[0036] FIG16(d-2) is a plan view showing a manufacturing process of the power semiconductor device according to the second embodiment, in which the cooling metal portion 207 is attached to FIG16(c-2).

[0037] FIG16(e-1) is a cross-sectional view showing a manufacturing process of the power semiconductor device according to the second embodiment, and is a view showing a state after the structure shown in FIG16(d-1) is sealed with resin.

[0038] FIG16(e-2) is a plan view showing a manufacturing process of the power semiconductor device according to the second embodiment, and is a view showing a state after the structure shown in FIG16(d-2) is sealed with resin. DETAILED DESCRIPTION

[0039] The following is an explanation of the implementation of the power semiconductor device involved in the present invention with reference to the accompanying drawings. In addition, the same elements in each figure will be recorded with the same symbols, and repeated descriptions will be omitted. The present invention is not limited to the following implementations, and its scope also includes various modifications and application examples in the technical concept of the present invention.

[0040] [Implementation method 1]

[0041] Reference Figures 1 to 10 A power semiconductor device 100 according to the first embodiment will be described.

[0042] Figure 1FIG. 1 is a front view of the appearance of the power semiconductor device 100 according to the first embodiment. Figure 1 As shown, the power semiconductor device 100 includes: a high potential side terminal 201; a low potential side terminal 202; an AC output terminal 203; positive electrode sensing terminals 204U and 204L; negative electrode sensing terminals 205U and 205L and a cooling metal portion 207. Each part is resin-sealed by a molding material 206. Thus, insulation between the components is ensured.

[0043] The high potential side terminal 201, the low potential side terminal 202, the AC output terminal 203, the positive electrode sensing terminal 204, and the negative electrode sensing terminal 205 protrude from the molding material 206 and are connected to external devices respectively. The surface of the cooling metal part 207 has fins. This can improve the cooling performance.

[0044] Next, refer to Figure 3 , Figures 8 to 10 The stacked structure of the power semiconductor device 100 will be described.

[0045] Figure 3 is from Figure 2 The power semiconductor device 100 shown is an internal structure diagram in which the high potential side wiring 301 and the low potential side wiring 302 are removed. Figure 8 Observe from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a section taken along the dashed line AA′. Fig. 9 Observe from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a section passing through the dashed line BB′. Fig.10 Observe from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a section taken along a dashed line CC′.

[0046] like Figure 8 , Fig. 9 and Fig.10 As shown in the figure, when viewed from the cross-sectional direction, a high potential side wiring 301 and a low potential side wiring 302 are formed on the surface of the upper insulating layer 306. In addition, a welding pattern 307 for thermally connecting the cooling metal portion 207 is formed on the surface on the opposite side. The welding pattern 307 is thermally connected to the cooling metal portion 207 via the welding material 602.

[0047] like Figure 3 and Figure 8 As shown, from the cross-sectional direction, an AC output wiring 303 and a positive electrode sensing wiring 304U (see Figure 3 )、Negative electrode sensing wiring 305U (refer to Figure 3)、High potential side terminal bonding pattern 308 (refer to Figure 3 )、low potential side terminal bonding pattern 309 (refer to Figure 3 On the other surface, a welding pattern 307 for thermally connecting the cooling metal portion 207 is formed. The welding pattern 307 is thermally connected to the cooling metal portion 207 via the welding material 602.

[0048] Figure 2 is from Figure 1 The internal structure of the power semiconductor device 100 shown is a diagram in which the molding material 206 , the cooling metal portion 207 , the insulating layer 306 , the soldering pattern 307 , and the soldering material 602 are removed.

[0049] like Figure 2 and Figure 3 As shown, the low potential side terminal 202 is electrically connected to the low potential side terminal bonding pattern 309 and the low potential side wiring 302 via the welding material 602. In addition, the low potential side terminal 202 is electrically connected to the low potential side of a capacitor (not shown) for smoothing the DC voltage from the battery by screw fastening, laser welding, etc.

[0050] Here, reference Figure 5 , Figure 6 and Figure 7 , the structure of submodule 400 is described.

[0051] Figure 5 It is a front view of the appearance of the submodule 400 involved in this embodiment. Figure 6 is from Figure 5 The submodule 400 shown is an internal structure diagram after the low-potential side conductor part 403 in the submodule is removed. Figure 7 Observe from the direction of the arrow Figure 5 A cross-sectional view of a submodule 400 is shown in section through the dash-dotted line DD′.

[0052] For example, MOSFET or IGBT may be used as the power semiconductor element 500. The power semiconductor device 100 includes a first power semiconductor element 505 constituting an upper arm of an inverter circuit and a second power semiconductor element 506 constituting a lower arm of the inverter circuit. Figures 5 to 7 A submodule 400 constituting the upper arm is shown.

[0053] like Figure 6As shown, the first power semiconductor element 505 includes: a positive sensing electrode 503, a negative sensing electrode 504, a low potential side electrode 501, and a high potential side electrode 502 (the back side of the power semiconductor element 500). In the case of IGBT, among these electrodes, the positive sensing electrode 503 is equivalent to the gate, the negative sensing electrode 504 is equivalent to the Kelvin emitter, the low potential side electrode 501 is equivalent to the emitter, and the high potential side electrode 502 is equivalent to the collector. In addition, in the case of MOSFET, the positive sensing electrode 503 is equivalent to the gate, the negative sensing electrode 504 is equivalent to the Kelvin source, the low potential side electrode 501 is equivalent to the source, and the high potential side electrode 502 is equivalent to the drain.

[0054] In addition, depending on the type of power semiconductor element, there is also a power semiconductor element that does not include the negative electrode sensing electrode 504 and uses the low potential side electrode 501 as the negative electrode sensing electrode. Such a semiconductor element can also be used in this embodiment.

[0055] like Figure 7 As shown, the sub-module high potential side conductor part 404 includes: an intra-sub-module insulating layer 407 , an intra-sub-module positive electrode sensing wiring 405 , and an intra-sub-module negative electrode sensing wiring 406 .

[0056] The submodule insulator layer 407 is formed on the surface of the high potential side conductor 404 in an area where the first power semiconductor element 505 is not mounted. The submodule insulator layer 407 insulates the high potential side conductor 404 from the submodule positive electrode sensing wire 405 and the submodule negative electrode sensing wire 406 .

[0057] The sub-module positive electrode sensing wiring 405 and the sub-module negative electrode sensing wiring 406 are formed on the surface of the sub-module insulation layer 407 , and transmit electrical signals to the power semiconductor element 500 , respectively.

[0058] In the present embodiment, the in-submodule insulating layer 407 is formed in a T-shape, but it is not necessarily required to be in a T-shape, and various shapes may be conceivable depending on the arrangement of the first power semiconductor element 505 .

[0059] The high potential side conductor portion 404 in the submodule is connected to the high potential side electrode 502 via the solder material 602 .

[0060] The low potential side electrode 501 is electrically connected to the intra-submodule low potential side electrode 403 via the solder material 602. The positive electrode sensing electrode 503 is electrically connected to the intra-submodule positive electrode sensing wiring 405 via the wire bonding 601. The negative electrode sensing electrode 504 is electrically connected to the intra-submodule negative electrode sensing wiring 406 via the wire bonding 601.

[0061] like Fig. 9 and Fig.10As shown, the intra-submodule low potential side conductor portion 403L of the first submodule 401 is electrically connected to the low potential side wiring 302 via the solder material 602. The intra-submodule high potential side conductor portion 404L of the first submodule 401 is electrically connected to the AC output wiring 303 via the solder material 602.

[0062] Figure 3 is from Figure 2 The power semiconductor device 100 shown is an internal structure diagram in which the high potential side wiring 301 and the low potential side wiring 302 are removed. Figure 4 is from Figure 3 The internal structure diagram of the power semiconductor device 100 is shown with the first submodule 401 and the second submodule 402 removed.

[0063] like Figure 3 As shown, the AC output terminal 203 is electrically connected to the AC output wiring 303 via the welding material 602. In addition, the AC output terminal 203 is electrically connected to a bus bar (not shown) connected to the motor by screw fastening, laser welding, etc.

[0064] The positive electrode sensing terminal 204L is electrically connected to the positive electrode sensing wiring 405L in the submodule via the wire bonding 601. The negative electrode sensing terminal 205L is electrically connected to the negative electrode sensing wiring 406L in the submodule via the wire bonding 601. The positive electrode sensing terminal 204L and the negative electrode sensing terminal 205L are electrically connected to the control substrate (not shown) and have the function of transmitting a control signal to the power semiconductor element 500.

[0065] like Figure 3 and Figure 8 As shown, the positive electrode sensing terminal 204U is electrically connected to the positive electrode sensing wiring 304U via the wire bonding 601. The negative electrode sensing wiring 304U is electrically connected to the signal relay conductor 701 via the solder material 602. The negative electrode sensing terminal 205U is electrically connected to the negative electrode sensing wiring 305U via the wire bonding 601.

[0066] like Figure 8 As shown, the negative electrode sensing wiring 305U is electrically connected to the signal relay conductor 701 via the welding material 602. The signal relay conductor 701 is electrically connected to the negative electrode sensing wiring 406U in the submodule via the welding material 602. The positive electrode sensing terminal 204U and the negative electrode sensing terminal 205U are electrically connected to the control substrate (not shown) and have the function of transmitting the control signal to the power semiconductor element 500.

[0067] like Figure 8As shown, the submodule low potential side conductor portion 403U of the second submodule 402 is electrically connected to the AC output wiring 303 via the solder material 602. The submodule high potential side conductor portion 404U of the second submodule 402 is electrically connected to the high potential side wiring 301 via the solder material 602.

[0068] In this way, the second submodule 402 is electrically connected to the AC output wiring 303 via the solder material 602 in a reverse direction to the first submodule 401. By reversely connecting the second submodule 402, the current path inside the power semiconductor device becomes shorter, and the effect of reducing inductance can be expected.

[0069] Here, in the molding process, since the power semiconductor device 100 is sandwiched by a metal mold, if the heights of the terminals are not aligned, problems such as resin leakage and positional deviation may occur, which may cause problems in manufacturing.

[0070] Furthermore, when the relay terminal 701 is not used, the power semiconductor device 100 needs to be reversed to perform wire bonding, which may reduce productivity.

[0071] To this end, by setting the signal relay conductor 701, the high potential side terminal 201, the low potential side terminal 202, the AC output terminal 203, the positive electrode sensing terminal 204 and the negative electrode sensing terminal 205 can be set to the same height and thickness when viewed from the A-A' cross-sectional direction, thereby ensuring productivity during the molding process.

[0072] like Figure 8 As shown, the negative electrode sensing terminal 305U is electrically connected to the signal relay conductor 701 via the solder material 602. The signal relay conductor 701 is electrically connected to the negative electrode sensing wiring 406U in the submodule via the solder material 602. Thus, the height of the wire bonding can be unified based on the negative electrode sensing wiring 305U, which can suppress the reduction of productivity.

[0073] The positive sensing wiring 304U is similarly connected to the intra-submodule positive sensing wiring 405 via the signal relay conductor 701. Thus, the positive sensing terminal 204U, the negative sensing terminal 205U, the high potential terminal 201, and the low potential terminal 202 can all have the same terminal height.

[0074] Therefore, according to the present embodiment, the heights of the terminals can be made uniform, thereby ensuring productivity during the molding process.

[0075] [Implementation method 2]

[0076] Reference Fig.11 and Fig.12 Embodiment 2 of the present invention will be described.

[0077] Fig.11 1 is a cross-sectional view of a cross section passing through a dashed line AA′ of the power semiconductor device 100 according to the second embodiment, as viewed from the direction of arrows. Fig.12 Implementation Example 2 is viewed from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a section passing through the dashed line BB′.

[0078] In this embodiment, if Fig.11 and Fig.12 As shown, the upper portion of the wire bond 601 has a non-laminated portion 702 when viewed from a direction perpendicular to the electrode surface of the power semiconductor element 500. Thus, the wire bond 601 can be easily bonded even after welding components other than the molding material 206. Therefore, productivity can be ensured.

[0079] FIG. 16 shows a manufacturing process of the power semiconductor device 100 according to the present embodiment.

[0080] FIG16(a-1) shows the manufacturing process and is a cross-sectional view of the first submodule 401 and the second submodule 402. FIG16(a-2) shows the manufacturing process and is a top view of the first submodule 401 and the second submodule 402. FIG16(b-1) shows the manufacturing process and is a cross-sectional view of the first submodule 401 and the second submodule 402 mounted on the AC output side substrate 801 and the DC input side substrate 802.

[0081] FIG16(b-2) shows the manufacturing process and is a top view of the first submodule 401 and the second submodule 402 mounted on the AC output side substrate 801 and the DC input side substrate 802. FIG16(c-1) shows the manufacturing process and is a cross-sectional view of the structure of FIG16(b-1) connected with the wire bonding 601. FIG16(c-2) shows the manufacturing process and is a top view of the structure of FIG16(b-2) connected with the wire bonding 601.

[0082] Since the DC input side substrate 802 is smaller than the AC output side substrate 801 , the wire bonding 601 can be connected even when the non-laminated portion 702 is present and submodules are mounted on both the DC input side substrate 802 and the AC output side substrate 801 .

[0083] Fig. 16(d-1) shows the manufacturing process and is a cross-sectional view of the structure of Fig. 16(c-1) with the cooling metal part 207 installed. Fig. 16(d-2) shows the manufacturing process and is a top view of the structure of Fig. 16(c-2) with the cooling metal part 207 installed.

[0084] Fig. 16 (e-1) shows the manufacturing process and is a cross-sectional view of the structure of Fig. 16 (d-1) sealed with resin. Fig. 16 (e-2) shows the manufacturing process and is a top view of the structure of Fig. 16 (d-2) sealed with resin.

[0085] The above manufacturing process can shorten the process compared to a general manufacturing process in which the DC input side substrate 802 and the AC output side substrate 801 are mounted on one side, and can also suppress scratches on the substrates that may occur when the substrates are mounted on one side.

[0086] [Implementation method 3]

[0087] Reference Fig.13 and Fig.14 Embodiment 3 of the present invention will be described.

[0088] Fig.13 Implementation Example 3 is viewed from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a section taken along the dashed line AA′. Fig.14 Implementation Example 3 is viewed from the direction of the arrow Figure 1 The power semiconductor device 100 shown is a cross-sectional view of a section passing through the dashed line BB′.

[0089] In this embodiment, the signal relay conductor 703 is hook-shaped. This allows the upper and lower arms to have the same shape and shortens the wire bonding process.

[0090] like Fig.13 and Fig.14 As shown, the negative electrode sensing terminal 205U is electrically connected to the negative electrode sensing wiring 305U via the soldering material 602. The negative electrode sensing wiring 305U is electrically connected to the hook-shaped signal relay conductor 703 via the soldering material 602. The signal relay conductor 703 is electrically connected to the negative electrode sensing wiring 406U and the fixing wiring 704 in the submodule via the soldering material 602.

[0091] The positive electrode sensing terminal 205U is electrically connected to the positive electrode sensing wiring 305U via the solder material 602. The positive electrode sensing wiring 305U is electrically connected to the signal relay conductor 703 via the solder material 602. The hook-shaped signal relay conductor 703 is electrically connected to the negative electrode sensing wiring 406U and the fixing wiring 704 in the submodule via the solder material 602.

[0092] Although not shown, the negative electrode sensing terminal 205L is also electrically connected to the negative electrode sensing wiring 305L via the soldering material 602. The negative electrode sensing wiring 305L is electrically connected to the signal relay conductor 703 via the soldering material 602. The signal relay conductor 703 is electrically connected to the intra-submodule negative electrode sensing wiring 406L and the fixing wiring 704 via the soldering material 602.

[0093] like Fig.14 As shown, the positive electrode sensing terminal 204L is electrically connected to the positive electrode sensing wiring 304L via the welding material 602. The positive electrode sensing wiring 304L is electrically connected to the hook-shaped signal relay conductor 703 via the welding material 602. The hook-shaped signal relay conductor 703 is electrically connected to the intra-submodule positive electrode sensing wiring 406L and the fixing wiring 704 via the welding material 602.

[0094] By using the signal relay conductor 703, the heights of the positive electrode sensing terminal 204U, the negative electrode sensing terminal 205U, the high potential side terminal 201, and the low potential side terminal 202 can all be made uniform. The heights of the positive electrode sensing terminal 204L, the negative electrode sensing terminal 205L, and the AC output terminal 203 can all be made uniform. By using the signal relay conductor 703, the shapes of the upper and lower arms are made the same, and the wire bonding process can be shortened. Therefore, productivity is improved.

[0095] [Implementation method 4] Fig.15 Implementation Example 4 is observed from the direction of the arrow Figure 1 The cross-sectional view of the cross section of the power semiconductor device 100 taken along the dashed line AA′ is shown. The fourth embodiment adopts the same connection as the first embodiment except for the signal relay conductor 701 .

[0096] like Fig.15 As shown, a signal relay conductor 705 is provided as a substitute for the signal relay conductor 701 of Embodiment 1. The signal relay conductor 705 is electrically connected to the negative electrode sense wiring 305U and the intra-submodule negative electrode sense wiring 406U by, for example, ultrasonic bonding.

[0097] The signal relay conductor 705 is electrically connected to the positive electrode sensing wiring 304U and the positive electrode sensing wiring 405U in the submodule by ultrasonic bonding. By using the signal relay conductor 705, electrical connection can be performed without using the welding material 602 used when connecting the signal relay conductor 701 in Embodiment 1, and a decrease in productivity due to the failure of the welding material to bond can be prevented.

[0098] The above-described embodiment is an example of a preferred embodiment of the present invention, but does not limit the scope thereof and can be modified within a scope not departing from the gist of the present invention.

[0099] Description of symbols

[0100] 100 power semiconductor device; 201 high potential side terminal; 202 low potential side terminal; 203 AC output terminal; 204 positive sensing terminal; 205 negative sensing terminal; 206 molding material; 207 cooling metal part; 301 high potential side wiring; 302 low potential side wiring; 303 AC output wiring; 304 positive sensing wiring; 305 negative sensing wiring; 306 insulating layer; 307 welding pattern; 308 high potential side terminal bonding pattern; 309 low potential side terminal bonding pattern; 400 submodule; 401 first submodule; 402 second submodule; 403 low potential side conductor part in submodule; 404 submodule High potential side conductor part in the block; 405 positive pole sensing wiring in the submodule; 406 negative pole sensing wiring in the submodule; 407 insulating layer in the submodule; 500 power semiconductor element; 501 low potential side electrode; 502 high potential side electrode; 503 positive pole sensing electrode; 504 negative pole sensing electrode; 505 first power semiconductor element; 506 second power semiconductor element; 601 wire bonding; 602 welding material; 701 signal relay conductor; 702 non-laminated part; 703 signal relay conductor; 704 wiring for fixing; 705 signal relay wire; 801 AC output side substrate; 802 DC input side substrate; U upper arm; L lower arm.

Claims

1. A power semiconductor device, characterized in that: include: A first submodule having a first power semiconductor element; a second submodule having a second power semiconductor element; A positive electrode side conductor portion and a negative electrode side conductor portion; an intermediate substrate forming a negative-side opposing portion and a positive-side opposing portion, wherein the negative-side opposing portion is opposed to the negative-side conductor portion via the first submodule, and the positive-side opposing portion is opposed to the positive-side conductor portion via the second submodule; and a plurality of signal terminals for transmitting signals for controlling the first power semiconductor element or the second power semiconductor element, The second submodule is arranged so that the electrode surface of the second power semiconductor element and the electrode surface of the first power semiconductor element are in opposite directions. a signal relay conductor portion is arranged in a space sandwiched between a portion of the second submodule and the intermediate substrate in a height direction of the second submodule; The intermediate substrate includes wiring connected to the signal relay conductor portion and electrically connected to the signal terminal.

2. The power semiconductor device according to claim 1, wherein: A bonding wire is provided to connect the wiring provided on the intermediate substrate to the signal terminal. The intermediate substrate is composed of a first intermediate substrate and a second intermediate substrate sandwiching the first submodule and the second submodule. When viewed from a direction perpendicular to the electrode surface of the second power semiconductor element, The first intermediate substrate has a non-laminated portion that does not overlap with the second intermediate substrate. The non-laminated portion is provided with a connection portion between the wiring and a bonding wire.

3. The power semiconductor device according to claim 1 or 2, characterized in that: The signal relay conductor is arranged in a space sandwiched between a part of the second submodule and the intermediate substrate in a height direction of the second submodule. The intermediate substrate includes wiring connected to the signal relay conductor portion and electrically connected to the signal terminal.

4. The power semiconductor device according to claim 1, wherein: a signal relay conductor is arranged in a space sandwiched between a part of the second submodule and the intermediate substrate in a height direction of the second submodule; The intermediate substrate has wiring connected to the signal relay wire and electrically connected to the signal terminal.

5. A method for manufacturing a power semiconductor device, the power semiconductor device comprising: A first submodule having a first power semiconductor element; a second submodule having a second power semiconductor element; A positive electrode side conductor portion and a negative electrode side conductor portion; A first intermediate substrate and a second intermediate substrate sandwiching the first submodule and the second submodule; as well as a plurality of signal terminals for transmitting signals for controlling the first power semiconductor element or the second power semiconductor element, The method for manufacturing a power semiconductor device is characterized by comprising: a first step of arranging the first submodule and the second submodule side by side on the first intermediate substrate via a solder material so that the electrode surface of the second power semiconductor element and the electrode surface of the first power semiconductor element are inverted in orientation; A second step of arranging the second intermediate substrate on the side opposite to the side where the first intermediate substrate is arranged, in the first submodule and the second submodule, via a solder material, so as to provide a non-laminated portion that does not overlap the second intermediate substrate with the first intermediate substrate; a third step of melting the solder material to bond the first submodule, the second submodule, the first intermediate substrate, and the second intermediate substrate together; and A fourth step is to connect the wiring provided in the non-laminated portion and the plurality of signal terminals via bonding wires.

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