Protection circuit for semiconductor switches

Abstract

The present invention relates to a protection circuit (9) for a semiconductor switch (3). The protection circuit (9) comprises a clamping diode (D2), an npn bipolar transistor (Q4), a pnp bipolar transistor (Q3), a capacitor (C1) and at least three resistors (R2, R4, R5). The bipolar transistors (Q3, Q4) are circuit-connected to form a thyristor structure, and the thyristor structure is connected to the cathode of the clamping diode (D2). The first resistor (R5) is connected in parallel to the base-emitter region of the npn bipolar transistor (Q4). The first electrode of the second resistor (R2) is connected to the base of the pnp bipolar transistor (Q3). The capacitor (C1) is connected in parallel to the base-emitter region of the pnp bipolar transistor (Q3). The third resistor (R4) is connected in parallel with the base emitter region of the pnp bipolar transistor (Q3), or the first electrode (R4_1) of the third resistor (R4) is connected with the emitter of the pnp bipolar transistor (Q3) and the second electrode (R4_2) of the third resistor (R4) is connected with the second electrode (R2_2) of the second resistor (R2).

Description

Technical Field

[0001] The invention relates to a protection circuit for a semiconductor switch having a gate controllable by a gate driver and a circuit arrangement having such a protection circuit. Background Art

[0002] The control terminal of the semiconductor switch is called the gate of the semiconductor switch. The present invention is mainly used as a protective voltage-controlled semiconductor switch, such as an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET), which is driven via a gate voltage or gate potential applied to the gate. In the event of excessive power losses (for example in the event of a short circuit), the semiconductor switch can be damaged or destroyed. In order to avoid such damage, it must be ensured that, for example, in the event of a short circuit, the gate voltage does not rise significantly above its specific switch-on value (maintaining the so-called "safe operating area"). In other cases, a rise in the gate voltage can lead to an excessively high current through the semiconductor switch, such as an excessively high collector current in the case of an IGBT or a drain current in the case of a MOSFET and a sharp increase in power losses.

[0003] In order to prevent excessive power losses, the voltage at the load end of the semiconductor switch, for example the collector voltage in the case of an IGBT or the drain voltage in the case of a MOSFET, can be detected and monitored, for example, by means of a high-voltage diode or an operational amplifier. Alternatively, the current through the semiconductor switch can be detected and monitored, for example, using a shunt or a current transformer. However, these methods can achieve a partial switching off of the semiconductor switch that is not fast enough, are cost-intensive and expensive because potential wells must be crossed, and / or have a high space requirement because of air gaps and creepage distances.

[0004] DE 37 23 786 A1 discloses an arrangement for automatic overcurrent shutdown of an insulated gate transistor or field effect transistor, wherein between the gate and the emitter feed of the insulated gate transistor or field effect transistor, a thyristor is connected to the gate feed with an anode-side port or a series circuit of two transistors emulating the switching function of a thyristor is connected to the gate feed with the collector port of the first transistor. Between the gate feed and the control electrode of the thyristor, respectively the base of the second transistor of the transistor series circuit, a Zener diode is connected to the gate feed with a cathode-side port and in the gate feed, respectively in the feed for applying the gate emitter voltage of the anode, a diode is connected to the gate with a cathode-side port. Summary of the invention

[0005] The object of the present invention is to specify an improved protection circuit for a semiconductor switch having a gate which can be controlled by a gate driver and a circuit arrangement having such a protection circuit.

[0006] According to the invention, this object is achieved by a protective circuit having the features of the invention and a circuit arrangement having the features of the invention.

[0007] Advantageous embodiments of the invention are the subject matter of the individual exemplary embodiments.

[0008] A protection circuit for a semiconductor switch having a gate controllable by a gate driver according to the present invention is connected to the gate in parallel with the gate driver. The protection circuit comprises a clamping diode, an npn bipolar transistor, a pnp bipolar transistor, a capacitor and (at least) three resistors. The collector of the npn bipolar transistor is connected to the base of the pnp bipolar transistor. The base of the npn bipolar transistor is connected to the collector of the pnp bipolar transistor. The emitter of the pnp bipolar transistor is connected to the cathode of the clamping diode. The first resistor is connected in parallel with the base emitter region of the npn bipolar transistor. The first pole of the second resistor is connected to the base of the pnp bipolar transistor. The capacitor is connected in parallel with the base emitter region of the pnp bipolar transistor. The third resistor is connected in parallel with the base emitter region of the pnp bipolar transistor, or the first pole of the third resistor is connected to the emitter of the pnp bipolar transistor and the second pole of the third resistor is connected to the second pole of the second resistor.

[0009] The protection circuit according to the present invention is used to protect semiconductor switches from excessive power losses. The core components of the protection circuit are two bipolar transistors connected to a thyristor structure and a clamping diode, the cathode of which is connected to the thyristor structure. The protection circuit is connected to the gate of the semiconductor switch via the clamping diode in parallel with the gate driver. It can be achieved that if the gate voltage of the semiconductor switch rises too sharply and the semiconductor switch is about to desaturate, the thyristor structure is started via the clamping diode. By starting the thyristor structure, the semiconductor switch can be temporarily or permanently turned off, or the gate voltage and the short-circuit current through the semiconductor switch can be reduced. The present invention realizes a simple protection circuit with very low-cost components (two bipolar transistors, resistors, clamping diodes, capacitors and possible other simple components), which has only a small space requirement. Therefore, in particular, the protection circuit can realize low-cost protection of the semiconductor switch without complicated access to the collector voltage or collector current.

[0010] One embodiment of the protection circuit provides a fourth resistor, which is connected to the anode of the clamping diode. By connecting the fourth resistor between the anode of the clamping diode and the gate of the semiconductor switch, this embodiment of the protection circuit can reduce the gate voltage and the short-circuit current flowing through the semiconductor switch. The reduction of the short-circuit current makes it possible to use semiconductor switches with a low saturation voltage, wherein the short-circuit time cannot be controlled without reducing the short-circuit current. The semiconductor switch can withstand the short-circuit harmlessly for a longer duration by reducing the short-circuit current, so that during this duration other monitoring circuits can initiate the shutdown of the semiconductor switch.

[0011] Another design of the protection circuit provides an additional diode, the cathode of which is connected directly or via a fifth resistor to the emitter of the pnp bipolar transistor and the cathode of the clamping diode. By applying the drive voltage of the gate driver to the cathode of the additional diode, the gate driver that drives the gate can be unloaded using this design of the protection circuit.

[0012] In another embodiment of the protection circuit, the clamping diode is a Schottky diode. The Schottky diode is suitable for the protection circuit in particular because of its shorter switching time than the clamping diode.

[0013] The circuit arrangement according to the invention comprises a semiconductor switch with a gate, a gate driver for driving the gate, and a protection circuit according to the invention, which is connected to the gate in parallel with the gate driver. The gate driver has an electronic switching unit that can be driven by a drive voltage of the gate driver, and the gate is connected to a switch-on potential via a switch-on gate resistor to switch the semiconductor switch on, and is connected to a switch-off potential via a switch-off gate resistor to switch the semiconductor switch off. The advantages of the circuit arrangement according to the invention are derived from the above-mentioned advantages of the protection circuit according to the invention.

[0014] In one embodiment of the circuit arrangement, the emitter of the npn bipolar transistor is connected to the switch-off potential and the second pole of the second resistor is connected to the switch-on potential. In this way, the protection circuit is connected in parallel with components of the gate driver between the switch-on potential and the switch-off potential.

[0015] In another embodiment of the circuit arrangement, the anode of the clamping diode is connected to the gate directly or via a fourth resistor. As already explained above, the short-circuit current through the semiconductor switch can be reduced particularly advantageously by means of the fourth resistor.

[0016] Another embodiment of the circuit arrangement provides an additional diode, the cathode of which is connected directly or via a fifth resistor to the emitter of the pnp bipolar transistor and the cathode of the clamping diode and has the drive voltage at its anode. As already described above, the gate driver can be unloaded by the additional diode.

[0017] In another embodiment of the circuit arrangement, the switch-on gate resistor is identical to the switch-off gate resistor. By using the same gate resistor for switching the semiconductor switch on and off, the number of components of the circuit arrangement can be reduced.

[0018] In a further embodiment of the circuit arrangement, a Zener diode is connected between the turn-on gate resistor and the gate driver, the cathode of the Zener diode being connected to the turn-on gate resistor.

[0019] In another embodiment of the circuit arrangement, the semiconductor switch is an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET). These embodiments of the circuit arrangement allow for both IGBTs and MOSFETs to be advantageously protected by the protection circuit according to the invention.

[0020] In another embodiment of the circuit arrangement, the electronic switching unit of the gate driver has a push-pull power amplifier with a power amplifier bipolar transistor or a power amplifier with a supplementary power amplifier metal oxide semiconductor field effect transistor. These embodiments of the circuit arrangement allow for the use of the protection circuit according to the invention in combination with both of the described types of gate drivers. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In conjunction with the following description of the embodiments according to the accompanying drawings, the above-mentioned characteristics, features and advantages of the present invention and the manner and method for achieving them are clearly and understandably explained. It is shown here:

[0022] Figure 1 A first exemplary embodiment of a circuit arrangement according to the invention is shown.

[0023] Figure 2 It is shown that when the semiconductor switch reaches its desaturation limit after being turned on, Figure 1 The time curves of the current and voltage of the circuit arrangement shown in,

[0024] Figure 3 It is shown that when the semiconductor switch reaches its desaturation limit after being turned on for the second time, Figure 1 The current and voltage curves over time for the circuit arrangement shown,

[0025] Figure 4 A second embodiment of a circuit arrangement according to the invention is shown,

[0026] Figure 5 It shows that when the semiconductor switch reaches its desaturation limit after being turned on, Figure 4 The current and voltage curves over time for the circuit arrangement shown,

[0027] Figure 6 It is shown that when the semiconductor switch reaches its desaturation limit after being turned on for the second time, Figure 4 The current and voltage curves over time for the circuit arrangement shown,

[0028] Figure 7 A third exemplary embodiment of a circuit arrangement according to the invention is shown.

[0029] Figure 8 It is shown that when the semiconductor switch reaches its desaturation limit after being turned on, Figure 7 The current and voltage curves over time for the circuit arrangement shown,

[0030] Fig. 9 A fourth exemplary embodiment of a circuit arrangement according to the invention is shown.

[0031] Fig.10 It is shown that in the case where the semiconductor switch reaches its desaturation limit in two consecutive switch-on phases, Fig. 9 The current and voltage curves over time for the circuit arrangement shown.

[0032] Parts that correspond to one another are provided with the same reference symbols in the figures. DETAILED DESCRIPTION

[0033] Figure 1 A first embodiment of a circuit arrangement 1 according to the invention is shown. The circuit arrangement 1 comprises a semiconductor switch 3 having a gate 5, a gate driver 7 for driving the gate 5 and a first embodiment of a protection circuit 9 according to the invention. The semiconductor switch 3 of this embodiment is an IGBT.

[0034] The gate driver 7 has an electronic switching unit 11, which is connected to the gate 5 via a gate resistor R1. The gate resistor R1 serves as an on-gate resistor when the semiconductor switch 3 is turned on and as an off-gate resistor when the semiconductor switch 3 is turned off.

[0035] With the electronic switch unit 11, the gate 5 is connected to the on potential via the gate resistor R1 for switching on the semiconductor switch 3, and is connected to the off potential for switching off the semiconductor switch. The on potential is generated by the on voltage source V1. The off potential is generated by the off voltage source V2. The electronic switch unit 11 is controlled by a drive voltage. The drive voltage is applied to the control input 10 of the electronic switch unit 11 by the drive voltage source V3 via the drive resistor R3. The voltage sources V1, V2, and V3 are respectively DC voltage sources.

[0036] The protection circuit 9 includes a clamping diode D2, a pnp bipolar transistor Q3, an npn bipolar transistor Q4, a capacitor C1, a first resistor R5, a second resistor R2, a third resistor R4 and an additional diode D1.

[0037] The collector of the npn bipolar transistor Q4 is connected to the base of the pnp bipolar transistor Q3. The base of the npn bipolar transistor Q4 is connected to the collector of the pnp bipolar transistor Q3. Therefore, the pnp bipolar transistor Q3 and the npn bipolar transistor Q4 are connected in a thyristor structure.

[0038] The first resistor R5 is connected in parallel with the base emitter region of the npn bipolar transistor Q4. The first pole R2_1 of the second resistor R2 is connected to the base of the pnp bipolar transistor Q3. The second pole R2_2 of the second resistor R2 is connected to the switch-on potential, ie, to the positive pole of the switch-on voltage source V1.

[0039] The capacitor C1 and the third resistor R4 are connected in parallel with the base emitter region of the pnp bipolar transistor Q3.

[0040] The cathode of the clamping diode D2 is connected to the emitter of the pnp bipolar transistor Q3. The anode of the clamping diode D2 is connected to the gate 5 of the semiconductor switch 3. The cathode of the additional diode D1 is connected to the emitter of the pnp bipolar transistor Q3 and the cathode of the clamping diode D2. A drive voltage is present at the anode of the additional diode D1, i.e. the anode of the additional diode D1 is connected to the control input 10 of the electronic switch unit 11. The protection circuit 9 is connected in parallel with the gate driver 7 between the control input 10 of the gate driver 7 and the gate 5.

[0041] exist Figure 1In the embodiment shown, the electronic switch unit 11 has a push-pull power amplifier 13 with power amplifier bipolar transistors Q1, Q2. The clamping diode D2 is a Schottky diode. The gate resistor R1 has a resistance value of 10Ω, for example. The drive resistor R3 has a resistance value of 470Ω, for example. The first resistor R5 has a resistance value of 200Ω, for example. The second resistor R2 has a resistance value of 1kΩ, for example. The third resistor R4 has a resistance value of 10kΩ, for example. The capacitor C1 has a capacitance of 1nF, for example.

[0042] Figure 2 The figure shows the case where the semiconductor switch 3 reaches its desaturation limit after being turned on. Figure 1 The curves of the currents I1, I2 and the voltages U1, U2, U3 of the circuit arrangement 1 are shown over the time t. These curves were generated using simulations in which Figure 1 As shown, the semiconductor switch 3 is connected to the half-bridge diode D3 and the leakage inductance L2 as a half-bridge, and the load connected to the half-bridge is simulated by the load inductance L1 and the load voltage source V4. The load voltage source V4 is a DC voltage source. The anode of the half-bridge diode D3 is connected to the collector of the semiconductor switch 3, the load inductance L1 is connected in parallel with the half-bridge diode D3, the leakage inductance L2 is connected between the parallel circuit of the half-bridge diode D3 and the load inductance L1 and the positive electrode of the load voltage source V4, and the negative electrode of the load voltage source V4 is connected to the emitter of the semiconductor switch 3. The emitter of the semiconductor switch 3 is connected to the negative electrodes of the voltage sources V1 and V3 and the positive electrode of the voltage source V2, that is, these electrodes are at the same ground potential. Voltages U1, U2, and U3 are respectively referenced to the ground potential, wherein U1 is the drive signal of the gate driver 7, i.e., the voltage generated by the drive voltage source V3 relative to the ground potential, U2 is the gate voltage applied to the gate 5 relative to the ground potential, and U3 is the collector voltage applied to the collector of the semiconductor switch 3 relative to the ground potential.

[0043] The simulation was performed with respect to a gate resistor R1 of 10Ω, a drive resistor R3 of 470Ω, a first resistor R5 of 200Ω, a second resistor R2 of 1kΩ, a third resistor R4 of 10kΩ, a capacitor C1 having a capacitance of 1nF, a load inductance L1 of 5μH, and a leakage inductance L2 of 200nH.

[0044] About 4 μs after the start of the simulation, the drive signal U1 of the gate driver 7 is increased from the off value -8 V to the on value 15 V in order to turn on the semiconductor switch 3. As a result, the gate voltage U2 applied to the gate 5 increases from the off gate voltage value approximately corresponding to the off value of the drive signal U1 and forms a reaction current I1 flowing through the gate resistor R1. Figure 2As the gate voltage U2 increases, the collector voltage U3 applied to the collector of the semiconductor switch 3 drops from 0.6 kV to nearly 0 V, and a collector current I2 flowing between the collector and emitter of the semiconductor switch 3 is formed, and the collector current increases linearly based on the load inductance L1.

[0045] The value of the reaction current I1 first increases after the change of the drive signal U1 and then decreases again when the gate voltage U2 rises. At about 5.5 μs after the start of the simulation, the reaction current I1 changes its direction (or its sign) because the Miller capacitance of the semiconductor switch 3 is charged and the reaction current I1 flows back into the gate 5. With the increase of the collector current I2, the semiconductor switch 3 reaches its desaturation limit at about 5.8 μs after the start of the simulation and the collector voltage U3 starts to rise again (slowly at first). Due to the Miller capacitance of the semiconductor switch 3, the gate voltage U2 rises above the switch-on value of the drive signal U1 of 15 V and the value of the reaction current I1 flowing back into the gate 5 increases. About 6 μs after the start of the simulation, the thyristor structure formed by the pnp bipolar transistor Q3 and the npn bipolar transistor Q4 is finally started via the clamping diode D2, whereby the gate voltage U2 is close to the turn-off gate voltage value, the reaction current I1 and the collector current I2 drop to zero again, the collector voltage U3 receives its output value 0.6 kV and turns off the semiconductor switch 3.

[0046] Figure 3 Similar to Figure 2 Shows Figure 1 The circuit arrangement 1 shown shows the time curves of the currents I1, I2 and the voltages U1, U2, U3 when the semiconductor switch 3 reaches its desaturation limit after the second switching on. These curves were generated using a simulation system, wherein, unlike in Figure 2 In the simulation shown in FIG. 1 , the load inductor L1 has an inductance value of 150 μH. In addition, the simulation is similar to that in Figure 2 The simulations shown in have the same parameters.

[0047] The semiconductor switch 3 is turned on approximately 4 μs after the start of the simulation by increasing the drive signal U1 of the gate driver 7 from the turn-off value -8 V to the turn-on value 15 V, and the semiconductor switch is turned off again approximately 29 μs after the start of the simulation by reducing the drive signal U1 again to -8 V. In the first turn-on phase, the gate voltage U2 rises only slightly above the turn-on value 15 V, so that the thyristor structure formed by the pnp bipolar transistor Q3 and the npn bipolar transistor Q4 is not activated.

[0048] At about 44 μs after the start of the simulation, the semiconductor switch 3 is turned on for the second time. In this second turn-on phase, the collector current I2 rises quickly to approximately the same value as at the end of the first turn-on phase after being turned on, and the gate voltage U2 rises more significantly than the first turn-on phase to exceed the turn-on value of 15 V, whereby the reaction current I1 flows back into the gate 5, and the thyristor structure formed by the pnp bipolar transistor Q3 and the npn bipolar transistor Q4 starts and turns off the semiconductor switch 3 after about 64 μs.

[0049] Figure 2 and 3 As shown, as long as the driver signal U1 is still at the switch-on value 15V, that is, the semiconductor switch 3 reaches its desaturation limit, Figure 1 The protection circuit 9 shown in FIG. 1 causes the semiconductor switch 3 to be turned off by activating a thyristor structure formed by a pnp bipolar transistor Q3 and an npn bipolar transistor Q4.

[0050] Figure 4 A second embodiment of a circuit arrangement 1 according to the invention is shown. Figure 1 The circuit arrangement 1 shown differs only in that the protection circuit 9 is not Figure 1 In addition to the components of the protection circuit 9 shown in FIG. 1 , a fourth resistor R7 and a fifth resistor R6 are also provided. A first electrode R7_1 of the fourth resistor R7 is connected to the anode of the clamping resistor D2. A second electrode R7_2 of the fourth resistor R7 is connected to the gate 5 and the electrode on the gate side of the gate resistor R1. A first electrode R6_1 of the fifth resistor R6 is connected to the cathode of the additional diode D1. A second electrode R6_2 of the fifth resistor R6 is connected to the emitter of the pnp bipolar transistor Q3 and the cathode of the clamping diode D2.

[0051] Figure 5 Shows Figure 4 The circuit arrangement 1 shown is similar to Figure 2 The time curves of the currents I1, I2 and the voltages U1, U2, U3 in the simulation shown. Figure 2 As shown in the simulation, the implementation Figure 5 The simulation shown is for a gate resistor R1 of 10Ω, a drive resistor R3 of 470Ω, a second resistor R2 of 1kΩ, a third resistor R4 of 10kΩ, a capacitor C1 having a capacitance of 1nF, a load inductance L1 of 5μH, and a leakage inductance L2 of 200nH. Figure 2 The simulation shown, Figure 5 The simulation shown was performed for a first resistor R5 of 1 kΩ, a fourth resistor R7 of 470 Ω, and a fifth resistor R6 of 2.2 kΩ.

[0052] About 4 μs after the start of the simulation, the drive signal U1 of the gate driver 7 is increased from the off value -8 V to the on value 20 V for turning on the semiconductor switch 3. Figure 2 In the simulation shown, the gate voltage U2 increases and forms a reaction current I1 flowing through the gate resistor R1. As the gate voltage U2 increases, the collector voltage U3 drops from 0.6 kV to nearly 0 V, and forms a collector current I2 flowing between the collector and emitter of the semiconductor switch 3, which increases linearly based on the load inductance L1.

[0053] The value of the reaction current I1 first increases after the drive signal U1 changes and then decreases again when the gate voltage U2 rises. At approximately 5.5 μs after the start of the simulation, the reaction current I1 changes its direction (or its sign) because the Miller capacitance of the semiconductor switch 3 is charged and the reaction current I1 flows back into the gate 5. With the increase of the collector current I2, the semiconductor switch 3 reaches its desaturation limit at approximately 6 μs after the start of the simulation and the collector voltage U3 begins to increase again. Due to the Miller capacitance of the semiconductor switch 3, the gate voltage U2 rises above the turn-on value of 20 V of the drive signal U1 and the value of the reaction current I1 flowing back into the gate 5 increases. At approximately 6.7 μs after the start of the simulation, the thyristor structure formed by the pnp bipolar transistor Q3 and the npn bipolar transistor Q4 is started via the clamping diode D2. However, by relatively Figure 1 The resistors R6 and R7 added to the protection circuit 9 shown in the figure are different from those in the embodiment shown in the figure after the bipolar transistors Q3 and Q4 are started. Figure 2 The semiconductor switch 3 is not turned off, but the gate voltage is reduced to about 15 V, thereby reducing the collector current I2 to a short-circuit current of about 160 A.

[0054] Figure 6 Shows Figure 4 The circuit arrangement 1 shown is similar to Figure 3 The curves of the currents I1, I2 and the voltages U1, U2, U3 over time in the simulation shown. These curves were generated using simulations, wherein, unlike Figure 4 In the simulation shown, the load inductor L1 has an inductance value of 150 μH. Figure 4 The simulations shown have the same parameters.

[0055] The semiconductor switch 3 is turned on approximately 4 μs after the start of the simulation by increasing the drive signal U1 of the gate driver 7 from the turn-off value -8 V to the turn-on value 20 V, and is turned off again approximately 29 μs after the start of the simulation by decreasing the drive signal U1 again to the turn-off value -8 V. In the first turn-on phase, the gate voltage U2 rises only slightly above the turn-on value 20 V, so that the thyristor structure formed by the pnp bipolar transistor Q3 and the npn bipolar transistor Q4 is not activated.

[0056] The semiconductor switch 3 is turned on for the second time at about 44 μs after the start of the simulation. In the second turn-on phase, the collector current I2 rises quickly after the turn-on to approximately the same value as at the end of the first turn-on phase, and the gate voltage U2 rises more significantly than in the first turn-on phase above the turn-on value of 20 V, whereby the reaction current I1 flows back into the gate 5, and the thyristor structure formed by the pnp bipolar transistor Q3 and the npn bipolar transistor Q4 starts after about 81 μs. Similar to Figure 5 , the gate voltage U2 drops to about 15V after starting the bipolar transistors Q3 and Q4, whereby the collector current I2 is reduced to a short-circuit current of about 160A.

[0057] Figure 5 and Figure 6 It is shown that if the semiconductor switch 3 is about to desaturate, Figure 4 The protective circuit 9 shown causes a reduction in the gate voltage U2 and the collector current I2. The reduced collector current I2 can then be switched off using a slower monitoring circuit, which for example comprises a current measurement with potential isolation and analog-to-digital conversion.

[0058] Figure 7 A third embodiment of a circuit arrangement 1 according to the invention is shown. Figure 1 The circuit arrangement 1 shown differs only in that the third resistor R4 is not connected in parallel with the capacitor C1 , but rather a first pole R4_1 of the third resistor R4 is connected to the emitter of the pnp bipolar transistor Q3 and a second pole R4_2 of the third resistor R4 is connected to a second pole R2_2 of the second resistor R2 and is therefore at a switch-on potential.

[0059] Figure 8 Shows Figure 7 The circuit arrangement 1 shown is similar to Figure 2 The time curves of the currents I1, I2 and the voltages U1, U2, U3 in the simulation shown. Figure 2 The simulation shown, performs Figure 8The simulation shown is for a gate resistor R1 of 10Ω, a drive resistor R3 of 470Ω, a first resistor R5 of 200Ω, a second resistor R2 of 1kΩ, a load inductance L1 of 5μH, and a leakage inductance L2 of 200nH. Figure 2 The simulation shown, implemented Figure 8 The simulation shown is for a third resistor R4 of 2.2 kΩ and a capacitor C1 with a capacitance of 2 nF.

[0060] About 4 μs after the start of the simulation, the drive signal U1 of the gate driver 7 is increased from the off value -8 V to the on value 15 V for turning on the semiconductor switch 3. Figure 2 In the simulation shown, the gate voltage U2 increases and forms a reaction current I1 flowing through the gate resistor R1. As the gate voltage U2 increases, the collector voltage U3 drops from 0.6 kV to nearly 0 V and forms a collector current I2 flowing between the collector and emitter of the semiconductor switch 3, which increases linearly based on the load inductance L1.

[0061] The reaction current I1 first increases after the change of the drive signal U1 and then decreases again when the gate voltage U2 rises. At about 5.5 μs after the start of the simulation, the reaction current I1 changes its direction (or its sign) because the Miller capacitance of the semiconductor switch 3 is charged and the reaction current I1 flows back into the gate 5. The semiconductor switch 3 reaches its desaturation limit at about 5.8 μs after the start of the simulation. Due to the Miller capacitance of the semiconductor switch 3, the gate voltage U2 rises above the turn-on value of the drive signal U1, 15 V, and the value of the reaction current I1 flowing back into the gate 5 increases. At about 6 μs after the start of the simulation, the thyristor structure formed by the pnp bipolar transistor Q3 and the npn bipolar transistor Q4 is started via the clamping diode D2, the gate voltage U2 drops to the negative turn-off gate voltage value and the semiconductor switch 3 is turned off. The third resistor R4 provides a continuous holding current for the bipolar transistors Q3 , Q4 of the protection circuit 9 , so that the gate voltage U2 remains negative even when the drive signal U1 is set to the switch-off value −8 V and then to the switch-on value 15 V again.

[0062] Figure 8 It is shown that when the semiconductor switch 3 reaches its desaturation limit, Figure 7 The protection circuit 9 shown causes the semiconductor switch 3 to be permanently switched off by activating the bipolar transistors Q3 , Q4 of the protection circuit 9 .

[0063] Fig. 9 A fourth embodiment of a circuit arrangement 1 according to the invention is shown. The circuit arrangement 1 differs from Figure 1The circuit arrangement 1 shown consists firstly in the fourth resistor R7 connected between the anode of the clamping diode D2 and the gate 5 of the semiconductor switch 3 and secondly in the implementation of the electronic switching unit 11 and its connection to the gate 5 .

[0064] The electronic switch unit 11 has a power amplifier 14 with supplementary power amplifier MOSFETs M1 to M4 instead of the push-pull power amplifier 13 with power amplifier bipolar transistors Q1, Q2. The first power amplifier MOSFET M1 and the second power amplifier MOSFET M2 of the power amplifier 14 are each designed as a p-channel MOSFET. The third power amplifier MOSFET M3 and the fourth power amplifier MOSFET M4 of the power amplifier 14 are each designed as an n-channel MOSFET. The gate terminals of the first power amplifier MOSFET M1 and the third power amplifier MOSFET M3 are connected to the control input 10 of the electronic switch unit 11. The drain terminal of the first power amplifier MOSFET M1 is connected to the gate terminal of the second power amplifier MOSFET M2. The drain terminal of the third power amplifier MOSFET M3 is connected to the gate terminal of the fourth power amplifier MOSFET M4. The source terminals of the first power amplifier MOSFET M1 and the second power amplifier MOSFET M2 are at the on potential, i.e., these source terminals are connected to the positive pole of the on voltage source V1. The source terminals of the third power amplifier MOSFET M3 and the fourth power amplifier MOSFET M4 are at the off potential, i.e., these source terminals are connected to the negative pole of the off voltage source V2. The drain terminal of the second power amplifier MOSFET M2 is connected to the gate 5 of the semiconductor switch 3 via a Zener diode D4 and an on-gate resistor R8, wherein the anode of the Zener diode D4 is connected to the drain terminal of the second power amplifier MOSFET M2 and the on-gate resistor R8 is connected between the cathode of the Zener diode D4 and the gate 5. The drain terminal of the fourth power amplifier MOSFET M4 is connected to the gate 5 of the semiconductor switch 3 via an off-gate resistor R9. The drain terminals of the first power amplifier MOSFET M1 and the third power amplifier MOSFET M3 are connected to each other via a connecting resistor R10.

[0065] Fig.10 It is shown that in the simulation for the turn-on gate resistor R8 and the turn-off gate resistor R9 of 10Ω, the drive resistor R3 of 470Ω, the first resistor R5 of 1kΩ, the second resistor R2 of 470Ω, the third resistor R4 of 10kΩ, the fourth resistor R7 of 100Ω, the connection resistor R10 of 50Ω, the capacitor C with a capacitance of 2nF, the load inductance L1 of 100μH and the leakage inductance L2 of 200nH, Fig. 9The collector current I2 , the gate current I3 through the gate 5 and the voltages U1 , U2 , U3 of the circuit arrangement 1 are shown over time.

[0066] About 1 μs after the start of the simulation, the drive signal U1 of the gate driver 7 is increased from the off value -8V to the on value 20V for turning on the semiconductor switch 3. Therefore, similar to Figure 2 In the simulation shown, the gate voltage U2 increases until it significantly exceeds the turn-on voltage value 20V, thereby starting the thyristor structure formed by the pnp bipolar transistor Q3 and the npn bipolar transistor Q4 of the protection circuit 9, and the gate voltage U2 drops again to the turn-off gate voltage value of about -8V and turns off the semiconductor switch 3. At about 31μs after the start of the simulation, the driver signal U1 is reset to the turn-off value -8V, and at about 46μs after the start of the simulation, it is increased again to the turn-on value 20V. At about 59μs after the start of the simulation, the gate voltage U2 once again significantly exceeds the turn-on voltage 20V, thereby starting the thyristor structure formed by the pnp bipolar transistor Q3 and the npn bipolar transistor Q4 of the protection circuit 9, and once again turns off the semiconductor switch 3. Different from Figure 8 The simulation shown, the gate voltage U2 is Fig.10 In the simulation shown, after the driver signal U1 increases to the switch-on value 20 V for the second time, it is not negative (“unlatched”), but increases again, because the fourth resistor R4 is not like Figure 7 That is based on Fig. 9 connect.

[0067] Fig.10 It is shown that when the semiconductor switch 3 reaches its desaturation limit during a switching cycle, Fig. 9 The protection circuit 9 shown causes the semiconductor switch 3 to be temporarily turned off for one switching cycle of the gate driver 7 by activating the bipolar transistors Q3 and Q4 of the protection circuit 9. In addition, Fig.10 It is shown that the protection circuit 9 according to the invention is also operated in conjunction with a gate driver 7 which has a power amplifier 14 with supplementary power amplifier MOSFETs M1 to M4 instead of the push-pull power amplifier 13 with power amplifier bipolar transistors Q1 , Q2 .

[0068] according to Figures 1 to 8 The described embodiments can be similar to those according to Fig. 9 and Fig.10 The embodiment described above is also implemented with a gate driver 7, which has a power amplifier 14 with supplementary power amplifier MOSFETs M1 to M4 instead of a push-pull power amplifier 13 with power amplifier bipolar transistors Q1, Q2. In addition, by using MOSFETs instead of IGBTs as semiconductor switches 3, it is also possible to convert Figures 1 to 10 The embodiment shown in .

[0069] Although the present invention has been illustrated and described in detail by means of preferred embodiments, the present invention is not limited to the disclosed examples and a person skilled in the art will be able to derive other variants without departing from the scope of protection of the present invention.

Claims

1. A protection circuit (9) for a semiconductor switch (3), the semiconductor switch having a gate (5) which can be driven by a gate driver (7), wherein: The protection circuit (9) and the gate driver (7) are connected to the gate (5) in parallel, and the protection circuit (9) comprises: - Clamping diode (D2), - npn bipolar transistor (Q4), - pnp bipolar transistor (Q3), - Capacitor (C1), - First resistor (R5), - The second resistor (R2) and - The third resistor (R4), where - the collector of the npn bipolar transistor (Q4) is connected to the base of the pnp bipolar transistor (Q3), - the base of the npn bipolar transistor (Q4) is connected to the collector of the pnp bipolar transistor (Q3), - the emitter of the pnp bipolar transistor (Q3) is connected to the cathode of the clamping diode (D2), - the first resistor (R5) is connected in parallel with the base emitter region of the npn bipolar transistor (Q4), - a first electrode of the second resistor (R2) is connected to the base of the pnp bipolar transistor (Q3), - the capacitor (C1) is connected in parallel with the base emitter region of the pnp bipolar transistor (Q3), and - the third resistor (R4) is connected in parallel with the base emitter region of the pnp bipolar transistor (Q3), wherein the capacitor (C1) is connected in parallel with the third resistor (R4), or - A first electrode (R4_1) of the third resistor (R4) is connected to the emitter of the pnp bipolar transistor (Q3) and a second electrode (R4_2) of the third resistor (R4) is connected to a second electrode (R2_2) of the second resistor (R2).

2. The protection circuit (9) according to claim 1, comprising a fourth resistor (R7), wherein the fourth resistor is connected to the anode of the clamping diode (D2).

3. The protection circuit (9) according to claim 1 or 2, comprising an additional diode (D1), the cathode of which is connected directly or via a fifth resistor (R6) to the emitter of the pnp bipolar transistor (Q3) and the cathode of the clamping diode (D2).

4. The protection circuit (9) according to claim 1 or 2, wherein: The clamping diode (D2) is a Schottky diode.

5. A circuit arrangement (1), comprising: - a semiconductor switch (3) having a gate (5), - a gate driver (7) for driving the gate (5), wherein the gate driver (7) has an electronic switching unit (11) controllable by a drive voltage of the gate driver (7), the gate (5) being connected to a switch-on potential via a switch-on gate resistor for switching on the semiconductor switch (3), and connected to a switch-off potential via a switch-off gate resistor for switching off the semiconductor switch (3), and - A protection circuit (9) according to any one of the preceding claims, which is connected to the gate (5) in parallel with the gate driver (7).

6. The circuit arrangement (1) according to claim 5, wherein: The emitter of the npn bipolar transistor (Q4) is connected to the switch-off potential and the second pole (R2_2) of the second resistor (R2) is connected to the switch-on potential.

7. The circuit arrangement (1) according to claim 5 or 6, wherein: The anode of the clamping diode (D2) is connected to the gate (5).

8. The circuit arrangement (1) according to claim 5 or 6, wherein: The anode of the clamping diode (D2) is connected to the gate (5) via a fourth resistor (R7).

9. The circuit arrangement (1) according to claim 5 or 6, comprising an additional diode (D1), the cathode of which is connected to the emitter of the pnp bipolar transistor (Q3) and to the cathode of the clamping diode (D2) and at the anode of which the drive voltage is present.

10. The circuit arrangement (1) according to claim 8, comprising an additional diode (D1), the cathode of which is connected to the emitter of the pnp bipolar transistor (Q3) and the cathode of the clamping diode (D2) via a fifth resistor (R6) and the drive voltage is present at the anode of the clamping diode.

11. The circuit arrangement (1) according to claim 5 or 6, wherein: The on-gate resistance is the same as the off-gate resistance.

12. The circuit arrangement (1) according to claim 5 or 6, wherein: A voltage-stabilizing diode (D4) is connected between the on-gate resistor and the gate driver (7), and a cathode of the voltage-stabilizing diode is connected to the on-gate resistor.

13. The circuit arrangement (1) according to claim 5 or 6, wherein: The semiconductor switch (3) is an insulated gate bipolar transistor or a metal oxide semiconductor field effect transistor.

14. The circuit arrangement (1) according to claim 5 or 6, wherein: The electronic switching unit (11) of the gate driver (7) has a push-pull power amplifier (13) with power amplifier bipolar transistors (Q1, Q2).

15. The circuit arrangement (1) according to claim 5 or 6, wherein: The electronic switching unit (11) of the gate driver (7) has a power amplifier (14) with a supplementary power amplifier metal oxide semiconductor field effect transistor.

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