Capacitor die for stacked integrated circuits

Abstract

An apparatus is provided, the apparatus comprising: a die stack having a first die and a second die disposed above a substrate; and a capacitor die disposed between the first die and the second die in the die stack. The capacitor die comprises a plurality of integrated circuit capacitors configured to selectively couple together to form a desired capacitor value coupled to at least one of the first die and the second die.

Description

Background Art

[0001] Strong demand for portable consumer electronic devices is driving the need for large-capacity storage devices. Nonvolatile semiconductor memory devices, such as flash memory storage cards, are widely used to meet the growing demand for digital information storage and exchange. The portability, versatility, and rugged design of nonvolatile semiconductor memory devices, along with their high reliability and large capacity, have made such memory devices an ideal choice for use in a wide variety of electronic devices, including, for example, digital cameras, digital music players, video game consoles, PDAs, mobile phones, and solid-state drives.

[0002] Semiconductor devices such as semiconductor memory devices are sometimes formed in a system-in-package (SiP) device that includes multiple semiconductor dies mounted in a stack on a substrate. The dies in the stack are typically electrically coupled to the substrate using wire bonds. In some semiconductor devices (e.g., memory devices), the stack may include a relatively large number of dies (e.g., 8, 16, 32, or 64 dies). As the number of dies in the stack increases, the length of the wire bonds that couple the die near the top of the stack to the substrate also increases. As the length increases, the effects of parasitic inductance and resistance in the wire bonds become problematic, particularly for high frequency operation.

[0003] As a result, power supply noise and ground bounce increase, which can adversely affect the signal integrity and power integrity of highly stacked integrated circuits, such as semiconductor memory devices. As semiconductor devices are continually designed to operate at higher frequencies, the parasitic inductance of wire bonds may limit the number of dies that can be stacked and mounted on a substrate. For semiconductor memory devices, this limitation may limit the capacity of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Like numbered elements in different drawings refer to common components.

[0005] Figure 1A and 1B Depicted are a side view and a top view, respectively, of a previously known semiconductor device including a stack of semiconductor dies.

[0006] Figure 2A Depicted is a side view of a semiconductor device including a semiconductor die stack and a capacitor die.

[0007] Figures 2B1 to 2B2 yes Figure 2A A top view of various embodiments of a capacitor die.

[0008] Figures 2C1 to 2C4 Depiction Figure 2B1 A simplified schematic diagram of an embodiment of a capacitor die.

[0009] Figures 2C5 to 2C6 Depiction Figure 2B2 A simplified schematic diagram of an embodiment of a capacitor die.

[0010] Figures 3A1 to 3T Various views of an embodiment of a capacitor die depicting the described technology.

[0011] Figures 4A to 4B A simplified schematic diagram depicting an embodiment of a capacitor die of the described technology. DETAILED DESCRIPTION

[0012] Figure 1A and 1B Depicted are a side view and a top view, respectively, of a previously known semiconductor device 100 that includes a semiconductor die stack 102 formed on a substrate 104, such as a printed circuit board (PCB), a lead frame, a tape automated bonding (TAB) tape, or other similar substrate. The die stack 102 includes sixteen dies 106 (e.g., semiconductor memory dies), although more or less than sixteen dies 106 may be used. A logic integrated circuit (e.g., an application specific integrated circuit (ASIC)) 108 is disposed on the substrate 104, and the die stack 102 is disposed above the ASIC 108 on a support 110.

[0013] A first group of dies 106 (e.g., D1-D8) are offset from each other in a first direction (e.g., +x axis), and a second group of dies 106 (e.g., D9-D16) are offset from each other in a second direction (e.g., -x axis) opposite to the first direction, wherein a film 112 (e.g., a thick adhesive film) is disposed between the first group of dies 106 and the second group of dies 106.

[0014] One or more bond pads 114 are disposed along an edge of the top surface of each die 106, one or more contact pads (or "bond fingers") 116 are disposed on the top surface of substrate 104, and one or more solder balls 118 are disposed along the bottom surface of substrate 104. To avoid overcrowding the drawing, each die 106 is shown as including four bond pads 114, and substrate 104 is shown as including eight contact pads 116.

[0015] Those of ordinary skill in the art will appreciate that integrated circuit dies typically include more than four bond pads, and substrates typically include more than eight contact pads. Bond pads 114 and contact pads 116 are used to electrically interconnect die 106 to each other and substrate 104 via wire bonds 120 (e.g., gold, gold alloy, or some other material). Substrate 104 includes one or more conductive traces 122 that electrically couple contact pads 116 to solder balls 118.

[0016] To avoid overcrowding the drawing, each die 106 is shown as including a first power bonding pad 114a (e.g., VDD) and a second power bonding pad 114b (e.g., GND), and the substrate 104 is shown as including first power contact pads 116a1 and 116a2 (e.g., VDD) and second power contact pads 116b1 and 116b2 (e.g., GND). One of ordinary skill in the art will appreciate that integrated circuit dies typically include more than two power bonding pads, and substrates typically include more than four power contact pads. The first power contact pad 116a1 and the second power contact pad 116b1 provide power to the dies D1-D8, and the first power contact pad 116a2 and the second power contact pad 116b2 provide power to the dies D9-D13.

[0017] Specifically, if Figure 1B As shown in FIG. 1 , the first power pad 114 a on each of the dies D9 - D16 is connected to the first power pad 114 a by wire bonding 120 S The first power pad 114a on the die D9 is coupled to each other through a wire bond 120 M1 The first power contact pad 116a2 is coupled to the first power pad 114a on the die D13 through the wire bonding 120 L1 Similarly, the power bonding pad 114b on each of the dies D9-D16 is connected to the first power contact pad 116a2 by wire bonding 120 S The power pad 114b on the die D9 is coupled to each other through the wire bonding 120 M2 The power supply pad 114b on the die D13 is coupled to the second power supply contact pad 116b2 and is connected to the power supply bonding pad 114b on the die D13 by wire bonding 120 L2 is coupled to the second power contact pad 116b2. Figure 1B Not visible in FIG. 1 , similar electrical connections are made between the first and second power bonding pads 114 a and 114 b and the first and second power contact pads 116 a 1 and 116 b 1 on the dies D1 - D8 .

[0018] Wire bonding 120 S With a relatively short length, the wirebond 120 M1 and 120 M2 has a relatively intermediate length and the wire bonding is 120 L1 and 120 L2 Each wire bond 120 (120 S , 120 M1 , 120 M2 , 120 L1 and 120 L2) includes parasitic resistance and inductance, each of which increases with increasing wire bond length.

[0019] For wire bonds 120 used to couple power (eg, VDD and GND) from substrate 104 to die 106, the parasitic resistance and inductance of long wire bonds (eg, wire bonds 120 L1 The first power pad 114a on the die D13 is coupled to the first power contact pad 116a2, and the wire bonding 120 L2 Coupling the second power bond pad 114b on die D13 to the second power contact pad 116b2 on substrate 104 may become problematic.

[0020] Specifically, at frequencies above about 300 MHz, the parasitic inductance of the long wire bonds begins to dominate and the impedance profile of the power delivery network becomes inductive, increasing with increasing frequency. As a result, high frequency noise is coupled to the power delivery network, which increases power supply noise and ground bounce and can adversely affect the signal integrity and power integrity of a highly stacked integrated circuit, such as a semiconductor memory device.

[0021] Conventional techniques for improving power delivery networks include adding decoupling capacitors and / or internal voltage regulators on substrate 104. Such conventional techniques are inadequate or undesirable for highly stacked integrated circuits. Adding decoupling capacitors to substrate 104 does not eliminate the long wire bond inductance "found" by stacked die 106. In addition, voltage regulators require additional discrete components, such as inductors and capacitors, which consume valuable real estate on substrate 104. Voltage regulators may also introduce noise and may cause thermal management issues.

[0022] A technique for a high stacked integrated circuit is described. A capacitor die including one or more integrated circuit capacitors is disposed between two adjacent dies in a die stack above a substrate. In an embodiment, the integrated circuit capacitors can be selectively coupled together to form a desired capacitor value for the capacitor die. In an embodiment, the integrated circuit capacitor includes a first capacitor plate and a second capacitor plate coupled to a bonding pad on the capacitor die. In an embodiment, the bonding pad on the capacitor die is coupled to a power bonding pad on one or more dies in the die stack. In an embodiment, the number of bonding pads on the capacitor die and / or the size of the bonding pads are selected to accommodate multiple wire bond connections between the capacitor die and the power contact pad on the substrate.

[0023] Without wishing to be bound by any particular theory, it is believed that increasing the number of parallel wirebond connections between the capacitor die and the power contact pads on the substrate can reduce the inductance seen by the high stacked die decoupled by the capacitor die. It is also believed that the parallel wirebonds will provide a low impedance path from the substrate to the high stacked die. Additionally, without wishing to be bound by any particular theory, it is believed that selectively coupling the integrated circuit capacitors to form the desired capacitor value of the capacitor die can form a low impedance distribution in the frequency domain with the parallel wirebonds from the substrate to the die stack in the power delivery network, and can reduce power supply noise and ground bounce in the power delivery network.

[0024] Figure 2A A side view of a semiconductor device 200 is depicted that includes a semiconductor die stack 202 formed on a substrate 104. In an embodiment, the die stack 202 includes sixteen dies 106 (e.g., semiconductor memory dies), although more or less than sixteen dies 106 may be used. An ASIC 108 (e.g., a memory controller) is disposed on the substrate 104, and the die stack 202 is disposed on a support 110, above the ASIC 108. The semiconductor device 200 is similar to Figure 1A-1B 1 , but further includes an integrated circuit capacitor die (“capacitor die”) 204 in the die stack 202 .

[0025] In an embodiment, the capacitor die 204 has substantially the same length and width as the die 106, and is disposed between adjacent die 106 (e.g., between die D12 and D13) in the die stack 202. In other embodiments, the semiconductor device 200 may include more than one capacitor die 204, and / or the capacitor die 204 may be disposed on top of the die stack or between other die 106 in the die stack 202. For example, in another embodiment, the capacitor die 204 may be disposed between die D8 and D9 to supply charge to the die D1-D8 and the die D9-D16.

[0026] In an embodiment, capacitor die 204 has a length between about 9 mm to about 14 mm, a width between about 2 mm to about 11 mm, and a height between about 10 μm to about 250 μm, although other dimensions may be used based on manufacturing capabilities and design requirements. In an embodiment, bonding pads 206 are disposed along a first edge 208 and a second edge 210 of the top surface of capacitor die 204. In other embodiments, bonding pads 206 may be disposed along the first edge 208 or the second edge 210 of the top surface of capacitor die 204. In an embodiment, bonding pads 206 are physically close to bonding pads 114 of dies D13 and D12.

[0027] As described in more detail below, in an embodiment, capacitor die 204 includes an integrated circuit capacitor having a first capacitor plate and a second capacitor plate separated by a thin layer of dielectric material, similar to the structure of a parallel plate capacitor. The first capacitor plate is coupled to one or more bonding pads 206a, which are coupled to a first power contact pad 116a2 on substrate 104 via one or more wire bonds, and the second capacitor plate is coupled to one or more bonding pads 206b, which are coupled to a second power contact pad 116b2 on substrate 104 via one or more wire bonds. In an embodiment, the first capacitor plate is also coupled to a first power bonding pad 114a on a die 106 (e.g., die D13) adjacent to capacitor die 204 via wire bonds, and the second capacitor plate is coupled to a second power bonding pad 114b on an adjacent die 106 (e.g., die D13) via wire bonds.

[0028] In an embodiment, the integrated circuit capacitors of capacitor die 204 have capacitance values ​​in the microfarad range (or greater) that are much greater than the capacitance values ​​of the capacitors on die 106 (typically on the order of a few nanofarads). Without wishing to be bound by any particular theory, it is believed that coupling the first and second capacitor plates of capacitor die 204 described above in close proximity to a “load” (e.g., die D13) can significantly reduce voltage rail drops, power supply noise, and ground bounce in semiconductor devices that include tall semiconductor die stacks, such as die stack 202.

[0029] Figure 2B1 yes Figure 2A 200a. In this embodiment, semiconductor device 200a includes a capacitor die 204a, the capacitor die including an integrated circuit capacitor having a first capacitor plate (not shown) coupled to a first bonding pad 206a and a second capacitor plate (not shown) coupled to a second bonding pad 206b. In an embodiment, capacitor die 204a includes four first bonding pads 206a and four second bonding pads 206b, but more or less than four first bonding pads 206a and four second bonding pads 206b may be used.

[0030] In order to provide power to the dies D9-D12, the first power bonding pad 114a on each of the dies D9-D12 is connected to the first power bonding pad 114a by the wire bonding 120 S The second power pad 114b on each of the dies D9-D12 is coupled to each other via a wire bond 120 S The first power pad 114a on the die D9 is coupled to each other through a wire bond 120 M1The first power contact pad 116a2 is coupled to the second power pad 114b on the die D9 through the wire bond 120 M2 Coupled to the second power contact pad 116b2.

[0031] In order to provide power to the dies D13-D16, the first power bonding pad 114a on each of the dies D13-D16 is connected to the first power bonding pad 114a by the wire bonding 120 S The second power pad 114b on each of the dies D13-D16 is coupled to each other by wire bonding 120 S The first power pad 114a on the die D13 is coupled to one or more of the first pads 206a of the capacitor die 204a, and the second power pad 114b on the die D13 is coupled to one or more of the second pads 206b of the capacitor die 204a. The first pad 206a of the capacitor die 204a is connected to the first pad 206a of the capacitor die 204a by the wire bonding 220. a -220 d The second bonding pad 206b of the capacitor die 204a is coupled to the first power contact pad 116a2 and is connected to the second power contact pad 206b of the capacitor die 204a by wire bonding 220 e -220 h Coupled to the second power contact pad 116b2.

[0032] By virtue of these electrical connections, the integrated circuit capacitors of the capacitor die 204a are coupled in parallel across the first power bond pads 114a and the second power bond pads 114b of the dies D9-D12 and act as power bypass capacitors. Without wishing to be bound by any particular theory, it is believed that the capacitor die 204a acts as a bypass capacitor for the long wire bonds 220. a -220 d and wire bonding 220 e -220 h small battery and can reduce power supply noise and ground bounce.

[0033] Additionally, since the capacitor die 204a includes a plurality of bonding pads 206a and 206b coupled to each of the first capacitor plate and the second capacitor plate, the plurality of wire bonds 220 a -220 d Can be wire bonded 220 a -220 d The first bonding pad 206a of the capacitor die 204a is coupled to the first power contact pad 116a2, and the plurality of wire bonds 220 e -220 hA second bonding pad 206b may be coupled between the second power contact pad 116b2 to reduce the inductance of such a long wire bond connection. In fact, by selectively controlling the number of wire bonds 220 coupled between the bonding pad 206 of the capacitor die 204a and the first power contact pad 116a2 and the second power contact pad 116b2, the inductance of the wire bonds 220 may be tuned to achieve a desired inductance value.

[0034] In an alternative embodiment (in Figure 2B1 In order to provide power to the die D9-D16, the first power bonding pad 114a on each of the die D9-D16 is connected to the first power bonding pad 114a by the wire bonding 120 S The second power pad 114b on each of the dies D9-D16 is coupled to each other via a wire bond 120 S The first power pad 114a on the die D13 is coupled to one or more of the first pads 206a of the capacitor die 204a, and the second power pad 114b on the die D13 is coupled to one or more of the second pads 206b of the capacitor die 204a. The first pad 206a of the capacitor die 204a is connected to the first pad 206a of the capacitor die 204a by the wire bonding 220. a -220 d The second bonding pad 206b of the capacitor die 204a is coupled to the first power contact pad 116a2 and is connected to the second power contact pad 206b of the capacitor die 204a by wire bonding 220 e -220 h Coupled to the second power contact pad 116b2. This configuration does not require wire bonding 120 M1 The first power pad 114a on the die D9 is coupled to the first power contact pad 116a2 and connected to the first power pad 116a2 by wire bonding 120. M2 The second power bond pad 114b on the die D9 is coupled to the second power contact pad 116b2.

[0035] As described above, in an embodiment, capacitor die 204a includes an integrated circuit capacitor having a first capacitor plate coupled to first bond pad 206a and a second capacitor plate coupled to second bond pad 206b. Fig.2C1 A simplified schematic diagram depicting an embodiment of a capacitor die 204a1 including two sets of first bonding pads 206a1-206a4, two sets of second bonding pads 206b1-206b4, and a single integrated circuit capacitor C B1, the integrated circuit capacitor has a first capacitor plate coupled to the first bonding pads 206a1-206a4 and a second capacitor plate coupled to the second bonding pads 206b1-206b4. In an embodiment, the first set of first bonding pads 206a1-206a4 and the first set of second bonding pads 206b1-206b4 are disposed adjacent to a first side of the capacitor die 204a1, and the second set of first bonding pads 206a1-206a4 and the second set of second bonding pads 206b1-206b4 are disposed adjacent to a second side of the capacitor die 204a1.

[0036] In this embodiment, capacitor die 204a1 has a fixed capacitor value (eg, C B1 = C), and the number of wire bonds 220 coupled between the bonding pad 206 of the capacitor die 204a1 and the first power contact pad 116a2 and the second power contact pad 116b2 may be selectively selected to combine a fixed capacitor value C B1 =C tunes the inductance of the wire bond 220 to achieve a desired inductance value. In this embodiment, two sets of first bonding pads 206a1-206a4 and two sets of second bonding pads 206b1-206b4 are used to allow the wire bond 220 to be connected on either side of the capacitor die 204a. In other embodiments, a single set of first bonding pads 206a1-206a4 and a single set of second bonding pads 206b1-206b4 may be used, and / or more or less than eight first bonding pads 206a1-206a4 and eight second bonding pads 206b1-206b4 may be used.

[0037] Figure 2C2 A simplified schematic diagram depicting an embodiment of a capacitor die 204a2 that includes two sets of first bonding pads 206a1-206a4, two sets of second bonding pads 206b1-206b4, and a single integrated circuit capacitor C B1 , the integrated circuit capacitor has a first capacitor plate coupled to two groups of first bonding pads 206a1-206a4 and a second capacitor plate coupled to two groups of second bonding pads 206b1-206b4. In this embodiment, the first bonding pads 206a1-206a4 alternate with the second bonding pads 206b1-206b4. In an embodiment, the first group of first bonding pads 206a1-206a4 and the first group of second bonding pads 206b1-206b4 are disposed adjacent to a first side of the capacitor die 204a2, and the second group of first bonding pads 206a1-206a4 and the second group of second bonding pads 206b1-206b4 are disposed adjacent to a second side of the capacitor die 204a2.

[0038] In this embodiment, capacitor die 204a2 has a fixed capacitor value (eg, C B1=C), and the number of wire bonds 220 coupled between the bonding pad 206 of the capacitor die 204a2 and the first power contact pad 116a2 and the second power contact pad 116b2 may be selectively selected to combine a fixed capacitor value C B1 =C tunes the inductance of wire bond 220 to achieve a desired inductance value. In other embodiments, a single set of first bonding pads 206a1-206a4 and a single set of second bonding pads 206b1-206b4 may be used, and / or more or less than eight first bonding pads 206a1-206a4 and eight second bonding pads 206b1-206b4 may be used.

[0039] Figure 2C3 A simplified schematic diagram depicting an embodiment of a capacitor die 204a3 comprising first bonding pads 206a1-206a4; second bonding pads 206b1-206b4; third bonding pads 206c1-206c4; fourth bonding pads 206d1-206d4; a first integrated circuit capacitor C B1a , which has a first capacitor plate coupled to the first bonding pads 206a1-206a4 and a second capacitor plate coupled to the second bonding pads 206b1-206b4; and a second integrated circuit capacitor C B1b , which has a first capacitor plate coupled to third bonding pads 206c1-206c4 and a second capacitor plate coupled to fourth bonding pads 206d1-206d4. In an embodiment, first bonding pads 206a1-206a4 and second bonding pads 206b1-206b4 are disposed adjacent to a first side of capacitor die 204a3, and third bonding pads 206c1-206c4 and fourth bonding pads 206d1-206d4 are disposed adjacent to a second side of capacitor die 204a3.

[0040] In this embodiment, capacitor die 204a3 has a fixed capacitor value (eg, C B1a =C1, C B1b = C2), and the number of wire bonds 220 coupled between the bonding pad 206 of the capacitor die 204a3 and the first power contact pad 116a2 and the second power contact pad 116b2 may be selectively selected to combine a fixed capacitor value C B1a = C1 and C B1b = C2 tunes the inductance of wire bond 220 to achieve a desired inductance value. In an embodiment, C1 = C2, but in other embodiments, C1 and C2 may have different values.

[0041] Figure 2C4 A simplified schematic diagram depicting an embodiment of a capacitor die 204a4 comprising: a first integrated circuit capacitor C B1, which has a first capacitor plate coupled to the first bonding pad 206a1 and a second capacitor plate coupled to the second bonding pad 206b1; the second integrated circuit capacitor C B2 , which has a first capacitor plate coupled to the first bonding pad 206a2 and a second capacitor plate coupled to the second bonding pad 206b2; a third integrated circuit capacitor C B3 , which has a first capacitor plate coupled to the first bonding pad 206a3 and a second capacitor plate coupled to the second bonding pad 206b3; and a fourth integrated circuit capacitor C B4 , which has a first capacitor plate coupled to the first bonding pad 206a4 and a second capacitor plate coupled to the second bonding pad 206b4. In other embodiments, two sets of first bonding pads 206a and two second bonding pads 206b may be used.

[0042] In an embodiment, the integrated circuit capacitor C B1 -C B4 Each has the same value (for example, C B1 =C B2 =C B3 =C B4 = C), or may have a different value (e.g., C B1 =C, C B2 =2C, C B3 =4C, C B4 =8C), and a desired capacitor value may be selected by selectively coupling wire bonds to first bonding pads 206a1-206a4 and second bonding pads 206b1-206b4. For example, if C B1 =C, C B2 =2C, C B3 =4C, C B4 =8C, the capacitor die 204a4 can be selectively configured to provide capacitor values ​​of C, 2C, 3C, ..., 14C, 15C.

[0043] In an embodiment, the first bonding pads 206a1-206a4 and the second bonding pads 206b1-206b4 are each sized to accommodate multiple wire bonds, and the number of wire bonds 220 coupled between the bonding pad 206 of the capacitor die 204a4 and the first power contact pad 116a2 and the second power contact pad 116b2 can be selectively selected to tune the inductance of the wire bonds 220 to achieve the desired inductance value in combination with the optional capacitor values ​​C, 2C, 3C, ..., 14C, 15C. In this regard, both the capacitor and the inductance values ​​can be selected to achieve a low impedance distribution in the frequency domain required for the power delivery network. In other embodiments, two sets of first bonding pads 206a1-206a4 and two sets of second bonding pads 206b1-206b4 can be used.

[0044] Figure 2B2 yes Figure 2A 200b. In this embodiment, semiconductor device 200b includes capacitor die 204b, the capacitor die including an integrated circuit capacitor having a first capacitor plate (not shown) coupled to a first bonding pad 206a and a second capacitor plate (not shown) coupled to a second bonding pad 206b. In an embodiment, capacitor die 204b includes one first bonding pad 206a and one second bonding pad 206b, but more or less than one first bonding pad 206a and one second bonding pad 206b may be used. In an embodiment, first bonding pad 206a and second bonding pad 206b are each sized to accommodate multiple wire bonds (e.g., 2 or more wire bonds).

[0045] Through Figure 2B1 In order to provide power to the dies D9-D12 in the same manner as in the embodiment of the present invention, the first power supply pad 114a on each of the dies D13-D16 is connected to the dies D9-D12 by wire bonding 120. S The second power pad 114b on each of the dies D13-D16 is coupled to each other by wire bonding 120 S The first power pad 114a on the die D13 is coupled to the first pad 206a of the capacitor die 204b, the second power pad 114b on the die D13 is coupled to the second pad 206b of the capacitor die 204b, and the first pad 206a of the capacitor die 204b is connected to the first pad 206a of the capacitor die 204b through the wire bonding 220. a -220 d The second bonding pad 206b of the capacitor die 204b is coupled to the first power contact pad 116a2 and is connected to the second power contact pad 206b of the capacitor die 204b by wire bonding 220 e -220 h Coupled to the second power contact pad 116b2.

[0046] By virtue of these electrical connections, the integrated circuit capacitors of the capacitor die 204b are coupled in parallel across the first power bond pads 114a and the second power bond pads 114b of the dies D9-D12 and act as power bypass capacitors. Without wishing to be bound by any particular theory, it is believed that the capacitor die 204b may act as a bypass capacitor for the long wire bonds 220. a -220 d and wire bonding 220 e -220 hA nearby charge reservoir (e.g., a small battery) is provided to power the needs of the load (e.g., die D13-D16) and to reduce power supply noise and ground bounce.

[0047] Additionally, since capacitor die 204b includes bond pads 206a and 206b that are each sized to accommodate multiple wire bonds, multiple wire bonds 220 a -220 d Can be wire bonded 220 a -220 d The first bonding pad 206a of the capacitor die 204b is coupled to the first power contact pad 116a2, and the plurality of wire bonds 220 e -220 h A wire bond 220 may be coupled between the second bonding pad 206b and the second power contact pad 116b2 to reduce the inductance of such a long wire bond connection. In fact, by selectively controlling the number of wire bonds 220 coupled between the first bonding pad 206a and the second bonding pad 206b of the capacitor die 204b and the first power contact pad 116a2 and the second power contact pad 116b2, the inductance of the wire bonds 220 may be tuned to achieve a desired inductance value.

[0048] As described above, in an embodiment, capacitor die 204b includes an integrated circuit capacitor having a first capacitor plate coupled to first bond pad 206a and a second capacitor plate coupled to second bond pad 206b. Figure 2C5 A simplified schematic diagram depicting an embodiment of a capacitor die 204b1 including a first bonding pad 206a, a second bonding pad 206b, and a single integrated circuit capacitor C B1 , the integrated circuit capacitor has a first capacitor plate coupled to the first bonding pad 206a and a second capacitor plate coupled to the second bonding pad 206b. In an embodiment, the first bonding pad 206 and the second bonding pad 206b are disposed adjacent to the first side of the capacitor die 204a1 and the second side of the capacitor die 204a1.

[0049] In this embodiment, capacitor die 204b1 has a fixed capacitor value (eg, C B1 =C), and the number of wire bonds 220 coupled between the bonding pad 206 of the capacitor die 204b1 and the first power contact pad 116a2 and the second power contact pad 116b2 may be selectively selected to combine a fixed capacitor value C B1 =C tunes the inductance of the wire bond 220 to achieve a desired inductance value. In other embodiments, a single first bond pad 206a and a single second bond pad 206b may be used.

[0050] Figure 2C6 A simplified schematic diagram depicting another alternative embodiment of a capacitor die 204b2 comprising a first integrated circuit capacitor C B1 , the second integrated circuit capacitor C B2 , the third integrated circuit capacitor C B3 , the fourth integrated circuit capacitor C B4 , first bonding pad 206a, second bonding pad 206b2 and switches 212a-212d. The first integrated circuit capacitor C B1 The second integrated circuit capacitor C has a first capacitor plate coupled to the first bonding pad 206a and a second capacitor plate coupled to the second bonding pad 206b via the switch 212a. B2 The third integrated circuit capacitor C has a first capacitor plate coupled to the first bonding pad 206a and a second capacitor plate coupled to the second bonding pad 206b via the switch 212b. B3 The fourth integrated circuit capacitor C has a first capacitor plate coupled to the first bonding pad 206a and a second capacitor plate coupled to the second bonding pad 206b via the switch 212c. B4 There is a first capacitor plate coupled to the first bond pad 206a and a second capacitor plate coupled to the second bond pad 206b via switch 212d.

[0051] In an embodiment, the integrated circuit capacitor C B1 -C B4 Each has the same value (for example, C B1 =C B2 =C B3 =C B4 = C) or may have different values ​​(e.g., C B1 =C, C B2 =2C, C B3 =4C, C B4 =8C), and the first integrated circuit capacitor C can be connected by selectively configuring switches 212a-212d to B1 , the second integrated circuit capacitor C B2 , the third integrated circuit capacitor C B3 and the fourth integrated circuit capacitor C B4 The second capacitor plate is coupled to the second bonding pad 206b to select the desired capacitor value. For example, if C B1 =C, C B2 =2C, C B3 =4C, C B4 =8C, then capacitor die 204b2 may be selectively configured to provide capacitor values ​​of C, 2C, 3C, ..., 14C, 15C.

[0052] In addition, since the first bonding pad 206a and the second bonding pad 206b are individually sized to accommodate multiple wire bonds, the number of wire bonds 220 coupled between the first bonding pad 206a and the second bonding pad 206n of the capacitor die 204b2 and the first power contact pad 116a2 and the second power contact pad 116b2 can be selectively selected to tune the inductance of the wire bonds 220 in combination with the selectable capacitor values ​​C, 2C, 3C, ..., 14C, 15C to achieve the desired inductance value. In this regard, both the capacitor and the inductance values ​​can be selected to achieve a low impedance distribution in the frequency domain required for the power delivery network. In other embodiments, two first bonding pads 206a and two second bonding pads 206b can be used.

[0053] Figures 3A1-3E Various views depicting an embodiment of a capacitor die 300a that is Figure 2A The capacitor die 204, Figure 2B2 The capacitor die 204b and Figure 2C5 The capacitor die 300a includes an integrated circuit capacitor C B1 , the integrated circuit capacitor comprises a stack of alternating first conductive layers 302 and second conductive layers 304 separated by capacitor dielectric layers 306, all formed over a substrate 308 (eg, bulk silicon). First conductive bonding layer 302 B and the second conductive bonding layer 304 B Disposed over the stack of alternating first conductive layers 302 and second conductive layers 304 .

[0054] In an embodiment, the first conductive layer 302 forms an integrated circuit capacitor C B1 The first capacitor plate and the second conductive layer 304 constitute the integrated circuit capacitor C B1 A dielectric material layer 310 (eg, polyimide or other suitable dielectric material layer) is formed on the first conductive bonding layer 302. B and the second conductive bonding layer 304 B A dielectric material layer 312 (eg, SiO 2 or other suitable dielectric material) is disposed above the stack.

[0055] The first conductive layer 302, the second conductive layer 304, and the first conductive bonding layer 302 B and the second conductive bonding layer 304 BEach may include any suitable conductive material deposited by any suitable method (eg, CVD, PVD, etc.). In an embodiment, each first conductive layer 302 is about 20 nm of tungsten, each second conductive layer 304 is about 20 nm of tungsten, and each first conductive bonding layer 302 is about 20 nm of tungsten. B is about 20 nm of aluminum, and each second conductive bonding layer 304 B About 20 nm of aluminum. Other conductive layer materials and / or thicknesses may be used.

[0056] The capacitor dielectric layer 306 is a high-K dielectric material, such as SiN x , Ta2O5, Al2O3, ZrO2, HfO2, or other similar dielectric materials. In an embodiment, each capacitor dielectric layer 306 may be about 15 nm SiN x . Other dielectric materials and / or thicknesses may be used. The higher the dielectric constant and / or thinner the dielectric material used, the higher the capacitance. Therefore, dielectric material properties and thickness are two design parameters that will be considered for this design requirement. These parameters may also vary between layers in this multi-layer structure, providing further design flexibility.

[0057] The first conductive via 314 extends through the stack of the first conductive layer 302, the second conductive layer 304, and the capacitor dielectric layer 306, and is connected to the first conductive layer 302 and the first conductive bonding layer 302. B In this regard, the first conductive bonding layer 302 B Coupled to the integrated circuit capacitor C B1 The second conductive via 316 extends through the stack of the first conductive layer 302, the second conductive layer 304 and the capacitor dielectric layer 306 and is connected to the second conductive layer 304 and the second conductive bonding layer 304. B In this regard, the second conductive bonding layer 304 B Coupled to the integrated circuit capacitor C B1 The first conductive via 314 may be the same material as the first conductive layer 302, or may be a different conductive material. The second conductive via 316 may be the same material as the second conductive layer 304, or may be a different conductive material.

[0058] A dielectric spacer 318 (e.g., SiO2 or other suitable dielectric material) surrounds the first conductive via 314 and insulates the first conductive via 314 from the second conductive layer 304, and surrounds the second conductive via 316 and insulates the second conductive via 316 from the first conductive layer 302. The opening 320 in the dielectric material layer 310 exposes the first conductive bonding layer 302. B and the second conductive bonding layer 304B The exposed portions respectively form first bonding pads 302 BP and the second bonding pad 304 BP In an embodiment, the opening 320 has a rectangular shape, but other shapes may be used. In an embodiment, the first bonding pad 302 BP and the second bonding pad 304 BP The capacitor die 300a includes two first bonding pads 302. BP and two second bonding pads 304 BP In other embodiments, more or less than two first bonding pads 302 may be used. BP and two second bonding pads 304 BP .

[0059] For example, Figures 3F1-3J Various views depicting an embodiment of a capacitor die 300b that is Figure 2A The capacitor die 204 and Figure 2C2 The capacitor die 300b includes an integrated circuit capacitor C B1 and similar to Figures 3A1-3E The capacitor die 300a is similar to the capacitor die 300b, except that the first conductive vias 314 and the second conductive vias 316 are alternated on each side of the capacitor die 300b. In addition, the capacitor die 300b includes eight first bonding pads 302 BP and eight second bonding pads 304 BP In other embodiments, more or less than eight first bonding pads 302 may be used. BP and eight second bonding pads 304 BP .

[0060] Figure 3K1-3O Various views depicting an embodiment of a capacitor die 300c that is Figure 2A The capacitor die 204 and Figure 2C3 Capacitor die 300c is similar to Figures 3F1-3J The capacitor die 300b of FIG. 300a is a capacitor die 300b, but includes integrated circuit capacitors C on each side of the capacitor die 300b. B1a and C B1b Specifically, the capacitor die 300c includes: an integrated circuit capacitor C B1a , the integrated circuit capacitor comprising a first stack of alternating first conductive layers 302a and second conductive layers 304a separated by capacitor dielectric layers 306a, all of which are formed over a substrate 308; and an integrated circuit capacitor C B1b, the integrated circuit capacitor includes a second stack of alternating first conductive layers 302b and second conductive layers 304b separated by capacitor dielectric layers 306b, all formed over a substrate 308.

[0061] First conductive bonding layer 302a B and the second conductive bonding layer 304a B Disposed over the first stack of alternating first conductive layers 302a and second conductive layers 304a. First conductive bonding layer 302b B and the second conductive bonding layer 304b B Disposed over the second stack of alternating first conductive layers 302b and second conductive layers 304b. In an embodiment, a dielectric material layer 322 (e.g., SiO2 or other similar dielectric material) is disposed between first conductive layers 302a and 302b, between second conductive layers 304a and 304b, and between capacitor dielectric layers 306a and 306b.

[0062] In an embodiment, the first conductive layer 302a constitutes an integrated circuit capacitor C B1a The first capacitor plate and the second conductive layer 304a constitute the integrated circuit capacitor C B1a The second capacitor plate of the integrated circuit and the first conductive layer 302b constitute the integrated circuit capacitor C B1b The first capacitor plate and the second conductive layer 304b constitute the integrated circuit capacitor C B1b of the second capacitor plate.

[0063] The first conductive layer 302a-302b, the second conductive layer 304a-304b, the first conductive bonding layer 302a B -302b B and the second conductive bonding layer 304a B -304b B Each may include any suitable conductive material deposited by any suitable method (e.g., CVD, PVD, etc.). In an embodiment, each first conductive layer 302a-302b is about 20nm of tungsten, each second conductive layer 304a-304b is about 20nm of tungsten, and each first conductive bonding layer 302a B -302b B is about 20 nm of aluminum, and each second conductive bonding layer 304a B -304a B About 20 nm of aluminum. Other conductive layer materials and / or thicknesses may be used.

[0064] The capacitor dielectric layers 306a-306b are high-K dielectric materials, such as SiN x, Ta2O5, Al2O3, ZrO2, HfO2, or other similar dielectric materials. In an embodiment, each capacitor dielectric layer 306a-306b may be about 15nm SiN x . Other dielectric materials and / or thicknesses may be used. The higher the dielectric constant and / or thinner the dielectric material used, the higher the capacitance. Therefore, dielectric material properties and thickness are two design parameters that will be considered for this design requirement. These parameters may also vary between layers in this multi-layer structure, providing further design flexibility.

[0065] The first conductive via 314a extends through the first stack of the first conductive layer 302a and the second conductive layer 304a and the capacitor dielectric layer 306a and is connected to the first conductive layer 302a and the first conductive bonding layer 302a. B In this regard, the first conductive bonding layer 302a B Coupled to the integrated circuit capacitor C B1a The second conductive via 316a extends through the first stack of the first conductive layer 302a, the second conductive layer 304a and the capacitor dielectric layer 306a and is connected to the second conductive layer 304a and the second conductive bonding layer 304a. B In this regard, the second conductive bonding layer 304a B Coupled to the integrated circuit capacitor C B1a The first conductive via 314a may be the same material as the first conductive layer 302a, or may be a different conductive material. The second conductive via 316a may be the same material as the second conductive layer 304a, or may be a different conductive material.

[0066] The opening 320a in the dielectric material layer 310 exposes the first conductive bonding layer 302a. B and the second conductive bonding layer 304a B The exposed portions respectively form first bonding pads 302a. BP and the second bonding pad 304a BP In an embodiment, the opening 320a has a rectangular shape, but other shapes may be used.

[0067] The first conductive via 314b extends through the second stack of the first conductive layer 302b and the second conductive layer 304b and the capacitor dielectric layer 306b and is connected to the first conductive layer 302b and the first conductive bonding layer 302b. B In this regard, the first conductive bonding layer 302b B Coupled to the integrated circuit capacitor C B1bThe second conductive via 316b extends through the second stack of the first conductive layer 302b and the second conductive layer 304b and the capacitor dielectric layer 306b and is connected to the second conductive layer 304b and the second conductive bonding layer 304b. B In this regard, the second conductive bonding layer 304b B Coupled to the integrated circuit capacitor C B1b The first conductive via 314b may be the same material as the first conductive layer 302b, or may be a different conductive material. The second conductive via 316b may be the same material as the second conductive layer 304b, or may be a different conductive material.

[0068] The opening 320b in the dielectric material layer 310 exposes the first conductive bonding layer 302b. B and the second conductive bonding layer 304b B The exposed portions respectively form first bonding pads 302b BP and the second bonding pad 304b BP In an embodiment, the opening 320b has a rectangular shape, but other shapes may be used.

[0069] Figure 3P1-3T Various views depicting an embodiment of a capacitor die 300d that is Figure 2A The capacitor die 300d is similar to the capacitor die 204 of FIG. Figure 3K1-3O The capacitor die 300c, however, contains four integrated circuit capacitors: C B1a , C B1b , C B1c and C B1d Specifically, the capacitor die 300d includes: an integrated circuit capacitor C B1a , which comprises a first stack of alternating first conductive layers 302a and second conductive layers 304a separated by capacitor dielectric layers 306a; an integrated circuit capacitor C B1b , which comprises a second stack of alternating first conductive layers 302b and second conductive layers 304b separated by capacitor dielectric layers 306b; an integrated circuit capacitor C B1c , which includes a third stack of alternating first conductive layers 302c and second conductive layers 304c separated by capacitor dielectric layers 306c; and an integrated circuit capacitor C B1d , which includes a fourth stack of alternating first conductive 302d and second conductive layers 304d separated by capacitor dielectric layers 306d, all of which are formed over a substrate 308.

[0070] First conductive bonding layer 302a Band the second conductive bonding layer 304a B Disposed over the first stack of alternating first conductive layers 302a and second conductive layers 304a. First conductive bonding layer 302b B and the second conductive bonding layer 304b B Disposed over the second stack of alternating first conductive layers 302b and second conductive layers 304b. First conductive bonding layer 302c B and the second conductive bonding layer 304c B The first conductive bonding layer 302d is disposed above the third stack of alternating first conductive layers 302c and second conductive layers 304c. B and the second conductive bonding layer 304d B Disposed over the fourth stack of alternating first conductive layers 302d and second conductive layers 304d. In an embodiment, a dielectric material layer 322 is disposed between the first conductive layers 302a, 302b, 302c, and 302d, between the second conductive layers 304a, 304b, 304c, and 304d, and between the capacitor dielectric layers 306a, 306b, 306c, and 306d.

[0071] In an embodiment, the first conductive layer 302a constitutes an integrated circuit capacitor C B1a The first capacitor plate and the second conductive layer 304a constitute the integrated circuit capacitor C B1a The first conductive layer 302b constitutes the integrated circuit capacitor C B1b The first capacitor plate and the second conductive layer 304b constitute the integrated circuit capacitor C B1b The first conductive layer 302c constitutes the integrated circuit capacitor C B1c The first capacitor plate and the second conductive layer 304c constitute the integrated circuit capacitor C B1c The second capacitor plate of the integrated circuit capacitor C B1d The first capacitor plate and the second conductive layer 304d constitute the integrated circuit capacitor C B1d of the second capacitor plate.

[0072] The first conductive layer 302a-302b, the second conductive layer 304a-304b, the first conductive bonding layer 302a B -302d B and the second conductive bonding layer 304a B -304d BEach may include any suitable conductive material deposited by any suitable method (e.g., CVD, PVD, etc.). In an embodiment, each first conductive layer 302a-302d is about 20nm of tungsten, each second conductive layer 304a-304d is about 20nm of tungsten, and each first conductive bonding layer 302a B -302d B is about 20 nm of aluminum, and each second conductive bonding layer 304a B -304d B About 20 nm of aluminum. Other conductive layer materials and / or thicknesses may be used.

[0073] The capacitor dielectric layers 306a-306d are high-K dielectric materials, such as SiN x , Ta2O5, Al2O3, ZrO2, HfO2, or other similar dielectric materials. In an embodiment, each capacitor dielectric layer 306a-306d may be about 10nm SiN x . Other dielectric materials and / or thicknesses may be used. The higher the dielectric constant and / or thinner the dielectric material used, the higher the capacitance. Therefore, dielectric material properties and thickness are two design parameters that will be considered for this design requirement. These parameters may also vary between layers in this multi-layer structure, providing further design flexibility.

[0074] The first conductive via 314a extends through the first stack of the first conductive layer 302a and the second conductive layer 304a and the capacitor dielectric layer 306a and is connected to the first conductive layer 302a and the first conductive bonding layer 302a. B In this regard, the first conductive bonding layer 302a B Coupled to the integrated circuit capacitor C B1a The second conductive via 316a extends through the first stack of the first conductive layer 302a and the second conductive layer 304a and the capacitor dielectric layer 306a and is connected to the second conductive layer 304a and the second conductive bonding layer 304a. B In this regard, the second conductive bonding layer 304a B Coupled to the integrated circuit capacitor C B1a The first conductive via 314a may be the same material as the first conductive layer 302a, or may be a different conductive material. The second conductive via 316a may be the same material as the second conductive layer 304a, or may be a different conductive material.

[0075] The opening 320a in the dielectric material layer 310 exposes the first conductive bonding layer 302a. B and the second conductive bonding layer 304a BThe exposed portions respectively form first bonding pads 302a. BP and the second bonding pad 304a BP In an embodiment, the opening 320a has a rectangular shape, but other shapes may be used.

[0076] The first conductive via 314b extends through the second stack of the first conductive layer 302b and the second conductive layer 304b and the capacitor dielectric layer 306b and is connected to the first conductive layer 302b and the first conductive bonding layer 302b. B In this regard, the first conductive bonding layer 302b B Coupled to the integrated circuit capacitor C B1b The second conductive via 316b extends through the second stack of the first conductive layer 302b and the second conductive layer 304b and the capacitor dielectric layer 306b and is connected to the second conductive layer 304b and the second conductive bonding layer 304b. B In this regard, the second conductive bonding layer 304b B Coupled to the integrated circuit capacitor C B1b The first conductive via 314b may be the same material as the first conductive layer 302b, or may be a different conductive material. The second conductive via 316b may be the same material as the second conductive layer 304b, or may be a different conductive material.

[0077] The opening 320b in the dielectric material layer 310 exposes the first conductive bonding layer 302b. B and the second conductive bonding layer 304b B The exposed portions respectively form first bonding pads 302b BP and the second bonding pad 304b BP In an embodiment, the opening 320b has a rectangular shape, but other shapes may be used.

[0078] The first conductive via 314c extends through the third stack of the first conductive layer 302c and the second conductive layer 304c and the capacitor dielectric layer 306c and is connected to the first conductive layer 302c and the first conductive bonding layer 302c. B In this regard, the first conductive bonding layer 302c B Coupled to the integrated circuit capacitor C B1c The second conductive via 316c extends through the third stack of the first conductive layer 302c and the second conductive layer 304c and the capacitor dielectric layer 306c and is connected to the second conductive layer 304c and the second conductive bonding layer 304c. B In this regard, the second conductive bonding layer 304c B Coupled to the integrated circuit capacitor CB1c The first conductive via 314c may be the same material as the first conductive layer 302c, or may be a different conductive material. The second conductive via 316c may be the same material as the second conductive layer 304c, or may be a different conductive material.

[0079] The opening 320c in the dielectric material layer 310 exposes the first conductive bonding layer 302c. B and the second conductive bonding layer 304c B The exposed portions respectively form first bonding pads 302c BP and the second bonding pad 304c BP In an embodiment, the opening 320c has a rectangular shape, but other shapes may be used.

[0080] The first conductive via 314d extends through the fourth stack of the first conductive layer 302d and the second conductive layer 304d and the capacitor dielectric layer 306d and is connected to the first conductive layer 302d and the first conductive bonding layer 302d. B In this regard, the first conductive bonding layer 302d B Coupled to the integrated circuit capacitor C B1d The second conductive via 316d extends through the fourth stack of the first conductive layer 302d and the second conductive layer 304d and the capacitor dielectric layer 306d and is connected to the second conductive layer 304d and the second conductive bonding layer 304d. B In this regard, the second conductive bonding layer 304d B Coupled to the integrated circuit capacitor C B1d The first conductive via 314d may be the same material as the first conductive layer 302d, or may be a different conductive material. The second conductive via 316d may be the same material as the second conductive layer 304d, or may be a different conductive material.

[0081] The opening 320d in the dielectric material layer 310 exposes the first conductive bonding layer 302d. B and the second conductive bonding layer 304d B The exposed portions respectively form first bonding pads 302d BP and the second bonding pad 304d BP In an embodiment, the opening 320b has a rectangular shape, but other shapes may be used.

[0082] Figure 4A is a simplified diagram of a top view of a capacitor die 400a, which is Figure 2A The capacitor die 400a includes six integrated circuit capacitors CB1a , C B1b ,……,C B1f , but more or less than six integrated circuit capacitors may be used. Integrated circuit capacitors C B1a , C B1b ,……,C B1f Each of includes two or more bond pads 206 coupled to first and second capacitor plates of a corresponding integrated circuit capacitor.

[0083] In this example embodiment, capacitor die 400a includes preconfigured capacitor values. For example, integrated circuit capacitor C B1a and C B1b is a 10μF capacitor, the integrated circuit capacitor C B1b and C B1e is a 2.2μF capacitor, and the integrated circuit capacitor C B1c and C B1f is a 4.7 μF capacitor. Other capacitor values ​​may be used. In addition, capacitor die 400a may optionally include an on-chip termination resistor R T , the on-chip termination resistor can be used to terminate Figure 2A signals in the semiconductor device 200 (eg, high-speed, high-performance signals such as input / output signals).

[0084] Figure 4B is a simplified diagram of a top view of a capacitor die 400b, which is Figure 2A The capacitor die 400b includes ten integrated circuit capacitors C B1a , C B1b ,……,C B1j , but more or less than ten integrated circuit capacitors may be used. Integrated circuit capacitor C B1a , C B1b ,……,C B1j Each of includes two (or more than two) bond pads 206 coupled to first and second capacitor plates of a corresponding integrated circuit capacitor.

[0085] In this example embodiment, capacitor die 400b includes repeatable unit capacitor values ​​that can be combined as needed to achieve a desired capacitor value. B1a , C B1b ,……,C B1jEach of the capacitors may be a 1 μF capacitor, which may be selectively coupled to achieve a desired capacitor value. Other capacitor values ​​may be used. In other embodiments, capacitor die 400b may include a combination of preconfigured capacitor values ​​and unit capacitor values. Additionally, capacitor die 400b may optionally include an on-chip termination resistor R T , the on-chip termination resistor can be used to terminate Figure 2A signals in the semiconductor device 200.

[0086] One embodiment includes an apparatus comprising: a die stack having a first die and a second die disposed above a substrate; and a capacitor die disposed between the first die and the second die in the die stack. The capacitor die includes a plurality of integrated circuit capacitors configured to selectively couple together to form a desired capacitor value coupled to at least one of the first die and the second die.

[0087] One embodiment includes an apparatus comprising: a die stack comprising a plurality of dies disposed above a substrate; and a capacitor die disposed in the die stack. The capacitor die comprises an integrated circuit capacitor and a bonding pad configured to accommodate a plurality of wire bonds.

[0088] One embodiment includes a method, the method comprising: placing a capacitor die in a die stack above a substrate, the capacitor die including a plurality of integrated circuit capacitors coupled to a bonding pad, the bonding pad being configured to accommodate a plurality of wire bonds, the substrate including a power contact pad; selectively coupling the plurality of integrated circuit capacitors to tune a capacitor value of the capacitor die; and selectively coupling the bonding pad to the power contact pad via a plurality of wire bonds to tune an inductance of the wire bonds.

[0089] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0090] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intermediate element. When an element is referred to as being directly connected to another element, there are no intermediate elements between the element and the other element. Two devices "communicate" if they are connected, directly or indirectly, so that the two devices can transmit electronic signals between them.

[0091] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0092] For the purposes of this document, the use of numerical terms such as a “first” object, a “second” object, and a “third” object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0093] For the purposes of this document, the term "set" of objects may refer to a "set" of one or more of the objects.

[0094] For the purposes of this document, the terms "top" and "bottom", "upper" and "lower", and "vertical" and "horizontal" as may be used herein are for example and illustrative purposes only, and are not intended to limit the description of the technology, as the items mentioned may exchange positions and orientations. In addition, as used herein, the terms "substantially", "approximately", and / or "approximately" indicate that for a given application, a particular dimension or parameter may vary within an acceptable manufacturing tolerance. In an embodiment, the acceptable manufacturing tolerance is ±.25%. As used herein, the term "semiconductor die" or simply "die" may refer to one or more semiconductor dies.

[0095] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. In view of the above teachings, many modifications and variations are possible. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize the technology in various embodiments and in various modifications suitable for the particular use contemplated. It is intended that the scope be defined by the appended claims.

Claims

1. A device, comprising: a die stack comprising a first die and a second die disposed over a substrate; as well as a capacitor die disposed between the first die and the second die in the die stack, wherein the capacitor die includes a plurality of integrated circuit capacitors configured to be selectively coupled together to form a desired capacitor value coupled to at least one of the first die and the second die, wherein the capacitor die further comprises a first plurality of bonding pads coupled to a first capacitor plate of the integrated circuit capacitor, and a second plurality of bonding pads coupled to a second capacitor plate of the integrated circuit capacitor, wherein the capacitor die further comprises a plurality of switches coupled to the plurality of integrated circuit capacitors, and Wherein the second capacitor plate is coupled to a bonding pad of the second plurality of bonding pads via a corresponding one of the plurality of switches.

2. The apparatus of claim 1, wherein the capacitor die further comprises a plurality of bond pads coupled to the integrated circuit capacitor, each bond pad being sized to accommodate a plurality of wire bonds.

3. The apparatus of claim 1, wherein the capacitor die further comprises a plurality of bond pads coupled to the integrated circuit capacitor, and wherein the apparatus further comprises a plurality of wire bonds coupled to the bond pads. 4 . The apparatus of claim 1 , wherein the first die comprises a power bond pad coupled to the capacitor die.

5. The apparatus of claim 1, wherein the substrate comprises a power contact pad coupled to the capacitor die.

6. The apparatus of claim 1, wherein the substrate comprises a first power contact pad coupled to a first bonding pad of the capacitor die through a first plurality of wire bonds, and a second power contact pad coupled to a second bonding pad of the capacitor die through a second plurality of wire bonds.

7. The apparatus of claim 1, wherein: Each of the plurality of integrated circuit capacitors is coupled to a corresponding pair of bond pads; and The bond pads are selectively coupled together to form the desired capacitor value.

8. The apparatus of claim 1, wherein: The plurality of switches are selectively configured to form the desired capacitor value.

9. The apparatus of claim 1, wherein the capacitor die comprises a power supply bypass capacitor.

10. The apparatus of claim 1, wherein the capacitor die comprises the same dimensions as dimensions of the first die and the second die.

11. The apparatus of claim 1, wherein the capacitor die comprises a first set of first bonding pads and a first set of second bonding pads disposed adjacent to a first side of the capacitor die, and a second set of first bonding pads and a second set of second bonding pads disposed adjacent to a second side of the capacitor die.

12. A device, comprising: a die stack comprising a plurality of dies disposed over a substrate; as well as a capacitor die disposed in the die stack and comprising a plurality of integrated circuit capacitors, each integrated circuit capacitor comprising a first capacitor plate coupled to a first bond pad and a second capacitor plate coupled to a second bond pad via a corresponding one of a plurality of switches, Wherein the first bond pad and the second bond pad are configured to accommodate a plurality of wire bonds.

13. The apparatus of claim 12, wherein the plurality of switches are configured to selectively couple the integrated circuit capacitor to form a desired capacitor value.

14. The apparatus of claim 12, wherein: The die stack includes a die including a power supply bond pad coupled to the capacitor die bond pad by a first plurality of wire bonds; and The substrate includes power contact pads coupled to the capacitor die bond pads through a second plurality of wire bonds.

15. The apparatus of claim 12, wherein the capacitor die further comprises a resistor configured to terminate a signal.

16. A method comprising: placing a capacitor die in a die stack above a substrate, the capacitor die comprising a plurality of integrated circuit capacitors coupled to bond pads, the bond pads being configured to accommodate a plurality of wire bonds, the substrate comprising power contact pads; selectively coupling the plurality of integrated circuit capacitors to tune a capacitor value of the capacitor die; as well as The bond pad is selectively coupled to the power contact pad via a plurality of wire bonds to tune an inductance of the wire bonds.

17. The method of claim 16, further comprising selectively tuning the capacitor value of the capacitor die and the inductance of the wire bonds to reduce power supply noise at dies in the die stack.

18. The method of claim 16, further comprising selectively tuning the capacitor value of the capacitor die and the inductance of the wire bonds to form a low impedance profile in a target frequency range of a power delivery network including the power contact pad.

19. The method of claim 16, further comprising electrically coupling the bond pads of the capacitor die to power bond pads of a die in the die stack.

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