Devices including transistors and related methods, memory devices and electronic systems

Abstract

The present application relates to devices and related methods, memory devices and electronic systems including transistors. The device includes a first conductive structure and at least one transistor electrically connected to the first conductive structure. The at least one transistor includes a lower conductive contact coupled to the first conductive structure and a split body channel on the lower conductive contact. The split body channel includes a first semiconductor column and a second semiconductor column horizontally adjacent to the first semiconductor column. The at least one transistor also includes a gate structure horizontally inserted between the first semiconductor column and the second semiconductor column of the split body channel, and an upper conductive contact vertically covering the gate structure and coupled to the split body channel. Portions of the gate structure surround three sides of each of the first semiconductor column and the second semiconductor column.

Description

[0001] Priority claim

[0002] This application claims priority to the filing date of U.S. patent application serial number 16 / 869,339 filed on May 7, 2020, with the invention name "APPARATUSES INCLUDING TRANSISTORS, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS". Technical Field

[0003] Embodiments disclosed herein relate to microelectronic devices and microelectronic device manufacturing. More specifically, embodiments disclosed herein relate to a device including a transistor including a gate electrode and an opposing channel region adjacent to the gate electrode, to related memory devices and electronic systems, and to methods of forming the device. Background Art

[0004] Fabrication of the device structure includes forming a transistor that can be used to access a memory component, such as a memory cell of the device structure. The transistor includes a channel region that includes a semiconductor material that is formulated and configured to conduct current in response to application of a threshold voltage and to resist the flow of current in the absence of the threshold voltage.

[0005] In a device structure including a memory cell, a transistor associated with the memory cell (e.g., as an access device) may include a so-called vertical transistor, such as a vertical thin film transistor (TFT). Forming a vertical transistor typically includes stacking materials that will ultimately form the transistor of the memory cell, including source and drain contacts, a channel region, and gate electrode materials. The stacked materials may be patterned to form a columnar structure including the stacked materials.

[0006] The channel region of a transistor contains semiconductor material. However, the semiconductor materials used in many conventional transistors achieve high off-state current (I off ), which may affect charge retention, current flow, and other electrical characteristics of horizontally adjacent transistors. For example, when a horizontally adjacent transistor is accessed, a high off current of a transistor may affect (e.g., interfere with) the state of a horizontally adjacent transistor. Such semiconductor materials may exhibit a low threshold voltage (V TH), even when the transistor is scaled and includes so-called "dual-gate or double-gate" electrodes (e.g., two gate electrodes disposed around a central channel region), and thus requires a large negative voltage when the transistor is in an off state. Therefore, when memory cells are scaled down in size to increase the density of memory cells, the dual-gate electrodes disposed around the central channel region may not be sufficient to reduce leakage due to coupling capacitance between horizontally adjacent transistors. Summary of the invention

[0007] According to an embodiment of the present disclosure, a device includes a first conductive structure and at least one transistor electrically connected to the first conductive structure. The at least one transistor includes a lower conductive contact coupled to the first conductive structure and a split body channel on the lower conductive contact. The split body channel includes a first semiconductor column and a second semiconductor column horizontally adjacent to the first semiconductor column. The at least one transistor includes a gate structure horizontally inserted between the first semiconductor column and the second semiconductor column of the split body channel, and an upper conductive contact vertically covering the gate structure and coupled to the split body channel. Portions of the gate structure surround three sides of each of the first semiconductor column and the second semiconductor column.

[0008] According to an embodiment of the present disclosure, a method for forming a device structure is disclosed. The method includes: forming a conductive line extending in a first direction; forming a semiconductor column structure on the conductive line; horizontally forming a conductive material between at least two semiconductor column structures; forming an opening extending vertically through the semiconductor column structure and the conductive material to divide each of the at least two semiconductor column structures into two relatively smaller semiconductor column structures, and forming a gate structure from the conductive material; and at least partially filling the opening with a dielectric material. The central portion of the gate structure extends in a second direction transverse to the first direction.

[0009] In addition, according to an embodiment of the present disclosure, a memory device includes a memory cell, which includes an access device electrically coupled to a memory element. The access device includes a conductive material, which includes an elongated portion extending in one direction and a lateral protrusion extending in another direction substantially transverse to the direction, a first channel region adjacent to a first side of the conductive material, and a second channel region adjacent to a second side of the conductive material. The second side is opposite to the first side. The access device includes a gate dielectric between the first channel region and the conductive material and between the second channel region and the conductive material.

[0010] According to an additional embodiment of the present disclosure, an electronic system includes at least one input device, at least one output device, at least one processor device operably coupled to the at least one input device and the at least one output device, and a memory device operably coupled to the at least one processor device. The memory device includes a transistor array. At least one transistor of the transistor array includes a gate structure covering a conductive contact, a first pillar structure horizontally adjacent to a first lateral side of the gate structure, and a second pillar structure horizontally adjacent to a second lateral side of the gate structure opposite to the first lateral side. The gate structure is located between the first pillar structure and the second pillar structure. The at least one transistor includes a passivation material that is adjacent to each of the first pillar structure and the second pillar structure on a side opposite to the gate structure. The passivation material is in direct physical contact with a portion of the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a simplified cross-sectional perspective view of a device including a transistor according to an embodiment of the present disclosure;

[0012] Figure 1B It is along Figure 1A The section line BB is cut Figure 1A A simplified top cross-sectional view of a device;

[0013] Figures 2A to 2K A method of forming a device according to an embodiment of the present disclosure is shown;

[0014] Figure 3 It is used for comparison with the traditional device structure Figure 1A and 1B A simplified top cross-sectional view of a portion of a device;

[0015] Figure 4 is a functional block diagram of a memory device according to an embodiment of the present disclosure; and

[0016] Figure 5 is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] A device (e.g., a microelectronic device, a semiconductor device, a memory device) is disclosed, which includes a first conductive line, a second conductive line, and a vertical transistor between the first conductive line and the second conductive line. The single transistor includes two channel regions and a gate structure (e.g., a gate electrode) horizontally inserted between the two channel regions. The two channel regions of the single transistor can be considered to be "separated" by the gate electrode. The gate electrode surrounds three sides of each of the two channel regions of the single transistor. The gate electrode surrounding each of the two channel regions of the transistor can allow for increased gate performance and reduced leakage due to coupling capacitance between horizontally adjacent transistors of the device. Using a single (e.g., only one) gate electrode between the two channel regions allows the gate electrode to have a greater thickness than the gate electrode of a conventional transistor (e.g., a transistor exhibiting a so-called "dual gate" configuration), while the spacing between horizontally adjacent transistors can be substantially the same as that of a conventional transistor. In addition, the relatively large thickness of the gate electrode increases its area, thereby reducing the resistance of the gate electrode compared to the conventional gate electrode configuration, to provide enhanced performance in microelectronic device structures (e.g., DRAM device structures, such as DRAM cells), microelectronic devices (e.g., DRAM devices), and electronic systems that rely on high feature density. The device may also include a passivation material on the side of each of the two channel regions opposite the gate electrode. In some embodiments, a conductive material (e.g., a shielding material) is located between adjacent transistors and may be configured to be electrically biased. Biasing the conductive material may reduce or prevent so-called "word line interference," in which the gate electrode of one transistor affects the gate electrode of an adjacent transistor when a voltage is applied to the transistor.

[0018] The following description provides specific details, such as material composition and processing conditions, in order to provide a comprehensive description of the disclosed embodiments. However, it will be appreciated by those skilled in the art that the disclosed embodiments may be implemented without these specific details. In fact, the disclosed embodiments may be implemented in conjunction with conventional manufacturing techniques employed in the semiconductor industry. In addition, the description provided below does not form a complete process flow for manufacturing equipment. The structures described below cannot form a complete microelectronic device. Only those process stages (e.g., actions) and structures necessary for understanding the disclosed embodiments are described in detail below. Additional stages for forming a complete microelectronic device may be performed by conventional manufacturing techniques.

[0019] The materials described herein may be formed by conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced ALD, or physical vapor deposition (PVD). Alternatively, the material may be grown in situ. Depending on the particular material to be formed, one of ordinary skill in the art may select a technique for depositing or growing the material. Removal of material may be accomplished by any suitable technique, including but not limited to etching, grinding planarization (e.g., chemical mechanical planarization), or other known methods, unless the context indicates otherwise.

[0020] The drawings given herein are for illustrative purposes only and are not meant to be actual views of any particular material, component, structure, device or system. As a result of, for example, manufacturing techniques and / or tolerances, variations in the shapes depicted in the figures are to be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes or regions shown, but rather include shape deviations, for example, caused by manufacturing. For example, a box-shaped region shown or described may have rough and / or nonlinear features, and a circular region shown or described may include some rough and / or linear features. In addition, the sharp angles shown may be rounded, and vice versa. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the region, and do not limit the scope of the present claims. The drawings are not necessarily drawn to scale. Additionally, elements shared between the drawings may retain the same numerical designations.

[0021] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0022] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] As used herein, "about" or "approximately" with respect to a numerical value of a particular parameter includes the numerical value and a degree of deviation from the numerical value, which degree of deviation will be understood by those of ordinary skill in the art to be within an acceptable tolerance range for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​within the range of 90.0% to 110.0% of the numerical value, such as within the range of 95.0% to 105.0% of the numerical value, within the range of 97.5% to 102.5% of the numerical value, within the range of 99.0% to 101.0% of the numerical value, within the range of 99.5% to 100.5% of the numerical value, or within the range of 99.9% to 100.1% of the numerical value.

[0024] As used herein, spatially relative terms, such as "below", "below", "below", "bottom", "above", "above", "top", "front", "back", "left", "right", etc., can be used to facilitate the description of the relationship of one element or feature to another element or feature shown in the figure. Unless otherwise stated, spatially relative terms are intended to include different orientations of materials other than the orientation depicted in the figure. For example, if the material in the figure is inverted, the element described as being "below" or "below" or "below" or "bottom" of other elements or features will be oriented as being "above" or "top" of other elements or features. Therefore, the term "below" can include both above and below orientations, depending on the context in which the term is used, which is obvious to one of ordinary skill in the art. The material can be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein are interpreted accordingly.

[0025] As used herein, the terms "vertical", "longitudinal", "horizontal" and "transverse" refer to a principal plane of a structure, not necessarily defined by the Earth's gravitational field. A "horizontal" or "transverse" direction is a direction substantially parallel to a principal plane of a structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to a principal plane of a structure. A principal plane of a structure is defined by a surface of the structure that has a relatively large area compared to other surfaces of the structure.

[0026] As used herein, the term "configured" refers to the size, shape, orientation, and arrangement of one or more of at least one structure and at least one device to facilitate operation of the one or more structures and devices in a predetermined manner.

[0027] As used herein, the term "pitch" refers to the distance between the same points in two adjacent (eg, neighboring) features.

[0028] As used herein, referring to an element as being "on" or "above" another element means and includes the element being directly on top of another element, directly adjacent to another element (e.g., directly laterally adjacent to another element, directly vertically adjacent to another element), directly below another element, or in direct contact with another element. It also includes the element being indirectly on top of another element, indirectly adjacent to another element (e.g., indirectly laterally adjacent to another element, indirectly vertically adjacent to another element), indirectly below or near another element, and with other elements between them. In contrast, when an element is referred to as being "directly on" or "directly adjacent to" another element, there are no intervening elements.

[0029] As used herein, features (e.g., regions, materials, structures, devices) described as being "adjacent" to one another refer to and include features of a disclosed identity (or identities) that are closest to one another (e.g., closest). Additional features (e.g., additional regions, additional materials, additional structures, additional devices) that do not match the disclosed identity (or identities) of the "adjacent" feature may be disposed between the "adjacent" features. In other words, the "adjacent" features may be positioned directly adjacent to one another, such that no other features intervene between the "adjacent" features; or the "adjacent" features may be positioned indirectly adjacent to one another, such that at least one feature having an identity different from that associated with at least one "adjacent" feature is located between the "adjacent" features. Thus, features described as being "vertically adjacent" to one another refer to and include features of a disclosed identity (or identities) that are closest to one another in the vertical direction (e.g., closest in the vertical direction). Additionally, features described as being "horizontally adjacent" to one another refer to and include features of a disclosed identity (or identities) that are closest to one another in the horizontal direction (e.g., closest in the horizontal direction).

[0030] As used herein, the term "memory device" refers to and includes a microelectronic device that exhibits memory functionality, but is not necessarily limited to memory functionality. In other words, and by way of example only, the term "memory device" refers to and includes not only traditional memory (e.g., traditional volatile memory, such as traditional dynamic random access memory (DRAM); traditional non-volatile memory, such as traditional NAND memory), but also includes application specific integrated circuits (ASICs) (e.g., system on chip (SoC)), microelectronic devices that combine logic and memory, and graphics processing units (GPUs) that combine memory.

[0031] The term "conductive material" as used herein refers to and includes a material comprising one or more of the following: at least one metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); at least one alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloys, Co and Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel); at least one conductive doped semiconductor material (conductively doped polysilicon, conductively doped germanium (Ge), conductively doped silicon germanium (SiGe)); and at least one conductive metal-containing material (for example, conductive metal nitrides, such as one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN) and titanium aluminum nitride (TiAlN); conductive metal silicides; conductive metal carbides; conductive metal oxides, such as one or more of iridium oxide (IrO) and ruthenium oxide (RuO)).

[0032] As used herein, the term "electrically insulating material" refers to and includes at least one dielectric material, such as at least one dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x ), zirconium oxide (ZrO x ), tantalum oxide (TaO x ) and magnesium oxide (MgO x ), at least one dielectric nitride material (e.g., silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y )) and at least one dielectric carboxyl nitride material (e.g., silicon carboxyl nitride (SiO x C z N y )). A formula (e.g., SiO x 、AlO x , HfO x、NbO x 、TiO x 、SiN y 、SiO x N y 、SiO x C z N y ) represents a material that contains an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of another element (if any) to each atom of the other element (e.g., Si, Al, Hf, Nb, Ti). Since the formula represents relative atomic proportions rather than strict chemical structures, the dielectric material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if any) may be integers or may be non-integers. As used herein, the term "non-stoichiometric compound" refers to and includes compounds whose elemental composition cannot be expressed in well-defined ratios of natural numbers and violates the laws of determining proportions.

[0033] As used herein, the phrase "coupled to" refers to structures that are operably connected to each other, such as by a direct ohmic connection or by an indirect connection (eg, electrically via another structure).

[0034] As used herein, the term "substantially" with respect to a given parameter, property, or condition refers to and encompasses the degree to which one of ordinary skill in the art would understand that a given parameter, property, or condition is met to a certain degree of variation, such as within an acceptable tolerance. As an example, depending on the particular parameter, property, or condition being substantially met, the parameter, property, or condition may be met by at least 90.0%, met by at least 95.0%, met by at least 99.0%, met by at least 99.9%, or even met by 100.0%.

[0035] As used herein, the term "substrate" refers to and includes a material (e.g., base material) or structure on which additional materials are formed. The substrate may be a semiconductor substrate, a base semiconductor material on a support structure, a metal electrode, or a semiconductor substrate on which one or more materials, layers, structures, or regions are formed. The materials on the semiconductor substrate may include, but are not limited to, semiconductor materials, insulating materials, conductive materials, and the like. The substrate may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer. As used herein, the term "bulk substrate" refers to and includes not only silicon wafers, but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates, silicon epitaxial layers on base semiconductor substrates, and other semiconductor or optoelectronic materials, such as silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped.

[0036] Figure 1A is a simplified cross-sectional perspective view of a microelectronic device structure 100 of a microelectronic device (eg, a memory device) according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A The section line BB is cut Figure 1A 1 is a simplified top cross-sectional view of a microelectronic device structure 100. The microelectronic device structure 100 includes a transistor 110 (e.g., an access device) on a base material 102. The base material 102 can be, for example, a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The base material 102 can be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material. The base material 102 can be doped or undoped.

[0037] refer to Figure 1A Combination Figure 1B , transistors 110 may be arranged in rows (e.g., extending in the X direction) and columns (e.g., extending in the Y direction). In some embodiments, the rows are substantially perpendicular to the columns. However, the present disclosure is not limited thereto, and transistors 110 may be arranged in different Figure 1A and Figure 1B The microelectronic device structure 100 may include, for example, any number of transistors 110, such as more than about 1,000 transistors 110, more than about 10,000 transistors 110, or more than about 100,000 transistors 110. For ease of description Figure 1A and 1B , the first direction can be defined as a direction, Figure 1A and 1B The second direction is transverse to (eg, perpendicular to) the first direction. Figure 1A and 1B The third direction, which is transverse to (eg, perpendicular to) each of the first direction and the second direction, may be defined as a direction (eg, a vertical direction), Figure 1A The Z direction is shown in FIG. Figures 2A to 2K As shown, similar directions can be defined, as discussed in more detail below.

[0038] like Figure 1AAs shown, the microelectronic device structure 100 can include a first conductive line 104 on at least a portion of a substrate material 102. In some embodiments, the first conductive line 104 is arranged in a row and extends in a first direction (e.g., an X direction) along the substrate material 102. The first conductive line 104 can be electrically connected to a single transistor 110 of a row of transistors 110. In some embodiments, the first conductive line 104 is used as a digital line (e.g., a data line, a bit line). In other embodiments, the first conductive line 104 is used as a source line.

[0039] First conductor 104 may be formed of and include at least one conductive material. In some embodiments, first conductor 104 is formed of and includes W. In other embodiments, first conductor 104 is formed of and includes Ru. Adjacent rows of first conductors 104 may be electrically insulated from each other, such as by electrically insulating material 106. In some embodiments, electrically insulating material 106 is formed of SiO2 and includes silicon dioxide.

[0040] Continue to refer Figure 1A Each of the transistors 110 may include a lower conductive contact 105, an upper conductive contact 114, a split body channel 116 (including a first channel region 116a and a second channel region 116b vertically located between the lower conductive contact 105 and the upper conductive contact 114), and a gate electrode structure 108 (horizontally inserted between the first channel region 116a and the second channel region 116b of the split body channel 116 and surrounded by a gate dielectric material 112 on at least some of its sides).

[0041] The lower conductive contact 105 may include, for example, a source contact or a drain contact. The lower conductive contact 105 of the transistor 110 may be electrically connected to the corresponding first conductive line 104. The lower conductive contact 105 may include a conductive material. In some embodiments, the lower conductive contact 105 is formed of and includes a material composition substantially the same as the first conductive line 104.

[0042] The electrically insulating material 106 may electrically insulate the lower conductive contacts 105 of some horizontally adjacent transistors 110. For clarity and ease of understanding of the drawings and the related description, Figure 1A , only two portions of the electrically insulating material 106 are shown between each of the first conductive lines 104 and an adjacent portion of the lower conductive contact 105. However, the present disclosure is not limited thereto, and additional portions of the electrically insulating material 106 may be included.

[0043] A channel region including a first channel region 116a (eg, a first semiconductor pillar) and a second channel region 116b (eg, a second semiconductor pillar) of the split body channel 116 may be laterally adjacent to the gate dielectric material 112. In some embodiments, as shown in FIG. Figure 1BAs shown, each of the first channel region 116a and the second channel region 116b is substantially surrounded by the gate dielectric material 112 on at least three sides. In other words, the gate dielectric material 112 can extend between the gate electrode structure 108 and the first channel region 116a and the second channel region 116b of the two adjacent (e.g., adjacent) split body channels 116. Each of the first channel region 116a and the second channel region 116b is formed of and includes a semiconductor material that is formulated and configured to respond to the application of a suitable voltage (e.g., a threshold voltage V) to the transistor 110 between the gate electrode structure 108 and the source region (e.g., the first conductive line 104). TH ) and exhibit conductivity. In some embodiments, each of the first channel region 116a and the second channel region 116b contacts the lower conductive contact 105 and extends along the sidewall of the gate dielectric material 112 to contact the upper conductive contact 114. Therefore, each of the first channel region 116a and the second channel region 116b can directly contact each of the lower conductive contact 105 and the upper conductive contact 114. The first channel region 116a and the second channel region 116b can each be electrically connected to each of the source region and the drain region of the transistor 110 associated with the first channel region 116a and the second channel region 116b.

[0044] As discussed above, each of the first channel region 116a and the second channel region 116b is formed of and includes a material that is configured to conduct current in response to application of a suitable voltage (e.g., a threshold voltage, a set bias voltage, a read bias voltage) to the transistor 110. In some embodiments, the first channel region 116a and the second channel region 116b include polycrystalline silicon (also referred to as "polysilicon") material. In other embodiments, the first channel region 116a and the second channel region 116b are formed of and include a semiconductor material having a larger band gap than polysilicon, such as a semiconductor material having a band gap greater than about 1.65 electron volts (eV), and may be referred to herein as a so-called "large band gap material". For example, each of the first channel region 116a and the second channel region 116b may be formed of and include an oxide semiconductor material, such as one or more of the following: zinc tin oxide (Zn 2O3); ... x Sn y O, commonly referred to as "ZTO"), indium zinc oxide (In x Zn y O, commonly referred to as "IZO"), zinc oxide (Zn x O), Indium Gallium Zinc Oxide (In xGa y Zn z O, commonly referred to as "IGZO"), indium gallium silicon oxide (In x Ga y Si z O, commonly referred to as "IGSO"), indium tungsten oxide (In x W y O, commonly referred to as "IWO"), indium oxide (In x O), tin oxide (Sn x O), titanium oxide (Ti x O), zinc oxide nitride (Zn x ON z ), magnesium zinc oxide (Mg x Zn y O), zirconium indium zinc oxide (Zr x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn x In y Zn z O), aluminum tin indium zinc oxide (Al x Sn y In z Zn a O), silicon indium zinc oxide (Si x In y Zn z O), aluminum zinc tin oxide (Al x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), zirconium zinc tin oxide (Zr x Zn y Sn z O) and other similar materials. A formula containing at least one of the above "x", "y", "z" and "a" (for example, Zn x Sn y O、In x Zn y O、In x Ga y Zn z O、In x W y O、In x Ga y Si z O、Al xSn y In z Zn a O) represents a composite material that contains an average ratio of "x" atoms of one element, "y" atoms of another element (if any), "z" atoms of another element (if any), and "d" atoms of another element (if any) to each oxygen atom (O) in one or more regions thereof. Since the formula represents a relative atomic ratio rather than a strict chemical structure, the channel region may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", "z" and "a" may be integers or may be non-integers. In some embodiments, the first channel region 116a and the second channel region 116b include IGZO. In some embodiments, the first channel region 116a and the second channel region 116b may have an In:Ga:Zn:O ratio of 1:1:1:4; may have an In2O3:Ga2O3:ZnO ratio of 2:2:1, or may be represented by the formula InGaO3(ZnO)5. In additional embodiments, the first channel region 116 a and the second channel region 116 b are formed of and include IGZO and IGSO.

[0045] In some embodiments, each of the first channel region 116a and the second channel region 116b includes a single material having a substantially uniform composition. In other embodiments, the first channel region 116a and the second channel region 116b include a composite structure that includes more than one semiconductor material (e.g., an oxide semiconductor material). The first channel region 116a and the second channel region 116b may also be so-called "multilayer" channel regions, including more than one semiconductor material. For example, the first channel region 116a and the second channel region 116b include two different semiconductor materials, three semiconductor materials, four semiconductor materials, five semiconductor materials, etc. For example, the material in the first channel region 116a and the second channel region 116b may show one or more atomic percentages of indium, gallium, and zirconium that are different from the adjacent channel materials. In addition, different channel materials may include the same elements as the adjacent channel materials, but may show different stoichiometry (and composition) from the adjacent channel materials. The materials of the first channel region 116a and the second channel region 116b in a single transistor 110 may be the same or different.

[0046] The thickness T3 of each of the discrete portions of the first channel region 116a and the second channel region 116b may be about 100 Å. to about Between, such as about to about Between, about to about Between, about to about Between, about to about Between, or about to about between.

[0047] In some such embodiments, a single transistor 110 may include a single gate electrode structure 108 and two discrete channel regions (e.g., a first channel region 116a and a second channel region 116b). The first channel region 116a and the second channel region 116b of the single transistor 110 may surround the gate electrode structure 108 and may be positioned adjacent to the gate electrode structure 108, such as on opposite sides of the gate electrode structure 108. In other words, the gate electrode structure 108 may be centrally located and extend around each of the first channel region 116a and the second channel region 116b of the respective transistor 110. Thus, each of the first channel region 116a and the second channel region 116b contacts the gate electrode structure 108 in a first plane (e.g., in the X direction) and in a second plane (e.g., in the Y direction) intersecting the first plane. The gate electrode structure 108 may be formed of and include a conductive material. In some embodiments, each gate electrode structure 108 is formed of and includes W or Ru.

[0048] The microelectronic device structure 100 may include a conductive contact 109 ( Figure 1B In some embodiments, each column of transistors 110 ( Figure 1A ) includes at least one conductive contact 109 electrically connected to the gate electrode structure 108 of its corresponding column. At least one conductive contact 109 (e.g., at least one conductive wiring structure) can be coupled to at least some of the gate electrode structures 108 and at least one other structure of the microelectronic device structure 100 and extend from between them. The conductive contact 109 is formed of and includes a conductive material. In some embodiments, the conductive contact 109 is formed of and includes a material composition substantially the same as the gate electrode structure 108. In other embodiments, the conductive contact 109 is formed of and includes a material different from the material of the gate electrode structure 108.

[0049] The conductive contact 109 may be in electrical communication with a voltage source configured to provide a suitable voltage (eg, a bias voltage) to the gate electrode structure 108 associated with the conductive contact 109. Figure 1B In FIG. 1 , only one conductive contact 109 is shown adjacent to one of the gate electrode structures 108 . However, the present disclosure is not limited thereto, and additional conductive contacts 109 may be included.

[0050] The gate dielectric material 112 may be disposed around at least some sides of the gate electrode structure 108. In some embodiments, the gate dielectric material 112 extends between the gate electrode structure 108 and the first channel region 116a and the second channel region 116b of the split body channel 116. In some such embodiments, the gate electrode structure 108 is substantially surrounded by dielectric material on all sides thereof (e.g., top, bottom, left, right, front, back, etc.). In other words, the gate dielectric material 112 may be horizontally located between the gate electrode structure 108 and three sides of each of the first channel region 116a and the second channel region 116b of the split body channel 116. As will be described herein, the gate dielectric material 112 may be located near the upper surface and / or sidewalls of the split body channel 116.

[0051] The gate dielectric material 112 may be formed of and include one or more electrically insulating materials. In some embodiments, the gate dielectric material 112 is formed of and includes silicon dioxide. In some embodiments, the gate dielectric material 112 is formed of and includes substantially the same material composition as the electrically insulating material 106.

[0052] The thickness of the gate dielectric material 112 may be about to about Between, such as about to about Between, about to about Between, about to about between, or about to about between.

[0053] The upper conductive contact 114 of the transistor 110 may cover the first channel region 116a and the second channel region 116b of the split body channel 116. In some embodiments, the upper conductive contact 114 vertically covers a portion of the gate electrode structure 108 and may be separated therefrom by an electrically insulating material (e.g., a gate dielectric material 112). In some embodiments, the upper conductive contact 114 includes, for example, one of the source contact or the drain contact of the transistor 110 (and the lower conductive contact 105 includes the other of the source contact or the drain contact). One or more dielectric materials (e.g., electrically insulating material 106, gate dielectric material 112, electrically insulating material 138) may be interposed vertically between the gate electrode structure 108 and the upper conductive contact 114, and horizontally between the gate electrode structure 108 and the upper conductive contact 114. The upper conductive contact 114 may include a conductive material. In some embodiments, the upper conductive contact 114 is formed of and includes substantially the same material composition as the lower conductive contact 105. In other embodiments, the upper conductive contact 114 is formed of and includes a different material composition than the lower conductive contact 105. Figure 1A , only two upper conductive contacts 114 are shown covering the first channel region 116a and the second channel region 116b of the split body channel 116. However, the present disclosure is not limited thereto, and additional upper conductive contacts 114 may be included.

[0054] The microelectronic device structure 100 may include a second conductive line 136 that serves as a gate electrode structure 108 of a single transistor 110 . Figure 1A A portion of the second conductive line 136 is shown, but it should be understood that in at least some embodiments, the second conductive line 136 extends in a second direction (eg, the Y direction) that is different from the first direction in which the first conductive line 104 extends. Figure 1B , the second conductive line 136 may include a central elongated portion 136a extending as a line extending in, for example, the Y direction and a lateral portion 136b extending away from the central elongated portion 136a in the X direction. In other words, the lateral portion 136b may extend between horizontally adjacent channel regions (e.g., the first channel region 116a and the second channel region 116b) of the split body channel 116, such as Figure 1B In other words, the second conductive line 136 may surround the split body channel 116 on at least three sides (eg, three adjacent sides). Figure 1A and 1BIn the illustrated embodiment, the transistor 110 including the configuration (e.g., shape) of the second conductive line 136 can be characterized as a so-called "triple-gate" transistor for a single device region 140. By using a tri-gate transistor, the device can achieve reliable gate control during use and operation.

[0055] The second conductor 136 is formed of and includes a conductive material. In some embodiments, the second conductor 136 is formed of and includes W or Ru. The conductive materials in the central elongated portion 136a and the lateral portion 136b can be the same or different. In some embodiments, the second conductor 136 is formed of and includes the same material composition as the first conductor 104. In other embodiments, the second conductor 136 is formed of and includes a different material composition than the first conductor 104.

[0056] The thickness T1 of the second conductive line 136 (eg, the combined portion of the central elongated portion 136a and the lateral portion 136b) may be about to about Between, such as about to about Between, about to about Between, about to about Between, or about to about The thickness T2 of the central elongated portion 136a (e.g., alone) of the second conductive line 136 may be between about to about Between, such as about to about Between, about to about Between, about to about Between, or about to about between.

[0057] Reference again Figure 1A and Figure 1B , the microelectronic device structure 100 may include a plurality of layers located in a second direction (eg, Figure 1A and 1BThe isolation region 122 in the opening 120 extends in the second direction (the Y direction in FIG. 1 ), the second direction being different from the first direction in which the first conductive line 104 extends and being substantially parallel to the second direction in which the second conductive line 136 extends. The isolation region 122 may be located between horizontally adjacent transistors 110 and between lateral portions 136 b of adjacent second conductive lines 136. Thus, the isolation region 122 may be located in the first direction (e.g., Figure 1B The isolation region 122 may include one or more dielectric materials, including but not limited to a passivation material 124, a dielectric material 126, and one or more air gaps 128 (e.g., void spaces). The passivation material 124 may be formed of at least one dielectric material and include at least one dielectric material, including but not limited to an oxide, a nitride, or a nitride oxide. In particular, the passivation material 124 may include but is not limited to an oxide material (e.g., silicon dioxide (SiO2), yttrium oxide (Y2O3)) or a nitride material (e.g., silicon nitride (SiN x )). The dielectric material 126 may be formed of and include at least one dielectric material, such as at least one oxide dielectric material (eg, SiO x 、AlO x , one or more of phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass), at least one nitride dielectric material (e.g., SiN y ) and at least one low-K dielectric material (e.g., silicon oxycarbide (SiO x C y ), silicon oxynitride (SiO x N y ), hydrogenated silicon oxycarbide (SiC x O y H z ) and silicon oxycarbonitride (SiO x C z N y ). In some embodiments, dielectric material 126 is formed of and includes substantially the same material composition as electrically insulating material 106. Air gap 128, if present, may extend adjacent to transistor 110 and may laterally intervene between adjacent portions of gate electrode structure 108 of second conductive line 136.

[0058] In some embodiments, the entire individual isolation region 122 comprises a single material, which comprises one of the passivation material 124, the dielectric material 126, or the air gap 128. In other embodiments, two or more dielectric materials are used in combination, such as Figure 1B, as shown in various configurations. For example, the passivation material 124 can be located near the exposed surface of each of the gate dielectric material 112, the first channel region 116a, the second channel region 116b, and the lateral portion 136b of the second conductive line 136, and another of the dielectric materials (e.g., dielectric material 126, air gap 128) can be located in the remaining portion (e.g., the central portion) of the isolation region 122 within the opening 120. In some embodiments, the passivation material 124 is in direct physical contact with a portion of the gate electrode structure 108. The isolation region 122 can include the passivation material 124, which is adjacent to the first channel region 116a on a first side and adjacent to the second channel region 116b on a second side. As a non-limiting example, each side of the passivation material 124 can have approximately to about (For example, about ), wherein the remainder of the central portion of the isolation region 122 is substantially filled with one or more dielectric materials 126 and air gaps 128. For example, the dielectric material 126 may have a thickness of about to about (For example, about ) with one or more air gaps 128 embedded therein. In yet other embodiments, the isolation region 122 may include three or more dielectric material regions. One of ordinary skill in the art will appreciate that the dielectric material of the isolation region 122 may be selectively positioned to achieve the desired requirement of isolating the transistors 110 from each other.

[0059] The thickness T4 of the isolation region 122 may be about to about Between, for example, to about Between, about to about Between, about to about Between, about to about Between, or about to about between.

[0060] The isolation region 122 may also include a shielding material 130 extending in a straight line along a second direction (e.g., the Y direction) and may be located between adjacent transistors 110 along a first direction (e.g., the X direction). Thus, each transistor 110 may include a shielding material 130 on a first side thereof and another shielding material 130 on an opposite second side thereof. The shielding material 130 may be electrically insulated and physically isolated from each of the first channel region 116a and the second channel region 116b by one or more dielectric materials (e.g., the passivation material 124, the dielectric material 126, the air gap 128). For example, the shielding material 130 may also be electrically insulated from the first conductive line 104 by at least the electrically insulating material 106.

[0061] As will be described herein, the shielding material 130 may be formulated, configured, and electrically biased to substantially reduce or prevent wordline to wordline capacitance between gate electrode structures 108 of adjacent transistors 110. Thus, the shielding material 130 may be configured to significantly reduce capacitance (e.g., wordline capacitance) between gate electrode structures 108 of adjacent transistors 110.

[0062] The thickness of the shielding material 130 may be about to about Between, such as about to about Between to about Between, or about to about The distance between the lower surface of the shielding material 130 and the lower surfaces of the first channel region 116a and the second channel region 116b may be about to about Between, such as about to about Between, such as about to about Between, about to about Between, or about to about The distance may be controlled by the thickness of the electrically insulating material 106 or the gate dielectric material 112 .

[0063] Shielding material 130 is formed of and includes a conductive material. In some embodiments, shielding material 130 includes a material having P+ type conductivity and may be referred to as a P+ body region. In other embodiments, shielding material 130 includes a conductive material. Suitable conductive doped semiconductor materials may be doped with P-type dopants, such as boron, aluminum, gallium, or a combination thereof. In some embodiments, shielding material 130 is formed of and includes tungsten. In other embodiments, shielding material 130 is formed of and includes ruthenium. In some embodiments, shielding material 130 is formed of and includes a material composition substantially the same as at least one of first conductive line 104 or second conductive line 136.

[0064] The shielding material 130 may be connected to the conductive contact 131 ( Figure 1B ), which can be configured to provide a suitable bias to the shielding material 130. In some embodiments, the conductive contact 131 is electrically connected to a voltage source configured to bias the conductive contact 131 and the associated shielding material 130. The voltage source with which the conductive contact 131 is electrically connected can be different from the voltage source with which the conductive contact 131 and the gate electrode structure 108 are electrically connected. For clarity and ease of understanding of the drawings and related descriptions, Figure 1B In FIG. 1 , only one conductive contact 131 is shown adjacent to the shielding material 130 , additional conductive contacts 131 . However, the present disclosure is not limited thereto, and additional conductive contacts 131 may be included.

[0065] In some embodiments, the conductive contact 131 is formed from and includes substantially the same material composition as the shielding material 130. In other embodiments, the conductive contact 131 includes a material different from the material of the shielding material 130. The conductive contact 131 may include substantially the same material composition as the conductive contact 109.

[0066] In some embodiments, the shielding material 130 is configured to be biased to a predetermined voltage (e.g., biased with a voltage) when the gate electrode structure 108 of at least one transistor 110 adjacent to the shielding material 130 is selected. Without being bound by any particular theory, it is believed that when a switching voltage is applied to the gate electrode structure 108, the first channel region 116a and the second channel region 116b of one transistor 110 may be affected by the gate electrode structure 108 of an adjacent transistor 110 because the first channel region 116a and the second channel region 116b are located outside (e.g., at the side) of the gate electrode structure 108 (rather than the gate electrode structure 108 being disposed around the channel region). In some embodiments, applying a suitable bias voltage to the shielding material 130 substantially prevents or reduces the voltage applied to the gate electrode structure 108 of the transistor 110 from affecting the channel region of the adjacent transistor 110. Therefore, the shielding material 130 may help reduce or prevent the so-called "word line to word line capacitance" between the second conductive lines 136 of the adjacent transistors 110. In some embodiments, the wordline capacitance of the microelectronic device structure 100 is approximately 35% less than the wordline capacitance of a conventional device structure that does not include the shielding material 130 .

[0067] In use and operation, the shielding material 130 may be biased at a voltage between -2.0 V and about 2.0 V, such as between about -2.0 V and about -1.5 V, between about -1.5 V and about -1.0 V, between about -1.0 V and about -0.5 V, between about -0.5 V and about 0 V, between about 0 V and about 0.5 V, between about 0.5 V and about 1.0 V, between about 1.0 V and about 1.5 V, or between about 1.5 V and about 2.0 V. In some embodiments, the shielding material 130 is biased at a voltage between about 0 V and about 0.5 V. In some embodiments, such as where the shielding material 130 is configured to be biased, the shielding material 130 may be referred to as a so-called "back gate" of the microelectronic device structure 100.

[0068] In use and operation, a voltage may be applied to one or more second conductive lines 136 (e.g., word lines). In some embodiments, another voltage (which may be different (e.g., having a different magnitude) than the voltage applied to the one or more second conductive lines 136) is applied to the shielding material 130, which is positioned adjacent to the second conductive lines 136 to which the voltage is applied. Applying another voltage to the shielding material 130 may reduce the word line to word line capacitance between the second conductive lines 136 of adjacent transistors 110.

[0069] Thus, each transistor 110 of the transistor array 110 may include a gate electrode structure 108, which may be located at a central portion of its corresponding transistor 110. The gate electrode structure 108 may be surrounded by a gate dielectric material 112 on one or more sides thereof. The gate dielectric material 112 may contact each of the first channel region 116a and the second channel region 116b at opposite sides of the gate electrode structure 108. In other words, the gate dielectric material 112 may be disposed between the gate electrode structure 108 and opposite portions of the first channel region 116a and the second channel region 116b. Each of the first channel region 116a and the second channel region 116b is formed of and includes an oxide semiconductor material. In some embodiments, each gate electrode structure 108 includes two channel regions associated therewith, and may be laterally located between two discrete channels including the first channel region 116a and the second channel region 116b. Since the first channel region 116a and the second channel region 116b are located on the outer side of the centrally located gate electrode structure 108, the gate electrode structure 108 of each transistor 110 can be formed with a greater thickness compared to conventional transistors, while the spacing of the transistors 110 is the same as that of conventional transistors, as shown in FIG. Figure 3 discussed in more detail.

[0070] Thus, in at least some embodiments, a device includes a first conductive structure and at least one transistor electrically connected to the first conductive structure. The at least one transistor includes a lower conductive contact coupled to the first conductive structure and a split body channel on the lower conductive contact. The split body channel includes a first semiconductor column and a second semiconductor column horizontally adjacent to the first semiconductor column. The at least one transistor also includes a gate structure horizontally inserted between the first semiconductor column and the second semiconductor column of the split body channel, and an upper conductive contact vertically covering the gate structure and coupled to the split body channel. Portions of the gate structure surround three sides of each of the first semiconductor column and the second semiconductor column.

[0071] Thus, in at least some embodiments, a method of operating a device structure includes applying a bias voltage to a gate electrode of a device structure including a transistor. The transistor includes a gate electrode, a gate dielectric material on at least opposite sides of the gate electrode, and a channel material on sides of the gate dielectric material, the gate electrode being located between different portions of the channel material and substantially surrounding the channel material on at least three sides. The method also includes applying another bias voltage to a conductive material located between the transistor and at least another transistor of the device structure.

[0072] In some embodiments, the microelectronic device structure 100 includes one or more arrays of transistors 110, such as lateral arrays of transistors 110 extending in the X-direction and the Y-direction. As non-limiting examples, the spacing between adjacent microelectronic device structures 100 in each lateral direction within the array can be about 48×48 (e.g., 48nm×48nm), about 40×40, about 32×32, about 20×20, or about 10×10. In some embodiments, the microelectronic device structure 100 includes a stack of transistors 110, such as in a 3D memory structure, such as in a stacked DRAM array. In some such embodiments, the microelectronic device structure 100 can include one or more layers of transistors 110, each layer vertically offset from the transistors 110 of other layers. Each layer of transistors 110 can be isolated from each other by an insulating material extending therebetween. For example, an electrically insulating material can be formed on the second conductive line 136. Another layer of first conductive lines 104 of transistors 110 may be formed on electrically insulating material 106 , and transistors 110 may be formed on another layer of first conductive lines 104 to form a structure including multiple layers (eg, two, three, four, eight, etc.) of transistors.

[0073] Figures 2A to 2K The above reference is shown in some embodiments according to the present disclosure. Figure 1A and 1B A method of constructing a microelectronic device 100 is described. Figure 2A 1 is a simplified perspective view of a microelectronic device structure 100. The microelectronic device structure 100 may include a first conductive line 104 adjacent to (e.g., above) a substrate material 102, a lower conductive contact 105 adjacent to (e.g., above) the first conductive line 104, and an electrically insulating material 106 adjacent to each of the first conductive line 104 and the lower conductive contact 105. The first conductive line 104 and the lower conductive contact 105 may be patterned before forming the electrically insulating material 106. The first conductive line 104 and the lower conductive contact 105 may include a line extending along a first direction (e.g., an X direction). In some embodiments, after the first conductive line 104 and the lower conductive contact 105 are patterned, the electrically insulating material 106 is formed near the first conductive line 104 and the lower conductive contact 105 (e.g., between adjacent portions of the first conductive line and the lower conductive contact). In other embodiments, the electrically insulating material 106 is formed and patterned before forming the first conductive line 104 and the lower conductive contact 105. Optionally, shielding material (not shown) may be formed within the electrically insulating material 106 to electrically shield adjacent first conductive lines 104 from each other, thereby reducing leakage that may be caused by coupling capacitance therebetween. The upper surface of the lower conductive contact 105 and / or the electrically insulating material 106 may be planarized, such as by one or more CMP operations. Figure 2AAs shown in the view of FIG. 1 , the electrically insulating material 106 may substantially fill the space between the patterned portion (eg, line) of the first conductive line 104 and the lower conductive contact 105 .

[0074] refer to Figure 2B , split body channel 116 ( Figure 1A ) can initially be formed as a semiconductor pillar 115 on the lower conductive contact 105 using conventional processes and conventional processing equipment, which are not described in detail herein. As a non-limiting example, the semiconductor material can be conventionally formed and patterned (e.g., masking, exposing, developing, and etching) to form the semiconductor pillar 115. For example, the semiconductor pillar 115 can be formed by ALD, CVD, PVD, LPCVD, PECVD, another deposition method, or a combination thereof. In some embodiments, the initial material for forming the semiconductor pillar 115 is formed by atomic layer deposition. In some embodiments, a single semiconductor pillar 115 of the microelectronic device structure 100 is formed using one or more patterning processes. The semiconductor pillar 115 can include substantially the same material composition as described above with reference to the first channel region 116a and the second channel region 116b of the split body channel 116 ( Figure 1A and 1B ).

[0075] refer to Figure 2C , additional portions of electrically insulating material 106 (e.g., upper portions 107) may be deposited to separate the individual semiconductor pillars 115 from each other and to electrically insulate (cover) the exposed portions of lower conductive contacts 105. In some embodiments, upper portions 107 include substantially the same material composition as electrically insulating material 106. Thus, electrically insulating material 106 and its upper portions 107 may include an integral insulating material, which may correspond to electrically insulating material 106.

[0076] refer to Figure 2D , gate dielectric material 112 may be formed near (e.g., above) the upper surface and sidewalls of semiconductor pillar 115 and near (e.g., above) the exposed upper surface of electrically insulating material 106. In some embodiments, gate dielectric material 112 is formed of and includes silicon dioxide. In some embodiments, gate dielectric material 112 is formed of and includes substantially the same material composition as electrically insulating material 106. Thus, electrically insulating material 106 and gate dielectric material 112 may include an integral insulating material, which may correspond to gate dielectric material 112. Although Figures 2C to 2K The electrically insulating material 106 and the gate dielectric material 112 are shown as separate components, but it is understood that the electrically insulating material 106 and the gate dielectric material 112 may comprise a unitary structure exhibiting a substantially uniform composition (eg, silicon dioxide).

[0077] The gate dielectric material 112 may be formed by, for example, ALD, CVD, PVD, LPCVD, PECVD, another deposition method, or a combination thereof. The gate dielectric material 112 may be conformally formed on the semiconductor pillars 115. In some embodiments, at least a portion of the gate dielectric material 112 and the electrically insulating material 106 between adjacent semiconductor pillars 115 is removed to expose a portion of the lower conductive contact 105. For example, a portion of the gate dielectric material 112 and the electrically insulating material 106 between adjacent semiconductor pillars 115 may be removed by exposing the gate dielectric material 112 and the electrically insulating material 106 between adjacent semiconductor pillars 115 to a suitable etching chemistry, such as exposure to a reactive ion etching chemistry, which is formulated and configured to remove the gate dielectric material 112 and the electrically insulating material 106 without substantially removing the lower conductive contact 105.

[0078] refer to Figure 2E , one or more conductive materials 135 may be formed on the microelectronic device structure 100, such as adjacent to the gate dielectric material 112 and between adjacent semiconductor pillars 115. The conductive material 135 may be formed using conventional processes (e.g., conventional deposition processes, such as one or more of in-situ growth, spin coating, blanket coating, CVD, ALD, and PVD) and conventional processing equipment, which are not described in detail herein. In some embodiments, as will be described herein, the conductive material 135 substantially surrounds a single semiconductor pillar 115 before subsequent processing.

[0079] refer to Figure 2F , a portion of the conductive material 135 between adjacent semiconductor pillars 115 may be removed by conventional techniques to recess the conductive material 135 and expose the upper surface of the semiconductor pillars 115. In some embodiments, at least a portion of the upper surface of the semiconductor pillars 115 is also removed. By way of example only, one or more dry etching processes or wet etching processes may be performed to remove the upper portion of the conductive material 135. Although Figure 2F An upper portion of the conductive material 135 is shown removed, but the present disclosure is not limited thereto and the conductive material 135 may be substantially coextensive with the semiconductor pillar 115 .

[0080] refer to Figure 2G, an electrically insulating material 138 may be deposited to separate the individual semiconductor pillars 115 from each other and to electrically insulate (cover) the exposed portions of the conductive material 135. In some embodiments, the electrically insulating material 138 is formed of SiO2 and includes silicon dioxide. In some embodiments, the electrically insulating material 138 is formed of and includes substantially the same material composition as the electrically insulating material 106 and / or the gate dielectric material 112. These materials may be subjected to at least one conventional planarization process (e.g., at least one conventional CMP process) to promote or enhance the planarity of the upper boundaries (e.g., upper surfaces) of the electrically insulating material 138 and the semiconductor pillars 115 for further processing thereon.

[0081] Combination Fig.2I refer to Figure 2H , the microelectronic device structure 100 can be patterned in the second direction (e.g., the Y direction). In some embodiments, a first mask material 132 (e.g., a mask or resist material) is placed on the electrically insulating material 138 and the semiconductor pillars 115, and the microelectronic device structure 100 is patterned in the second direction using a second mask material 134 (e.g., one or more chopping masks) to form the opening 120, such as Figure 2H For example, a conventional method of forming the opening 120 includes transferring the pattern of openings and features in the second mask material 134 into the first mask material 132 covering the electrically insulating material 138, and then using the first mask material 132 to selectively remove (e.g., selectively etch, selectively dry etch) the underlying material in a first etching process to form the opening 120.

[0082] The first mask material 132 may also be referred to as a hard mask herein. As a non-limiting example, the first mask material 132 may be formed of and include at least one of amorphous carbon, silicon, silicon oxide, silicon nitride, silicon oxycarbide, aluminum oxide, and silicon oxynitride. In some embodiments, the first mask material 132 is formed of and includes at least one oxide dielectric material (e.g., one or more of silicon dioxide and aluminum oxide). In other embodiments, the first mask material 132 is formed of and includes silicon nitride. The first mask material 132 may be homogeneous (e.g., may include a single material), or may be heterogeneous (e.g., may include a stack that includes at least two different materials). The first mask material 132 and the second mask material 134 may each be formed separately using conventional processes and patterned using conventional patterning and material removal processes (e.g., conventional photolithography exposure processes, conventional development processes, conventional etching processes) and conventional processing devices, which are not described in detail herein.

[0083] The first mask material 132 can substantially protect the underlying materials (e.g., the first conductive line 104 and the lower conductive contact 105) from the etchant during patterning of the transistor. In some embodiments, portions of each of the electrically insulating material 138, the gate electrode structure 108, the gate dielectric material 112, the conductive material 135, the electrically insulating material 106, and the semiconductor pillar 115 are patterned to form the transistor 110 ( Figure 1A ). In some embodiments, portions of the upper conductive contact 114 and the semiconductor pillar 115 are removed by exposing the semiconductor material to a wet etch or dry etch chemistry, for example, to separate the first channel region 116a from the second channel region 116b within a separate split body channel 116, thereby forming a so-called "split body" transistor. In other embodiments, as will be described herein, one or more sacrificial materials (e.g., electrically insulating material 138, gate electrode structure 108, gate dielectric material 112, conductive material 135, electrically insulating material 106, and semiconductor pillar 115) having different etching characteristics than the remaining materials can be first formed in a designated location that is based at least in part on the subsequent location of the opening 120 and the placement of additional materials therein.

[0084] like Fig.2I As shown, material may be removed to a first depth D1 within the opening 120. The first depth D1 may correspond to a distance between an upper surface of the electrically insulating material 138 within the opening 120 and an exposed upper surface of the electrically insulating material 106 (e.g., in the Z direction). In other words, a vertical dimension (e.g., a length) of the opening 120 corresponds to the first depth D1. The second depth D2 may correspond to a distance between an upper surface of the electrically insulating material 138 and an upper surface of the lower conductive contact 105, and the third depth D3 may correspond to a distance between an upper surface of the electrically insulating material 138 and a lower surface of the conductive material 135 (e.g., an upper surface of the electrically insulating material 106 and / or a gate dielectric material 112 below the conductive material 135). In some embodiments, the first depth D1 is relatively smaller than the second depth D2 and relatively greater than the third depth D3. In other words, the opening 120 may be formed to extend a distance beyond the lower surface of the conductive material 135 (e.g., to the first depth D1) without extending to the upper surface of the lower conductive contact 105, as shown. Fig.2IAs shown. In other embodiments, the opening 120 is formed a certain distance so that the opening 120 is adjacent to the upper surface of the lower conductive contact 105. In still other embodiments, the opening 120 can be formed to extend beyond the upper surface of the lower conductive contact 105 without extending to the upper surface of the first conductive line 104. Therefore, the opening 120 can extend through the entire height of the split body channel 116. As a non-limiting example, the first depth D1 of the opening 120 can be between about 10 nm and about 100 nm, such as between about 10 nm and about 25 nm, between about 25 nm and about 50 nm, between about 50 nm and about 75 nm, or between about 75 nm and about 100 nm.

[0085] Once formed, the opening 120 can separate horizontally adjacent portions of the conductive material 135 to form a second conductive line 136 (eg, an access line, a word line). Figure 1A and 1B As described, the second conductive line 136 can be characterized as a so-called "single word line" for a single tri-gate transistor. Thus, by substantially filling the space between the semiconductor pillars 115 ( Figure 2H ), and then forming an opening 120 to form a split body channel 116 by splitting the single semiconductor pillar 115 ( Figure 2H ), a second conductive line 136 may be formed adjacent to (e.g., above) the gate dielectric material 112. Benefits of using a single word line include wider manufacturing tolerances in forming the split body channel 116 compared to conventional device structures that include dual gate electrodes on opposing sides of a conventional pillar structure. An additional benefit of utilizing a single word line that is centered between opposing portions of the first channel region 116a and the second channel region 116b may also allow the thickness of the channel material to be reduced as the size of the transistor 110 is scaled down without reducing vertical stability within the split body channel 116.

[0086] refer to Figure 2J , the opening 120 between the horizontally adjacent transistors 110 may be substantially filled with the material of the isolation region 122 (eg, one or more of the passivation material 124, the dielectric material 126, the air gap 128, and the shielding material 130), as shown in reference Figure 1B The material of the isolation region 122 may be formed by, for example, ALD, CVD, PVD, LPCVD, PECVD, another deposition method, or a combination thereof. The conductive contact 131 ( Figure 1B) can be formed before or after the shielding material 130 is formed. By forming the microelectronic device structure 100 using the above-described process, a number of advantages are achieved. By utilizing the isolation region 122 within the opening 120, increased accessibility can be achieved by providing enhanced access to the back side of the transistor 110 (e.g., opposite the second conductive line 136). For example, access to the back side of the transistor 110 can allow a so-called "back passivation" process to form the passivation material 124 within the opening 120, which is not available in conventional devices having a single-column structure. Without being bound by any theory, it is believed that the presence of the passivation material 124 adjacent to the back side of the transistor 110 acts to minimize instabilities typically found in the channel material of conventional transistors, and improves device reliability by, for example, improving the so-called "photoresponse" in the channel material of the first channel region 116a and the second channel region 116b.

[0087] After the material of the isolation region 122 is formed within the opening 120, the horizontally adjacent transistors 110 are physically isolated and electrically insulated from each other. In other words, the material forming the isolation region 122 substantially fills the volume between the horizontally adjacent transistors 110. Thus, the space between the first channel region 116a and the second channel region 116b of the split body channel 116 (e.g., the opening 120), and the space between the horizontally adjacent portions of the lateral portion 136b of the second conductive line 136, can be substantially filled with one or more materials of the isolation region 122, such as Figure 2J As shown. The lower surface of the isolation region 122 may extend below the lower surface of each of the gate dielectric material 112 and the second conductive line 136. In some embodiments, the lower surface of the isolation region 122 is adjacent to the electrically insulating material 106 without extending to the upper surface of the lower conductive contact 105. In other embodiments, the lower surface of the isolation region 122 abuts the upper surface of the lower conductive contact 105. In still other embodiments, the lower surface of the isolation region 122 extends beyond the upper surface of the lower conductive contact 105 without being adjacent to the first conductive line 104.

[0088] The upper surfaces of the electrically insulating material 138, the gate dielectric material 112, the split body channels 116, and the material of the isolation region 122 may be planarized, such as by one or more CMP actions after the formation of the isolation region 122, to promote or enhance the planarity of the upper boundaries (e.g., upper surfaces) of the electrically insulating material 138 and the split body channels 116 for further processing thereon. Thus, the upper surfaces of each of the electrically insulating material 138, the gate dielectric material 112, each of the first channel region 116a and the second channel region 116b of the split body channels 116, and the material of the isolation region 122 (e.g., the passivation material 124, the dielectric material 126, and / or the shielding material 130) may be substantially coplanar with each other. In some embodiments, the upper portion of the shielding material 130 is not coplanar with the upper portion of the gate electrode structure 108.

[0089] refer to Figure 2K , showing a second conductive line 136, including a gate electrode structure 108 of a single transistor 110 ( Figure 2J ). For clarity and ease of understanding of the drawings and related descriptions, Figure 2K The surrounding materials of the isolation region 122, the electrically insulating material 106, the electrically insulating material 138, the split body trench 116, and the isolation region 122 are not included. Figure 1B As discussed in more detail, the second conductive line 136 may include a central elongated portion 136a extending as a line extending in, for example, the Y direction and a lateral portion 136b extending away from the central elongated portion 136a. Thus, the second conductive line 136 may surround the split body channel 116 ( Figure 2J ), and the second conductive line 136 can be characterized as a so-called “mono-word line” for a single tri-gate transistor within a single device region 140.

[0090] although Figures 2A to 2K The various components of the microelectronic device structure 100 have been described as being formed in a particular order, but the present disclosure is not limited thereto. For example, although the upper conductive contact 114 has been described as being formed after forming the second conductive line 136 including the gate electrode structure 108, the present disclosure is not limited to a particular order of forming the components of the microelectronic device structure 100. In other embodiments, the upper conductive contact 114 may be formed after forming the isolation region 122 within the opening 120 by forming a first upper conductive contact 114 in contact with the first channel region 116a of the split body channel 116 and forming a second upper conductive contact 114 in contact with the second channel region 116b thereof. In some such embodiments, the shielding material 130 and the electrically insulating material 106 ( Figure 2J) to form an opening in the shielding material 130 and the electrically insulating material 106 and expose an upper portion of the gate dielectric material 112. An upper conductive contact 114 may be formed within the opening. Thereafter, the upper conductive contact 114, the shielding material 130, and the electrically insulating material 106 may be removed from the upper surface of the microelectronic device structure 100, such as by chemical mechanical planarization. A device including the transistor 110 of the microelectronic device structure 100 formed according to an embodiment of the present disclosure may be formed by performing additional process actions, which are not described in detail herein.

[0091] Figure 3 Compared with the traditional device structure, Figure 1B 1 is a simplified top cross-sectional view of a portion of the microelectronic device structure 100. As discussed above, since the relative channel regions are located on the outer side of the centrally located gate electrode structure 108 ( Figure 1B ), the gate electrode structure 108 corresponding to the portion of the second conductive line 136 within each transistor 110 can be formed to be thicker than a conventional transistor, while the spacing of the transistors 110 is the same as the spacing of the conventional transistors. The larger thickness of the gate electrode structure 108 increases its area, thereby reducing its resistance. As a result, the RC (product of resistance and capacitance) of the transistor 110 can be reduced, which can be associated with an increase in the switching speed of the transistor 110. The transistor 110 can deliver the same current as a conventional transistor arranged with the same spacing (e.g., about 5μA / Dev). In some embodiments, the larger thickness of the gate electrode structure 108 (in Figure 1B The thickness T2 of the gate electrode structure 108 is twice the thickness of the gate electrode of the conventional device structure. As a non-limiting example, in some embodiments, the thickness T2 of the gate electrode structure 108 can be about 10 nm. In contrast, the thickness of each of the two word lines associated with a conventional device (e.g., a dual-gate device) can be about 5 nm. In some embodiments, according to the disclosed embodiments, the resistivity of the microelectronic device structure 100 is about 30% lower than the resistivity of a conventional device structure having the same spacing.

[0092] Additional benefits of the configuration of the second conductive line 136 (e.g., a single word line) include reduced leakage due to coupling capacitance between adjacent transistors as compared to dual gate word lines of conventional device structures. For example, when a target word line is "on," large word line to word line capacitance may result in leakage between word lines. Without being limited to any particular theory, it is believed that by reducing the surface area of ​​adjacent word lines presented to the second conductive line 136, undesired leakage may be minimized (e.g., prevented). In other words, the reduced surface area of ​​the end surface of each lateral portion 136b of the second conductive line 136 presented to the other end surface of the lateral portion 136b of the adjacent second conductive line 136 is significantly less than the surface area of ​​the full length of the dual gate word line (e.g., electrode) presented to the adjacent word line of a conventional device. In some embodiments, the reduced surface area of ​​the end surface of the lateral portion 136b substantially prevents or reduces the effect of a voltage applied to one of the second conductive lines 136 on the adjacent second conductive line 136, and thereby prevents or reduces the effect on the gate electrode structure 108 of the adjacent transistor 110 ( Figure 1A ). Therefore, compared with conventional transistors, the transistor 110 of the microelectronic device structure 100 can exhibit a higher threshold voltage (V TH ) and can also exhibit lower off-state current (I off ) amplitude. In some embodiments, transistor 110 may be in an off state, with approximately 0V applied to gate electrode structure 108 ( Figure 1B ). In other words, a negative voltage may not be applied to the gate electrode structure 108 when the transistor 110 is in the off state. In contrast, a conventional transistor, including a large surface area along the entire length of the word line and not including the lateral portion 136b of the tri-gate device, may exhibit leakage current when the transistor is in the off state if a significant negative voltage (e.g., a magnitude greater than about 1.0 of the off voltage) is not applied to the gate electrode. In some embodiments, applying a voltage to the gate electrode structure 108 of one transistor 110 does not affect the gate electrode structure 108 or the channel region of an adjacent transistor 110. In other embodiments, a lower negative voltage (e.g., less than -1 V) may be used to suppress the off current (I off ) to reduce the coupling capacitance between adjacent transistors.

[0093] Therefore, the transistor 110 may be formed by and include a first channel region 116a and a second channel region 116b located on the side of the gate electrode structure 108. In some embodiments, the gate electrode structure 108 of each transistor 110 is located at a lateral center position of the transistor 110, and the first channel region 116a and the second channel region 116b are located near, such as opposite sides (e.g., lateral sides) of the gate electrode structure 108. The gate electrode structure 108 may surround each of the first channel region 116a and the second channel region 116b on at least three sides. The vertical length (e.g., in the Z direction) of each of the first channel region 116a and the second channel region 116b may be greater than the vertical length of the gate electrode structure 108.

[0094] Thus, in at least some embodiments, a method of forming a device structure includes: forming a conductive line extending in a first direction; forming a semiconductor pillar structure on the conductive line; horizontally forming a conductive material between at least two semiconductor pillar structures; forming an opening extending vertically through the semiconductor pillar structure and a portion of the conductive material to divide each of the at least two semiconductor pillar structures into two relatively smaller semiconductor pillar structures, and forming a gate structure from the conductive material; and at least partially filling the opening with a dielectric material. A central portion of the gate structure extends in a second direction transverse to the first direction.

[0095] Figure 4 4 shows a functional block diagram of a memory device 400 according to an embodiment of the present disclosure. The memory device 400 may include, for example, an embodiment of the microelectronic device structure 100 previously described herein. Figure 4 As shown, the memory device 400 may include a storage unit 402, a digital line 404 (eg, corresponding to Figures 1A to 1B The first conductive line 104 of the microelectronic device structure 100 shown in FIG. 1 ), the word line 406 (eg, corresponding to Figure 1A and 1B The microelectronic device structure 100 shown includes a second conductor 136 ), a row decoder 408 , a column decoder 410 , a memory controller 412 , a sensing device 414 , and an input / output device 416 .

[0096] The memory cell 402 of the memory device 400 is programmable to at least two different logic states (e.g., logic 0 and logic 1). Each memory cell 402 may individually include a capacitor and a transistor (e.g., a pass transistor). The capacitor stores a charge representing the programmable logic state of the memory cell 402 (e.g., a charged capacitor may represent a first logic state, such as logic 1; and an uncharged capacitor may represent a second logic state, such as logic 0). The transistor grants access to the capacitor when a minimum threshold voltage is applied to its semiconductor channel (e.g., through one of the word lines 406) to operate (e.g., read, write, rewrite) the capacitor.

[0097] Digital line 404 passes through the transistor of memory cell 402 (eg, corresponding to Figure 1A and 1B 404 and 406. The transistor 110 of the microelectronic device structure 100 is shown connected to the capacitor of the memory cell 402. The word line 406 extends perpendicular to the digit line 404 and is connected to the gate of the transistor of the memory cell 402. By activating the appropriate digit line 404 and word line 406, operations can be performed on the memory cell 402. Activating the digit line 404 or word line 406 can include applying a voltage potential to the digit line 404 or word line 406. Each column of memory cells 402 can be individually connected to one of the digit lines 404, and each row of memory cells 402 can be individually connected to one of the word lines 406. Individual memory cells 402 can be addressed and accessed through the intersection (e.g., cross point) of the digit line 404 and the word line 406.

[0098] The memory controller 412 can control the operation of the memory cell 402 through various components, including the row decoder 408, the column decoder 410, and the sensing device 414. The memory controller 412 can generate row address signals directed to the row decoder 408 to activate (e.g., apply a voltage potential thereto) a predetermined word line 406, and can generate column address signals directed to the column decoder 410 to activate (e.g., apply a voltage potential thereto) a predetermined digit line 404. The memory controller 412 can also generate and control various voltage potentials employed during the operation of the memory device 400. In general, the magnitude, shape, and / or duration of the applied voltage can be adjusted (e.g., varied) and can be different for various operations of the memory device 400.

[0099] During use and operation of the memory device 400, after being accessed, the memory cell 402 can be read (e.g., sensed) by the sensing device 414. The sensing device 414 can compare the signal (e.g., voltage) of the appropriate digital line 404 with the reference signal to determine the logic state of the memory cell 402. For example, if the digital line 404 has a higher voltage than the reference voltage, the sensing device 414 can determine that the storage logic state of the memory cell 402 is a logic 1, and vice versa. The sensing device 414 can include transistors and amplifiers to detect and amplify the difference in the signal (commonly referred to as "latching" in the art). The detected logic state of the memory cell 402 can be output to the input / output device 416 through the column decoder 410. In addition, the memory cell 402 can be set (e.g., written) by similarly activating the appropriate word line 406 and the appropriate digital line 404 of the memory device 400. By controlling the digital line 404 while activating the word line 406, the memory cell 402 can be set (e.g., a logic value can be stored in the memory cell 402). The column decoder 410 can accept data from the input / output device 416 to write it to the memory cell 402. In addition, the memory cell 402 can also be refreshed (e.g., recharged) by reading the memory cell 402. The read operation places the contents of the memory cell 402 on the appropriate digital line 404, which is then pulled to a full level (e.g., fully charged or fully discharged) by the sensing device 414. When the word line 406 associated with the memory cell 402 is deactivated, all memory cells 402 in the row associated with the word line 406 are restored to a full charge or discharge.

[0100] Therefore, a memory device according to an embodiment of the present disclosure includes a memory cell, which includes an access device electrically coupled to a memory element. The access device includes a conductive material, which includes an elongated portion extending in one direction and a lateral protrusion extending in another direction substantially transverse to the direction, a first channel region adjacent to a first side of the conductive material, and a second channel region adjacent to a second side of the conductive material. The second side is opposite to the first side. The access device also includes a gate dielectric between the first channel region and the conductive material and between the second channel region and the conductive material.

[0101] According to an embodiment of the present disclosure, a device structure (e.g., microelectronic device structure 100) including a split-body transistor 110 (which includes a channel region (e.g., a first channel region 116a, a second channel region 116b)) and a gate electrode structure 108 horizontally inserted between the first channel region 116a and the second channel region 116b of the split-body channel 116 can be used in an embodiment of an electronic system of the present disclosure. For example, Figure 5is a block diagram of an illustrative electronic system 500 according to an embodiment of the present disclosure. Electronic system 500 may include, for example, a computer or computer hardware component, a server or other network hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer, such as, for example or Tablet computer, electronic book, navigation device, etc. The electronic system 500 includes at least one memory device 502. The memory device 502 may include, for example, one or more embodiments of the device structure (e.g., microelectronic device structure 100) and microelectronic device (e.g., memory device 400) previously described herein. The electronic system 500 may also include at least one electronic signal processor device 504 (commonly referred to as a "microprocessor"). The electronic signal processor device 504 may optionally include an embodiment of the device structure (e.g., microelectronic device structure 100) and microelectronic device (e.g., memory device 400) previously described herein. The electronic system 500 may also include one or more input devices 506 for inputting information to the electronic system 500 by a user, such as a mouse or other pointing device, keyboard, touch pad, button, or control panel. The electronic system 500 may also include one or more output devices 508 for outputting information to the user (e.g., visual or audio output), such as, for example, a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, input device 506 and output device 508 may include a single touch screen device that can be used to input information to electronic system 500 and output visual information to a user. Input device 506 and output device 508 may be in electrical communication with one or more of memory device 502 and electronic signal processor device 504.

[0102] Therefore, according to an embodiment of the present disclosure, an electronic system includes at least one input device, at least one output device, at least one processor device operably coupled to the at least one input device and the at least one output device, and a device operably coupled to the at least one processor device. The device includes a transistor array. At least one transistor of the transistor array includes a gate structure covering a conductive contact, a first column structure horizontally adjacent to a first lateral side of the gate structure, and a second column structure horizontally adjacent to a second lateral side of the gate structure opposite to the first lateral side. The gate structure is located between the first column structure and the second column structure. The at least one transistor also includes a passivation material, which is adjacent to each of the first column structure and the second column structure on a side surface opposite to the gate structure. The passivation material is in direct physical contact with a portion of the gate structure.

[0103] The disclosed embodiments may be further characterized without limitation as set forth below.

[0104] Embodiment 1: A device comprises: a first conductive structure; and at least one transistor, the at least one transistor being electrically connected to the first conductive structure and comprising: a lower conductive contact, the lower conductive contact being coupled to the first conductive structure; a split body channel, the split body channel being on the lower conductive contact and comprising: a first semiconductor column; and a second semiconductor column, the second semiconductor column being horizontally adjacent to the first semiconductor column; a gate structure, the gate structure being horizontally inserted between the first semiconductor column and the second semiconductor column of the split body channel, a portion of the gate structure surrounding three sides of each of the first semiconductor column and the second semiconductor column; and an upper conductive contact, the upper conductive contact vertically covering the gate structure and coupled to the split body channel.

[0105] Embodiment 2: The apparatus of Embodiment 1, further comprising a gate dielectric material horizontally located between the gate structure and the three sides of each of the first and second semiconductor pillars of the split body channel.

[0106] Embodiment 3: The apparatus of Embodiment 1 or Embodiment 2, further comprising a dielectric material vertically interposed between the gate structure and the upper conductive contact and horizontally interposed between the gate structure and the upper conductive contact.

[0107] Embodiment 4: The device of any one of Embodiments 1 to 3, wherein the first semiconductor pillar and the second semiconductor pillar each include at least one oxide semiconductor material.

[0108] Embodiment 5: The apparatus of any one of Embodiments 1 to 4, wherein the first semiconductor pillar and the second semiconductor pillar of the split body channel are both vertically located on the lower conductive contact.

[0109] Embodiment 6: The apparatus of any one of Embodiments 1 to 5, further comprising at least one conductive wiring structure coupled to the gate structure and at least one other structure and extending from between the gate structure and the at least one other structure.

[0110] Embodiment 7: The device of any one of Embodiments 1 to 6, further comprising a passivation material on a side of each of the first semiconductor pillar and the second semiconductor pillar that is not surrounded by the gate structure.

[0111] Embodiment 8: A device according to any one of Embodiments 1 to 7, wherein the at least one transistor includes at least two horizontally adjacent transistors, and the conductive material is horizontally inserted between and electrically insulated from the at least two horizontally adjacent transistors.

[0112] Embodiment 9: A method for forming a device, the method comprising: forming a conductive line extending in a first direction; forming a semiconductor pillar structure on the conductive line; horizontally forming a conductive material between at least two of the semiconductor pillar structures; forming an opening vertically extending through a portion of the semiconductor pillar structure and the conductive material to separate each of the at least two semiconductor pillar structures into two relatively smaller semiconductor pillar structures, and forming a gate structure from the conductive material, the central portion of the gate structure extending in a second direction transverse to the first direction; and at least partially filling the opening with a dielectric material.

[0113] Embodiment 10: The method according to Embodiment 9 further includes forming a gate dielectric material between the gate structure and the semiconductor pillar structure before forming the opening.

[0114] Embodiment 11: The method according to Embodiment 9 or Embodiment 10, further comprising vertically forming at least two conductive contact structures between the conductive line and the semiconductor pillar structure.

[0115] Embodiment 12: The method according to any one of Embodiments 9 to 11, further comprising: recessing the conductive material before forming the opening; and forming an electrical insulating material on the recessed conductive material.

[0116] Embodiment 13: The method of any one of Embodiments 9 to 12, further comprising partially filling the opening with a conductive material, the conductive material being horizontally surrounded by the dielectric material.

[0117] Embodiment 14: A memory device comprises: a memory cell, the memory cell comprising an access device electrically coupled to a memory element, the access device comprising: a conductive material, the conductive material comprising an elongated portion extending in one direction and a lateral protrusion extending in another direction substantially transverse to the direction; a first channel region, the first channel region being adjacent to a first side of the conductive material; a second channel region, the second channel region being adjacent to a second side of the conductive material, the second side being opposite to the first side; and a gate dielectric, the gate dielectric being between the first channel region and the conductive material and between the second channel region and the conductive material.

[0118] Embodiment 15: The memory device of Embodiment 14, wherein each of the first channel region and the second channel region contacts the conductive material in a first plane and in a second plane intersecting the first plane.

[0119] Embodiment 16: The memory device of Embodiment 14 or Embodiment 15 further comprising a passivation material adjacent to each of the first channel region and the second channel region on a side opposite to the conductive material.

[0120] Embodiment 17: The memory device of Embodiment 16, wherein each of the first channel region and the second channel region comprises an oxide semiconductor material, and the passivation material comprises at least one of a silicon nitride material or an yttrium oxide material.

[0121] Embodiment 18: The memory device of any one of Embodiments 14 to 17, wherein each of the first channel region and the second channel region comprises at least one of the following: ZTO, IZO, ZnO x , IGZO, IGSO, InO x 、In2O3、SnO2、TiO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a , Ga x Zn ySn z O a 、Zr x Zn y Sn z O a , InGaSiO or IWO.

[0122] Embodiment 19: A memory device according to any one of Embodiments 14 to 18, wherein the lateral protrusions of the conductive material extend from the elongated portion thereof on a first side and an opposite second side, the lateral protrusions of the first side extend between horizontally adjacent portions of corresponding first channel regions of adjacent transistors, and the lateral protrusions of the second side extend between horizontally adjacent portions of corresponding second channel regions of adjacent transistors.

[0123] Embodiment 20: The memory device of any one of Embodiments 14 to 19, further comprising a shielding material and at least one dielectric material horizontally separating adjacent access devices.

[0124] Embodiment 21: An electronic system comprises: at least one input device; at least one output device; at least one processor device, the at least one processor device being operably coupled to the at least one input device and the at least one output device; and a memory device, the memory device being operably coupled to the at least one processor device, the memory device comprising: a transistor array, at least one transistor of the transistor array comprising: a gate structure, the gate structure covering a conductive contact; a first pillar structure, the first pillar structure being horizontally adjacent to a first lateral side of the gate structure; a second pillar structure, the second pillar structure being horizontally adjacent to a second lateral side of the gate structure opposite to the first lateral side, the gate structure being located between the first pillar structure and the second pillar structure; and a passivation material, the passivation material being adjacent to each of the first pillar structure and the second pillar structure on a side opposite to the gate structure, the passivation material being in direct physical contact with a portion of the gate structure.

[0125] Although certain illustrative embodiments have been described in conjunction with the accompanying drawings, those of ordinary skill in the art will recognize and appreciate that the embodiments encompassed by the present disclosure are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications may be made to the embodiments described herein, such as those required below, including legal equivalents, without departing from the scope of the embodiments encompassed by the present disclosure. Furthermore, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the present disclosure.

Claims

1. An electronic device, comprising: Conductive structure; as well as At least two horizontally adjacent transistors in a volatile memory device, the at least two horizontally adjacent transistors being in electrical communication with the conductive structure, the at least two horizontally adjacent transistors respectively comprising: a lower conductive contact coupled to one of the conductive structures; a split body channel on the lower conductive contact and comprising: a first semiconductor column; and a second semiconductor column, the second semiconductor column being horizontally adjacent to the first semiconductor column; a gate structure horizontally interposed between the first semiconductor pillar and the second semiconductor pillar of the split body channel, the gate structure being configured as a single access line having a portion of the gate structure surrounding three sides of each of the first semiconductor pillar and the second semiconductor pillar; an upper conductive contact vertically overlying the gate structure and coupled to the split-body channel; and A conductive material is horizontally interposed between and electrically insulated from the at least two horizontally adjacent transistors. 2 . The electronic device of claim 1 , further comprising a single gate dielectric material directly horizontally located between the gate structure and the three sides of each of the first and second semiconductor pillars of the split body channel. 3 . The electronic device of claim 1 , further comprising a dielectric material vertically interposed between the gate structure and the upper conductive contact and horizontally interposed between the gate structure and the upper conductive contact. 4 . The electronic device according to claim 1 , wherein the first semiconductor column and the second semiconductor column each include at least one oxide semiconductor material. 5 . The electronic device according to claim 1 , wherein the first semiconductor pillar and the second semiconductor pillar of the split body channel are both vertically located on the lower conductive contact.

6. The electronic device of any one of claims 1 to 3, further comprising at least one conductive wiring structure coupled to the gate structure and at least one other structure and extending from between the gate structure and the at least one other structure.

7. The electronic device according to any one of claims 1 to 3 further includes a single passivation material on the side of each of the first semiconductor column and the second semiconductor column that is not surrounded by the gate structure, and the single passivation material is in direct physical contact with the gate structure and the semiconductor material of each of the first semiconductor column and the second semiconductor column. 8 . The electronic device of claim 1 , wherein the gate structure comprises a single continuous portion of conductive material horizontally interposed between the first semiconductor pillar and the second semiconductor pillar.

9. A method of forming an electronic device, the method comprising: forming a conductive structure extending in a first direction; forming a lower conductive contact over and coupled to one of the conductive structures; forming a first semiconductor pillar and a second semiconductor pillar on the lower conductive contact to form a split body channel, the second semiconductor pillar being horizontally adjacent to the first semiconductor pillar; forming a conductive material horizontally between the first semiconductor pillar and the second semiconductor pillar; forming an opening vertically extending through the first semiconductor pillar, the second semiconductor pillar, and a portion of the conductive material to separate each of the first semiconductor pillar and the second semiconductor pillar into two relatively smaller semiconductor pillars, and forming a gate structure from the conductive material, a central portion of the gate structure being horizontally interposed between the first semiconductor pillar and the second semiconductor pillar and extending in a second direction transverse to the first direction, The gate structure is configured as a single access line having a portion of the gate structure surrounding three sides of each of the first semiconductor pillar and the second semiconductor pillar; at least partially filling the opening with a dielectric material; forming an upper conductive contact over the gate structure and coupled to the split body channel to form a transistor of a volatile memory device; as well as A conductive material is formed that is horizontally interposed between and electrically insulated from at least two horizontally adjacent transistors. 10 . The method of claim 9 , further comprising forming a gate dielectric material between the gate structure and each of the first and second semiconductor pillars before forming the opening. 11 . The method of claim 9 or claim 10 , further comprising forming an additional conductive contact structure vertically between the conductive structure and each of the first semiconductor pillar and the second semiconductor pillar.

12. The method according to claim 9 or claim 10, further comprising: recessing the conductive material before forming the opening; as well as An electrical insulating material is formed on the recessed conductive material.

13. The method of claim 9 or claim 10, further comprising partially filling the opening with the conductive material, the conductive material being horizontally surrounded by the dielectric material.

14. A memory device comprising: A memory cell in a volatile memory device, the memory cell comprising an access device electrically coupled to a memory element, the access device comprising: a conductive material of the gate structure, the conductive material comprising an elongated portion extending in a first horizontal direction and a lateral protrusion extending in a second horizontal direction substantially transverse to the first horizontal direction, the elongated portion and the lateral protrusion of the conductive material being configured as a single access line; a first channel region, the first channel region being adjacent to a first side of the conductive material; a second channel region, the second channel region being adjacent to a second side surface of the conductive material, the second side surface being opposite to the first side surface; a gate dielectric between the first channel region and the conductive material of the gate structure and between the second channel region and the conductive material; and A shielding material and at least one dielectric material isolating horizontally adjacent access devices, the shielding material comprising a conductive material electrically insulated and physically isolated from each of the first channel region and the second channel region. 15 . The memory device of claim 14 , wherein each of the first channel region and the second channel region is adjacent to the conductive material in a first horizontal plane and in a second horizontal plane intersecting the first horizontal plane.

16. The memory device of claim 14, further comprising a single passivation material directly adjacent to each of the first channel region and the second channel region on a side opposite the conductive material. 17 . The memory device of claim 16 , wherein each of the first channel region and the second channel region comprises an oxide semiconductor material, and the single passivation material comprises a silicon nitride material or a yttrium oxide material.

18. The memory device according to any one of claims 14 to 17, wherein each of the first channel region and the second channel region comprises at least one of the following: ZTO, IZO, ZnO x , IGZO, IGSO, InO x 、In2O3、SnO2、TiO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Si x In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a , Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InGaSiO or IWO.

19. A memory device according to any one of claims 14 to 17, wherein the lateral protrusion of the conductive material extends horizontally from the elongated portion at a first side of the elongated portion and an opposite second side of the elongated portion, the lateral protrusion of the first side extends between horizontally adjacent portions of corresponding first channel regions of adjacent transistors, and the lateral protrusion of the second side extends between horizontally adjacent portions of corresponding second channel regions of adjacent transistors.

20. The memory device of any one of claims 14 to 17, wherein the access device comprises a tri-gate transistor comprising a single gate structure.

21. The memory device of any one of claims 14 to 17, wherein the volatile memory device is a DRAM device comprising dynamic random access memory (DRAM) memory cells.

22. A memory device according to any one of claims 14 to 17, wherein the gate dielectric comprises a single material directly located between the first channel region and the conductive material of the gate structure and between the second channel region and the conductive material, the gate dielectric extending in a first horizontal direction and a second horizontal direction and substantially surrounding each of the first channel region and the second channel region on three continuous sides.

23. An electronic system comprising: at least one input device; at least one output device; at least one processor device operatively coupled to the at least one input device and the at least one output device; as well as a dynamic random access memory (DRAM) device, the memory device being operatively coupled to the at least one processor device, the DRAM device comprising: A transistor array, wherein at least one transistor of the transistor array comprises: a gate structure covering the conductive contacts; a first pillar structure, the first pillar structure being horizontally adjacent to a first lateral side of the gate structure; a second pillar structure horizontally adjacent to a second lateral side of the gate structure opposite the first lateral side, the gate structure being located between the first pillar structure and the second pillar structure and configured as a single word line of the at least one transistor; a passivation material adjacent to each of the first pillar structure and the second pillar structure at a side opposite the gate structure, the passivation material being in direct physical contact with a portion of the gate structure; and A shielding material is adjacent to the passivation material and isolates horizontally adjacent transistors of the transistor array, the shielding material comprising a conductive material that is electrically insulated and physically isolated from a channel region of each of the first pillar structure and the second pillar structure. 24 . The electronic system of claim 23 , further comprising a digit line and a digit line contact overlying the digit line, the gate structure overlying the digit line contact.

25. The electronic system of claim 23, wherein the passivation material comprises a single material directly adjacent to each of the first pillar structure and the second pillar structure.

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