Semiconductor devices

Abstract

The semiconductor device of the embodiment comprises: an insulating substrate; a first main terminal; a second main terminal; an output terminal; a first metal layer connected to the first main terminal; a second metal layer connected to the second main terminal; a third metal layer located between the first metal layer and the second metal layer and connected to the output terminal; a first semiconductor chip and a second semiconductor chip disposed on the first metal layer; and a third semiconductor chip and a fourth semiconductor chip disposed on the third metal layer. In addition, the second metal layer includes a first slit. Alternatively, the third metal layer includes a second slit.

Description

[0001] This application claims the benefit of priority based on Japanese Patent Application No. 2020-82417 (filing date: May 8, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments mainly relate to semiconductor devices. Background Art

[0003] For a power semiconductor module, for example, a power semiconductor chip is mounted on a metal substrate with an insulating substrate sandwiched between them. For example, a power semiconductor chip is a MOSFET (Metallic Oxide Semiconductor Field Effect transistor). For a power semiconductor module, in order to reduce power consumption, it is expected to reduce the on-off time and the on-off loss. Summary of the invention

[0004] Embodiments provide a semiconductor device capable of reducing switching loss.

[0005] A semiconductor device according to an embodiment comprises: an insulating substrate having one end and another end on the opposite side of the one end; a first main terminal provided on the one end side; a second main terminal provided on the one end side; an output terminal provided on the other end side; a first metal layer provided on the insulating substrate and having a first region, the first region being electrically connected to the first main terminal; a second metal layer provided on the insulating substrate and having a second region, a third region and a fourth region, the second region being electrically connected to the second main terminal; a third metal layer provided on the insulating substrate and located between the first metal layer and the second metal layer, having a fifth region, a sixth region and a seventh region, the seventh region being electrically connected to the output terminal; a first semiconductor chip including a first upper electrode, a first lower electrode and a first gate electrode, provided on the first metal layer, the first upper electrode being electrically connected to the fifth region, the first lower electrode being electrically connected to the first metal layer; a second semiconductor chip including a second upper electrode, a second lower electrode and a second gate electrode, provided on the first metal layer, the second upper electrode and the second lower electrode being electrically connected to the first metal layer; The upper electrode is electrically connected to the sixth region, the second lower electrode is electrically connected to the first metal layer, and the distance from the first region is farther than the first semiconductor chip; a third semiconductor chip, including a third upper electrode, a third lower electrode and a third gate electrode, is arranged on the third metal layer, the third upper electrode is electrically connected to the third region, and the third lower electrode is electrically connected to the third metal layer; and a fourth semiconductor chip, including a fourth upper electrode, a fourth lower electrode and a fourth gate electrode, is arranged on the third metal layer, the fourth upper electrode is electrically connected to the fourth region, the fourth lower electrode is electrically connected to the third metal layer, and the distance from the fifth region is farther than the third semiconductor chip, the second metal layer has a first end on the side opposite to the third metal layer and a second end on the side opposite to the first end, and includes a first slit located between the third region and the second end; or the third metal layer has a third end on the side opposite to the first metal layer and a fourth end on the side opposite to the third end, and includes a second slit located between the fifth region and the fourth end. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a schematic plan view of the semiconductor device according to the first embodiment.

[0007] Figure 2 It is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0008] Figure 3 It is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0009] Figure 4 It is an equivalent circuit diagram of the semiconductor device according to the first embodiment.

[0010] Figure 5 It is a schematic top view of a semiconductor device according to a comparative example.

[0011] Figure 6 It is a schematic plan view of a semiconductor device according to a second embodiment.

[0012] Figure 7 It is a schematic plan view of a semiconductor device according to a third embodiment.

[0013] Figure 8 It is a schematic plan view of a semiconductor device according to a fourth embodiment.

[0014] Fig. 9 It is a schematic plan view of a semiconductor device according to a modification of the fourth embodiment.

[0015] Fig.10 It is a schematic plan view of a semiconductor device according to a fifth embodiment.

[0016] Fig.11 It is a schematic plan view of a semiconductor device according to a modification of the fifth embodiment. DETAILED DESCRIPTION

[0017] In this specification, the same reference numerals are given to the same or similar components, and duplicate description may be omitted.

[0018] In this specification, in order to express the positional relationship of components, the upper direction of the drawings may be described as "up" and the lower direction of the drawings may be described as "down". In this specification, the concepts of "up" and "down" are not necessarily terms that express the relationship with the direction of gravity.

[0019] (First Embodiment)

[0020] A semiconductor device according to a first embodiment comprises: an insulating substrate; a first main terminal, arranged at one end side of the insulating substrate; a second main terminal, arranged at one end side of the insulating substrate; an output terminal, arranged at the other end side of the insulating substrate; a first metal layer, arranged on the insulating substrate, having a first region, and electrically connected to the first main terminal in the first region; a second metal layer, arranged on the insulating substrate, having a second region, a third region and a fourth region, and electrically connected to the second main terminal in the second region; a third metal layer, arranged on the insulating substrate, located between the first metal layer and the second metal layer, having a fifth region, a sixth region and a seventh region, and electrically connected to the output terminal in the seventh region; a first semiconductor chip, including a first upper electrode, a first lower electrode and a first gate electrode, arranged on the first metal layer, the first upper electrode being electrically connected to the fifth region, the first lower electrode being electrically connected to the fifth region, the first lower electrode being electrically connected to the fifth region, the second lower electrode being electrically connected to the fifth region, and the third lower electrode being electrically connected to the fifth region. a lower electrode electrically connected to the first metal layer; a second semiconductor chip including a second upper electrode, a second lower electrode and a second gate electrode, disposed on the first metal layer, the second upper electrode electrically connected to the sixth region, the second lower electrode electrically connected to the first metal layer, and the distance from the first region is farther than the first semiconductor chip; a third semiconductor chip including a third upper electrode, a third lower electrode and a third gate electrode, disposed on the third metal layer, the third upper electrode electrically connected to the third region, the third lower electrode electrically connected to the third metal layer; and a fourth semiconductor chip including a fourth upper electrode, a fourth lower electrode and a fourth gate electrode, disposed on the third metal layer, the fourth upper electrode electrically connected to the fourth region, the fourth lower electrode electrically connected to the third metal layer, and the distance from the fifth region is farther than the third semiconductor chip. In addition, the second metal layer has a first end on the side opposite to the third metal layer and a second end on the side opposite to the first end, and includes a first slit between the third region and the second end.

[0021] Figure 1 It is a schematic plan view of the semiconductor device according to the first embodiment. Figure 2 It is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 express Figure 1 AA' section. Figure 3 It is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 3 express Figure 1 BB' section. Figure 4 It is an equivalent circuit diagram of the semiconductor device according to the first embodiment.

[0022] The semiconductor device of the first embodiment is a power semiconductor module 100. Figure 4As shown, the power semiconductor module 100 of the first embodiment is a so-called "2in1" type module that can form a half-bridge circuit with one module. The power semiconductor module 100 connects three half-bridge units in parallel. For example, a three-phase inverter circuit can be formed by using three power semiconductor modules of the first embodiment.

[0023] like Figure 4 As shown, the power semiconductor module 100 includes a positive terminal P (first main terminal), a negative terminal N (second main terminal), an AC output terminal AC (output terminal), a high-side MOSFET 11, a high-side MOSFET 12, a high-side MOSFET 13, a low-side MOSFET 21, a low-side MOSFET 22, and a low-side MOSFET 23. In addition to the pn junction diode, each MOSFET also has a built-in Schottky barrier diode (SBD). The SBD has a function of flowing a return current, for example. In addition, each MOSFET has a built-in gate resistor.

[0024] The high-side MOSFET 11, the high-side MOSFET 12, and the high-side MOSFET 13 are connected in parallel. The low-side MOSFET 21, the low-side MOSFET 22, and the low-side MOSFET 23 are connected in parallel. The high-side MOSFET 11 and the low-side MOSFET 21, the high-side MOSFET 12 and the low-side MOSFET 22, and the high-side MOSFET 13 and the low-side MOSFET 23 are connected in series, respectively.

[0025] The power semiconductor module 100 of the first embodiment is as follows Figure 1 , Figure 2 and Figure 3 The device shown has a positive terminal P (first main terminal), a negative terminal N (second main terminal), an AC output terminal AC (output terminal), a high-side MOSFET 11 (first semiconductor chip), a high-side MOSFET 12 (second semiconductor chip), a high-side MOSFET 13, a low-side MOSFET 21 (third semiconductor chip), a low-side MOSFET 22 (fourth semiconductor chip), a low-side MOSFET 23, a resin case 24, a cover 26, a metal base 28, an insulating substrate 30, a first metal layer 31, a second metal layer 32, a third metal layer 33, a first gate metal layer 36, a second gate metal layer 37, a back metal layer 40, a first gate terminal 41, a second gate terminal 42, a bonding wire 44, and a sealing resin 50.

[0026] The high-side MOSFET 11 (first semiconductor chip) includes a source electrode 11a (first upper electrode), a drain electrode 11b (first lower electrode), a gate electrode 11c (first gate electrode), a gate resistor 11x (first gate resistor), and a Schottky barrier diode 11y (first Schottky barrier diode). The high-side MOSFET 12 (second semiconductor chip) includes a source electrode 12a (second upper electrode), a drain electrode 12b (second lower electrode), a gate electrode 12c (second gate electrode), a gate resistor 12x (second gate resistor), and a Schottky barrier diode 12y (second Schottky barrier diode). The high-side MOSFET 13 includes a source electrode 13a, a drain electrode 13b, a gate electrode 13c, a gate resistor 13x, and a Schottky barrier diode 13y.

[0027] The low-side MOSFET 21 (third semiconductor chip) includes a source electrode 21a (third upper electrode), a drain electrode 21b (third lower electrode), a gate electrode 21c (third gate electrode), a gate resistor 21x (third gate resistor), and a Schottky barrier diode 21y (third Schottky barrier diode). The low-side MOSFET 22 (fourth semiconductor chip) includes a source electrode 22a (fourth upper electrode), a drain electrode 22b (fourth lower electrode), a gate electrode 22c (fourth gate electrode), a gate resistor 22x (fourth gate resistor), and a Schottky barrier diode 22y (fourth Schottky barrier diode). The low-side MOSFET 23 includes a source electrode 23a, a drain electrode 23b, a gate electrode 23c, a gate resistor 23x (first gate resistor), and a Schottky barrier diode 23y (first Schottky barrier diode).

[0028] The first metal layer 31 includes a first region 31a. The second metal layer 32 includes a second region 32a, a third region 32b, a fourth region 32c, a first slit 32x, a first end E1, and a second end E2. The third metal layer 33 includes a fifth region 33a, a sixth region 33b, a seventh region 33c, a third end E3, and a fourth end E4.

[0029] Figure 1 This is a plan view of the power semiconductor module 100 in a state where the cover 26 and the sealing resin 50 are removed.

[0030] The metal base 28 is made of copper, for example. For example, when the power semiconductor module 100 is mounted on a product, a heat sink (not shown) is connected to the back surface of the metal base 28 .

[0031] The insulating substrate 30 is disposed on the metal base 28. The insulating substrate 30 is disposed between the metal base 28 and the high-side MOSFET 11, between the metal base 28 and the high-side MOSFET 12, between the metal base 28 and the high-side MOSFET 13, between the metal base 28 and the low-side MOSFET 21, between the metal base 28 and the low-side MOSFET 22, and between the metal base 28 and the low-side MOSFET 23.

[0032] The insulating substrate 30 has the function of electrically isolating the metal substrate 28 and the high-side MOSFET 11, the metal substrate 28 and the high-side MOSFET 12, the metal substrate 28 and the high-side MOSFET 13, the metal substrate 28 and the low-side MOSFET 21, the metal substrate 28 and the low-side MOSFET 22, and the metal substrate 28 and the low-side MOSFET 23.

[0033] The insulating substrate 30 is, for example, ceramics. The insulating substrate 30 is, for example, aluminum oxide, aluminum nitride, or silicon nitride.

[0034] A first metal layer 31, a second metal layer 32, a third metal layer 33, a first gate metal layer 36 and a second gate metal layer 37 are provided on the surface of the insulating substrate 30. The first metal layer 31, the second metal layer 32, the third metal layer 33, the first gate metal layer 36 and the second gate metal layer 37 are, for example, copper.

[0035] A back metal layer 40 is provided on the back surface of the insulating substrate 30. The back metal layer 40 is made of copper, for example. The back metal layer 40 is bonded to the metal base 28 using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0036] The resin case 24 is provided around the metal base 28 and the insulating substrate 30. A portion of the resin case 24 is provided on the metal base 28. The resin case 24 has a function of protecting the high-side MOSFET 11, the high-side MOSFET 12, the high-side MOSFET 13, the low-side MOSFET 21, the low-side MOSFET 22, the low-side MOSFET 23 and the insulating substrate 30.

[0037] A cover 26 is provided on the resin case 24. The cover 26 has a function of protecting the high-side MOSFETs 11, 12, 13, the low-side MOSFETs 21, 22, 23, and the insulating substrate 30.

[0038] The high-side MOSFET 11 is disposed on the first metal layer 31. The high-side MOSFET 11 includes a source electrode 11a, a drain electrode 11b, a gate electrode 11c, a gate resistor 11x, and a Schottky barrier diode 11y. The source electrode 11a is an example of a first upper electrode. The drain electrode 11b is an example of a first lower electrode. The gate electrode 11c is an example of a first gate electrode. The gate resistor 11x is an example of a first gate resistor. The Schottky barrier diode 11y is an example of a first Schottky barrier diode.

[0039] The source electrode 11a is electrically connected to the fifth region 33a of the third metal layer 33. The source electrode 11a and the fifth region 33a are electrically connected using, for example, a bonding wire 44. The drain electrode 11b is electrically connected to the first metal layer 31. The drain electrode 11b is electrically connected to the first metal layer 31 using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0040] The high-side MOSFET 12 is provided on the first metal layer 31. The distance from the first region 31a to the high-side MOSFET 12 is greater than the distance from the first region 31a to the high-side MOSFET 11.

[0041] The high-side MOSFET 12 includes a source electrode 12a, a drain electrode 12b, a gate electrode 12c, a gate resistor 12x, and a Schottky barrier diode 12y. The source electrode 12a is an example of a second upper electrode. The drain electrode 12b is an example of a second lower electrode. The gate electrode 12c is an example of a second gate electrode. The gate resistor 12x is an example of a second gate resistor. The Schottky barrier diode 12y is an example of a second Schottky barrier diode.

[0042] The source electrode 12a is electrically connected to the sixth region 33b of the third metal layer 33. The source electrode 12a and the sixth region 33b are electrically connected, for example, using a bonding wire 44. The drain electrode 12b is electrically connected to the first metal layer 31. The drain electrode 12b is electrically connected to the first metal layer 31 using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0043] The high-side MOSFET 13 is provided on the first metal layer 31. The distance from the first region 31a to the high-side MOSFET 13 is greater than the distance from the first region 31a to the high-side MOSFET 12.

[0044] The high-side MOSFET 13 includes a source electrode 13 a , a drain electrode 13 b , a gate electrode 13 c , a gate resistor 13 x , and a Schottky barrier diode 13 y .

[0045] The source electrode 13a is electrically connected to the third metal layer 33. The source electrode 13a and the third metal layer 33 are electrically connected using, for example, a bonding wire 44. The drain electrode 13b is electrically connected to the first metal layer 31. The drain electrode 13b is electrically connected to the first metal layer 31 using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0046] The low-side MOSFET 21 is provided on the third metal layer 33. The low-side MOSFET 21 includes a source electrode 21a, a drain electrode 21b, a gate electrode 21c, a gate resistor 21x, and a Schottky barrier diode 21y. The source electrode 21a is an example of a third upper electrode. The drain electrode 21b is an example of a third lower electrode. The gate electrode 21c is an example of a third gate electrode. The gate resistor 21x is an example of a third gate resistor. The Schottky barrier diode 21y is an example of a third Schottky barrier diode.

[0047] The source electrode 21a is electrically connected to the third region 32b of the second metal layer 32. The source electrode 21a and the third region 32b are electrically connected, for example, using a bonding wire 44. The drain electrode 21b is electrically connected to the third metal layer 33. The drain electrode 21b is electrically connected to the third metal layer 33 using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0048] The low-side MOSFET 22 is provided on the third metal layer 33. The distance from the fifth region 33a to the low-side MOSFET 22 is greater than the distance from the fifth region 33a to the low-side MOSFET 21.

[0049] The low-side MOSFET 22 includes a source electrode 22a, a drain electrode 22b, a gate electrode 22c, a gate resistor 22x, and a Schottky barrier diode 22y. The source electrode 22a is an example of a fourth upper electrode. The drain electrode 22b is an example of a fourth lower electrode. The gate electrode 22c is an example of a fourth gate electrode. The gate resistor 22x is an example of a fourth gate resistor. The Schottky barrier diode 22y is an example of a fourth Schottky barrier diode.

[0050] The source electrode 22a is electrically connected to the fourth region 32c of the second metal layer 32. The source electrode 22a and the fourth region 32c are electrically connected, for example, using a bonding wire 44. The drain electrode 22b is electrically connected to the third metal layer 33. The drain electrode 22b is electrically connected to the third metal layer 33 using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0051] The low-side MOSFET 23 is provided on the third metal layer 33. The distance from the fifth region 33a to the low-side MOSFET 23 is greater than the distance from the fifth region 33a to the low-side MOSFET 22.

[0052] The low-side MOSFET 23 includes a source electrode 23 a , a drain electrode 23 b , a gate electrode 23 c , a gate resistor 23 x , and a Schottky barrier diode 23 y .

[0053] The source electrode 23a is electrically connected to the second metal layer 32. The source electrode 23a and the second metal layer 32 are electrically connected using, for example, a bonding wire 44. The drain electrode 23b is electrically connected to the third metal layer 33. The drain electrode 23b is electrically connected to the third metal layer 33 using, for example, a solder layer or a silver nanoparticle layer (not shown).

[0054] The high-side MOSFET 11, the high-side MOSFET 12, the high-side MOSFET 13, the low-side MOSFET 21, the low-side MOSFET 22, and the low-side MOSFET 23 are formed using, for example, silicon carbide (SiC). The high-side MOSFET 11, the high-side MOSFET 12, the high-side MOSFET 13, the low-side MOSFET 21, the low-side MOSFET 22, and the low-side MOSFET 23 include silicon carbide. The high-side MOSFET 11, the high-side MOSFET 12, the high-side MOSFET 13, the low-side MOSFET 21, the low-side MOSFET 22, and the low-side MOSFET 23 include a silicon carbide layer not shown.

[0055] The sealing resin 50 is filled in the resin case 24. The sealing resin 50 is surrounded by the resin case 24. The sealing resin 50 covers the high-side MOSFET 11, the high-side MOSFET 12, the high-side MOSFET 13, the low-side MOSFET 21, the low-side MOSFET 22, the low-side MOSFET 23 and the insulating substrate 30.

[0056] The sealing resin 50 has a function of protecting the high-side MOSFET 11, the high-side MOSFET 12, the high-side MOSFET 13, the low-side MOSFET 21, the low-side MOSFET 22, the low-side MOSFET 23, and the insulating substrate 30. In addition, it has a function of insulating the high-side MOSFET 11, the high-side MOSFET 12, the high-side MOSFET 13, the low-side MOSFET 21, the low-side MOSFET 22, the low-side MOSFET 23, and the insulating substrate 30.

[0057] The sealing resin 50 includes resin. The sealing resin 50 is, for example, silicone. The sealing resin 50 may also be other resins such as epoxy resin and polyimide resin.

[0058] The positive terminal P is provided on one end side of the insulating substrate 30. Figure 1In the embodiment, the positive terminal P is provided on the right side of the insulating substrate 30. The positive terminal P has a wiring connection hole.

[0059] The positive terminal P is electrically connected to the first metal layer 31. The positive terminal P is electrically connected to the first region 31a of the first metal layer 31. The positive terminal P is electrically connected to the first region 31a using a bonding wire 44, for example.

[0060] For example, a positive voltage is applied to the positive terminal P from the outside.

[0061] The positive terminal P is formed of metal. The positive terminal P is, for example, copper.

[0062] The negative terminal N is provided on one end side of the insulating substrate 30. The negative terminal N and the positive terminal P are provided on the same side of the insulating substrate 30. Figure 1 In the embodiment, the negative terminal N is provided on the right side of the insulating substrate 30. The negative terminal N has a wiring connection hole.

[0063] The negative terminal N is electrically connected to the second metal layer 32. The negative terminal N is electrically connected to the second region 32a of the second metal layer 32. The negative terminal N is electrically connected to the second region 32a using a bonding wire 44, for example.

[0064] For example, a negative voltage is applied to the negative terminal N from the outside.

[0065] The negative terminal N is formed of metal, such as copper.

[0066] The AC output terminal AC is provided on the other end side of the insulating substrate 30. The AC output terminal AC is provided on the opposite side of the positive terminal P and the negative terminal N with the insulating substrate 30 interposed therebetween. Figure 1 In the embodiment, the AC output terminal AC is provided on the left side of the insulating substrate 30. The AC output terminal AC has a wiring connection hole. Figure 1 In FIG. 1 , a case where there are two AC output terminals AC is exemplified.

[0067] The AC output terminal AC is electrically connected to the third metal layer 33. The AC output terminal AC is electrically connected to the seventh region 33c of the third metal layer 33. The AC output terminal AC is electrically connected to the seventh region 33c using a bonding wire 44, for example.

[0068] The AC output terminal AC outputs the output current of the half-bridge circuit.

[0069] The first gate terminal 41 is electrically connected to the gate electrode 11c of the high-side MOSFET 11. The first gate terminal 41 is electrically connected to the gate electrode 11c using, for example, the first gate metal layer 36 and the bonding wire 44. No gate resistance component is provided between the first gate terminal 41 and the gate electrode 11c. The resistance between the first gate terminal 41 and the gate electrode 11c is, for example, 5Ω or less.

[0070] The first gate terminal 41 is electrically connected to the gate electrode 12c of the high-side MOSFET 12. The first gate terminal 41 is electrically connected to the gate electrode 12c using, for example, the first gate metal layer 36 and the bonding wire 44. No gate resistance component is provided between the first gate terminal 41 and the gate electrode 12c. The resistance between the first gate terminal 41 and the gate electrode 12c is, for example, 5Ω or less.

[0071] The first gate terminal 41 is electrically connected to the gate electrode 13c of the high-side MOSFET 13. The first gate terminal 41 is electrically connected to the gate electrode 13c using, for example, the first gate metal layer 36 and the bonding wire 44. No gate resistance component is provided between the first gate terminal 41 and the gate electrode 13c. The resistance between the first gate terminal 41 and the gate electrode 13c is, for example, 5Ω or less.

[0072] The second gate terminal 42 is electrically connected to the gate electrode 21c of the low-side MOSFET 21. The second gate terminal 42 is electrically connected to the gate electrode 21c using, for example, the second gate metal layer 37 and the bonding wire 44. No gate resistance component is provided between the second gate terminal 42 and the gate electrode 21c. The resistance between the second gate terminal 42 and the gate electrode 21c is, for example, 5Ω or less.

[0073] The second gate terminal 42 is electrically connected to the gate electrode 22c of the low-side MOSFET 22. The second gate terminal 42 is electrically connected to the gate electrode 22c using, for example, the second gate metal layer 37 and the bonding wire 44. No gate resistance component is provided between the second gate terminal 42 and the gate electrode 22c. The resistance between the second gate terminal 42 and the gate electrode 22c is, for example, 5Ω or less.

[0074] The second gate terminal 42 is electrically connected to the gate electrode 23c of the low-side MOSFET 23. The second gate terminal 42 is electrically connected to the gate electrode 23c using, for example, the second gate metal layer 37 and the bonding wire 44. No gate resistance component is provided between the second gate terminal 42 and the gate electrode 23c. The resistance between the second gate terminal 42 and the gate electrode 23c is, for example, 5Ω or less.

[0075] The first metal layer 31 is disposed on the insulating substrate 30. The first metal layer 31 includes a first region 31a. The first metal layer 31 is electrically connected to the positive terminal P in the first region 31a.

[0076] The second metal layer 32 is provided on the insulating substrate 30. The second metal layer 32 includes a second region 32a, a third region 32b, and a fourth region 32c. The second metal layer 32 is electrically connected to the negative terminal N in the second region 32a. The second metal layer 32 is electrically connected to the source electrode 21a of the low-side MOSFET 21 in the third region 32b. The second metal layer 32 is electrically connected to the source electrode 22a of the low-side MOSFET 22 in the fourth region 32c.

[0077] The second metal layer 32 includes a first end E1 and a second end E2. The first end E1 is an end on the side facing the third metal layer 33. The second end E2 is an end on the opposite side to the first end E1, sandwiching the second metal layer 32.

[0078] The second metal layer 32 includes a first slit 32 x. The first slit 32 x is located between the third region 32 b and the second end portion E2. The first slit 32 x extends, for example, in a first direction from the low-side MOSFET 21 toward the low-side MOSFET 22.

[0079] For example, the first distance ( Figure 1 d1) is less than the second distance ( Figure 1 For example, the first distance d1 is less than 80% of the second distance d2.

[0080] The first slit 32 x has a function of increasing the parasitic inductance of the wiring of the low-side MOSFET 21 .

[0081] The length of the first slit 32x in the first direction ( Figure 1 L1 in the figure is, for example, greater than the length ( Figure 1 For example, the length L1 of the first slit 32x is not less than 120% and not more than 400% of the length L2 of the low-side MOSFET 21.

[0082] For the region including the first slit 32 x between the third region 32 b and the second end E2 , the density of the metal layer is lower than that between the fourth region 32 c and the second end E2 .

[0083] The third metal layer 33 is disposed on the insulating substrate 30. The third metal layer 33 includes a fifth region 33a, a sixth region 33b, and a seventh region 33c. The third metal layer 33 is electrically connected to the source electrode 11a of the high-side MOSFET 11 in the fifth region 33a. The third metal layer 33 is electrically connected to the source electrode 12a of the high-side MOSFET 12 in the sixth region 33b. The third metal layer 33 is electrically connected to the AC output terminal AC in the seventh region 33c.

[0084] The third metal layer 33 includes a third end E3 and a fourth end E4. The third end E3 is an end on the side opposite to the first metal layer 31. The fourth end E4 is an end on the side opposite to the third end E3, sandwiching the third metal layer 33. The fourth end E4 is an end on the side opposite to the second metal layer 32.

[0085] Next, the operation and effects of the power semiconductor module 100 according to the first embodiment will be described.

[0086] In order to reduce power consumption, it is desirable to reduce the on-off time and the on-off loss of a power semiconductor module. When a power semiconductor chip includes a MOSFET that performs unipolar operation, for example, compared with an IGBT (Insulated Gate Bipolar Transistor) that performs bipolar operation, the on-off time can be shortened.

[0087] Figure 5 It is a schematic top view of a semiconductor device according to a comparative example. Figure 5 is with Figure 1 The corresponding figure.

[0088] The semiconductor device of the comparative example is a power semiconductor module 900. The power semiconductor module 900 of the comparative example is different from the power semiconductor module 100 of the first embodiment in that the second metal layer 32 does not include the first slit 32x.

[0089] In addition, the power semiconductor module 900 of the comparative example is different from the power semiconductor module 100 of the first embodiment in that a gate resistor component is provided on the insulating substrate 30. That is, the power semiconductor module 900 includes a first gate resistor 51, a second gate resistor 52, a third gate resistor 53, a fourth gate resistor 61, a fifth gate resistor 62, and a sixth gate resistor 63. The first gate resistor 51, the second gate resistor 52, the third gate resistor 53, the fourth gate resistor 61, the fifth gate resistor 62, and the sixth gate resistor 63 are, for example, 5Ω or more, respectively.

[0090] The first gate resistor 51 is electrically connected between the first gate terminal 41 and the high-side MOSFET 11. The second gate resistor 52 is electrically connected between the first gate terminal 41 and the high-side MOSFET 12. The third gate resistor 53 is electrically connected between the first gate terminal 41 and the high-side MOSFET 13.

[0091] The fourth gate resistor 61 is electrically connected between the second gate terminal 42 and the low-side MOSFET 21. The fifth gate resistor 62 is electrically connected between the second gate terminal 42 and the low-side MOSFET 22. The sixth gate resistor 63 is electrically connected between the second gate terminal 42 and the low-side MOSFET 23.

[0092] The first gate resistor 51 , the second gate resistor 52 , the third gate resistor 53 , the fourth gate resistor 61 , the fifth gate resistor 62 , and the sixth gate resistor 63 have a function of suppressing an inrush current applied to the gate electrode of each MOSFET and suppressing ringing of the output of the power semiconductor module 900 .

[0093] The power semiconductor module 900 has high-side MOSFET 11, high-side MOSFET 12 and high-side MOSFET 13 connected in parallel similarly to the power semiconductor module 100. Also, the power semiconductor module 900 has low-side MOSFET 21, low-side MOSFET 22 and low-side MOSFET 23 connected in parallel similarly to the power semiconductor module 100.

[0094] For example, in the power semiconductor module 900, the wiring length from the negative terminal N to the MOSFET increases in the order of the low-side MOSFET 21, the low-side MOSFET 22, and the low-side MOSFET 23. Therefore, the parasitic inductance of the MOSFET wiring increases in the order of the low-side MOSFET 21, the low-side MOSFET 22, and the low-side MOSFET 23.

[0095] If the parasitic inductances of the MOSFETs arranged in parallel are different, a surge voltage generated by a voltage between a gate electrode and a source electrode of each MOSFET (hereinafter referred to as a gate voltage) fluctuates when the power semiconductor module 900 is turned on and off. Also, if the parasitic inductances of the MOSFETs arranged in parallel are different, a surge current flowing through, for example, an SBD built into each MOSFET fluctuates when the power semiconductor module 900 is turned on and off.

[0096] For example, when the high-side MOSFET is turned on, the surge voltage generated by the gate voltage of the low-side MOSFET in the off state is biased. For example, if a positive surge voltage is applied to the gate electrode, there is a possibility that a problem of false triggering and flow-through current may flow in the power semiconductor module 900. If the flow-through current flows, the power semiconductor module 900 may be damaged due to heat generation, for example.

[0097] In addition, for example, if a negative surge voltage is applied to the gate electrode, there is a possibility that the gate insulating film of the MOSFET may be damaged. If the gate insulating film of the MOSFET is damaged, the power semiconductor module 900 may be damaged.

[0098] For example, in the power semiconductor module 900 , a positive surge voltage is easily applied to the low-side MOSFET 21 close to the negative terminal N. Also, for example, a negative surge voltage is easily applied to the low-side MOSFET 23 far from the negative terminal N.

[0099] In addition, for example, when the high-side MOSFET is turned off, the magnitude of the surge current flowing through the SDB of the low-side MOSFET in the off state varies. If the surge current flowing through the SDB increases, the current flowing through the pn junction diode of the MOSFET may increase. In the case where the MOSFET is formed using silicon carbide, if a current flows through the pn junction diode of the bipolar operation, the on-resistance of the MOSFET may increase as the stacking defect grows. Due to the increase in the on-resistance of the MOSFET, the reliability of the power semiconductor module 900 may decrease.

[0100] For example, in the power semiconductor module 900 , a surge current flowing through the built-in SBD of the low-side MOSFET 21 close to the negative terminal N is likely to be larger than a surge current flowing through the SBD of the low-side MOSFET 22 and a surge current flowing through the SBD of the low-side MOSFET 23 .

[0101] As described above, the power semiconductor module 900 is susceptible to damage and reduced reliability during switching of the power semiconductor module 900 due to the deviation of the parasitic inductance of the wiring of the MOSFETs arranged in parallel. For example, by reducing the switching speed of the power semiconductor module 900, the surge voltage and surge current are reduced, so the above-mentioned problem can be solved. However, if the switching speed is reduced, the switching loss of the power semiconductor module 900 increases.

[0102] The second metal layer 32 of the power semiconductor module 100 of the first embodiment includes a first slit 32x. By providing the first slit 32x, the actual wiring length between the low-side MOSFET 21 closest to the negative terminal N and the negative terminal N becomes longer than that of the power semiconductor module 900 of the comparative example. Therefore, the parasitic inductance of the wiring between the low-side MOSFET 21 and the negative terminal N is increased compared with the power semiconductor module 900 of the comparative example. Therefore, the deviation of the parasitic inductance of the wiring of the MOSFETs arranged in parallel is reduced, and the damage and reduction of reliability when the power semiconductor module 100 is turned on and off are suppressed. Therefore, the on-off loss of the power semiconductor module 100 is reduced.

[0103] From the viewpoint of reducing the fluctuation of the parasitic inductance of the MOSFETs arranged in parallel, it is preferable that the first distance ( Figure 1 d1) is less than the second distance ( Figure 1 The first distance d1 is preferably less than 80% of the second distance d2, and more preferably less than 60%.

[0104] From the viewpoint of reducing the fluctuation of the parasitic inductance of the MOSFETs arranged in parallel, it is preferable that the length ( Figure 1 L1 in the figure is greater than the length of the low-side MOSFET 21 in the first direction ( Figure 1 The length L1 of the first slit 32x is preferably 120% or more of the length L2 of the low-side MOSFET 21, and more preferably 150% or more.

[0105] In addition, the power semiconductor module 100 of the first embodiment does not include a gate resistor component. Since there is no gate resistor component, there is no need to provide a space for the gate resistor component on the insulating substrate 30. Therefore, for example, the width of the first metal layer 31, the second metal layer 32, or the third metal layer 33 in the second direction can be made wider than that of the power semiconductor module 900 of the comparative example. Therefore, the parasitic inductance of the power semiconductor module 100 can be reduced, and the switching loss of the power semiconductor module 100 can be reduced.

[0106] Furthermore, each MOSFET of the power semiconductor module 100 according to the first embodiment has a gate resistor built into the chip, thereby suppressing an inrush current applied to each MOSFET and suppressing ringing of the output of the power semiconductor module 100 .

[0107] The power semiconductor module 100 does not include a gate resistor component. Therefore, the resistance between the first gate terminal 41 and the gate electrode of each high-side MOSFET is, for example, 5Ω or less. Also, the resistance between the second gate terminal 42 and the gate electrode of each low-side MOSFET is, for example, 5Ω or less.

[0108] According to the first embodiment described above, by reducing the fluctuation of the parasitic inductance of the power semiconductor chips arranged in parallel, the switching loss of the power semiconductor module can be reduced.

[0109] (Second Embodiment)

[0110] The third metal layer of the semiconductor device of the second embodiment has a third end on the side opposite to the first metal layer and a fourth end on the side opposite to the third end, and includes a second slit between the fifth region and the fourth end, which is different from the semiconductor device of the first embodiment. Below, the description of the contents repeated with the first embodiment will be omitted.

[0111] Figure 6 It is a schematic plan view of a semiconductor device according to a second embodiment. Figure 6 The first embodiment Figure 1 The corresponding figure.

[0112] The semiconductor device of the second embodiment is a power semiconductor module 200. The power semiconductor module 200 of the second embodiment is a so-called "2in1" type module that can configure a half-bridge circuit with one module. The power semiconductor module 200 connects three half-bridge units in parallel.

[0113] The third metal layer 33 is provided on the insulating substrate 30. The third metal layer 33 includes a fifth region 33a, a sixth region 33b, and a seventh region 33c. The third metal layer 33 is electrically connected to the source electrode 11a of the high-side MOSFET 11 in the fifth region 33a. The third metal layer 33 is electrically connected to the source electrode 12a of the high-side MOSFET 12 in the sixth region 33b. The third metal layer 33 is electrically connected to the AC output terminal AC in the seventh region 33c.

[0114] The third metal layer 33 includes a third end E3 and a fourth end E4. The third end E3 is an end on the side opposite to the first metal layer 31. The fourth end E4 is an end on the side opposite to the third end E3, sandwiching the third metal layer 33. The fourth end E4 is an end on the side opposite to the second metal layer 32.

[0115] The third metal layer 33 includes a second slit 33 x. The second slit 33 x is located between the fifth region 33 a and the fourth end portion E4. The second slit 33 x extends, for example, in a first direction from the low-side MOSFET 21 toward the low-side MOSFET 22.

[0116] For example, the third distance ( Figure 6 d3) is less than the fourth distance ( Figure 6 For example, the third distance d3 is less than 80% of the fourth distance d4.

[0117] The second slit 33 x has a function of increasing the parasitic inductance of the wiring of the high-side MOSFET 11 .

[0118] The length of the second slit 33x in the first direction ( Figure 6 L3 in the figure is, for example, greater than the length ( Figure 6 For example, the length L3 of the second slit 33x is not less than 120% and not more than 400% of the length L4 of the high-side MOSFET 11.

[0119] For the region including the second slit 33 x between the fifth region 33 a and the fourth end E4 , the density of the metal layer is lower than that between the sixth region 33 b and the fourth end E4 .

[0120] The power semiconductor module 200 of the second embodiment reduces the fluctuation of the parasitic inductance of the wiring of the MOSFETs arranged in parallel by providing the second slits 33x, thereby suppressing damage and reduction in reliability when the power semiconductor module 200 is turned on and off. Therefore, the switching loss of the power semiconductor module 200 is reduced.

[0121] From the viewpoint of reducing the fluctuation of the parasitic inductance of the MOSFETs arranged in parallel, the third distance ( Figure 6 d3) is less than the fourth distance ( Figure 6 The third distance d3 is preferably less than 80% of the fourth distance d4, and more preferably less than 60%.

[0122] From the viewpoint of reducing the fluctuation of the parasitic inductance of the MOSFETs arranged in parallel, it is preferable that the length ( Figure 6 L3 in the figure is greater than the length of the high-side MOSFET 11 in the first direction ( Figure 6 The length L3 of the second slit 33x is preferably 120% or more of the length L4 of the high-side MOSFET 11, and more preferably 150% or more.

[0123] According to the second embodiment described above, similarly to the first embodiment, by reducing the fluctuation of the parasitic inductance of the power semiconductor chips arranged in parallel, it is possible to reduce the switching loss of the power semiconductor module.

[0124] (Third Embodiment)

[0125] The second metal layer includes a first slit and the third metal layer includes a second slit, which is different from the semiconductor device of the first embodiment and the semiconductor device of the second embodiment.

[0126] Figure 7 It is a schematic plan view of a semiconductor device according to a third embodiment. Figure 7 The first embodiment Figure 1 The corresponding figure.

[0127] The semiconductor device of the third embodiment is a power semiconductor module 300. The power semiconductor module 300 of the third embodiment is a so-called "2in1" type module that can configure a half-bridge circuit with one module. The power semiconductor module 300 connects three half-bridge units in parallel.

[0128] The second metal layer 32 includes a first slit 32 x. The first slit 32 x is located between the third region 32 b and the second end portion E2. The first slit 32 x extends, for example, in a first direction from the low-side MOSFET 21 toward the low-side MOSFET 22.

[0129] The third metal layer 33 includes a second slit 33 x. The second slit 33 x is located between the fifth region 33 a and the fourth end portion E4. The second slit 33 x extends, for example, in a first direction from the low-side MOSFET 21 toward the low-side MOSFET 22.

[0130] The power semiconductor module 300 of the third embodiment reduces the fluctuation of the parasitic inductance of the wiring of the MOSFETs arranged in parallel by providing the first slit 32x and the second slit 33x. Therefore, damage and reduction in reliability during switching of the power semiconductor module 300 are suppressed. Therefore, the switching loss of the power semiconductor module 300 is reduced.

[0131] According to the third embodiment described above, similarly to the first and second embodiments, by reducing the fluctuation of the parasitic inductance of the power semiconductor chips arranged in parallel, it is possible to reduce the switching loss of the power semiconductor module.

[0132] (Fourth Embodiment)

[0133] The semiconductor device of the fourth embodiment comprises: an insulating substrate having one end and another end opposite to the one end; a first main terminal arranged on the one end side; a second main terminal arranged on the one end side; an output terminal arranged on the other end side; a first metal layer arranged on the insulating substrate, having a first region, and electrically connected to the first main terminal in the first region; a second metal layer arranged on the insulating substrate, having a second region, a third region, and a fourth region, and electrically connected to the second main terminal in the second region; a third metal layer arranged on the insulating substrate, located between the first metal layer and the second metal layer, having a fifth region, a sixth region, and a seventh region, and electrically connected to the output terminal in the seventh region; a first semiconductor chip, including a first upper electrode, a first lower electrode, and a first gate electrode, arranged on the first metal layer, and the first upper electrode and the fifth The first region is electrically connected, and the first lower electrode is electrically connected to the first metal layer; a second semiconductor chip, including a second upper electrode, a second lower electrode and a second gate electrode, is arranged on the first metal layer, the second upper electrode is electrically connected to the sixth region, the second lower electrode is electrically connected to the first metal layer, and the distance from the first region is farther than the first semiconductor chip; a third semiconductor chip, including a third upper electrode, a third lower electrode and a third gate electrode, is arranged on the third metal layer, the third upper electrode is electrically connected to the third region, and the third lower electrode is electrically connected to the third metal layer; and a fourth semiconductor chip, including a fourth upper electrode, a fourth lower electrode and a fourth gate electrode, is arranged on the third metal layer, the fourth upper electrode is electrically connected to the fourth region, the fourth lower electrode is electrically connected to the third metal layer, and the distance from the fifth region is farther than the third semiconductor chip. Furthermore, the second metal layer has a first end on the side opposite to the third metal layer and a second end on the opposite side to the first end, and includes a region between the third region and the second end where the density of the metal layer is lower than that between the fourth region and the second end; or the third metal layer has a third end on the side opposite to the first metal layer and a fourth end on the opposite side to the third end, and includes a region between the fifth region and the fourth end where the density of the metal layer is lower than that between the sixth region and the fourth end. The second metal layer of the semiconductor device of the fourth embodiment includes a plurality of holes instead of the first slit, which is different from the semiconductor device of the first embodiment. Below, some of the contents repeated in the first embodiment will be omitted.

[0134] Figure 8 It is a schematic plan view of a semiconductor device according to a fourth embodiment. Figure 8 The first embodiment Figure 1 The corresponding figure.

[0135] The semiconductor device of the fourth embodiment is a power semiconductor module 400. The power semiconductor module 400 of the fourth embodiment is a so-called "2in1" type module that can configure a half-bridge circuit with one module. The power semiconductor module 400 connects three half-bridge units in parallel.

[0136] The second metal layer 32 is provided on the insulating substrate 30. The second metal layer 32 includes a second region 32a, a third region 32b, and a fourth region 32c. The second metal layer 32 is electrically connected to the negative terminal N in the second region 32a. The second metal layer 32 is electrically connected to the source electrode 21a of the low-side MOSFET 21 in the third region 32b. The second metal layer 32 is electrically connected to the source electrode 22a of the low-side MOSFET 22 in the fourth region 32c.

[0137] The second metal layer 32 includes a first end E1 and a second end E2. The first end E1 is an end on the side facing the third metal layer 33. The second end E2 is an end on the opposite side to the first end E1, sandwiching the second metal layer 32.

[0138] The second metal layer 32 includes a plurality of holes 70. The plurality of holes 70 are located between the third region 32b and the second end portion E2.

[0139] For the region including the plurality of holes 70 between the third region 32 b and the second end E2 , the density of the metal layer is lower than that between the fourth region 32 c and the second end E2 .

[0140] The plurality of holes 70 have a function of increasing the parasitic inductance of the wiring of the low-side MOSFET 21 .

[0141] In the power semiconductor module 400 of the fourth embodiment, since a plurality of holes 70 are provided in the second metal layer 32, fluctuations in parasitic inductance of the wiring of the MOSFETs arranged in parallel are reduced. Therefore, damage and reduction in reliability during switching of the power semiconductor module 400 are suppressed. Therefore, switching losses of the power semiconductor module 400 are reduced.

[0142] (Variation Example)

[0143] Fig. 9 It is a schematic plan view of a semiconductor device according to a modification of the fourth embodiment. Fig. 9 is with Figure 8 The corresponding figure.

[0144] The semiconductor device according to the modification of the fourth embodiment is a power semiconductor module 450 . The power semiconductor module 450 is different from the power semiconductor module 400 in the arrangement pattern of the plurality of holes 70 .

[0145] The region including the plurality of holes 70 between the third region 32 b and the second end E2 has a lower density of the metal layer than that between the fourth region 32 c and the second end E2 .

[0146] According to the fourth embodiment and its modified example described above, similarly to the first to third embodiments, by reducing the fluctuation of the parasitic inductance of the power semiconductor chips arranged in parallel, it is possible to reduce the switching loss of the power semiconductor module.

[0147] (Fifth Embodiment)

[0148] The third metal layer of the semiconductor device of the fifth embodiment has a third end portion on the side opposite to the first metal layer and a fourth end portion on the side opposite to the third end portion, and includes a region between the fifth region and the fourth end portion where the density of the metal layer is lower than that between the sixth region and the fourth end portion, which is different from the semiconductor device of the fourth embodiment. Below, the description of the contents repeated with the fourth embodiment will be partially omitted.

[0149] Fig.10 It is a schematic plan view of a semiconductor device according to a fifth embodiment. Fig.10 The fourth embodiment Figure 8 The corresponding figure.

[0150] The semiconductor device of the fifth embodiment is a power semiconductor module 500. The power semiconductor module 500 of the fifth embodiment is a so-called "2in1" type module that can configure a half-bridge circuit with one module. The power semiconductor module 500 connects three half-bridge units in parallel.

[0151] The third metal layer 33 is provided on the insulating substrate 30. The third metal layer 33 includes a fifth region 33a, a sixth region 33b, and a seventh region 33c. The third metal layer 33 is electrically connected to the source electrode 11a of the high-side MOSFET 11 in the fifth region 33a. The third metal layer 33 is electrically connected to the source electrode 12a of the high-side MOSFET 12 in the sixth region 33b. The third metal layer 33 is electrically connected to the AC output terminal AC in the seventh region 33c.

[0152] The third metal layer 33 includes a third end E3 and a fourth end E4. The third end E3 is an end on the side opposite to the first metal layer 31. The fourth end E4 is an end on the side opposite to the third end E3, sandwiching the third metal layer 33. The fourth end E4 is an end on the side opposite to the second metal layer 32.

[0153] The third metal layer 33 includes a plurality of holes 70. The plurality of holes 70 are located between the fifth region 33a and the fourth end portion E4.

[0154] In the region including the plurality of holes 70 between the fifth region 33 a and the fourth end E4 , the density of the metal layer is lower than that between the sixth region 33 b and the fourth end E4 .

[0155] The plurality of holes 70 have a function of increasing the parasitic inductance of the wiring of the high-side MOSFET 11 .

[0156] In the power semiconductor module 500 of the fifth embodiment, since a plurality of holes 70 are provided in the third metal layer 33, fluctuations in parasitic inductance of wiring of MOSFETs arranged in parallel are reduced. Therefore, damage and reduction in reliability during switching of the power semiconductor module 500 are suppressed. Therefore, switching losses of the power semiconductor module 500 are reduced.

[0157] (Variation Example)

[0158] Fig.11 It is a schematic plan view of a semiconductor device according to a modification of the fifth embodiment. Fig.11 is with Fig.10 The corresponding figure.

[0159] The semiconductor device according to the modification of the fifth embodiment is a power semiconductor module 550. The power semiconductor module 550 is different from the power semiconductor module 500 in that the second metal layer 32 also includes a plurality of holes 70.

[0160] For the region including the plurality of holes 70 between the third region 32 b and the second end E2 of the second metal layer 32 , the density of the metal layer is lower than that between the fourth region 32 c and the second end E2 .

[0161] According to the fifth embodiment and its modified example described above, similarly to the first to fourth embodiments, by reducing the fluctuation of the parasitic inductance of the power semiconductor chips arranged in parallel, it is possible to reduce the switching loss of the power semiconductor module.

[0162] In the first to fifth embodiments, the case where MOSFET is used as a semiconductor chip is described as an example, but the power semiconductor chip is not limited to MOSFET. For example, other transistors such as IGBT can also be used as a power semiconductor chip. In addition, as a power semiconductor chip, for example, MOSFET without built-in SBD can also be used.

[0163] In the first to fifth embodiments, the case where the number of power semiconductor chips arranged in parallel is three is described as an example, but the number of power semiconductor chips may be two, or may be four or more.

[0164] In the first to fifth embodiments, the power semiconductor module is described as a “2in1” type module. However, the power semiconductor module may have another circuit configuration such as a “4in1” type or a “6in1” type.

[0165] In the first to fifth embodiments, the case where the power semiconductor chip is formed using silicon carbide (SiC) is described as an example, but the power semiconductor chip may be formed using other semiconductors such as silicon or gallium nitride.

[0166] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the main purpose of the invention. For example, the constituent elements of one embodiment can also be replaced or changed with the constituent elements of other embodiments. These embodiments and their variations are included in the scope or main purpose of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device comprising: An insulating substrate having one end and another end opposite to the one end; A first main terminal, disposed on the one end side; A second main terminal is arranged at the one end side; An output terminal, arranged at the other end side; A first metal layer, disposed on the insulating substrate, having a first region, and electrically connected to the first main terminal in the first region; A second metal layer is disposed on the insulating substrate, has a second region, a third region and a fourth region, and is electrically connected to the second main terminal in the second region; A third metal layer, disposed on the insulating substrate, located between the first metal layer and the second metal layer, having a fifth region, a sixth region and a seventh region, wherein the seventh region is electrically connected to the output terminal; A first semiconductor chip, comprising a first upper electrode, a first lower electrode and a first gate electrode, disposed on the first metal layer, wherein the first upper electrode is electrically connected to the fifth region, and the first lower electrode is electrically connected to the first metal layer; a second semiconductor chip, comprising a second upper electrode, a second lower electrode and a second gate electrode, disposed on the first metal layer, the second upper electrode being electrically connected to the sixth region, the second lower electrode being electrically connected to the first metal layer, and the second semiconductor chip being farther from the first region than the first semiconductor chip; a third semiconductor chip, comprising a third upper electrode, a third lower electrode and a third gate electrode, disposed on the third metal layer, wherein the third upper electrode is electrically connected to the third region, and the third lower electrode is electrically connected to the third metal layer; as well as a fourth semiconductor chip, comprising a fourth upper electrode, a fourth lower electrode and a fourth gate electrode, disposed on the third metal layer, the fourth upper electrode being electrically connected to the fourth region, the fourth lower electrode being electrically connected to the third metal layer, the fourth semiconductor chip being farther from the fifth region than the third semiconductor chip, The second metal layer has a first end on the side opposite to the third metal layer and a second end on the side opposite to the first end, and includes a first slit between the third region and the second end, and includes a plurality of holes between the third region and the second end. The third metal layer has a third end opposite to the first metal layer and a fourth end opposite to the third end, includes a second slit between the fifth region and the fourth end, and includes a plurality of holes between the fifth region and the fourth end.

2. The semiconductor device according to claim 1, wherein A first distance between the first end and the first slit is smaller than a second distance between the first slit and the second end.

3. The semiconductor device according to claim 1, wherein A third distance between the third end and the second slit is smaller than a fourth distance between the second slit and the fourth end.

4. The semiconductor device according to claim 1, wherein A length of the first slit in a first direction from the third semiconductor chip toward the fourth semiconductor chip is greater than a length of the third semiconductor chip in the first direction.

5. The semiconductor device according to claim 1, wherein A length of the second slit in a first direction from the third semiconductor chip toward the fourth semiconductor chip is greater than a length of the first semiconductor chip in the first direction.

6. The semiconductor device according to claim 1, wherein The first semiconductor chip includes a first gate resistor, the second semiconductor chip includes a second gate resistor, the third semiconductor chip includes a third gate resistor, and the fourth semiconductor chip includes a fourth gate resistor.

7. The semiconductor device according to claim 6, wherein: The semiconductor device further comprises: A first gate terminal is electrically connected to the first gate electrode and the second gate electrode, and a resistance between the first gate electrode and the second gate electrode is less than 5Ω; The second gate terminal is electrically connected to the third gate electrode and the fourth gate electrode, and a resistance between the second gate terminal and the third gate electrode and a resistance between the second gate terminal and the fourth gate electrode are 5Ω or less.

8. The semiconductor device according to claim 1, wherein The first semiconductor chip includes a first Schottky barrier diode, the second semiconductor chip includes a second Schottky barrier diode, the third semiconductor chip includes a third Schottky barrier diode, and the fourth semiconductor chip includes a fourth Schottky barrier diode.

9. The semiconductor device according to claim 1, wherein: The first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip include silicon carbide.

10. A semiconductor device comprising: An insulating substrate having one end and another end opposite to the one end; A first main terminal, disposed on the one end side; A second main terminal is arranged at the one end side; An output terminal, arranged at the other end side; A first metal layer, disposed on the insulating substrate, having a first region, and electrically connected to the first main terminal in the first region; A second metal layer is disposed on the insulating substrate, has a second region, a third region and a fourth region, and is electrically connected to the second main terminal in the second region; A third metal layer, disposed on the insulating substrate, located between the first metal layer and the second metal layer, having a fifth region, a sixth region and a seventh region, wherein the seventh region is electrically connected to the output terminal; A first semiconductor chip, comprising a first upper electrode, a first lower electrode and a first gate electrode, disposed on the first metal layer, wherein the first upper electrode is electrically connected to the fifth region, and the first lower electrode is electrically connected to the first metal layer; a second semiconductor chip, comprising a second upper electrode, a second lower electrode and a second gate electrode, disposed on the first metal layer, the second upper electrode being electrically connected to the sixth region, the second lower electrode being electrically connected to the first metal layer, and the second semiconductor chip being farther from the first region than the first semiconductor chip; a third semiconductor chip, comprising a third upper electrode, a third lower electrode and a third gate electrode, disposed on the third metal layer, wherein the third upper electrode is electrically connected to the third region, and the third lower electrode is electrically connected to the third metal layer; as well as a fourth semiconductor chip, comprising a fourth upper electrode, a fourth lower electrode and a fourth gate electrode, disposed on the third metal layer, the fourth upper electrode being electrically connected to the fourth region, the fourth lower electrode being electrically connected to the third metal layer, the fourth semiconductor chip being farther from the fifth region than the third semiconductor chip, The second metal layer has a first end on the side opposite to the third metal layer and a second end on the side opposite to the first end, includes a region between the third region and the second end where the density of the metal layer is lower than that between the fourth region and the second end, and includes a plurality of holes between the third region and the second end, The third metal layer has a third end on the side opposite to the first metal layer and a fourth end on the side opposite to the third end, and includes an area between the fifth area and the fourth end where the density of the metal layer is lower than that between the sixth area and the fourth end, and contains multiple holes between the fifth area and the fourth end.

11. The semiconductor device according to claim 10, wherein The second metal layer includes a plurality of holes.

12. The semiconductor device according to claim 10, wherein: The third metal layer includes a plurality of holes.

13. The semiconductor device according to claim 10, wherein: The first semiconductor chip includes a first gate resistor, the second semiconductor chip includes a second gate resistor, the third semiconductor chip includes a third gate resistor, and the fourth semiconductor chip includes a fourth gate resistor.

14. The semiconductor device according to claim 13, wherein: The semiconductor device further comprises: A first gate terminal is electrically connected to the first gate electrode and the second gate electrode, and a resistance between the first gate electrode and the second gate electrode is less than 5Ω; The second gate terminal is electrically connected to the third gate electrode and the fourth gate electrode, and a resistance between the second gate terminal and the third gate electrode and a resistance between the second gate terminal and the fourth gate electrode are 5Ω or less.

15. The semiconductor device according to claim 10, wherein The first semiconductor chip includes a first Schottky barrier diode, the second semiconductor chip includes a second Schottky barrier diode, the third semiconductor chip includes a third Schottky barrier diode, and the fourth semiconductor chip includes a fourth Schottky barrier diode.

16. The semiconductor device according to claim 10, wherein: The first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip include silicon carbide.

Images