Drive circuit equipped with power gate circuit

Abstract

Disclosed herein is an apparatus including a first buffer circuit, a plurality of first drive circuits configured to drive the first buffer circuit, and a plurality of first switch circuits configured to supply operating voltages to the first drive circuits, respectively. The first drive circuits are commonly arranged in a matrix form in a first region, and the first switch circuits are commonly arranged in a second region different from the first region.

Description

Background Technology

[0001] For example, a semiconductor device using dynamic random access memory (DRAM) uses an output buffer to drive read data from a memory cell array and outputs the data to the outside via a data terminal. Multiple drive circuits driving the output buffer are arranged in front of it. To reduce off-state leakage current, there are cases where a switching circuit is placed in each of these drive circuits between the source of the transistor constituting the drive circuit and the power supply line. However, when multiple drive circuits are arranged in an array, the question arises regarding where to place the switching circuit. Summary of the Invention

[0002] This document discloses example devices for semiconductor apparatuses. In one aspect of this disclosure, an apparatus includes a first buffer circuit, a plurality of first drive circuits configured to drive the first buffer circuit, and a plurality of first switch circuits configured to supply operating voltages to the first drive circuits, respectively. The first drive circuits are arranged in a matrix configuration in a first region. The first switch circuits are arranged in a second region different from the first region.

[0003] In another aspect of this disclosure, a device includes an external terminal electrode, a first buffer circuit connected between a first power line and the external terminal electrode, and a second buffer circuit connected between a second power line and the external terminal electrode. The device further includes a first drive circuit configured to drive the first buffer circuit, a second drive circuit configured to drive the second buffer circuit, a first switching circuit configured to supply an operating voltage to the first drive circuit, and a second switching circuit configured to supply an operating voltage to the second drive circuit. The first drive circuit and the second drive circuit are arranged between the first switching circuit and the second switching circuit.

[0004] In another aspect of this disclosure, an apparatus includes a buffer circuit and a plurality of driving circuits configured to drive the buffer circuit, the driving circuits being arranged along a first direction, each of the driving circuits including a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type. The apparatus further includes a first switching circuit connected to the source of the first MOS transistor via a first source line, and a second switching circuit connected to the source of the second MOS transistor via a second source line. The first and second source lines extend along a second direction such that the first source line intersects the second MOS transistor. Attached Figure Description

[0005] Figure 1 This is a schematic plan view showing the layout of a semiconductor device according to the present disclosure.

[0006] Figure 2This is a layout diagram showing the configuration of the I / O control circuit.

[0007] Figure 3 This is a waveform diagram of the clock signal.

[0008] Figure 4 This is a block diagram showing the configuration of the I / O control circuit.

[0009] Figure 5 This is a circuit diagram showing the configuration of the relevant parts of the clock synchronization circuit.

[0010] Figure 6 It is a timing diagram used to explain the operation of the clock synchronization circuit.

[0011] Figure 7 This is the circuit diagram of the output buffer.

[0012] Figure 8 It is a circuit block that corresponds to the driver circuit and output buffer of a data terminal.

[0013] Figure 9 This is a block diagram showing the configuration of the pull-up circuit.

[0014] Figure 10 This is a block diagram showing the configuration of the pull-down circuit.

[0015] Figure 11 This is a block diagram showing the configuration of the pull-up pre-emphasis circuit.

[0016] Figure 12 This is a block diagram showing the configuration of the pull-down pre-emphasis circuit.

[0017] Figure 13 This is the circuit diagram of a speed selector.

[0018] Figure 14 It is a circuit diagram of a pull-up driver or a pull-down driver.

[0019] Figure 15 This is the layout diagram of the drive circuit.

[0020] Figure 16 This is a diagram showing the power lines formed on the drive circuit.

[0021] Figure 17 It is a diagram showing the layout of the drive circuit in more detail. Detailed Implementation

[0022] Various embodiments of the invention will be described in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments of the invention that can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be used and structural, logical, and electrical changes may be made without departing from the scope of the invention. Hereinafter, a layout or layout diagram may be defined as showing a physical arrangement of circuits and / or circuit blocks that differs from a logic diagram. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0023] According to this disclosure, the semiconductor device 10 is a low-power double data rate 5 (LPDDR5) DRAM, and as Figure 1 As shown, the device includes a memory cell array 11, multiple data terminals 12, and multiple command address terminals 13. Terminals 12 and 13 are arranged along one side extending in the x-direction of the semiconductor device 10. Other terminals, such as power terminals, are also present. The data terminals 12 are arranged in two separate locations, with the command address terminals 13 arranged between them. The memory cell array 11 and the data terminals 12 are connected via I / O control circuitry 14, and the memory cell array 11 and the command address terminals 13 are connected via access control circuitry 15. When a read command and its corresponding address signal are input from the command address terminals 13, read data read from the memory cell array 11 is output to the data terminals 12 via the I / O control circuitry 14. When a write command and its corresponding address signal are input from the command address terminals 13, write data input to the data terminals 12 is written to the memory cell array 11 via the I / O control circuitry 14.

[0024] like Figure 2As shown, data terminals 12 include terminals 120 to 127 for inputting and outputting data DQ0 to DQ7 respectively, terminal 12M for inputting and outputting data mask signals, terminal 12S for inputting and outputting complementary strobe signals DQST and DQSB respectively, and terminal 12C for inputting complementary clock signals WCKt and WCKc respectively. I / O control circuitry 20 is assigned to terminals 120 to 127 and 12M respectively. I / O control circuitry 20 is connected to memory cell array 11 via read / write bus 16. I / O control circuitry 20 includes read system circuitry and write system circuitry. The read system circuitry includes read data storage circuitry 21, read clock synchronization circuitry (parallel-to-serial conversion circuitry) 22, driver circuitry 23, and output buffer 24. The write system circuitry includes input buffer 25, timing adjustment circuitry 26, write clock synchronization circuitry (serial-to-parallel conversion circuitry) 27, and write data output circuitry 28. The I / O control circuit 20 is arranged along the y-direction according to the x-coordinate of the corresponding data terminal of the data terminal 12, so that data reading and data writing can flow along the y-direction.

[0025] Clock signals WCKt and WCKc are input to clock signal generation circuit 30. Clock signal generation circuit 30 generates read clock signals R0 to R3 and write clock signals W0 to W3 based on clock signals WCKt and WCKc. For example... Figure 3 As shown, the read clock signals R0 to R3 are four-phase clock signals with twice the time interval, provided that the phases of clock signals WCKt and WCKc differ by 90 degrees. Read clock signals R0 to R3 are supplied to the read clock synchronization circuit 22 via read clock lines RL0 to RL3. The read clock synchronization circuit 22 performs parallel-to-serial conversion of the read data synchronously with the read clock signals R0 to R3. Write clock signals W0 to W3 are 90 degrees out of phase with each other and are supplied to the input buffer 25 via write clock lines WL0 to WL3. The input buffer 25 performs serial-to-parallel conversion of the write data synchronously with the write clock signals W0 to W3. Both read clock lines RL0 to RL3 and write clock lines WL0 to WL3 extend along the x-direction.

[0026] Figure 4This is a block diagram showing the configuration of the I / O control circuit 20. The read data storage circuit 21, read clock synchronization circuit 22, drive circuit 23, and output buffer 24 constitute the read system circuit and are connected in this order between the read / write bus 16 and the data terminal 12. The output electrostatic discharge (ESD) protection circuit 29A is located near the output buffer 24. The input buffer 25, timing adjustment circuit 26, write clock synchronization circuit 27, and write data output circuit 28 constitute the write system circuit and are connected in this order between the data terminal 12 and the read / write bus 16. The input ESD protection circuit 29B is located near the input buffer 25.

[0027] The read data storage circuit 21 stores the parallel read data supplied from the read / write bus 16 and supplies the read data to the read clock synchronization circuit 22. The read clock synchronization circuit 22 converts the parallel read data into serial data based on read clock signals R0 to R3, generating complementary pull-up data DATAu and pull-down data DATAd. The drive circuit 23 drives the output buffer 24 based on the pull-up data DATAu and pull-down data DATAd, thereby outputting serial write data DQ from the data terminal 12. The impedance, drive strength, and rotation speed of the output buffer 24 are adjusted by the drive circuit 23.

[0028] Figure 5 This is a circuit diagram showing the configuration of relevant parts of the clock synchronization circuit 22. For example... Figure 5 As shown, the read clock synchronization circuit 22 has four tri-state buffer circuits 110 to 113. Activating one of the tri-state buffer circuits 110 to 113 leaves the remaining three with outputs based on the read clock signals R0 to R3 being in a high-impedance state. The output nodes of the tri-state buffer circuits 110 to 113 are collectively connected to signal node 101. Figure 6 As shown, the read clock signals R0 to R3 are four-phase clock signals with a 90-degree phase difference. The tri-state buffer circuits 110 to 113 output the read data D0 to D3 to signal node 101 in response to the rising edges of the read clock signals R0 to R3, respectively. Therefore, the frequencies of the serial read data D0 to D3 presented at signal node 101 are four times higher than the frequencies of the parallel read data D0 to D3 input to the tri-state buffer circuits 110 to 113.

[0029] Inverter circuits 102 and 103 are cascaded after signal node 101. The output of inverter circuit 103 is used as pull-up data DATAu, and the output of inverter circuit 102 is used as pull-down data DATAd. The pull-up data DATAu and pull-down data DATAd are supplied to driver circuit 23. Driver circuit 23 is the circuit that drives output buffer 24. Figure 7As shown, output buffer 24 includes a switching transistor 130, an output transistor 131, and an output transistor 132 connected in series. Switching transistor 130 is an N-channel MOS transistor with a thickened gate dielectric film, and a reset signal / SCr is supplied to its gate electrode. The reset signal / SCr goes high during the read operation. Output transistors 131 and 132 are N-channel MOS transistors, and their gate electrodes are driven by drive circuit 23.

[0030] Figure 8 This is a circuit block corresponding to the drive circuit 23 and the output buffer 24 of a data terminal 12. For example... Figure 8 As shown, the pull-up data DATAu is supplied to the pull-up circuit 71 and the pre-emphasis circuit 73. The pull-up circuit 71 is activated during the pull-up operation, that is, when data DQ is read from the high-level output of data terminal 12. The pull-up circuit 71 has three speed selectors 41H to 43H belonging to the high-speed path and three speed selectors 41L to 43L belonging to the low-speed path, as shown... Figure 9As shown in the diagram. To select whether to use a high-speed path or a low-speed path, a speed mode signal Hs is input to the drive circuit 40. When a high-speed path is selected, one or two or more speed selectors 41H to 43H are selected based on a driver strength selection signal. When a low-speed path is selected, one or two or more speed selectors 41L to 43L are selected based on a driver strength selection signal. The driver sizes of speed selectors 41H to 43H may differ from each other. Similarly, the driver sizes of speed selectors 41L to 43L may differ from each other. Speed ​​selectors 41H, 42H, 43H, 41L, 42L, and 43L have pull-up drive circuits 411H to 414H, 421H to 424H, 431H to 434H, 411L to 414L, 421L to 424L, and 431L to 434L, respectively. These pull-up drive circuits 411H, 414H, 421H to 424H, 431H to 434H, 411L to 414L, 421L to 424L, and 431L to 434L are circuits that selectively drive adjustment MOS transistors, each contained in a plurality of output stage circuits having equal impedance, so as to correct the impedance of each of the output stage circuits to a desired value based on the impedance selection signal ZQ. The number of output stage circuits controlled by the speed selectors 41H / L to 43H / L differs from each other. For example, circuit 41H / L controls three output stage circuits, circuit 42H / L controls two output stage circuits, and circuit 43H / L controls one output stage circuit. In this configuration, the pull-up drive circuits 411H to 414H or 411L to 414L in circuit 41H / L each drive the adjustment MOS transistors corresponding to the three output stage circuits; the pull-up drive circuits 421H to 424H or 421L to 424L in circuit 42H / L each drive the adjustment MOS transistors corresponding to the two output stage circuits; and the pull-up drive circuits 431H to 434H or 431L to 434L in circuit 43H / L each drive the adjustment MOS transistors corresponding to one output stage circuit. Therefore, the output impedance during the pull-up operation can be selected with accurate impedance at the desired driver strength. The speed mode signal Hs and the slewing rate selection signal SR are also jointly supplied to the pull-up drive circuits.

[0031] The pull-down data DATAd is supplied to the pull-down circuit 72 and the pre-emphasis circuit 74. The pull-down circuit 72 is activated during the pull-down operation, that is, when data DQ is read from the low level output of data terminal 12. The drive circuit 59 included in the pull-down circuit 72 is activated when a non-target on-die stop (ODT) operation is performed. Figure 10 As shown, the pull-down circuit 72 has three speed selectors 51H to 53H belonging to the high-speed path and three speed selectors 51L to 53L belonging to the low-speed path. Figure 10 A drive circuit 59 performing non-targeted ODT operations is also shown. The speed mode signal Hs input to the drive circuit 50 selects whether a high-speed path or a low-speed path will be used. When a high-speed path is selected, one or two or more speed selectors 51H to 53H are selected based on a driver strength selection signal. When a low-speed path is selected, one or two or more speed selectors 51L to 53L are selected based on a driver strength selection signal. The driver sizes of speed selectors 51H to 53H may be different from each other. Similarly, the driver sizes of speed selectors 51L to 53L may be different from each other. Speed ​​selectors 51H, 52H, 53H, 51L, 52L, and 53L have pull-down drive circuits 511H to 514H, 521H to 524H, 531H to 534H, 511L to 514L, 521L to 524L, and 531L to 534L, respectively. These pull-down drive circuits 511H to 514H, 521H to 524H, 531H to 534H, 511L to 514L, 521L to 524L, and 531L to 534L are circuits that selectively drive adjustment MOS transistors contained in multiple output stage circuits with equal impedance, so as to correct the impedance of each of the output stage circuits to a desired value based on the impedance selection signal ZQ. The speed selectors 51H / L to 53H / L control different numbers of output stage circuits from one another. For example, circuit 51H / L controls three output stage circuits, circuit 52H / L controls two output stage circuits, and circuit 53H / L controls one output stage circuit. In this configuration, the pull-down drive circuits 511H to 514H or 511L to 514L in circuit 51H / L each drive the adjustment MOS transistors corresponding to the three output stage circuits; the pull-down drive circuits 521H to 524H or 521L to 524L in circuit 52H / L each drive the adjustment MOS transistors corresponding to the two output stage circuits; and the pull-down drive circuits 531H to 534H or 531L to 534L in circuit 53H / L each drive the adjustment MOS transistors corresponding to one output stage circuit. Therefore, the output impedance during the pull-down operation can be selected with accurate impedance at the desired driver strength. The speed mode signal Hs and the slewing rate selection signal SR are also jointly supplied to the pull-down drive circuits.

[0032] The pull-down circuit 72 includes a drive circuit 59 for performing non-target ODT operations. The drive circuit 59 is composed of speed selectors 51H / L to 53H / L and portions of pull-down drive circuits 511H / L to 514H / L, 521H / L to 524H / L, and 531H / L to 534H / L, and is activated during non-target ODT operations regardless of the speed mode signal Hs. Which of the speed selectors 51H / L to 53H / L will be activated during the non-target ODT operation is selected by a driver strength selection signal DSnt dedicated to non-target ODT operations. The impedance of the pull-down drive circuits 511H / L to 514H / L, 521H / L to 524H / L, and 531H / L to 534H / L during the non-target ODT operation is specified by an impedance selection signal ZQ.

[0033] The pre-emphasis circuits 73 and 74 provide the function of compensating for skin resistance losses or dielectric losses that occur during high-frequency operation by temporarily reducing the output resistance only during the period in which data changes. Therefore, data can also change at an appropriate rate of rotation during high-frequency operation, and the data terminal 12 can be driven with a set resistor in a steady state.

[0034] When the read data DQ transitions to a high level, the pre-emphasis circuit 73 is activated to make the rising edge of the read data DQ steeper. For example... Figure 11 As shown, the pre-emphasis circuit 73 has a single-trigger pulse generation circuit 45, speed selectors 44H and 46 belonging to the high-speed path, and a speed selector 44L belonging to the low-speed path. Speed ​​selector 44H controls three pull-up drive circuits 441H to 443H, and speed selector 44L controls three pull-up drive circuits 441L to 443L.

[0035] When the read data DQ transitions to a low level, the pre-emphasis circuit 74 is activated to make the falling edge of the read data DQ steeper. For example... Figure 12 As shown, the pre-emphasis circuit 74 includes a single-trigger pulse generation circuit 55, speed selectors 54H and 56 belonging to the high-speed path, and a speed selector 54L belonging to the low-speed path. Speed ​​selector 54H controls three pull-up drive circuits 541H to 543H, and speed selector 54L controls three pull-up drive circuits 541L to 543L.

[0036] Figure 13 This is the circuit diagram of a speed selector. Each speed selector contains a NAND gate 140 and a NOR gate 150. The NAND gate 140 is based on either pull-up data DATAu or pull-down data DATAd and the control signal ctrl. 1 and ctrl 2A data signal DATAp is generated. High-speed transistors with reduced threshold voltages are used as transistors 141 to 145 to constitute the NAND gate circuit 140. The NOR gate circuit 150 is based on pull-up data DATAu or pull-down data DATAd and a control signal ctrl. 3 to ctrl 5 Generates the data signal DATAn. High-speed transistors with reduced threshold voltages are also used as transistors 151 to 156 to form the NOR gate circuit 150. Control signal ctrl. 1 to ctrl 5 It is a speed mode signal, a timing signal, a non-target ODT enable signal, or a signal obtained by logical synthesis of these signals.

[0037] Figure 14 This is a circuit diagram of a pull-up or pull-down driver. The pull-up or pull-down driver is a tri-state buffer with transistors 161 to 166 connected in series, and outputs a drive signal DRV from the connection point between transistors 163 and 164. The data signal DATAp is supplied to the gate electrode of transistor 163, and the data signal DATAn is supplied to the gate electrode of transistor 164. Transistors 161 and 166 are transistors used to activate the corresponding pull-up or pull-down driver, and the control signal ctrl is obtained through the logical synthesis of a speed mode signal and a timing signal. 6 The input is sent to its gate electrode. Transistors 161 and 166 may be high-voltage transistors with a thickened gate dielectric film. When transistors 161 and 166 are turned off, the associated pull-up or pull-down driver is deactivated and its output node becomes a high-impedance state. Transistor 162 is composed of a plurality of transistors 1620 to 1622 connected in parallel, and transistor 165 is composed of a plurality of transistors 1650 to 1652 connected in parallel. The inverted signals (e.g., / SR0 to / SR2) constituting the spin rate code signal SR are supplied to the gate electrodes of transistors 1620 to 1622, respectively. The bits SR0 to SR2 constituting the spin rate code signal SR are supplied to the gate electrodes of transistors 1650 to 1652, respectively. The spin rate code signal SR may contain impedance code information.

[0038] With this configuration, one of the transistors 131 and 132 constituting the output buffer 24 is turned on based on the pull-up data DATAu and pull-down data DATAd, and a high-level or low-level read data DQ is output from the data terminal 12 during the read operation. On the other hand, during the write operation, the write data DQ input to the data terminal 12 is supplied to the input buffer 25. The input buffer 25 converts the serial write data DQ into parallel four-bit write data DQ based on the write clock signals W0 to W3. The timing of the parallel four-bit write data DQ is adjusted by the timing adjustment circuit 26. Thereafter, the parallel four-bit write data DQ is further converted into parallel 16-bit write data DQ by the write clock synchronization circuit 27 and output to the read / write bus 16 via the write data output circuit 28.

[0039] Figure 15 This is the layout diagram of the driver circuit 23. (For example...) Figure 15 As shown, speed selectors 41H to 44H and 41L to 44L, along with pull-up drive circuits 411H to 414H, 421H to 424H, 431H to 434H, 441H to 444H, 411L to 414L, 421L to 424L, 431L to 434L, and 441L to 444L, are arranged together in an array in region 400. Similarly, speed selectors 51H to 54H and 51L to 54L, along with pull-down drive circuits 511H to 514H, 521H to 524H, 531H to 534H, 541H to 544H, 511L to 514L, 521L to 524L, 531L to 534L, and 544L to 544L, are arranged together in an array in region 500. Among the transistors constituting the pull-up drive circuits... Figure 14 Transistors 161 and 166 shown are both arranged in region 600 and not in region 400. Similarly, among the transistors constituting the pull-down drive circuit, Figure 14 Transistors 161 and 166 shown are arranged together in region 700 but not in region 500. Regions 600, 400, 500, and 700 are arranged in this order along the x-direction. Region 600 includes regions 601 and 602 arranged along the x-direction. Some transistors of transistors 161 and 166 constituting the pull-up drive circuit are arranged together in region 601, and the remaining transistors of transistors 161 and 166 constituting the pull-up drive circuit are arranged together in region 602. Similarly, region 700 includes regions 701 and 702 arranged along the x-direction. Some transistors of transistors 161 and 166 constituting the pull-down drive circuit are arranged together in region 701, and the remaining transistors of transistors 161 and 166 constituting the pull-down drive circuit are arranged together in region 702.

[0040] Figure 15The symbols shown are 411H / L to 414H / L, 421H / L to 424H / L, 431H / L to 434H / L, and 441H / L to 444H / L. Figure 9 and 11 The drive circuit shown is located in region 600. The drive circuits contained in the high-speed path and the drive circuits contained in the low-speed path are arranged adjacent to each other along the x-direction. For example, drive circuits 411L and 411H are arranged adjacent to each other along the x-direction. The outputs of these drive circuits are used to control a common output transistor (not shown). Drive circuit 421H contained in the high-speed path is located on the opposite side of drive circuit 411H relative to drive circuit 411L. A drive circuit with a larger size is located closer to region 600. Similarly, Figure 15 The symbols shown are 511H / L to 514H / L, 521H / L to 524H / L, 531H / L to 534H / L, and 541H / L to 544H / L. Figure 10 and 12 The drive circuits shown are located in the zone. The drive circuits contained in the high-speed path and the drive circuits contained in the low-speed path are arranged adjacent to each other along the x-direction. For example, drive circuits 511L and 511H are arranged adjacent to each other along the x-direction. Drive circuit 521H contained in the high-speed path is located on the opposite side of drive circuit 511H relative to drive circuit 511L. The drive circuit with a larger size is located closer to zone 700. The layout of the circuits arranged in zones 400 and 600 and the layout of the circuits arranged in zones 500 and 700 are symmetrical with respect to the straight line Ly extending along the y-direction. Speed ​​selectors 41H / L to 44H / L and speed selectors 51H / L to 54H / L are also arranged symmetrically with respect to the straight line Ly.

[0041] like Figure 16As shown, drive circuits 411H / L to 414H / L, 421H / L to 424H / L, 431H / L to 434H / L, and 441H / L to 444H / L arranged in region 400 are connected to transistors 161 and 166 arranged in region 600 via power lines 800 extending in the x-direction. Similarly, drive circuits 511H / L to 514H / L, 521H / L to 524H / L, 531H / L to 534H / L, and 541H / L to 544H / L arranged in region 500 are connected to transistors 161 and 166 arranged in region 700 via power lines 800 extending in the x-direction. In this manner, according to the invention, transistors 161 and 166, which act as power switches, are jointly arranged in regions 600 and 700, and other transistors are jointly arranged in regions 400 and 500, which are sandwiched between regions 600 and 700. If the transistors acting as switches are distributed in the corresponding drive circuits, then the size of the drive circuit increases along at least one of the x and y directions, and the path of the data signal line is correspondingly lengthened. For the layout of the transistors arranged together as described above, the path of the data signal line is shortened, which facilitates high-speed operation of the circuit.

[0042] Figure 17 To show in more detail Figure 15 The diagram shows the layout of area 520. (See diagram for example.) Figure 17 As shown, block 521, containing drive circuits 521H and 521L; block 522, containing drive circuits 522H and 522L; block 523, containing drive circuits 523H and 523L; and block 524, containing drive circuits 524H and 524L, are arranged in region 520. These blocks 521 to 524 are arranged along the y-direction. Region 520 has Figure 14 The P-channel MOS transistors 162 and 163 shown are disposed in region 520P, and Figure 14N-channel MOS transistors 164 and 165 shown are arranged in region 520N. Region 520P is shared by drive circuits 521H to 524H and drive circuits 521L to 524L. Data signal INH is input to drive circuits 521H to 524H via signal lines 801P and 801N extending along the y-direction along the boundary between region 520P and region 520N, and data signal INL is input to drive circuits 521L to 524L via signal lines 802P and 802N extending along the y-direction along the boundary between region 520P and region 520N. Therefore, signal lines 801P and 801N cross power line 803, which supplies power to P-channel MOS transistors 162 and 163 located in region 520P, and power line 804, which supplies power to N-channel MOS transistors 164 and 165 located in drive circuits 521H to 524H located in region 520N. Meanwhile, signal lines 802P and 802N cross power line 804, but not power line 803.

[0043] Although the invention has been disclosed in the context of certain preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the invention and its obvious modifications and equivalents. Furthermore, other modifications within the scope of the invention will be apparent to those skilled in the art based on this disclosure. Various combinations or sub-combinations of specific features and aspects of the embodiments are also contemplated and will still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for each other to form variations of the invention. Therefore, it is intended that the scope of at least some of the invention disclosed herein should not be limited to the specific disclosed embodiments described above.

Claims

1. A device for memory operations, comprising: First buffer circuit; Multiple first driving circuits are configured to drive the first buffer circuit; and A plurality of first switching circuits are configured to supply operating voltages to the first driving circuits, wherein the first driving circuits are arranged in a matrix in a first region. The first switching circuits are all arranged in a second area that is different from the first area; Second buffer circuit; A plurality of second driving circuits configured to drive the second buffer circuit, wherein the first driving circuit and the second driving circuit are arranged along a first direction; and Multiple second switching circuits are configured to supply operating voltages to the second drive circuits, wherein the second drive circuits are arranged in a matrix in the third region. The second switching circuit is arranged in a fourth zone, which is different from the third zone; and The first region and the third region are adjacent in the first direction.

2. The device according to claim 1, wherein the second region is adjacent to the first region.

3. The device of claim 2, wherein each of the first switching circuits includes a first transistor configured to supply a first potential to an associated first driving circuit in the first driving circuit, and a second transistor configured to supply a second potential to the associated first driving circuit in the first driving circuit.

4. The device according to claim 3, The second region includes the first sub-region and the second sub-region. The first transistors are all arranged in the first sub-region, and The second transistor is arranged together in the second sub-region.

5. The device according to claim 1, wherein the fourth region is adjacent to the third region.

6. The device according to claim 1, wherein the first zone and the third zone are arranged between the second zone and the fourth zone.

7. The device of claim 6, wherein each of the second switching circuits includes a third transistor configured to supply a first potential to an associated second driving circuit in the second driving circuit, and a fourth transistor configured to supply a second potential to an associated second driving circuit in the second driving circuit.

8. The device according to claim 7, The fourth region comprises the third sub-region and the fourth sub-region. The third transistors are arranged together in the third sub-region, and The fourth transistor is arranged together in the fourth sub-region.

9. The device according to claim 8, further comprising an external terminal electrode. The first buffer circuit and the second buffer circuit are both connected to the external terminal electrode.

10. The device of claim 9, wherein the first buffer circuit and the second buffer circuit are configured to be uniquely activated.

11. A device for memory operations, comprising: External terminal electrodes; A first buffer circuit is connected between the first power line and the external terminal electrode; The second buffer circuit is connected between the second power line and the external terminal electrode. A first driving circuit is configured to drive the first buffer circuit. A second driving circuit is configured to drive the second buffer circuit; A first switching circuit is configured to supply an operating voltage to the first drive circuit; and A second switching circuit is configured to supply an operating voltage to the second drive circuit. The first driving circuit and the second driving circuit are arranged between the first switching circuit and the second switching circuit.

12. The device according to claim 11, The first driving circuit includes a first transistor and a second transistor connected in series between the third power line and the fourth power line. The second driving circuit includes a third transistor and a fourth transistor connected in series between the third power line and the fourth power line. The first buffer circuit has an input node connected to a first connection node between the first transistor and the second transistor, and The second buffer circuit has an input node connected to a second connection node between the third transistor and the fourth transistor.

13. The device according to claim 12, The first switching circuit includes a fifth transistor connected between the third power line and the first connection node, and The second switching circuit includes a sixth transistor connected between the third power line and the second connection node.

14. The device according to claim 13, The first switching circuit further includes a seventh transistor connected between the fourth power line and the first connection node, and The second switching circuit further includes an eighth transistor connected between the fourth power line and the second connection node.

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