Display device

Abstract

The presently disclosed embodiments provide a display device that can reduce the number of intersections of scan lines and data lines. According to the disclosed embodiments, the display device includes a substrate, scan lines extending in a first direction, data lines extending in a second direction intersecting the first direction, a first switching element, a first pixel electrode connected to a first source electrode of the first switching element, a second switching element, and a second pixel electrode connected to a second source electrode of the second switching element. The first pixel electrode and the second pixel electrode are disposed along the second direction, and a first source electrode and a first drain electrode of the first switching element extend along the second direction in an area in which a first active layer of the first switching element is stacked.

Description

Technical Field

[0001] The disclosure relates to a display device. Background Technology

[0002] Liquid crystal displays (LCDs) are one of the most widely used types of display devices. An LCD consists of a pair of substrates with pixel electrodes and a common electrode, and a liquid crystal layer disposed between the two substrates. In an LCD, a voltage is applied to the pixel electrodes and the common electrode to generate an electric field in the liquid crystal layer, thereby driving the liquid crystal molecules in the layer and controlling the polarization of incident light. Thus, an image is displayed on the LCD.

[0003] To apply voltage to the pixel electrodes, an LCD may include scan lines extending in one direction, data lines extending in another direction intersecting the first direction, and sub-pixels connected to the scan lines and data lines respectively. Each sub-pixel is turned on by a scan signal through the scan line to connect the pixel electrode to the data line. In an LCD, the scan lines and data lines inevitably intersect each other, but due to particles at the intersection points, short circuits are very likely to occur between the scan lines and data lines. Summary of the Invention

[0004] The currently disclosed embodiments provide a display device that can reduce the number of intersections between scan lines and data lines.

[0005] According to a disclosed embodiment, the display device includes: a substrate; scan lines disposed on the substrate and extending along a first direction; data lines disposed on the substrate and extending along a second direction intersecting the first direction; a first switching element including a first active layer, a first gate electrode connected to the first scan line in the scan lines, a first drain electrode connected to the first data line in the data lines, and a first source electrode facing the first drain electrode; a first pixel electrode connected to the first source electrode of the first switching element; a second switching element including a second active layer, a second gate electrode connected to the first scan line, a second drain electrode connected to the second data line in the data lines, and a second source electrode facing the second drain electrode; and a second pixel electrode connected to the second source electrode of the second switching element. The first pixel electrode and the second pixel electrode are disposed along the second direction, and the first source electrode and the first drain electrode extend along the second direction in the region overlapping with the first active layer of the first switching element.

[0006] According to a disclosed embodiment, the display device includes: a substrate; scan lines disposed on the substrate and extending along a first direction; data lines disposed on the substrate and extending along a second direction intersecting the first direction; a first switching element including a first active layer, a first gate electrode connected to the first scan line in the scan lines, a first drain electrode connected to the first data line in the data lines, and a first source electrode facing the first drain electrode; a first pixel electrode connected to the first source electrode of the first switching element through a first contact hole; a second switching element including a second active layer, a second gate electrode connected to the first scan line, a second drain electrode connected to the second data line in the data lines, and a second source electrode facing the second drain electrode; and a second pixel electrode connected to the second source electrode of the second switching element through a second contact hole. The first switching element is stacked with the first contact hole in the second direction, and the second switching element is stacked with the second contact hole in the second direction.

[0007] According to a disclosed embodiment, the display device includes: a substrate; scan lines disposed on the substrate and extending along a first direction; data lines disposed on the substrate and extending along a second direction intersecting the first direction; a first switching element including a first active layer, a first gate electrode connected to the first scan line in the scan lines, a first drain electrode connected to the first data line in the data lines, and a first source electrode facing the first drain electrode; a first pixel electrode connected to the first source electrode of the first switching element; a first source connection extending from the first source electrode and connected to the first pixel electrode through a first contact hole; and a first storage electrode superimposed on the first source connection in a plan view. One edge of the first storage electrode protrudes further than one edge of the first source connection in the first direction or the second direction.

[0008] According to the disclosed embodiments, short circuits between storage lines and data lines caused by particles can be reduced by decreasing the number of intersection points between the storage lines and data lines. Therefore, the manufacturing yield of the display panel can be increased.

[0009] It should be noted that the effects of this disclosure are not limited to those described above. Other effects of this disclosure will be clear to those skilled in the art based on the following description. Attached Figure Description

[0010] The above and other features of the inventive concept will become clearer by describing in detail, with reference to the accompanying drawings, in which:

[0011] Figure 1 This is a perspective view of a display device according to an embodiment;

[0012] Figure 2 This is a block diagram of a display device according to an embodiment;

[0013] Figure 3 This is a circuit diagram showing the sub-pixels of a display panel according to an embodiment;

[0014] Figure 4 This is a layout diagram of the sub-pixels of a display panel according to an embodiment;

[0015] Figure 5 This is a circuit diagram showing the sub-pixels of a display panel according to an embodiment;

[0016] Figure 6 This is a layout diagram of the sub-pixels of a display panel according to an embodiment;

[0017] Figure 7 It shows in detail Figure 6 An enlarged layout diagram of an example of a first switching element and a first contact hole of a first sub-pixel, and a second switching element and a second contact hole of a second sub-pixel;

[0018] Figure 8 It is along Figure 7 A cross-sectional view of an example display panel, taken by line I-I';

[0019] Figure 9 , Figure 10 and Figure 11 It shows in detail Figure 8 An enlarged layout diagram of the first switching element, the first source connection portion, and the first storage electrode of the first sub-pixel;

[0020] Figure 12 It shows Figure 6 A layout diagram of an example of the subpixels and light-blocking components of the display panel shown;

[0021] Figure 13 It shows Figure 6 A layout diagram of an example of the subpixels and light-blocking components of the display panel shown;

[0022] Figure 14 It shows Figure 6 A layout diagram of an example of the subpixels and light-blocking components of the display panel shown;

[0023] Figure 15 This is a layout diagram of the sub-pixels of a display panel according to an embodiment;

[0024] Figure 16 It shows in detail Figure 15 An enlarged layout diagram of the first switching element and the first contact hole of the first sub-pixel, and the second switching element and the second contact hole of the second sub-pixel;

[0025] Figure 17 This is a layout diagram of the subpixels of a display panel according to an embodiment; and

[0026] Figure 18 It shows in detail Figure 17 An enlarged layout diagram of the first switching element and the first contact hole of the first sub-pixel, and the second switching element and the second contact hole of the second sub-pixel. Detailed Implementation

[0027] The inventive concept will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the inventive concept can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. The same reference numerals throughout denote the same elements.

[0028] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on the other layer or substrate, or there may be intermediate layers. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements.

[0029] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teaching herein, the first “element,” “component,” “region,” “layer,” or “part” discussed below may be designated as a second element, component, region, layer, or part.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, which include “at least one.” “Or” means “and / or.” “At least one of A and B” means “A and / or B.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprising,” “including,” and variations thereof indicate the presence of the stated features, areas, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0031] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another element as shown in the accompanying drawings. It will be understood that these relative terms are intended to cover different orientations of the device other than those depicted in the drawings. For example, if a device in one of the drawings is flipped, an element described as being “below” the other element will subsequently be positioned on the “above” side of said other element. Thus, the exemplary term “below” can encompass both “below” and “above” orientations depending on the specific orientation in the drawings. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other element will subsequently be positioned “above” the other element. Thus, the exemplary terms “below” or “under” can encompass both “above” and “below” orientations.

[0032] As used herein, “about” or “approximately” includes the stated value and indicates an acceptable range of deviation from the specific value as determined by a person skilled in the art considering the measurements discussed and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense.

[0034] Exemplary embodiments are described herein with reference to schematic cross-sectional views as idealized embodiments. Thus, variations in the illustrated shapes, such as those caused by manufacturing techniques and / or tolerances, will be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the areas shown herein, but will include deviations in shape caused, for example, by manufacturing processes. For example, areas shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the acute angles (or “sharp angles”) shown may be rounded (rounded). Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the areas, nor are they intended to limit the scope of the claims.

[0035] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 This is a perspective view of the display device 10 according to an embodiment.

[0037] Reference Figure 1The display device 10 according to the embodiment is a device for displaying moving or still images. The display device 10 can be used as a display screen in portable electronic devices (such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs)) and various products (such as televisions, laptops, monitors, billboards, and the Internet of Things (IoT)).

[0038] The display device 10 according to the embodiments may be an LCD display device, or an organic light-emitting display device such as an organic light-emitting diode (OLED), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including inorganic semiconductors, or a micro light-emitting display device using micro LEDs. The following description will primarily focus on the case where the display device 10 is an LCD display device, but this disclosure is not limited thereto.

[0039] The display device 10 according to an embodiment includes a display panel 110, a first source drive circuit 121, a first flexible film 122, a second source drive circuit 123, a second flexible film 124, a first source circuit board 140, a second source circuit board 141, a first cable 150, a second cable 153, a control circuit board 160, and a timing control circuit 170.

[0040] The display panel 110 can be rectangular in plan view. For example, the display panel 110 can have a rectangular planar shape, having a long side in a first direction (X-axis direction) and a short side in a second direction (Y-axis direction). Each angle where the long side extending in the first direction (X-axis direction) intersects the short side extending in the second direction (Y-axis direction) can be a right angle, or can be rounded with a predetermined curvature. The planar shape of the display panel 110 is not limited to a rectangular shape, but can also be another polygonal shape, a circular shape, or an elliptical shape. Although the display panel 110 is in... Figure 1 The display panel 110 may be flat, but this disclosure is not limited thereto. The display panel 110 may also be bent at a predetermined curvature.

[0041] The display panel 110 may include a first substrate 111 and a second substrate 112. The first substrate 111 and the second substrate 112 may be made of glass or plastic. The display panel 110 may be implemented as a liquid crystal display panel including a liquid crystal layer disposed between the first substrate 111 and the second substrate 112. A lower polarizing film may be disposed on the outer surface of the first substrate 111, and an upper polarizing film may be disposed on the outer surface of the second substrate 112.

[0042] Display panel 110 can be a display panel with a high resolution such as 4K Ultra High Definition (UHD) or 8K UHD. 4K UHD refers to a resolution of 3840×2160, and 8K UHD refers to a resolution of 7680×4320. The resolution of 8K UHD is four times that of 4K UHD.

[0043] The length of the second substrate 112 in the second direction (Y-axis direction) can be smaller than the length of the first substrate 111 in the second direction (Y-axis direction). Therefore, the surfaces of the first substrate 111 on the first and second sides of the display panel 110 can be exposed and not covered by the second substrate 112. The second side of the display panel 110 can be opposite to the first side of the display panel 110 in the second direction (Y-axis direction). In this specification, the following will be mainly described: Figure 1 The case shown is where the first side of the display panel 110 is the lower side of the display panel 110 and the second side of the display panel 110 is the upper side of the display panel 110.

[0044] Scan drive 130 (see Figure 2 The first scan driver 131 (see) Figure 3 The scan driver 130 (see [link]) can be positioned on the third side of the display panel 110. Figure 2 The second scan driver 132 (see) Figure 3 The fourth side of the display panel 110 can be disposed on the fourth side of the display panel 110. The fourth side of the display panel 110 can be opposite to the third side of the display panel 110 in the first direction (X-axis direction). In this specification, the following will be mainly described: Figure 1 The case shown is where the third side of the display panel 110 is the left side of the display panel 110 and the fourth side of the display panel 110 is the right side of the display panel 110.

[0045] First scan driver 131 (see Figure 3 The timing control circuit 170 can generate a first scan signal in response to a first scan control signal, and sequentially output the first scan signal to the scan lines of the display panel 110. The second scan driver 132 (see...) Figure 3 The system can generate a second scan signal in response to a second scan control signal from the timing control circuit 170, and sequentially output the second scan signal to the scan lines of the display panel 110. The first scan signal and the second scan signal can be synchronized.

[0046] The first flexible film 122 can be disposed on the lower side of the display panel 110. The first flexible film 122 can be arranged in a first direction (X-axis direction). The second flexible film 124 can be disposed on the upper side of the display panel 110. The second flexible film 124 can be arranged in the first direction (X-axis direction).

[0047] One side of each of the first flexible films 122 may be attached to the exposed surface of the first substrate 111 that is not covered by the second substrate 112. The other side of each of the first flexible films 122 may be attached to the surface of any of the first source circuit boards 140. Each of the first flexible films 122 may be attached to the surface of the first substrate 111 and the surface of the first source circuit board 140 using an anisotropic conductive film.

[0048] One side of each of the second flexible films 124 may be disposed on the exposed surface of the first substrate 111 that is not covered by the second substrate 112. The other side of each of the second flexible films 124 may be attached to the surface of any of the second source circuit boards 141. Each of the second flexible films 124 may be attached to the surface of the first substrate 111 and the surface of the second source circuit board 141 using an anisotropic conductive film.

[0049] Each of the first flexible film 122 and the second flexible film 124 can be a flexible film such as a tape-on package or a chip-on-film. The first flexible film 122 and the second flexible film 124 can be bent to be disposed under the first substrate 111. Therefore, the first source circuit board 140, the second source circuit board 141, the first cable 150, the second cable 153, the control circuit board 160, and the timing control circuit 170 can be disposed under the first substrate 111.

[0050] Although Figure 1 The first flexible film 122 and the second flexible film 124 are shown, but either the first flexible film 122 or the second flexible film 124 may be omitted in this specification. For example, when the display panel 110 has a high resolution such as 8K UHD, both the first flexible film 122 and the second flexible film 124 are required. However, when the display panel 110 has 4K UHD, either the first flexible film 122 or the second flexible film 124 may be omitted.

[0051] In addition, although Figure 1 Eight first flexible films 122 and eight second flexible films 124 are attached to the first substrate 111 of the display panel 110. However, in this specification, the number of first flexible films 122 and the number of second flexible films 124 are not limited thereto. For example, the number of first flexible films 122 and the number of second flexible films 124 can vary depending on the number of channels in each of the first flexible films 122 and the number of channels in each of the second flexible films 124. The number of channels in each of the first flexible films 122 indicates the number of lead pads in each of the first flexible films 122 that are connected to the first pad (or "soldering pad") of the display panel 110. The number of channels in each of the second flexible films 124 indicates the number of lead pads in each of the second flexible films 124 that are connected to the second pad of the display panel 110.

[0052] The first source drive circuit 121 can be disposed on the first flexible film 122. The first source drive circuit 121 can be formed as an integrated circuit. Each of the first source drive circuits 121, in response to the first source control signal of the timing control circuit 170, converts digital video data into analog data voltage and outputs the analog data voltage to the data line of the display panel 110 through the first flexible film 122.

[0053] The second source drive circuit 123 can be disposed on the second flexible film 124. The second source drive circuit 123 can be formed as an integrated circuit. Each of the second source drive circuits 123, in response to the second source control signal of the timing control circuit 170, converts digital video data into analog data voltage and outputs the analog data voltage to the data line of the display panel 110 through the second flexible film 124.

[0054] Each of the first source circuit boards 140 can be connected to the control circuit board 160 via a first cable 150. Each of the first source circuit boards 140 may include a first connection portion 151a connected to the first cable 150.

[0055] Each of the second source circuit boards 141 can be connected to the control circuit board 160 via the second cable 153. Each of the second source circuit boards 141 may include a third connector 154 connected to the second cable 153.

[0056] The first source circuit board 140 and the second source circuit board 141 can be flexible printed circuit boards or printed circuit boards. The first cable 150 and the second cable 153 can be flexible cables.

[0057] The control circuit board 160 can be connected to the first source circuit board 140 via a first cable 150. The control circuit board 160 may include a second connection portion 152 connected to the first cable 150. The control circuit board 160 can be connected to the second source circuit board 141 via a second cable 153. The control circuit board 160 may include a fourth connection portion 155 connected to the second cable 153. The control circuit board 160 may be a flexible printed circuit board or a printed circuit board.

[0058] exist Figure 1 In this configuration, four first cables 150 connect the first source circuit board 140 and the control circuit board 160, and four second cables 153 connect the second source circuit board 141 and the control circuit board 160. However, in this specification, the number of first cables 150 and second cables 153 is not limited to this. Furthermore, in... Figure 1The diagram shows two first source circuit boards 140 and two second source circuit boards 141. However, the number of first source circuit boards 140 and second source circuit boards 141 is not limited to this in this specification.

[0059] Timing control circuit 170 can be disposed on control circuit board 160. Timing control circuit 170 can be formed as an integrated circuit. Timing control circuit 170 can receive digital video data and timing signals from the on-chip system of system circuit board (not shown). Timing control circuit 170 can generate a first source control signal for controlling the timing of the first source drive circuit 121 and a second source control signal for controlling the timing of the second source drive circuit 123, based on the timing signals. Timing control circuit 170 can also generate signals for controlling the first scan driver 131 (see...) Figure 3 The timing of the first scan control signal and the timing of the second scan driver 132 (see...) Figure 3 The second scan control signal of the timing sequence.

[0060] The system-on-a-chip (SoC) can be mounted on a system circuit board connected to the control circuit board 160 via another flexible cable, and can be formed as an integrated circuit. The SoC can be a processor of a smart TV, a central processing unit (CPU) or graphics card of a computer or laptop, or an application processor of a smartphone or tablet PC. The system circuit board can be a flexible printed circuit board or a printed circuit board.

[0061] The power supply circuitry may be additionally attached to the surface of the control circuit board 160. The power supply circuitry can use the main power applied from the system circuit board to generate and supply the voltage required to drive the display panel 110. For example, the power supply circuitry may generate and supply voltage for driving the first scan driver 131 (see...). Figure 3 ), second scan driver 132 (see Figure 2 The power supply circuit provides the driving voltage for the first source drive circuit 121, the second source drive circuit 123, the timing control circuit 170, etc. The power supply circuit can be formed as an integrated circuit. Optionally, the power supply circuit can be located on a power circuit board formed separately from the control circuit board 160. The power circuit board can be a flexible printed circuit board or a printed circuit board.

[0062] Figure 2 This is a block diagram of the display device 10 according to an embodiment.

[0063] Reference Figure 2 The display panel 110 may include a display area DA that displays images using subpixels SP and a non-display area NDA surrounding the display area DA. In the display area DA, not only can the subpixels SP be set, but also the scan lines SL and data lines DL connected to the subpixels SP can be set.

[0064] The scan line SL can extend in a first direction (X-axis direction) and can be set in a second direction (Y-axis direction). The data line DL can extend in a second direction (Y-axis direction) that intersects with the first direction (X-axis direction) and can be set in the first direction (X-axis direction).

[0065] Each sub-pixel SP can be connected to any of the scan lines SL and any of the data lines DL. Each sub-pixel SP may include at least one transistor, a storage capacitor, and a pixel electrode. The transistor can be turned on in response to a scan signal received from the scan line SL. Therefore, a data voltage of the data line DL can be applied to the pixel electrode. An electric field can be applied to the liquid crystal layer based on the voltage difference between the data voltage applied to the pixel electrode and the common voltage applied to the common electrode. Therefore, the liquid crystal in the liquid crystal layer can be driven by the electric field. The storage capacitor is used to maintain the data voltage applied to the pixel electrode for a predetermined period of time.

[0066] The non-display area NDA can be defined as the area extending from the outside of the display area DA to the edge of the display panel 110. Within the non-display area NDA, a scan driver 130 can be provided for transmitting scan signals to the scan line SL.

[0067] Scan driver 130 can receive scan control signal SCS from timing control circuit 170. Scan driver 130 can generate scan signals according to scan control signal SCS and output scan signals sequentially to scan lines SL. Figure 3 As shown, the scan driver 130 may include a first scan driver 131 disposed on the third side of the display panel 110 (see Figure 131). Figure 3 ) and a second scan driver 132 disposed on the fourth side of the display panel 110 (see Figure 3 ).

[0068] The data driver 120 may include a first source drive circuit 121 and a second source drive circuit 123. The data driver 120 converts digital video data DATA into analog positive / negative data voltages and outputs these analog positive / negative data voltages to the data line DL. Therefore, the data voltages can be supplied to the sub-pixel SP selected by the scan signal of the scan driver 130.

[0069] The timing control circuit 170 can receive digital video data DATA and timing signals from the system-on-chip. Based on the timing signals, the timing control circuit 170 can generate a scan control signal SCS for controlling the operating timing of the scan driver 130 and a data control signal DCS for controlling the operating timing of the data driver 120. The timing control circuit 170 can output the scan control signal SCS to the scan driver 130 and the data control signal DCS to the data driver 120.

[0070] Figure 3 This is a circuit diagram showing sub-pixels SP1 and SP2 of a display panel 110 according to an embodiment. For ease of description, in Figure 3 The image shows sub-pixels SP1 and SP2 connected to the first scan lines SL1 to the fourth scan lines SL4, the first data lines DL1 to the fourth data lines DL4, and the (m-3)th data lines DLm-3 to the mth data lines DLm (where m is a positive integer of 8 or greater).

[0071] Reference Figure 3 The first sub-pixel SP1 can be connected to odd-numbered scan lines SL1 and SL3, and the second sub-pixel SP2 can be connected to even-numbered scan lines SL2 and SL4. The first sub-pixel SP1, connected to either of the odd-numbered scan lines SL1 and SL3, can be arranged in a first direction (X-axis direction). The second sub-pixel SP2, connected to either of the even-numbered scan lines SL2 and SL4, can also be arranged in the first direction (X-axis direction). The first sub-pixel SP1 and the second sub-pixel SP2 can be arranged alternately in a second direction (Y-axis direction).

[0072] Because adjacent odd-numbered and even-numbered scan lines are connected to each other, the same scan signal can be transmitted to both adjacent odd-numbered and even-numbered scan lines. For example, adjacent first scan line SL1 and second scan line SL2 can be connected to each other, and the same scan signal can be transmitted to both first scan line SL1 and second scan line SL2. Adjacent third scan line SL3 and fourth scan line SL4 can be connected to each other, and the same scan signal can be transmitted to both third scan line SL3 and fourth scan line SL4.

[0073] In the first sub-pixel SP1 and the second sub-pixel SP2, which are arranged alternately along the second direction (Y-axis direction), the first sub-pixel SP1 can be connected to an odd number of data lines, and the second sub-pixel SP2 can be connected to an even number of data lines.

[0074] The first scan driver 131 can be disposed on the third side of the display panel 110, and the second scan driver 132 can be disposed on the fourth side of the display panel 110. Each of the first scan driver 131 and the second scan driver 132 can be connected to scan lines SL1 to SL4. The first scan driver 131 and the second scan driver 132 can output synchronized scan signals to the corresponding scan lines SL1 to SL4.

[0075] Each of the first scan driver 131 and the second scan driver 132 may include multiple transistors to output a scan signal in response to a scan control signal SCS. The transistors may be thin-film transistors similar to the first switching element T1 of each first sub-pixel SP1 and the second switching element T2 of each second sub-pixel SP2.

[0076] Each of the first sub-pixels SP1 may include a first switching element T1, a first liquid crystal capacitor Clc1, and a first storage capacitor Cst1.

[0077] The first switching element T1 may include a first gate electrode connected to an odd number of scan lines, a first electrode connected to an odd number of data lines, and a second electrode connected to a first pixel electrode PXE1. The first switching element T1 can be turned on when a scan signal is transmitted to an odd number of scan lines, and can apply the data voltage of the odd number of data lines to the first pixel electrode PXE1.

[0078] The first switching element T1 can be a thin-film transistor. In this case, either the first electrode or the second electrode of the first switching element T1 can be the source electrode, and the other can be the drain electrode.

[0079] The first liquid crystal capacitor Clc1 may include a first pixel electrode PXE1 to which a data voltage is applied and a common electrode CE to which a common voltage Vcom is applied. The first liquid crystal capacitor Clc1 can be charged by the voltage difference between the data voltage of the first pixel electrode PXE1 and the common voltage Vcom of the common electrode CE.

[0080] The first storage capacitor Cst1 may include a first pixel electrode PXE1 to which a data voltage is applied and a first storage electrode STE1 to which a storage voltage Vcst is applied. The first storage capacitor Cst1 can be charged by the voltage difference between the data voltage of the first pixel electrode PXE1 and the storage voltage Vcst of the first storage electrode STE1.

[0081] Each of the second sub-pixels SP2 may include a second switching element T2, a second liquid crystal capacitor Clc2, and a second storage capacitor Cst2.

[0082] The second switching element T2 may include a second gate electrode connected to an even number of scan lines, a first electrode connected to an even number of data lines, and a second electrode connected to a second pixel electrode PXE2. The second switching element T2 can be turned on when the scan signal is transmitted to an even number of scan lines, and can apply the data voltage of the even number of data lines to the second pixel electrode PXE2.

[0083] The second switching element T2 can be a thin-film transistor. In this case, either the first electrode or the second electrode of the second switching element T2 can be the source electrode, and the other can be the drain electrode.

[0084] The second liquid crystal capacitor Clc2 may include a second pixel electrode PXE2 to which a data voltage is applied and a common electrode CE to which a common voltage Vcom is applied. The second liquid crystal capacitor Clc2 can be charged by the voltage difference between the data voltage of the second pixel electrode PXE2 and the common voltage Vcom of the common electrode CE.

[0085] The second storage capacitor Cst2 may include a second pixel electrode PXE2 to which a data voltage is applied and a second storage electrode STE2 to which a storage voltage Vcst is applied. The second storage capacitor Cst2 can be charged by the voltage difference between the data voltage of the second pixel electrode PXE2 and the storage voltage Vcst of the second storage electrode STE2.

[0086] like Figure 3 As shown, since adjacent odd-numbered and even-numbered scan lines are connected to each other, when the same scan signal is transmitted to adjacent odd-numbered and even-numbered scan lines, the first switching element T1 of the first sub-pixel SP1 and the second switching element T2 of the second sub-pixel SP2 are simultaneously turned on. Therefore, the first pixel electrode PXE1 and the second pixel electrode PXE2 can be charged simultaneously with different data voltages. Therefore, when the display panel 110 has a high resolution such as 8K UHD, a decrease in the charging rate of the data voltage in the pixel electrodes can be prevented. This prevents horizontal or vertical line defects due to a decrease in the charging rate of the data voltage in the pixel electrodes.

[0087] Figure 4 This is a layout diagram showing the sub-pixels SP1 and SP2 of the display panel 110 according to an embodiment. For ease of description, in Figure 4 Only sub-pixels SP1 and SP2 connected to the first scan line SL1, the second scan line SL2, and the first data lines DL1 to the sixth data lines DL6 are shown.

[0088] exist Figure 4For ease of description, this section will primarily focus on the first sub-pixel SP1 connected to the first scan line SL1 and the first data line DL1, and the second sub-pixel SP2 connected to the second scan line SL2 and the second data line DL2. Additionally, in Figure 4 In the first switching element T1, the first electrode is the first drain electrode DE1, and the second electrode is the first source electrode SE1.

[0089] Reference Figure 4 The first sub-pixel SP1 may include a first switching element T1, a first pixel electrode PXE1, a first source connection SCE1, a first storage electrode STE1, a first storage line STL1, and a first shielding line SHL1.

[0090] The first switching element T1 may include a first gate electrode GE1 connected to a first scan line SL1, a first source electrode SE1 connected to a first source connection SCE1, a first drain electrode DE1 connected to a first data line DL1, and a first active layer ACT1 superimposed on the first gate electrode GE1.

[0091] The first gate electrode GE1 can be a portion of the first scan line SL1.

[0092] The first active layer ACT1 can be stacked not only with the first gate electrode GE1, but also with the first source electrode SE1 and the first drain electrode DE1. The first active layer ACT1 can have a quadrilateral planar shape, but this disclosure is not limited thereto.

[0093] The first source electrode SE1 may protrude from the first source connection portion SCE1 in the second direction (Y-axis direction). The first source electrode SE1 may extend in the second direction (Y-axis direction) to overlap with the first active layer ACT1.

[0094] The first drain electrode DE1 may include a first protrusion PP1 protruding from the first data line DL1 in a first direction (X-axis direction), a first extension EP1 extending from the end of the first protrusion PP1 in a second direction (Y-axis direction), and a second extension EP2 extending from the middle of the first protrusion PP1 in the second direction (Y-axis direction). The first protrusion PP1, the first extension EP1, and the second extension EP2 may form a U-shape in a plan view.

[0095] Each of the first extension EP1 and the second extension EP2 can be separated from the first source electrode SE1 in a first direction (X-axis direction). The first extension EP1, the first source electrode SE1, and the second extension EP2 can be arranged in the first direction (X-axis direction). The first source electrode SE1 can be arranged between the first extension EP1 and the second extension EP2 in the first direction (X-axis direction). The gap between the first extension EP1 and the first source electrode SE1 in the first direction (X-axis direction) and the gap between the second extension EP2 and the first source electrode SE1 in the first direction (X-axis direction) can be defined as the channel region of the first switching element T1.

[0096] The first source connection portion SCE1 can extend from the first source electrode SE1 and can be connected to the first pixel electrode connection portion PCE1 of the first pixel electrode PXE1 through the first contact hole CNT1. The first source connection portion SCE1 can be stacked with the first pixel electrode connection portion PCE1 of the first pixel electrode PXE1. The first source connection portion SCE1 can have a quadrilateral planar shape, but this disclosure is not limited thereto.

[0097] The first source connection SCE1 can be stacked with the first storage electrode STE1. The stacked first source connection SCE1 and the first storage electrode STE1 can form a first storage capacitor Cst1.

[0098] The first pixel electrode PXE1 may include a first horizontal trunk PHSE1 extending in a first direction (X-axis direction), a first vertical trunk PVSE1 extending in a second direction (Y-axis direction), a plurality of first branches PBE1 extending outward from the first horizontal trunk PHSE1 and the first vertical trunk PVSE1, and a first pixel electrode connection portion PCE1 extending from the first vertical trunk PVSE1 and / or the first branches PBE1 and superimposed on the first source connection portion SCE1.

[0099] The first pixel electrode PXE1 may include four domains DM1 to DM4 defined by the first horizontal backbone PHSE1 and the first vertical backbone PVSE1. The first horizontal backbone PHSE1 and the first vertical backbone PVSE1 may be arranged in a cross shape in a plan view.

[0100] The slit SLT can be set between two adjacent first branches PBE1. That is, two adjacent first branches PBE1 can be separated by the slit SLT.

[0101] The first branch PBE1 can extend in different directions in each of the four domains DM1 to DM4. For example, the first branch PBE1 located in the first domain DM1, which is positioned on the upper right side, can extend obliquely upwards to the upper right. The first branch PBE1 located in the second domain DM2, which is positioned on the lower right side, can extend obliquely upwards to the lower right. The first branch PBE1 located in the third domain DM3, which is positioned on the upper left side, can extend obliquely upwards to the upper left. The first branch PBE1 located in the fourth domain DM4, which is positioned on the lower left side, can extend obliquely upwards to the lower left. The ends of the first branches PBE1 can be connected to each other.

[0102] The first shielding line SHL1 may extend in a first direction (X-axis direction). The first shielding line SHL1 may be superimposed on at least a portion of the first scan line SL1. The first shielding line SHL1 may be superimposed on at least a portion of the first switching element T1. The first shielding line SHL1 may be made of the same material as the first pixel electrode PXE1 and may be disposed on the same layer as the first pixel electrode PXE1. The first shielding line SHL1 can prevent parasitic capacitors from forming between the first scan line SL1 and the common electrode CE, and between the first switching element T1 and the common electrode CE, thereby preventing liquid crystal driving failure.

[0103] The first scan line SL1 may include a first sub-scan line SL11 and a second sub-scan line SL12. Each of the first sub-scan line SL11 and the second sub-scan line SL12 may extend in a first direction (X-axis direction). The first sub-scan line SL11 and the second sub-scan line SL12 may be positioned in a second direction (Y-axis direction). Each of the first sub-scan line SL11 and the second sub-scan line SL12 may be connected to a first gate electrode GE1.

[0104] Each of the first sub-scan lines SL11 and SL12 may intersect with the first data line DL1 and the second data line DL2. During the manufacturing process of the sub-scan lines SL11 and SL12 and the data lines DL1 and DL2, if particles are present at any of the intersection points of the sub-scan lines SL11 and SL12 with the data lines DL1 and DL2, the sub-scan lines and data lines are very likely to short-circuit at any intersection point due to the particles. However, since more than one sub-scan line (e.g., two sub-scan lines) intersects with the data lines, a short-circuit fault can be prevented by cutting any short-circuited sub-scan line when any sub-scan line and data line are short-circuited.

[0105] The first memory line STL1 may include a first sub-memory line STL11 and a second sub-memory line STL12 extending in a second direction (Y-axis direction), and a third sub-memory line STL13 and a fourth sub-memory line STL14 extending in a first direction (X-axis direction). The first memory line STL1 may be made of the same material as the first scan line SL1 and may be disposed on the same layer as the first scan line SL1.

[0106] The first sub-memory line STL11 can be located outside the first data line DL1. That is, the first sub-memory line STL11 can be located to the left of the first data line DL1.

[0107] The second sub-memory line STL12 can be located outside the second data line DL2. That is, the second sub-memory line STL12 can be located to the right of the second data line DL2.

[0108] The third sub-memory line STL13 can connect to the lower end of the first sub-memory line STL11 and the lower end of the second sub-memory line STL12. The third sub-memory line STL13 can be positioned in the second direction (Y-axis direction) between the first vertical trunk PVSE1 and the first scan line SL1. The first memory electrode STE1 can protrude from the third sub-memory line STL13 in the second direction (Y-axis direction).

[0109] The fourth sub-memory line STL14 can be connected to the upper end of the first sub-memory line STL11 and the upper end of the second sub-memory line STL12.

[0110] The second sub-pixel SP2 may include a second switching element T2, a second pixel electrode PXE2, a second source connection SCE2, a second storage electrode STE2, a second storage line STL2, and a second shielding line SHL2.

[0111] The second pixel electrode PXE2, the second source connection SCE2, the second storage electrode STE2, the second storage line STL2, and the second shielding line SHL2 of the second sub-pixel SP2 are substantially the same as or similar to the first pixel electrode PXE1, the first source connection SCE1, the first storage electrode STE1, the first storage line STL1, and the first shielding line SHL1 of the first sub-pixel SP1, therefore their detailed description will be omitted.

[0112] In addition, except that the second gate electrode GE2 is connected to the second scan line SL2 instead of the first scan line SL1 and the second drain electrode DE2 is connected to the second data line DL2 instead of the first data line DL1, the second switching element T2 of the second sub-pixel SP2 is the same as the first switching element T1 of the first sub-pixel SP1, so a detailed description of the second sub-pixel SP2 will be omitted.

[0113] In the first sub-pixel SP1 and the second sub-pixel SP2, the first data line DL1 intersects with the third sub-storage line STL13 and the fourth sub-storage line STL4 of the first storage line STL1, the first sub-scan line SL11 and the second sub-scan line SL12 of the first scan line SL1, the third sub-storage line STL23 and the fourth sub-storage line STL24 of the second storage line STL2, and the first sub-scan line SL21 and the second sub-scan line SL22 of the second scan line SL2. That is, in the first sub-pixel SP1 and the second sub-pixel SP2, the first data line DL1 intersects with eight lines.

[0114] When particles are present at the intersection of scan lines and data lines, the scan lines and data lines are very likely to short-circuit at the intersection due to the particles. Additionally, when particles are present at the intersection of storage lines and data lines, the storage lines and data lines are very likely to short-circuit at the intersection due to the particles. Therefore, in order to increase the manufacturing yield of the display panel or reduce the number of display panel repairs during the manufacturing process, it is necessary to reduce the number of intersections between the first data line DL1 and scan lines SL1 and SL2, or the number of intersections between the first data line DL1 and storage lines STL1 and STL2 in the first sub-pixel SP1 and the second sub-pixel SP2.

[0115] Figure 5 This is a circuit diagram showing sub-pixels SP1 and SP2 of the display panel 110 according to an embodiment.

[0116] For ease of description, in Figure 5 The diagram shows sub-pixels SP1 and SP2 connected to the first scan line SL1 and the second scan line SL2, the first data lines DL1 to the fourth data lines DL4, and the (m-3)th data lines DLm-3 to the mth data lines DLm (where m is a positive integer of 8 or greater).

[0117] Reference Figure 5 The first sub-pixel SP1 and the second sub-pixel SP2, which are arranged adjacent to each other in the second direction (Y-axis direction), can be connected to a single scan line. That is, the first sub-pixel SP1 and the second sub-pixel SP2, which are arranged adjacent to each other in the second direction (Y-axis direction), can be connected to the same scan line.

[0118] The first sub-pixel SP1, connected to any scan line, can be arranged in the first direction (X-axis direction). The second sub-pixel SP2, connected to any scan line, can be arranged in the first direction (X-axis direction). The first sub-pixel SP1 and the second sub-pixel SP2 can be arranged alternately in the second direction (Y-axis direction).

[0119] In the alternating arrangement of first sub-pixels SP1 and second sub-pixels SP2 along the second direction (Y-axis direction), first sub-pixels SP1 can be connected to an odd number of data lines, and second sub-pixels SP2 can be connected to an even number of data lines. For example, in the alternating arrangement of first sub-pixels SP1 and second sub-pixels SP2 along the second direction (Y-axis direction), first sub-pixels SP1 can be connected to a first data line DL1, and second sub-pixels SP2 can be connected to a second data line DL2.

[0120] The first scan driver 131 can be disposed on the third side of the display panel 110, and the second scan driver 132 can be disposed on the fourth side of the display panel 110. Each of the first scan driver 131 and the second scan driver 132 can be connected to scan lines SL1 and SL2. The first scan driver 131 and the second scan driver 132 can output synchronized scan signals to scan lines SL1 and SL2.

[0121] Each of the first scan driver 131 and the second scan driver 132 may include multiple transistors to output a scan signal in response to a scan control signal SCS. The transistors may be thin-film transistors similar to the first switching element T1 of each first sub-pixel SP1 and the second switching element T2 of each second sub-pixel SP2.

[0122] Each of the first sub-pixels SP1 may include a first switching element T1, a first liquid crystal capacitor Clc1, and a first storage capacitor Cst1.

[0123] The first switching element T1 may include a first gate electrode connected to a scan line, a first electrode connected to an odd number of data lines, and a second electrode connected to a first pixel electrode PXE1. The first switching element T1 can be turned on when a scan signal is transmitted to the scan line, and can apply the data voltage of the odd number of data lines to the first pixel electrode PXE1.

[0124] The first switching element T1 can be a thin-film transistor. In this case, either the first electrode or the second electrode of the first switching element T1 can be the source electrode, and the other can be the drain electrode.

[0125] The first liquid crystal capacitor Clc1 and the first storage capacitor Cst1 are referenced above. Figure 3 The first liquid crystal capacitor Clc1 and the first storage capacitor Cst1 are essentially the same, so their description will be omitted.

[0126] Each of the second sub-pixels SP2 may include a second switching element T2, a second liquid crystal capacitor Clc2, and a second storage capacitor Cst2.

[0127] The second switching element T2 may include a second gate electrode connected to the first gate electrode of the first switching element T1 and connected to the scan line thereto, a first electrode connected to an even number of data lines, and a second electrode connected to the second pixel electrode PXE2. The second switching element T2 can be turned on when the scan signal is transmitted to the scan line, and can apply the data voltage of the even number of data lines to the second pixel electrode PXE2.

[0128] The second switching element T2 can be a thin-film transistor. In this case, either the first electrode or the second electrode of the second switching element T2 can be the source electrode, and the other can be the drain electrode.

[0129] The second liquid crystal capacitor Clc2 and the second storage capacitor Cst2 are referenced above. Figure 3 The second liquid crystal capacitor Clc2 and the second storage capacitor Cst2 are essentially the same, so their description will be omitted.

[0130] like Figure 5 As shown, since the first sub-pixel SP1 and the second sub-pixel SP2, which are adjacent to each other in the second direction (Y-axis direction), are connected to the same scan line, the first switching element T1 of the first sub-pixel SP1 and the second switching element T2 of the second sub-pixel SP2 can be turned on simultaneously. Therefore, the first pixel electrode PXE1 and the second pixel electrode PXE2 can be charged simultaneously with different data voltages. Thus, when the display panel 110 has a high resolution such as 8K UHD, a decrease in the charging rate of the data voltage in the pixel electrodes can be prevented. Therefore, horizontal or vertical line defects due to a decrease in the charging rate of the data voltage in the pixel electrodes can be prevented.

[0131] Figure 6 This is a layout diagram showing the sub-pixels SP1 and SP2 of the display panel 110 according to an embodiment. Figure 7 It shows in detail Figure 6 An enlarged layout diagram of an example of the first switching element T1 and the first contact hole CNT1 of the first sub-pixel SP1, and the second switching element T2 and the second contact hole CNT2 of the second sub-pixel SP2.

[0132] For ease of description, in Figure 6 Only sub-pixels SP1 and SP2, connected to the first scan line SL1 and the first data lines DL1 to the sixth data lines DL6, are shown. Figure 6 and Figure 7 For ease of description, this section will primarily focus on the first sub-pixel SP1 connected to the first scan line SL1 and the first data line DL1, and the second sub-pixel SP2 connected to the first scan line SL1 and the second data line DL2. Additionally, in Figure 6 and Figure 7In the first switching element T1, the first electrode is the first drain electrode DE1, and the second electrode is the first source electrode SE1.

[0133] Reference Figure 6 and Figure 7 The first sub-pixel SP1 may include a first switching element T1, a first pixel electrode PXE1, a first source connection SCE1, a first storage electrode STE1, and a first storage line STL1.

[0134] The first switching element T1 may include a first gate electrode GE1 connected to a first scan line SL1, a first source electrode SE1 connected to a first source connection SCE1, a first drain electrode DE1 connected to a first data line DL1, and a first active layer ACT1 superimposed on the first gate electrode GE1.

[0135] The first gate electrode GE1 may protrude from the first scan line SL1 in the second direction (Y-axis direction). The first gate electrode GE1 may protrude from the first scan line SL1 toward the second pixel electrode PXE2. The first gate electrode GE1 may protrude from the first scan line SL1 to be adjacent to the second pixel electrode PXE2 in the second direction (Y-axis direction).

[0136] The first active layer ACT1 can be stacked not only with the first gate electrode GE1, but also with the first source electrode SE1 and the first drain electrode DE1. The first active layer ACT1 can have a quadrilateral planar shape, but this disclosure is not limited thereto.

[0137] The first source electrode SE1 may protrude from the first source connection portion SCE1 in the second direction (Y-axis direction) to be superimposed on the first active layer ACT1. The first source electrode SE1 may protrude from the first source connection portion SCE1 toward the second pixel electrode PXE2. The first source electrode SE1 may extend in the second direction (Y-axis direction).

[0138] The first drain electrode DE1 may include a first protrusion PP1 protruding from the first data line DL1 in a first direction (X-axis direction) and a first extension EP1 extending from the first protrusion PP1 in a second direction (Y-axis direction). The first extension EP1 may protrude from the middle of the first protrusion PP1 in the second direction (Y-axis direction) to overlap with the first active layer ACT1. The first extension EP1 may protrude toward the first pixel electrode PXE1. The first protrusion PP1 may extend in the first direction (X-axis direction), and the first extension EP1 may extend in the second direction (Y-axis direction).

[0139] The first extension EP1 can be separated from the first source electrode SE1 in a first direction (X-axis direction). The first extension EP1 and the first source electrode SE1 can be disposed in the first direction (X-axis direction). The first source electrode SE1 and the first extension EP1 can extend along a second direction (Y-axis direction) in the region superimposed with the first active layer ACT1. The gap between the first extension EP1 and the first source electrode SE1 in the first direction (X-axis direction) can be defined as the first channel region CH1 of the first switching element T1.

[0140] The first source connection portion SCE1 can extend from the first source electrode SE1 and can be connected to the first pixel electrode connection portion PCE1 of the first pixel electrode PXE1 through the first contact hole CNT1. The first source connection portion SCE1 can be stacked with the first pixel electrode connection portion PCE1 of the first pixel electrode PXE1. The first source connection portion SCE1 can have a quadrilateral planar shape, but this disclosure is not limited thereto.

[0141] The first storage electrode STE1 may protrude from the third sub-storage line STL13 of the first storage line STL1 in the second direction (Y-axis direction). The first storage electrode STE1 may protrude toward the second pixel electrode PXE2. The first storage electrode STE1 may be stacked with the first source connection portion SCE1. The first storage electrode STE1 and the first source connection portion SCE1 may form a first storage capacitor Cst1.

[0142] The first pixel electrode PXE1 is referenced above. Figure 4 The first pixel electrode PXE1 described is essentially the same, therefore its description will be omitted. Except that the first memory line STL1 does not include the fourth sub-memory line STL14, the first memory line STL1 is identical to the one described above. Figure 4 The first memory line STL1 is essentially the same as described, so its description will be omitted.

[0143] The second sub-pixel SP2 may include a second switching element T2, a second pixel electrode PXE2, a second source connection SCE2, a second storage electrode STE2, and a second storage line STL2.

[0144] The second switching element T2 may include a second gate electrode GE2 connected to the first scan line SL1, a second source electrode SE2 connected to the second source connection SCE2, a second drain electrode DE2 connected to the second data line DL2, and a second active layer ACT2 superimposed on the second gate electrode GE2.

[0145] The second gate electrode GE2 can protrude from the first scan line SL1 in the second direction (Y-axis direction). The second gate electrode GE2 can protrude from the first scan line SL1 toward the first pixel electrode PXE1. The second gate electrode GE2 can protrude from the first scan line SL1 to be adjacent to the first pixel electrode PXE1 in the second direction (Y-axis direction).

[0146] The second active layer ACT2 can be stacked not only with the second gate electrode GE2, but also with the second source electrode SE2 and the second drain electrode DE2. The second active layer ACT2 can have a quadrilateral planar shape, but this disclosure is not limited thereto.

[0147] The second source electrode SE2 can protrude from the second source connection portion SCE2 in the second direction (Y-axis direction) to overlap with the second active layer ACT2. The second source electrode SE2 can protrude from the second source connection portion SCE2 toward the first pixel electrode PXE1. The second source electrode SE2 can extend in the second direction (Y-axis direction) to overlap with the second active layer ACT2.

[0148] The second drain electrode DE2 may include a second protrusion PP2 protruding from the second data line DL2 in a first direction (X-axis direction) and a second extension EP2 extending from the second protrusion PP2 in a second direction (Y-axis direction). The second extension EP2 may protrude from the end of the second protrusion PP2 in the second direction (Y-axis direction). The second extension EP2 may protrude toward the second pixel electrode PXE2. The second protrusion PP2 may extend in the first direction (X-axis direction), and the second extension EP2 may extend in the second direction (Y-axis direction).

[0149] The second extension EP2 can be separated from the second source electrode SE2 in the first direction (X-axis direction). The second extension EP2 and the second source electrode SE2 can be disposed in the first direction (X-axis direction). The gap between the second extension EP2 and the second source electrode SE2 in the first direction (X-axis direction) can be defined as the second channel region CH2 of the second switching element T2.

[0150] The second source electrode connection portion SCE2 can extend from the second source electrode SE2 and can be connected to the second pixel electrode connection portion PCE2 of the second pixel electrode PXE2 through the second contact hole CNT2. The second source electrode connection portion SCE2 can be stacked with the second pixel electrode connection portion PCE2 of the second pixel electrode PXE2. The second source electrode connection portion SCE2 can have a quadrilateral planar shape, but this disclosure is not limited thereto.

[0151] The second source connection SCE2 can be stacked with the second storage electrode STE2. The second source connection SCE2 and the second storage electrode STE2 can form a second storage capacitor Cst2.

[0152] In addition to the second pixel electrode connection portion PCE2 and the second source electrode connection portion SCE2 being stacked, the second pixel electrode PXE2 and Figure 4 The first pixel electrode PXE1 is essentially the same, so its description will be omitted. Additionally, except that the second memory line STL2 does not include the fourth sub-memory line STL24, the second memory line STL2 is... Figure 4 The first memory line STL1 is essentially the same, so its description will be omitted.

[0153] The shielding line SHL can extend in a first direction (X-axis direction). The shielding line SHL can be disposed in a second direction (Y-axis direction) between the first pixel electrode PXE1 and the second pixel electrode PXE2. The shielding line SHL can be superimposed on at least a portion of the first scan line SL1. The shielding line SHL can be superimposed on at least a portion of the first switching element T1 and at least a portion of the second switching element T2. The shielding line SHL can be made of the same material as the first pixel electrode PXE1 and disposed on the same layer as the first pixel electrode PXE1. The shielding line SHL can prevent parasitic capacitors from forming between the first scan line SL1 and the common electrode CE, between the first switching element T1 and the common electrode CE, and between the second switching element T2 and the common electrode CE, thereby preventing liquid crystal driving failure.

[0154] The first scan line SL1 may include a first sub-scan line SL11 and a second sub-scan line SL12. Each of the first sub-scan line SL11 and the second sub-scan line SL12 may extend in a first direction (X-axis direction). The first sub-scan line SL11 and the second sub-scan line SL12 may be positioned in a second direction (Y-axis direction). Each of the first sub-scan line SL11 and the second sub-scan line SL12 may be connected to a first gate electrode GE1.

[0155] Each of the first sub-scan line SL11 and the second sub-scan line SL12 may intersect with the first data line DL1 and the second data line DL2. During the manufacturing process of the sub-scan lines SL11 and SL12 and the data lines DL1 and DL2, if particles are present at any of the intersection points of the sub-scan lines SL11 and SL12 with the data lines DL1 and DL2, the sub-scan lines and data lines are very likely to short-circuit at any intersection point due to the particles. However, since more than one sub-scan line intersects with the data lines, a short-circuit fault can be prevented by cutting any of the sub-scan lines when any of the sub-scan lines and data lines are short-circuited.

[0156] In the first sub-pixel SP1 and the second sub-pixel SP2, the first data line DL1 intersects with the third sub-storage line STL13 of the first storage line STL1, the first sub-scan line SL11 and the second sub-scan line SL12 of the first scan line SL1, and the third sub-storage line STL23 of the second storage line STL2. That is, in the first sub-pixel SP1 and the second sub-pixel SP2, the first data line DL1 intersects with only four lines. Therefore, with... Figure 4 Compared to the embodiments shown, due to in Figure 6 In the illustrated embodiment, the fourth sub-memory lines STL14 and STL24 can be omitted, thus reducing the number of intersections between the first data line DL1 and the memory lines STL1 and STL2. Therefore, short circuits between the first data line DL1 and the memory lines STL1 and STL2 caused by particles can be reduced, thereby increasing the manufacturing yield of the display panel.

[0157] Additionally, refer to Figure 6 The first sub-storage line STL11 of the first storage line STL1 and the first sub-storage line STL21 of the second storage line STL2 can be connected to each other in the space between the upper side of the first pixel electrode PXE1 and the lower side of the second pixel electrode PXE2. The second sub-storage line STL12 of the first storage line STL1 and the second sub-storage line STL22 of the second storage line STL2 can be connected to each other in the space between the upper side of the first pixel electrode PXE1 and the lower side of the second pixel electrode PXE2. Therefore, in the first sub-pixel SP1 and the second sub-pixel SP2 that do not share the same scan line and are adjacent to each other in the second direction (Y-axis direction), the first storage line STL1 and the second storage line STL2 can be connected in a grid shape in the first direction (X-axis direction) and the second direction (Y-axis direction).

[0158] like Figure 7 As shown, the first switching element T1 and the first contact hole CNT1 can be positioned close to each other in the second direction (Y-axis direction), and the second switching element T2 and the second contact hole CNT2 can also be positioned close to each other in the second direction (Y-axis direction). For example, the first active layer ACT1 and the first contact hole CNT1 of the first switching element T1 can be positioned close to each other in the second direction (Y-axis direction). Similarly, the second active layer ACT2 and the second contact hole CNT2 of the second switching element T2 can be positioned close to each other in the second direction (Y-axis direction).

[0159] Furthermore, the first switching element T1 and the second contact hole CNT2 can be positioned close to each other in the first direction (X-axis direction), and the second switching element T2 and the first contact hole CNT1 can be positioned close to each other in the first direction (X-axis direction). For example, at least one of the first source electrode SE1 and the first drain electrode DE1 of the first switching element T1 and the second contact hole CNT2 can be positioned close to each other in the first direction (X-axis direction). At least one of the second source electrode SE2 and the second drain electrode DE2 of the second switching element T2 and the first contact hole CNT1 can be positioned close to each other in the first direction (X-axis direction).

[0160] Furthermore, the first pixel electrode PXE1 and the second pixel electrode PXE2 can be set in the second direction (Y-axis direction).

[0161] In this scenario, if either the first switching element T1 or the second switching element T2 is determined to be defective, it can be easily repaired. For example, when the first switching element T1 is defective, the electrical connection between the first source electrode SE1 and the first pixel electrode PXE1 of the first switching element T1 can be cut using a laser, and a pixel connection electrode connecting the first pixel electrode PXE1 and the second pixel electrode PXE2 can be added using an inkjet process. In this case, the inkjet process can be simple because the pixel connection electrode only needs to extend in the second direction (Y-axis direction).

[0162] Alternatively, when the second switching element T2 is defective, the electrical connection between the second source electrode SE2 and the second pixel electrode PXE2 of the second switching element T2 can be cut using a laser, and a pixel connection electrode connecting the first pixel electrode PXE1 and the second pixel electrode PXE2 can be added using an inkjet process. In this case, since the pixel connection electrode only needs to extend in the second direction (Y-axis direction), the inkjet process can be simple.

[0163] Figure 8 It is along Figure 7 The example cross-sectional view of display panel 110 is taken by line I-I'. Now refer to... Figure 7 and Figure 8 A detailed description of the cross-section of the first sub-pixel SP1 of the display panel 110.

[0164] Reference Figure 7 and Figure 8 The first switching element T1 and the first pixel electrode PXE1 of the first sub-pixel SP1 can be disposed on the first substrate 111 of the display panel 110, and the common electrode CE can be disposed on the second substrate 112. The liquid crystal layer 300 including the liquid crystal 310 can be disposed between the first substrate 111 and the second substrate 112.

[0165] The first substrate 111 may be a transparent insulating substrate. For example, the first substrate 111 may include an insulating material such as glass, quartz, or a polymer resin. The polymer material may be polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl compounds, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. The first substrate 111 may also be flexible.

[0166] A first conductive layer, including a first scan line SL1, a first storage line STL1, a first gate electrode GE1, and a second gate electrode GE2, can be disposed on the first substrate 111. That is, the first scan line SL1, the first storage line STL1, the first gate electrode GE1, and the second gate electrode GE2 can be formed simultaneously and made of the same material. The first conductive layer can include any one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), or an alloy thereof. Optionally, the first conductive layer can have a molybdenum / aluminum-neodymium, molybdenum / aluminum, or copper / titanium bilayer structure.

[0167] A gate insulating layer GI may be disposed on the first conductive layer. The gate insulating layer GI may comprise an inorganic insulating material such as a silicon compound or a metal oxide. For example, the gate insulating layer GI may comprise silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or combinations thereof.

[0168] The first active layer ACT1, the second active layer ACT2, and the short-circuit blocking pattern SBP can be disposed on the gate insulating layer GI. The first active layer ACT1 may include a first channel region CH1 disposed in the first direction (X-axis direction) between the first source electrode SE1 and the first drain electrode DE1. The first channel region CH1 may be stacked with the first gate electrode GE1. The second active layer ACT2 may include a second channel region CH2 disposed in the first direction (X-axis direction) between the second source electrode SE2 and the second drain electrode DE2. The second channel region CH2 may be stacked with the second gate electrode GE2.

[0169] The first active layer ACT1, the second active layer ACT2, and the short-circuit blocking pattern SBP may comprise silicon-based semiconductor materials such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. Optionally, the first active layer ACT1, the second active layer ACT2, and the short-circuit blocking pattern SBP may comprise oxide semiconductors.

[0170] An ohmic contact layer can be disposed on the first active layer ACT1 and the second active layer ACT2. Specifically, the ohmic contact layer can be disposed between the first source electrode SE1 and the first semiconductor layer ACT1, between the first drain electrode DE1 and the first semiconductor layer ACT1, between the second source electrode SE2 and the second semiconductor layer ACT2, and between the second drain electrode DE2 and the second semiconductor layer ACT2. The ohmic contact layer can reduce the contact resistance by lowering the Schottky barrier (i.e., work function) between the metal and silicon. The ohmic contact layer can be made of heavily doped amorphous silicon with n-type impurities.

[0171] The short-circuit blocking pattern SBP can be set at the intersection points of the first data line DL1 and sub-scan lines SL11, SL12, SL21, and SL22, and at the intersection points of the first data line DL1 and memory lines STL1 and STL2. Specifically, the short-circuit blocking pattern SBP can be set between the first data line DL1 and the first sub-scan line SL11 of the first scan line SL1, between the first data line DL1 and the second sub-scan line SL12 of the first scan line SL1, between the first data line DL1 and the third sub-storage line STL13 of the first storage line STL1, and between the first data line DL1 and the third sub-storage line STL23 of the second storage line STL2.

[0172] When a particle is present at any of the intersection points of the first data line DL1 and the sub-scan lines SL11, SL12, SL21, and SL22, the sub-scan lines and the first data line DL1 are highly likely to short-circuit due to the particle located at any intersection point between the sub-scan lines and the first data line DL1. However, when the short-circuit blocking pattern SBP is located at the intersection points of the first data line DL1 and the sub-scan lines SL11, SL12, SL21, and SL22, even if a particle is present at any of the intersection points, the short-circuit blocking pattern SBP can prevent a short circuit between the sub-scan lines and the first data line DL1. Therefore, the possibility of a short circuit between the sub-scan lines and the first data line DL1 can be reduced. Furthermore, even if a particle is present at any of the intersection points of the first data line DL1 and the memory lines STL1 and STL2, the memory lines and the first data line DL1 will not directly contact each other due to the short-circuit blocking pattern SBP located at any intersection point. Therefore, the possibility of a short circuit between the memory lines STL1 and STL2 and the first data line DL1 can be reduced.

[0173] The second conductive layer can be disposed on the gate insulating layer GI, the first semiconductor layer ACT1, the second semiconductor layer ACT2, and the short-circuit blocking pattern SBP. The second conductive layer may include a first data line DL1, a second data line DL2, a first source electrode SE1, a first drain electrode DE1, a second source electrode SE2, and a second drain electrode DE2. That is, the first data line DL1, the second data line DL2, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 can be formed simultaneously and made of the same material. The second conductive layer may include any one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), or an alloy thereof. Optionally, the second conductive layer may have a molybdenum / aluminum-neodymium, molybdenum / aluminum, or copper / titanium bilayer structure, or a molybdenum / titanium / molybdenum or molybdenum / aluminum / molybdenum trilayer structure.

[0174] The first source electrode SE1 and the first drain electrode DE1 can be disposed on the first semiconductor layer ACT1. The second source electrode SE2 and the second drain electrode DE2 can be disposed on the second semiconductor layer ACT2.

[0175] Color filter 212 can be disposed on the first switching element T1 and the second switching element T2. Color filter 212 can be a red color filter, a green color filter, or a blue color filter. A red color filter can be disposed on... Figure 6 The first sub-pixel SP1 is connected to the first data line DL1, and the second sub-pixel SP2 is connected to the second data line DL2. Additionally, a green filter can be set... Figure 6 The first sub-pixel SP1, connected to the third data line DL3, and the second sub-pixel SP2, connected to the fourth data line DL4, are also included. Additionally, a blue filter can be set... Figure 6 The first sub-pixel SP1 is connected to the fifth data line DL5 and the second sub-pixel SP2 is connected to the sixth data line DL6.

[0176] An insulating layer 113 may be disposed on the color filter 212. The insulating layer 113 may comprise organic or inorganic insulating materials. For example, the insulating layer 113 may be an outer coating made of an organic insulating material.

[0177] A third conductive layer, including the first pixel electrode PXE1, the second pixel electrode PXE2, and the shielding line SHL, can be disposed on the insulating layer 113. That is, the first pixel electrode PXE1, the second pixel electrode PXE2, and the shielding line SHL can be formed simultaneously and made of the same material. The first pixel electrode connection portion PCE1 of the first pixel electrode PXE1 can be connected to the first source electrode SE1 through the first contact hole CNT1 formed through the color filter 212 and the insulating layer 113.

[0178] The third conductive layer can be made of a transparent material through which light can pass. For example, the third conductive layer can be made of indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). However, this disclosure is not limited thereto, and any transparent and conductive material can be used.

[0179] Similar to the first substrate 111, the second substrate 112 facing the first substrate 111 can be a transparent insulating substrate. The second substrate 112 can also be flexible.

[0180] A first light-blocking member BM1 may be disposed on the surface of the second substrate 112 facing the first substrate 111. The first light-blocking member BM1 may be stacked with a first switching element T1, a first contact hole CNT1, a second switching element T2, and a second contact hole CNT2. The first light-blocking member BM1 may include a light-blocking pigment such as carbon black or an opaque metallic material such as chromium (Cr). Optionally, the first light-blocking member BM1 may include a photosensitive organic material. The first light-blocking member BM1 may also be disposed on the first substrate 111.

[0181] The common electrode CE can be disposed on the surface of the first light-blocking member BM1 facing the first substrate 111. The common electrode CE can be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). The common electrode CE can be formed on the entire surface of the second substrate 112.

[0182] A liquid crystal layer 300 may be disposed between a first substrate 111 and a second substrate 112. The liquid crystal layer 300 may include liquid crystal 310 having dielectric anisotropy. When a data voltage is applied to the first pixel electrode PXE1 and a common voltage Vcom is applied to the common electrode CE, an electric field can be formed between the first pixel electrode PXE1 and the common electrode CE. The arrangement of the liquid crystal 310 in the liquid crystal layer 300 can be changed according to the electric field applied between the first pixel electrode PXE1 and the common electrode CE, thereby controlling the transmittance of light passing through the first sub-pixel SP1.

[0183] Specifically, when an electric field is formed between the first pixel electrode PXE1 and the common electrode CE, the liquid crystal 310 can rotate in a specific direction, thereby adjusting the phase retardation value of the light passing through the liquid crystal layer 300. The amount by which the phase retardation value changes due to the rotation of the liquid crystal 310 determines the amount of light that passes through the lower polarizing film disposed on the lower surface of the first substrate 111 and then through the upper polarizing film disposed on the upper surface of the second substrate 112. Therefore, the transmittance of light passing through the first sub-pixel SP1 can be controlled.

[0184] The cross-sectional structure of the second sub-pixel SP2 can be referenced above. Figure 8 The cross-sectional structure of the first sub-pixel SP1 is basically the same, so its description will be omitted.

[0185] Figures 9 to 11 It shows in detail Figure 8 An enlarged layout diagram of the first switching element T1, the first source connection SCE1, and the first storage electrode STE1 of the first sub-pixel SP1.

[0186] exist Figure 9 In this configuration, the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 are precisely aligned. Figure 10 In the middle, the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 are shifted to the left. Figure 11 In the middle, the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 are shifted to the right.

[0187] Reference Figures 9 to 11 The first source electrode SE1 can extend along a second direction (Y-axis direction) in the region superimposed with the first active layer ACT1. The first drain electrode DE1 can extend along the second direction (Y-axis direction) in the region superimposed with the first active layer ACT1. The first source electrode SE1 and the first drain electrode DE1 on the first active layer ACT1 can be separated from each other in a first direction (X-axis direction). The first active layer ACT1 between the first source electrode SE1 and the first drain electrode DE1 in the first direction (X-axis direction) can be defined as a first channel region CH1.

[0188] The length of the first active layer ACT1 in the second direction (Y-axis direction) can be defined as the channel width CW of the first channel region CH1. The length between the first source electrode SE1 and the first drain electrode DE1 in the first direction (X-axis direction) can be defined as the channel length CL.

[0189] Since the first source electrode SE1 is stacked with the first scan line SL1, a parasitic capacitance is formed between the first source electrode SE1 and the first scan line SL1. Due to this parasitic capacitance, the first source electrode SE1 is affected by changes in the voltage of the first scan line SL1. For example, when the scan signal of the first scan line SL1 changes from the gate on voltage to the gate off voltage, the voltage of the first source electrode SE1 can be changed by the backflush voltage ΔVp. The backflush voltage ΔVp can be defined as in equation (1).

[0190]

[0191] In equation (1), ΔVp can be the recoil voltage, Cgs can be the parasitic capacitance between the first gate electrode GE1 and the first source electrode SE1, CAlc1 can be the capacitance of the first liquid crystal capacitor Clc1, CAst1 can be the capacitance of the first storage capacitor Cst1, Von can be the gate on voltage level of the scan signal transmitted to the first scan line SL1, and Voff can be the gate off voltage level of the scan signal transmitted to the first scan line SL1.

[0192] The region where parasitic capacitance is formed between the first source electrode SE1 and the first scan line SL1 may include a first conducting superimposed region CON, a first cutoff superimposed region COF1, and a second cutoff superimposed region COF2.

[0193] The first conduction overlay region CON refers to the region of parasitic capacitance formed between the first active layer ACT1 and the first scan line SL1 when the first channel region CH1 of the first switching element T1 is activated by the gate conduction voltage applied to the first scan line SL1. The first conduction overlay region CON may include the overlay region between the first source electrode SE1 and the first active layer ACT1, a region extending from the first side of the first source electrode SE1 facing the first drain electrode DE1 to half the channel length CL of the first channel region CH1, and a region extending from the second side of the first source electrode SE1 opposite to the first side to the end of the first active layer ACT1.

[0194] The first cutoff overlay region COF1 and the second cutoff overlay region COF2 refer to the regions of parasitic capacitance formed between the first source electrode SE1 and the first scan line SL1 when the first channel region CH1 of the first switching element T1 is activated and deactivated. The first cutoff overlay region COF1 is the region where the first source electrode SE1 and the first scan line SL1 face each other, and can be defined as a region located outside the lower side of the first active layer ACT1. The second cutoff overlay region COF2 is the region where the first source electrode SE1 and the first scan line SL1 face each other, and can be defined as a region located outside the upper side of the first active layer ACT1.

[0195] When the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 are misaligned during the manufacturing of the display panel 110, as... Figure 10 As shown, when shifting left, the first conduction overlay region CON is increased. Specifically, as... Figure 10 As shown, with Figure 9 Compared to the distance D1 shown, the distance D2 from the second side of the first source electrode SE1 opposite to the first side to the end of the first active layer ACT1 will increase. Therefore, the parasitic capacitance formed between the first source electrode SE1 and the first scan line SL1 will increase due to the increase in the first conduction stacked region CON. On the other hand, since the lower end of the first source electrode SE1 protrudes further than the lower end of the first gate electrode GE1, the first cutoff stacked region COF1 can be maintained as is. The second cutoff stacked region COF2 can also be maintained as is.

[0196] Additionally, when the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 are misaligned during the manufacturing of the display panel 110, as... Figure 11 As shown, shifting to the right can reduce the first conduction overlay region CON. Specifically, as... Figure 11 As shown, with Figure 9 Compared to the distance D1 shown, the distance D3 from the second side of the first source electrode SE1 opposite to the first side to the end of the first active layer ACT1 can be reduced. Therefore, the parasitic capacitance formed between the first source electrode SE1 and the first scan line SL1 can be reduced. On the other hand, since the lower end of the first source electrode SE1 protrudes further than the lower end of the first gate electrode GE1, the first cutoff stacking region COF1 can be maintained as is. The second cutoff stacking region COF2 can also be maintained as is.

[0197] like Figures 9 to 11 As shown, when the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 shift to the left or right due to misalignment during the manufacturing of the display panel 110, the first conduction stacking region CON changes, thereby changing the parasitic capacitance formed between the first source electrode SE1 and the first scan line SL1. Therefore, the recoil voltage ΔVp affecting the voltage of the first source electrode SE1 changes. Referring to equation (1), when the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 shift to the left, the parasitic capacitance between the first gate electrode GE1 and the first source electrode SE1 increases, thereby increasing the recoil voltage ΔVp. Conversely, when the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 shift to the right, the parasitic capacitance between the first gate electrode GE1 and the first source electrode SE1 decreases, thereby decreasing the recoil voltage ΔVp.

[0198] Here, the left end of the first storage electrode STE1 can protrude further than the left end of the first source connection SCE1 in the first direction (X-axis direction), and the right end of the first source connection SCE1 can protrude further than the right end of the first storage electrode STE1 in the first direction (X-axis direction). Therefore, when the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 are as follows... Figure 10 When shifted to the left as described above, the overlapping area between the first storage electrode STE1 and the first source connection SCE1 can be increased. Figure 10 The length W1' of the overlapping region between the first storage electrode STE1 and the first source connection SCE1 in the first direction (X-axis direction) can be greater than... Figure 9 The length W1 shown is large. For example... Figure 9 and Figure 10 As shown, the length W2 of the overlapping region between the first storage electrode STE1 and the first source connection SCE1 in the second direction (Y-axis direction) can remain substantially unchanged.

[0199] Therefore, the capacitance of the first storage capacitor Cst1 can be increased. That is, when the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 are as follows: Figure 10 When shifting to the left as shown, the capacitance of the first storage capacitor Cst1 can be increased due to the increase in the overlapping area between the first storage electrode STE1 and the first source connection SCE1. Referring to equation (1), when the capacitance of the first storage capacitor Cst1 increases, the recoil voltage ΔVp affecting the voltage of the first source electrode SE1 can be reduced. Therefore, even if the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 are as shown, the voltage of the first source electrode SE1 can be reduced. Figure 10 As shown, the change in recoil voltage ΔVp when shifted to the left can also be insignificant.

[0200] Additionally, when the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 are as follows: Figure 11 As shown, shifting to the right reduces the overlap area between the first storage electrode STE1 and the first source connection SCE1. Specifically, Figure 11 The length W1” of the overlapping region between the first storage electrode STE1 and the first source connection SCE1 in the first direction (X-axis direction) can be greater than Figure 9 The length W1 shown is small. For example... Figure 9 and Figure 11 As shown, the length W2 of the overlapping region between the first storage electrode STE1 and the first source connection SCE1 in the second direction (Y-axis direction) can remain substantially unchanged.

[0201] Therefore, the capacitance of the first storage capacitor Cst1 can be reduced. That is, when the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 are as follows: Figure 11 When shifted to the right as shown, the capacitance of the first storage capacitor Cst1 can be reduced by decreasing the overlapping area between the first storage electrode STE1 and the first source connection SCE1. Therefore, even if the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 are as shown... Figure 11 As shown, the change in recoil voltage ΔVp when shifted to the right can also be insignificant.

[0202] Since the parasitic capacitance Cgs is not large, in order to prevent the capacitance of the first storage capacitor Cst from changing too much due to the displacement of the first source electrode SE1, the first drain electrode DE1 and the first source connection SCE1, the length W2 of the overlapping area between the first storage electrode STE1 and the first source connection SCE1 in the second direction (Y-axis direction) can be larger than the length W1, W1' or W1” in the first direction (X-axis direction) regardless of the displacement of the first source electrode SE1, the first drain electrode DE1 and the first source connection SCE1.

[0203] like Figures 9 to 11 As shown, even if the parasitic capacitance Cgs changes due to misalignment during the manufacturing process caused by the displacement of the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1, the change in the recoil voltage ΔVp affecting the first source electrode SE1 can be prevented by changing the capacitance of the first storage capacitor Cst1.

[0204] When the area of ​​the first channel region CH1 is reduced, the parasitic capacitance Cgs formed between the first source electrode SE1 and the first scan line SL1 can be reduced. For example, the channel length CL of the first channel region CH1 can be 4.3 μm or less, and the channel width CW can be 10 μm or less. When the channel length CL of the first channel region CH1 is less than 2.5 μm or when the channel width CW is less than 5 μm, the processing difficulty increases, thereby increasing process dispersion. Therefore, the uniformity of the channel length CL and channel width CW of the first channel region CH1 is reduced. Therefore, the channel length CL of the first channel region CH1 can be from 2.5 μm to 4.3 μm, and the channel width CW can be from 5 μm to 10 μm.

[0205] Furthermore, as the linewidth LW of the first source electrode SE1 increases, the first conductive overlap region CON formed between the first source electrode SE1 and the first scan line SL1 decreases, thereby reducing the parasitic capacitance Cgs. For example, the linewidth LW of the first source electrode SE1 can be approximately 3.5 μm or greater. However, when the linewidth LW of the first source electrode SE1 is 7 μm or greater, the first cutoff overlap region COF1 and the second cutoff overlap region COF2 increase the parasitic capacitance Cgs, thereby increasing the parasitic capacitance Cgs. Therefore, the linewidth LW of the first source electrode SE1 can be from 3.5 μm to 7 μm.

[0206] The second storage electrode STE2, the second source connection SCE2, the channel length of the second channel region CH2, the channel width of the second channel region CH2, and the linewidth of the second source electrode SE2 are as described above. Figures 9 to 11 The first storage electrode STE1, the first source connection SCE1, the channel length CL of the first channel region CH1, the channel width CW of the first channel region CH1, and the linewidth LW of the first source electrode SE1 are basically the same, therefore, their descriptions will be omitted.

[0207] Figure 12 and Figure 13 It shows Figure 6 The layout diagram shows an example of the sub-pixels SP1 and SP2 of the display panel 110 and the light-blocking member.

[0208] Reference Figure 12 The first light-blocking member BM1 can be stacked with the first switching element T1, the first source connection portion SCE1, the first pixel electrode connection portion PCE1, and the first contact hole CNT1 of the first sub-pixel SP1. The first horizontal trunk PHSE1, the first vertical trunk PVSE1, and the multiple first branches PBE1 disposed in the four domains DM1 to DM4 of the first pixel electrode PXE1 can be exposed and not covered by the first light-blocking member BM1. Therefore, the arrangement of the liquid crystal 310 of the liquid crystal layer 300 disposed between the first pixel electrode PXE1 and the common electrode CE can be changed by the electric field between the first pixel electrode PXE1 and the common electrode CE.

[0209] Furthermore, the first light-blocking member BM1 can be stacked with the second switching element T2, the second source connection portion SCE2, the second pixel electrode connection portion PCE2, and the second contact hole CNT2 of the second sub-pixel SP2. The second horizontal trunk PHSE2, the second vertical trunk PVSE2, and the multiple second branches PBE2 disposed in the four domains DM1 to DM4 of the second pixel electrode PXE2 can be exposed without being covered by the first light-blocking member BM1. Therefore, the arrangement of the liquid crystal 310 of the liquid crystal layer 300 disposed between the second pixel electrode PXE2 and the common electrode CE can be changed by the electric field between the second pixel electrode PXE2 and the common electrode CE.

[0210] like Figure 12 As shown, the first light-blocking member BM1 can be disposed between the lower side of the first vertical backbone PVSE1 of the first pixel electrode PXE1 and the upper side of the second vertical backbone PVSE2 of the second pixel electrode PXE2. Figure 13 As shown, the first light-blocking member BM1 can cover the lower portion of the first vertical trunk PVSE1 of the first pixel electrode PXE1 and the upper portion of the second vertical trunk PVSE2 of the second pixel electrode PXE2. In this case, the first source connection portion SCE1 and the first branch PBE1 provided in each of the second domain DM2 and the fourth domain DM4 of the first pixel electrode PXE1 can be covered by the first light-blocking member BM1. In addition, the second source connection portion SCE2 and the second branch PBE2 provided in each of the first domain DM1 and the third domain DM3 of the second pixel electrode PXE2 can be covered by the first light-blocking member BM1. The length of the first light-blocking member BM1 in the second direction (Y-axis direction) can be approximately 60 μm to 100 μm.

[0211] Figure 14 It shows Figure 6 The layout diagram shows an example of the sub-pixels SP1 and SP2 of the display panel 110 and the light-blocking member.

[0212] Figure 14 Implementation examples and Figure 13 The difference in the embodiment is that the second light-blocking member BM2 is added between the upper side of the first pixel electrode PXE1 and the lower side of the second pixel electrode PXE2.

[0213] Reference Figure 14 The second light-blocking member BM2 can cover the upper portion of the first vertical backbone PVSE1 of the first pixel electrode PXE1 and the lower portion of the second vertical backbone PVSE2 of the second pixel electrode PXE2. In this case, as... Figure 14As shown, the first branch PBE1 in each of the first domain DM1 and the third domain DM3 of the first pixel electrode PXE1 can be covered by the second light-blocking member BM2. Additionally, as... Figure 14 As shown, the second branch PBE2 in each of the second domain DM2 and the fourth domain DM4 of the second pixel electrode PXE2 can be covered by the second light-blocking member BM2.

[0214] The length of the second light-blocking component BM2 in the second direction (Y-axis direction) can be smaller than the length of the first light-blocking component BM1 in the second direction (Y-axis direction). For example, the length of the second light-blocking component BM2 in the second direction (Y-axis direction) can be between 10 μm and 40 μm. When the length of the second light-blocking component BM2 in the second direction (Y-axis direction) is less than 10 μm, it increases the manufacturing difficulty and thus increases process dispersion. Therefore, it reduces the uniformity of the length of the second light-blocking component BM2 in the second direction (Y-axis direction). In addition, when the length of the second light-blocking component BM2 in the second direction (Y-axis direction) is greater than 40 μm, it reduces the opening area of ​​the first sub-pixel SP1 and the opening area of ​​the second sub-pixel SP2, thereby reducing the light transmittance of the first sub-pixel SP1 and the second sub-pixel SP2.

[0215] Figure 15 This is a layout diagram showing the sub-pixels SP1 and SP2 of the display panel 110 according to an embodiment. Figure 16 It shows in detail Figure 15 An enlarged layout diagram of the first switching element T1 and the first contact hole CNT1 of the first sub-pixel SP1, and the second switching element T2 and the second contact hole CNT2 of the second sub-pixel SP2.

[0216] For ease of description, in Figure 15 Only sub-pixels SP1 and SP2, connected to the first scan line SL1 and the first data lines DL1 to the sixth data lines DL6, are shown. Figure 15 and Figure 16 For ease of description, this section will primarily focus on the first sub-pixel SP1 connected to the first scan line SL1 and the first data line DL1, and the second sub-pixel SP2 connected to the first scan line SL1 and the second data line DL2. Additionally, in Figure 15 and Figure 16 In the first switching element T1, the first electrode is the first drain electrode DE1, and the second electrode is the first source electrode SE1.

[0217] Reference Figure 15 and Figure 16 The first sub-pixel SP1 may include a first switching element T1, a first pixel electrode PXE1, a first source connection SCE1, a first storage electrode STE1, and a first storage line STL1.

[0218] The first switching element T1 may include a first gate electrode GE1 connected to a first scan line SL1, a first source electrode SE1 connected to a first source connection SCE1, a first drain electrode DE1 connected to a first data line DL1, and a first active layer ACT1 superimposed on the first gate electrode GE1.

[0219] Apart from the first gate electrode GE1 and the first drain electrode DE1, the first switching element T1 can be referenced above. Figure 6 The first switching element T1 described is essentially the same.

[0220] The first gate electrode GE1 may be a portion of the first scan line SL1. For example, the first gate electrode GE1 may be defined as the region of the first scan line SL1 that overlaps with the first active layer ACT1.

[0221] The first drain electrode DE1 may include a first protrusion PP1 protruding from the first data line DL1 in a first direction (X-axis direction) and a first extension EP1 extending from the first protrusion PP1 in a second direction (Y-axis direction). The first extension EP1 may protrude from the end of the first protrusion PP1 in the second direction (Y-axis direction). The first extension EP1 may protrude toward the first pixel electrode PXE1 and the second pixel electrode PXE2. The first protrusion PP1 may extend in the first direction (X-axis direction), and the first extension EP1 may extend in the second direction (Y-axis direction).

[0222] The first extension EP1 can be separated from the first source electrode SE1 in a first direction (X-axis direction). The first extension EP1 and the first source electrode SE1 can be disposed in the first direction (X-axis direction). The first source electrode SE1 and the first extension EP1 can extend along a second direction (Y-axis direction) in the region superimposed with the first active layer ACT1. The region between the first extension EP1 and the first source electrode SE1 in the first direction (X-axis direction) can be defined as the first channel region CH1 of the first switching element T1.

[0223] The first source connection SCE1 is referenced above. Figure 6 The first source connection SCE1 described is essentially the same, so its description will be omitted.

[0224] The first storage electrode STE1 may protrude from the third sub-storage line STL13 of the first storage line STL1 in the second direction (Y-axis direction). The first storage electrode STE1 may protrude toward the second pixel electrode PXE2, but this disclosure is not limited thereto. The first storage electrode STE1 may also protrude toward the first pixel electrode PXE1. The first storage electrode STE1 may be stacked with the first source connection portion SCE1. The first storage electrode STE1 and the first source connection portion SCE1 may form a first storage capacitor Cst1.

[0225] The left end of the first storage electrode STE1 can protrude further than the left end of the first source connection SCE1 in the first direction (X-axis direction), and the right end of the first source connection SCE1 can protrude further than the right end of the first storage electrode STE1 in the first direction (X-axis direction). Therefore, even if the parasitic capacitance Cgs passes through the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 due to... Figures 9 to 11 The misalignment in the manufacturing process described herein, which causes a shift to the left or right, can also prevent changes in the recoil voltage ΔVp of the first source electrode SE1.

[0226] The first pixel electrode PXE1 is referenced above. Figure 4 The first pixel electrode PXE1 described is essentially the same, therefore its description will be omitted. Except that the first memory line STL1 does not include the fourth sub-memory line STL14, the first memory line STL1 is identical to the one described above. Figure 4 The first memory line STL1 is essentially the same as described, so its description will be omitted.

[0227] The second sub-pixel SP2 may include a second switching element T2, a second pixel electrode PXE2, a second source connection SCE2, a second storage electrode STE2, and a second storage line STL2.

[0228] The second switching element T2 may include a second gate electrode GE2 connected to the first scan line SL1, a second source electrode SE2 connected to the second source connection SCE2, a second drain electrode DE2 connected to the second data line DL2, and a second active layer ACT2 superimposed on the second gate electrode GE2.

[0229] In addition to the second gate electrode GE2 and the second drain electrode DE2, the second switching element T2 can be referenced above. Figure 6 The second switching element T2 described is essentially the same.

[0230] The second gate electrode GE2 can be a portion of the first scan line SL1. For example, the second gate electrode GE2 can be defined as the region of the first scan line SL1 that overlaps with the second active layer ACT2.

[0231] The second drain electrode DE2 may include a second protrusion PP2 protruding from the second data line DL2 in a first direction (X-axis direction) and a second extension EP2 extending from the second protrusion PP2 in a second direction (Y-axis direction). The second extension EP2 may protrude from the end of the second protrusion PP2 in the second direction (Y-axis direction). The second extension EP2 may protrude toward the first pixel electrode PXE1 and the second pixel electrode PXE2. The second protrusion PP2 may extend in the first direction (X-axis direction), and the second extension EP2 may extend in the second direction (Y-axis direction).

[0232] The second extension EP2 can be separated from the second source electrode SE2 in the first direction (X-axis direction). The second extension EP2 and the second source electrode SE2 can be disposed in the first direction (X-axis direction). The second source electrode SE2 and the second extension EP2 can extend along the second direction (Y-axis direction) in the region superimposed with the second active layer ACT2. The region between the second extension EP2 and the second source electrode SE2 in the first direction (X-axis direction) can be defined as the second channel region CH2 of the second switching element T2.

[0233] The first extension EP1 of the first drain electrode DE1, the first source electrode SE1, the second source electrode SE2, and the second extension EP2 of the second drain electrode DE2 can be arranged in the first direction (X-axis direction).

[0234] The second source connection SCE2 is referenced above. Figure 6 The second source connection SCE2 is basically the same as described, so its description will be omitted.

[0235] The second storage electrode STE2 may protrude from the third sub-storage line STL23 of the second storage line STL2 in the second direction (Y-axis direction). The second storage electrode STE2 may protrude toward the first pixel electrode PXE1, but this disclosure is not limited thereto. The second storage electrode STE2 may also protrude toward the second pixel electrode PXE2. The second storage electrode STE2 may be stacked with the second source connection portion SCE2. The second storage electrode STE2 and the second source connection portion SCE2 may form a second storage capacitor Cst2.

[0236] The right end of the second storage electrode STE2 can protrude further than the right end of the second source connection SCE2 in the first direction (X-axis direction), and the left end of the second source connection SCE2 can protrude further than the left end of the second storage electrode STE2 in the first direction (X-axis direction). Therefore, even if the parasitic capacitance Cgs passes through the second source electrode SE2, the second drain electrode DE2, and the second source connection SCE2 due to... Figures 9 to 11The misalignment in the manufacturing process described herein, which causes a leftward or rightward shift, can also be altered by changing the capacitance of the second storage capacitor Cst2 to prevent changes in the recoil voltage ΔVp of the second source electrode SE2.

[0237] In addition to the second pixel electrode connection portion PCE2 and the second source electrode connection portion SCE2 being stacked, the second pixel electrode PXE2 and Figure 4 The first pixel electrode PXE1 is essentially the same, so its description will be omitted. Additionally, except that the second memory line STL2 does not include the fourth sub-memory line STL24, the second memory line STL2 is... Figure 4 The first memory line STL1 is essentially the same, so its description will be omitted.

[0238] Shielded cable SHL (not shown) and reference above Figure 6 The shielded cable SHL is essentially the same, so its description will be omitted.

[0239] In the first sub-pixel SP1 and the second sub-pixel SP2, the first data line DL1 intersects with the third sub-storage line STL13 of the first storage line STL1, the first sub-scan line SL11 and the second sub-scan line SL12 of the first scan line SL1, and the third sub-storage line STL23 of the second storage line STL2. That is, in the first sub-pixel SP1 and the second sub-pixel SP2, the first data line DL1 intersects with four lines. Therefore, with... Figure 4 Compared to the embodiments shown, in Figure 15 In the illustrated embodiment, the number of intersections between the first data line DL1 and the memory lines STL1 and STL2 can be reduced. Therefore, short circuits between the first data line DL1 and the memory lines STL1 and STL2 caused by particles can be reduced, thereby increasing the manufacturing yield of the display panel.

[0240] like Figure 16 As shown, the first switching element T1 and the first contact hole CNT1 can be arranged in the second direction (Y-axis direction), and the second switching element T2 and the second contact hole CNT2 can be arranged in the second direction (Y-axis direction). For example, the first active layer ACT1 and the first contact hole CNT1 of the first switching element T1 can be arranged in the second direction (Y-axis direction). The second active layer ACT2 and the second contact hole CNT2 of the second switching element T2 can be arranged in the second direction (Y-axis direction).

[0241] Furthermore, the first switching element T1 and the second switching element T2 can be disposed in a first direction (X-axis direction). The first switching element T1 and the second switching element T2 can also be disposed in a second direction (Y-axis direction) between the first contact hole CNT1 and the second contact hole CNT2. For example, the first active layer ACT1 of the first switching element T1 and the second active layer ACT2 of the second switching element T2 can be disposed in the second direction (Y-axis direction) between the first contact hole CNT1 and the second contact hole CNT2.

[0242] Furthermore, the first pixel electrode PXE1 and the second pixel electrode PXE2 can be set in the second direction (Y-axis direction).

[0243] In this scenario, if either the first switching element T1 or the second switching element T2 is determined to be defective, it can be easily repaired. For example, when the first switching element T1 is defective, the electrical connection between the first source electrode SE1 and the first pixel electrode PXE1 of the first switching element T1 can be cut using a laser, and a pixel connection electrode connecting the first pixel electrode PXE1 and the second pixel electrode PXE2 can be added using an inkjet process. In this case, the inkjet process can be simple because the pixel connection electrode only needs to extend in the second direction (Y-axis direction).

[0244] Alternatively, when the second switching element T2 is defective, the electrical connection between the second source electrode SE2 and the second pixel electrode PXE2 of the second switching element T2 can be cut using a laser, and a pixel connection electrode connecting the first pixel electrode PXE1 and the second pixel electrode PXE2 can be added using an inkjet process. In this case, since the pixel connection electrode only needs to extend in the second direction (Y-axis direction), the inkjet process can be simple.

[0245] Figure 17 This is a layout diagram showing the sub-pixels SP1 and SP2 of the display panel 110 according to an embodiment. Figure 18 It shows in detail Figure 17 An enlarged layout diagram of the first switching element T1 and the first contact hole CNT1 of the first sub-pixel SP1, and the second switching element T2 and the second contact hole CNT2 of the second sub-pixel SP2.

[0246] For ease of description, in Figure 17 Only sub-pixels SP1 and SP2, connected to the first scan line SL1 and the first data lines DL1 to the sixth data lines DL6, are shown. Figure 17 and Figure 18For ease of description, this section will primarily focus on the first sub-pixel SP1 connected to the first scan line SL1 and the first data line DL1, and the second sub-pixel SP2 connected to the first scan line SL1 and the second data line DL2. Additionally, in Figure 17 and Figure 18 In the first switching element T1, the first electrode is the first drain electrode DE1, and the second electrode is the first source electrode SE1.

[0247] Reference Figure 17 and Figure 18 The first sub-pixel SP1 may include a first switching element T1, a first pixel electrode PXE1, a first source connection SCE1, a first storage electrode STE1, and a first storage line STL1.

[0248] The first switching element T1 may include a first gate electrode GE1 connected to a first scan line SL1, a first source electrode SE1 connected to a first source connection SCE1, a first drain electrode DE1 connected to a first data line DL1, and a first active layer ACT1 superimposed on the first gate electrode GE1.

[0249] The first gate electrode GE1 can protrude from the first scan line SL1 in the second direction (Y-axis direction). The first gate electrode GE1 can protrude from the first scan line SL1 toward the first pixel electrode PXE1.

[0250] The first active layer ACT1 can be stacked not only with the first gate electrode GE1, but also with the first source electrode SE1 and the first drain electrode DE1. The first active layer ACT1 can have a quadrilateral planar shape, but this disclosure is not limited thereto.

[0251] The first source electrode SE1 may protrude from the first source connection portion SCE1 in a first direction (X-axis direction). The first source electrode SE1 may protrude from the first source connection portion SCE1 toward the first data line DL1. The first source electrode SE1 may extend in the first direction (X-axis direction).

[0252] The first drain electrode DE1 may protrude from the first data line DL1 in a first direction (X-axis direction). The first drain electrode DE1 may protrude from the first data line DL1 toward the second data line DL2. The first drain electrode DE1 may extend in the first direction (X-axis direction).

[0253] The first source electrode SE1 and the first drain electrode DE1 can extend along a first direction (X-axis direction) in the region superimposed with the first active layer ACT1. The region between the first source electrode SE1 and the first drain electrode DE1 in a second direction (Y-axis direction) can be defined as the first channel region CH1 of the first switching element T1.

[0254] The first source connection SCE1 and the first storage electrode STE1 are referenced above. Figure 6 The first source connection SCE1 and the first storage electrode STE1 are substantially the same, so their description will be omitted.

[0255] The lower end of the first storage electrode STE1 can protrude further than the lower end of the first source connection SCE1 in the second direction (Y-axis direction), and the upper end of the first source connection SCE1 can protrude further than the upper end of the first storage electrode STE1 in the second direction (Y-axis direction). Therefore, even if the parasitic capacitance Cgs passes through the first source electrode SE1, the first drain electrode DE1, and the first source connection SCE1 due to its relationship with... Figures 9 to 11 The description is similar to the misalignment in the manufacturing process that causes upward or downward shift, which can also be changed by changing the capacitance of the first storage capacitor Cst1 to prevent changes that affect the recoil voltage ΔVp of the first source electrode SE1.

[0256] The first pixel electrode PXE1 is referenced above. Figure 4 The first pixel electrode PXE1 described is essentially the same, therefore its description will be omitted. Except that the first memory line STL1 does not include the fourth sub-memory line STL14, the first memory line STL1 is identical to the one described above. Figure 4 The first memory line STL1 is essentially the same as described, so its description will be omitted.

[0257] The second sub-pixel SP2 may include a second switching element T2, a second pixel electrode PXE2, a second source connection SCE2, a second storage electrode STE2, and a second storage line STL2.

[0258] The second switching element T2 may include a second gate electrode GE2 connected to the first scan line SL1, a second source electrode SE2 connected to the second source connection SCE2, a second drain electrode DE2 connected to the second data line DL2, and a second active layer ACT2 superimposed on the second gate electrode GE2.

[0259] The second gate electrode GE2 can protrude from the first scan line SL1 in the second direction (Y-axis direction). The second gate electrode GE2 can protrude from the first scan line SL1 toward the second pixel electrode PXE2.

[0260] The second active layer ACT2 can be stacked not only with the second gate electrode GE2, but also with the second source electrode SE2 and the second drain electrode DE2. The second active layer ACT2 can have a quadrilateral planar shape, but this disclosure is not limited thereto.

[0261] The second source electrode SE2 may protrude from the second source connection portion SCE2 in the first direction (X-axis direction). The second source electrode SE2 may protrude from the second source connection portion SCE2 toward the second data line DL2. The second source electrode SE2 may extend in the first direction (X-axis direction).

[0262] The second drain electrode DE2 may protrude from the second data line DL2 in the first direction (X-axis direction). The second drain electrode DE2 may protrude from the second data line DL2 toward the first data line DL1. The second drain electrode DE2 may extend in the first direction (X-axis direction).

[0263] The second source electrode SE2 and the second drain electrode DE2 can extend along a first direction (X-axis direction) in the region superimposed with the second active layer ACT2. The region between the second source electrode SE2 and the second drain electrode DE2 in a second direction (Y-axis direction) can be defined as the second channel region CH2 of the second switching element T2.

[0264] The second source connection SCE2 and the second storage electrode STE2 are referenced above. Figure 6 The second source connection SCE2 and the second storage electrode STE2 are basically the same, so their description will be omitted.

[0265] The upper end of the second storage electrode STE2 can protrude further than the upper end of the second source connection SCE2 in the second direction (Y-axis direction), and the lower end of the second source connection SCE2 can protrude further than the lower end of the second storage electrode STE2 in the second direction (Y-axis direction). Therefore, even if the parasitic capacitance Cgs passes through the second source electrode SE2, the second drain electrode DE2, and the second source connection SCE2 due to its relationship with... Figures 9 to 11 The description is similar to the misalignment in the manufacturing process that causes upward or downward shift, which can also be changed by changing the capacitance of the second storage capacitor Cst2 to prevent changes in the recoil voltage ΔVp of the second source electrode SE2.

[0266] In addition to the second pixel electrode connection portion PCE2 and the second source electrode connection portion SCE2 being stacked, the second pixel electrode PXE2 and Figure 4 The first pixel electrode PXE1 is essentially the same, so its description will be omitted. Additionally, except that the second memory line STL2 does not include the fourth sub-memory line STL24, the second memory line STL2 is... Figure 4 The first memory line STL1 is essentially the same, so its description will be omitted.

[0267] Shielded SHL cable and reference above Figure 7 The shielded cable SHL is essentially the same, so its description will be omitted.

[0268] In the first sub-pixel SP1 and the second sub-pixel SP2, the first data line DL1 intersects with the third sub-storage line STL13 of the first storage line STL1, the first sub-scan line SL11 (not shown) and the second sub-scan line SL12 (not shown) of the first scan line SL1, and the third sub-storage line STL23 of the second storage line STL2. That is, in the first sub-pixel SP1 and the second sub-pixel SP2, the first data line DL1 intersects with four lines. Therefore, with... Figure 4 Compared to the embodiments shown, in Figure 17 In the illustrated embodiment, the number of intersections between the first data line DL1 and the memory lines STL1 and STL2 can be reduced. Therefore, short circuits between the first data line DL1 and the memory lines STL1 and STL2 caused by particles can be reduced, thereby increasing the manufacturing yield of the display panel.

[0269] like Figure 18 As shown, the first switching element T1 and the first contact hole CNT1 can be arranged in the first direction (X-axis direction), and the second switching element T2 and the second contact hole CNT2 can be arranged in the first direction (X-axis direction). For example, at least any one of the first active layer ACT1 and the first drain electrode DE1 of the first switching element T1, as well as the first contact hole CNT1, can be arranged in the first direction (X-axis direction). At least any one of the second active layer ACT2 and the second drain electrode DE2 of the second switching element T2, as well as the second contact hole CNT2, can be arranged in the first direction (X-axis direction).

[0270] Additionally, the first switching element T1 and the second contact hole CNT2 can be arranged in the second direction (Y-axis direction). For example, at least any one of the first active layer ACT1, the first source electrode SE1 and the first drain electrode DE1 of the first switching element T1, and the second contact hole CNT2 can be arranged in the second direction (Y-axis direction). The second switching element T2 and the first contact hole CNT1 can also be arranged in the second direction (Y-axis direction). For example, at least any one of the second active layer ACT2, the second source electrode SE2 and the second drain electrode DE2 of the second switching element T2, and the first contact hole CNT1 can be arranged in the second direction (Y-axis direction).

[0271] Furthermore, the first pixel electrode PXE1 and the second pixel electrode PXE2 can be set in the second direction (Y-axis direction).

[0272] The present disclosure should not be construed as limiting itself to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0273] While the present disclosure has been specifically shown and described with reference to some embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made herein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. A display device, the display device comprising: Base; Scan lines are disposed on the substrate and extend along a first direction; A data cable is disposed on the substrate and extends along a second direction intersecting the first direction; The first switching element includes a first active layer, a first gate electrode connected to the first scan line in the scan line, a first drain electrode connected to the first data line in the data line, and a first source electrode facing the first drain electrode. The first pixel electrode is connected to the first source electrode of the first switching element; The second switching element includes a second active layer, a second gate electrode connected to the first scan line, a second drain electrode connected to a second data line in the data line, and a second source electrode facing the second drain electrode. The second pixel electrode is connected to the second source electrode of the second switching element; A first source electrode connection portion extends from the first source electrode and is connected to the first pixel electrode through a first contact hole; as well as The second source electrode connection portion extends from the second source electrode and is connected to the second pixel electrode through the second contact hole. The first pixel electrode and the second pixel electrode are disposed along the second direction, and the first source electrode and the first drain electrode extend along the second direction in the region overlapping with the first active layer of the first switching element. Wherein, the first switching element and the second contact hole are arranged along the first direction, and the second switching element and the first contact hole are arranged along the first direction, and The first switching element and the first contact hole are arranged along the second direction, and the second switching element and the second contact hole are also arranged along the second direction.

2. The display device according to claim 1, wherein, The first source electrode intersects the first gate electrode completely along the second direction.

3. The display device according to claim 1, further comprising: The first storage electrode is stacked with the first source electrode connection portion in the plan view. Wherein, one edge of the first storage electrode extending along the second direction protrudes further in the first direction than one edge of the first source connection extending along the second direction.

4. The display device according to claim 3, wherein, The other edge of the first source connection extending along the second direction protrudes further in the first direction than the other edge of the first storage electrode extending along the second direction.

5. The display device according to claim 3, wherein, The length of the overlapping region between the first storage electrode and the first source electrode connection portion along the second direction is greater than the length of the overlapping region along the first direction.

6. The display device according to claim 3, wherein, The first active layer and the first contact hole are disposed along the second direction.

7. The display device according to claim 3, wherein, The second source electrode and the second drain electrode extend along the second direction in the region where they overlap with the second active layer of the second switching element.

8. The display device according to claim 7, further comprising: The second storage electrode is stacked with the second source electrode connection portion in the plan view. The second active layer and the second contact hole are disposed along the second direction.

9. The display device according to claim 8, wherein, The first switching element and the second switching element are disposed between the first contact hole and the second contact hole along the second direction.

10. The display device according to claim 8, wherein, The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are arranged along the first direction.

11. The display device according to claim 1, wherein, The first gate electrode protrudes from the first scan line toward the second pixel electrode along the second direction, and the second gate electrode protrudes from the first scan line toward the first pixel electrode along the second direction.

12. A display device, the display device comprising: Base; Scan lines are disposed on the substrate and extend along a first direction; A data cable is disposed on the substrate and extends along a second direction intersecting the first direction; The first switching element includes a first active layer, a first gate electrode connected to the first scan line in the scan line, a first drain electrode connected to the first data line in the data line, and a first source electrode facing the first drain electrode. The first pixel electrode is connected to the first source electrode of the first switching element through the first contact hole; The second switching element includes a second active layer, a second gate electrode connected to the first scan line, a second drain electrode connected to a second data line in the data line, and a second source electrode facing the second drain electrode. as well as The second pixel electrode is connected to the second source electrode of the second switching element through the second contact hole. Wherein, the first switching element is stacked with the first contact hole in the second direction, and the second switching element is stacked with the second contact hole in the second direction. Wherein, the first switching element and the second contact hole are arranged along the first direction, and the second switching element and the first contact hole are arranged along the first direction, and The first switching element and the first contact hole are arranged along the second direction, and the second switching element and the second contact hole are also arranged along the second direction.

13. The display device according to claim 12, wherein, The first pixel electrode and the second pixel electrode are disposed along the second direction.

14. The display device according to claim 12, wherein, The first switching element and the second switching element are disposed between the first contact hole and the second contact hole along the second direction.

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