Microprocessor and method implemented in microprocessor

Abstract

The present invention provides a microprocessor and a method implemented in the microprocessor. In one embodiment, a microprocessor includes: a translation lookaside buffer (TLB) configured to indicate that a virtual page address corresponding to a physical page address of a memory page attempted to be accessed by a memory access instruction is not hit in the TLB; a first micro-operation corresponding to the first memory access instruction, and the first micro-operation is configured to initiate a first speculative table lookup based on the first virtual page address not being hit in the TLB; and a second micro-operation corresponding to the second memory access instruction, and the second micro-operation is configured to take over the current first speculative table lookup of the first micro-operation at the current processing stage of the first micro-operation based on a virtual page address and attributes that are earlier than the first micro-operation and also match the first virtual page address and attributes for the first memory access instruction.

Description

Technical Field

[0001] The present invention relates generally to microprocessors and, in particular, to a microprocessor that performs a page table walk in response to a translation lookaside buffer miss. Background Art

[0002] Many modern microprocessors support the concept of virtual memory. In a virtual memory system, the instructions of a program executed on a microprocessor refer to data using virtual addresses or linear addresses in the microprocessor's virtual address space. The microprocessor translates the virtual addresses into physical addresses used to access physical memory.

[0003] The usual virtual memory scheme supported by a microprocessor is a paged memory system. A paged memory system employs a paging mechanism for translating or mapping virtual addresses to physical addresses. The physical address space is divided into physical pages of fixed size. A typical page size is 4KB. A virtual address includes a virtual page address portion and a page offset portion. The virtual page address specifies a virtual page (e.g., 4KB) in the virtual address space. The paging mechanism of the microprocessor translates the virtual page address into a physical page address. This process is called page translation. The page offset specifies the physical offset in the virtual and physical pages (e.g., a virtual or physical offset relative to the virtual or physical page address).

[0004] The operating system determines which physical pages in the memory will be mapped to each virtual page, and maintains the page mapping information of the specified mapping. When the microprocessor encounters an instruction (such as a load or store instruction) for specifying a virtual address to access a location in the memory, the microprocessor translates the virtual address into a suitable physical address by using the page mapping information of the operating system. The operating system maintains page mapping information in the system memory. Therefore, the microprocessor reads appropriate page mapping information from the memory to translate the virtual address into a physical address. The page mapping information is generally arranged in layers to reduce its size, which requires the microprocessor to traverse the hierarchy by performing read operations at multiple levels of the hierarchy. For this reason, and because at least a portion of the page mapping information is generally referred to as a page table, the process of the microprocessor traversing the page mapping information to translate the virtual address into a physical address is generally referred to as a page table lookup, or simply referred to as a table lookup, or the table lookup mainly used in this article. More information about table lookups can be found in U.S. Patent 7,996,650 (hereinafter referred to as the 650 patent), the entire contents of which are incorporated herein by reference.

[0005] In the '650 patent, a translation lookaside buffer (TLB) is described as part of a mechanism to reduce the number of table lookups to system memory by caching page mapping information. When a microprocessor encounters a memory access instruction (e.g., a load or store instruction), the microprocessor provides the virtual address to the TLB, and the TLB performs a lookup of the virtual page address. If the virtual page address hits in the TLB, the TLB provides the corresponding translated physical page address and page characteristics, thereby avoiding the need for a table lookup. However, if the virtual page address does not hit in the TLB, the microprocessor must perform a table lookup.

[0006] With the foregoing background in mind, it is further noted that many microprocessors are superscalar. A superscalar microprocessor includes features such as having multiple execution units and having the ability to issue multiple instructions to the execution units in a single clock cycle. Additional capabilities of superscalar microprocessors include performing out-of-order execution (e.g., the microprocessor can execute out-of-order instructions specified by a program that includes the instructions) and performing speculative execution of instructions (e.g., the microprocessor executes instructions, or at least performs some actions specified by the instructions, before knowing with certainty whether the instructions will actually complete). Although the microprocessor can speculatively perform some actions specified by the instructions, the microprocessor is not architecturally permitted to update the architectural state of the system with the results of the instructions until the instruction is no longer speculative, i.e., until it is determined that the instruction will complete (corresponding to the earliest state of the machine).

[0007] The '650 patent improves the traditional approach to TLB misses that require table lookups. For example, for a traditional out-of-order microprocessor (which suffers from a TLB miss that requires a table lookup), the microprocessor serializes the table lookup with other unfinished program instructions. That is, the traditional microprocessor waits until all program instructions earlier than the initiator instruction (the instruction that causes the TLB miss) have exited before it performs a table lookup, and does not issue any program instructions for executing newer than the initiator instruction to the execution unit until it completes the table lookup. In the '650 patent, a microprocessor is described that performs a table lookup speculatively and serializes the table lookup only in the following cases: 1) the system memory access associated with the table lookup needs to be strictly ordered on the processor bus; 2) the processor needs to write to the system memory to update the page mapping information, thereby performing a table lookup; or 3) the system memory page that the table lookup will update the TLB is a global page. However, the table lookup can still be improved. Summary of the invention

[0008] In one embodiment, a microprocessor includes: a translation lookaside buffer, or TLB, configured to indicate that a virtual page address corresponding to a physical page address of a memory page attempted to be accessed by a memory access instruction is not hit in the TLB; a first micro-operation, corresponding to the first memory access instruction, and configured to initiate a first speculative table lookup based on the first virtual page address not being hit in the TLB; and a second micro-operation, corresponding to a second memory access instruction, and configured to take over the current speculative table lookup of the first micro-operation at a current processing stage of the first micro-operation based on the second micro-operation being earlier than the first micro-operation and also based on having a virtual page address and attributes that match the first virtual page address and attributes for the first memory access instruction.

[0009] By examining the following drawings and detailed description, other systems, methods, features and advantages of the present invention will be or will become apparent to those skilled in the art. All these additional systems, methods, features and advantages are intended to be included within this description, within the scope of the present invention, and protected by the following claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] With reference to the following drawings, various aspects of the present invention may be better understood. The components in the drawings are not necessarily drawn to scale, but emphasis is placed on clearly illustrating the principles of the present invention. In addition, in the drawings, the same reference numerals represent corresponding parts in multiple views.

[0011] Figure 1 is a block diagram illustrating an exemplary microprocessor implementing an embodiment of a table lookup takeover system.

[0012] Figure 2 is a flow chart of an embodiment of an exemplary table lookup takeover method.

[0013] Figure 3 is a flow chart illustrating an embodiment of another exemplary table lookup takeover method. DETAILED DESCRIPTION

[0014] Certain embodiments of a table lookup takeover system and method are disclosed that improve upon past speculative table lookup mechanisms by remedying some of the inefficiencies involved in implementing a machine earliest state for a strictly ordered scenario. In one embodiment, a table lookup takeover system enables a table lookup for an earlier memory access instruction (e.g., a store or load instruction) to assume or take over (e.g., assume or take over at a current stage of table lookup processing where a newer memory access instruction has arrived) an active speculative table lookup without restarting the table lookup. The takeover occurs under certain conditions, namely, that the respective memory access instructions corresponding to the respective table lookups point to the same virtual page address (e.g., the same virtual page) and that they match in their attributes, as further described below. By doing so, processing results obtained from speculative table lookups for newer memory access instructions are retained rather than discarded, while updating the machine earliest state if a strictly ordered scenario is encountered.

[0015] In short, the table lookup mechanism of the past was inefficient because if an earlier (but later dispatched into the pipeline) micro-op corresponding to a memory access instruction encounters a newer micro-op that is currently performing a table lookup, the newer micro-op is evicted and the earlier micro-op initiates its own, new speculative table lookup. In these cases, particularly when the work of the evicted micro-op is almost complete or may have been completed, the newer micro-op is evicted in favor of the earlier micro-op and a new table lookup is initiated, which results in the loss of the work already performed by the now evicted micro-op and is extremely inefficient. In contrast, certain embodiments of a table lookup takeover system phase out the micro-ops that are currently and speculatively performing table lookups, but take over the speculative table lookup processing at the current processing stage, rather than restarting the table lookup, thereby utilizing the work already performed by the now evicted micro-op during the table lookup processing.

[0016] Having summarized certain features of the table lookup takeover system of the present invention, reference will now be made in detail to the description of the table lookup takeover system as illustrated in the accompanying drawings. Although the table lookup takeover system will be described in conjunction with these drawings, it is not intended to be limited to the embodiments disclosed herein. That is, although the present invention is susceptible to various modifications and alternative forms, its specific embodiments are shown by way of example in the accompanying drawings and will be described herein in detail enough to be understood by those skilled in the art. However, it should be understood that the drawings and their detailed description are not intended to limit the present invention to the specific form disclosed. On the contrary, it is intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the present invention as defined by the appended claims. As used in this application, the word "may" is used in a permissive sense (i.e., meaning possible) rather than a mandatory sense (i.e., meaning must). Similarly, the word "include" means including but not limited to.

[0017] Various units, modules, circuits, logic, or other components may be described as being "configured to" perform one or more tasks. In such a context, "configured to" is a broad description of a structure, which generally means "having circuits or other physical structures that perform or are capable of performing one or more tasks during operation." The circuit may be a dedicated circuit, or a more general processing circuit that operates under the control of coded instructions. That is, when describing certain aspects or features of various implementations of the present invention, terms such as "unit", "module", "circuit", "logic", and "component" may be used herein. Those skilled in the art will understand that the corresponding features are implemented using a circuit, whether the circuit is a dedicated circuit or a more general circuit that operates under the control of micro-coded instructions.

[0018] In addition, the unit / module / circuit / logic / component can be configured to perform tasks even when the unit / module / circuit / logic / component is not currently in operation. The description of the unit / module / circuit / logic / component configured to perform one or more tasks is obviously not intended to functionally define the unit / module / circuit / logic / component. In this regard, it will be understood by those skilled in the art that the specific structure or interconnection of the circuit elements will generally be determined by the compiler of the design automation tool (such as the register transfer language (RTL) compiler). The RTL compiler runs on a script that is very similar to the assembly language code to compile the script into a form for the layout or manufacture of the final circuit.

[0019] That is, integrated circuits (such as those of the present invention) are designed using more advanced software tools to model the desired functional operation of the circuit. As is well known, "electronic design automation" (or EDA) is a class of software tools for designing electronic systems such as integrated circuits. EDA tools are also used to program design functions into field programmable gate arrays (FPGAs). A high-level representation of a circuit is created using hardware descriptor languages ​​(HDLs) such as Verilog and very high-speed integrated circuit hardware description languages ​​(VHDLs), from which lower-level representations and final actual wiring can be inferred. In fact, since modern semiconductor chips can have billions of components, EDA tools are considered essential for their design. In practice, circuit designers use programming languages ​​such as C / C++ to specify operating functions. EDA software tools translate the specified function into RTL. Then, the hardware descriptor language (e.g., Verilog) translates the RTL into a discrete netlist of gates. The netlist defines the actual circuit produced by, for example, a foundry. In fact, these tools are so well known and understood for their role and use in facilitating the design process of electronic and digital systems that they do not need to be described here.

[0020] Note that references to table lookups include terms with the same or similar functionality, including page table lookups or table lookups, etc., and include page table lookups for virtual or linear space. In addition, in some embodiments, the table lookup includes three steps. The first step is to read the necessary page mapping information required to translate the virtual address into a physical address from the memory and obtain the page characteristics. The second step is to update the page mapping information in the system memory (if necessary). The third step is to allocate a translation lookaside buffer (TLB) entry and update it with the new page mapping information. Note that references to handover and takeover are intended to express the same process.

[0021] Reference now Figure 1, a block diagram is shown, which shows a microprocessor 100 according to the present invention. The microprocessor 100 includes an instruction translator 102, a microcode 104, a rename / dispatch unit 106, a reorder buffer (ROB) 108, an execution unit 112, a retirement unit 114, a bus interface unit (BIU) 116, and a memory subsystem 118. The memory subsystem 118 includes a level (L1) instruction cache 122, an L1 data cache 124, a level (L2) cache 126, a translation lookaside buffer (TLB) 128, a load unit 132, a store unit 134, a load buffer 136, a store buffer 138, and a table lookup engine 142. In an embodiment, the load unit 132 and the store unit 134 are included in the execution unit 112. The BIU 116 connects the microprocessor 100 to a processor bus to which a system memory and other devices such as a system chipset are coupled. For example, the BIU 116 receives a load or store request that needs to bypass both the cache hierarchy and the write combine buffer (e.g., a load or store to an uncacheable memory, an MMIO device, a cacheable memory with a write-through feature, or an atomic read-modify-write sequence that spans two cache lines (a so-called split lock transaction). When the BIU 116 receives one of these load or store requests, it determines the final destination (e.g., DRAM, V4 interface, PCIe, etc.) and splits the request into multiple transactions if necessary. The operating system running on the microprocessor 100 stores page mapping information in the system memory, which the microprocessor 100 reads and writes to for table lookups, as described herein.

[0022] The instruction translator 102 receives macroinstructions from the memory subsystem 118 (such as the L1 instruction cache 122, etc.) and translates the macroinstructions into microinstructions that it provides to the renaming / dispatch unit 106. For certain macroinstructions, the instruction translator 102 transfers control to the microcode 104, which provides the microinstructions to the renaming / dispatch unit 106. Some microinstructions (microoperations) are load or store instructions that access memory, also referred to herein as memory access instructions. That is, the load / store instruction specifies a virtual address to access a memory or other device in the memory space of the microprocessor 100, where the BIU 116 uses a physical memory address to access the memory or other device on the processor bus. The TLB 128 caches the virtual to physical page address translations and page characteristics of the most recently accessed memory pages to reduce the amount of time required for the microprocessor 100 to execute the load / store instruction.

[0023] The rename / dispatch unit 106 allocates entries in the ROB 108 for each microinstruction that is not completed in the microprocessor 100. The microinstructions are dispatched to the ROB 108 in program order, even though the execution units 112 may not execute the microinstructions dispatched to them in program order, and are retired from the ROB 108 in program order by the retirement unit 114. In one embodiment, the age of a given micro-operation may be determined based on the relationship between the indexes of the ROB 108 and the retirement unit 108. The store unit 134 executes store instructions by writing data to the store buffer 138, which then writes the data to a memory such as system memory, L2 cache 126, and / or L1 data cache 124. The load unit 132 executes load instructions by reading data from the system memory, L2 cache 126, and / or L1 data cache 124 to the load buffer 136.

[0024] When a load / store instruction misses in TLB 128, the corresponding micro-operation is used with table lookup engine 142 to perform a table lookup operation, as described below with respect to Figure 2 described.

[0025] Now focus on Figure 2, which illustrates an embodiment of an exemplary table lookup takeover method 144. Before beginning the description of the method 144, it should be noted that the table lookup takeover of the disclosed embodiments can be performed regardless of whether there is an ordered situation that requires serialization (e.g., there is a serialization condition that requires the table lookup to be the oldest table lookup before continuing). For example, the table lookup engine 142 (or in some embodiments, other logic of the microprocessor 100) determines whether the current table lookup load operation is strictly ordered. The table lookup load operation is a load of page mapping information (such as a page directory entry or a page table entry (also including a paging entry)) from memory to the microprocessor 100, which causes the table lookup engine 142 to enable or trigger the table lookup engine 142 to promote the table lookup operation. In one embodiment, if the memory location contains a non-cacheable paging entry (e.g., by definition, speculative access to the paging entry is not allowed), then the table lookup load is strictly ordered. In one embodiment, the table lookup engine 142 determines whether the memory location of the paging entry has a non-cacheable characteristic (whether its page-level cache disable (PCD) bit in the page mapping information is set). Specifically, the microprocessor 100 checks to avoid requesting the BIU 116 to perform a transaction on the processor bus associated with a table lookup that is in an incorrect order because the memory location of the paging entry is designated as non-cacheable. Note that other and / or additional mechanisms may be used to determine whether the memory location of the paging entry is non-cacheable. For example, a memory type range register (MTRR) is combined with a page attribute table (PAT) mechanism to use the PCD / PAT / PWT bits as a reference that is combined with the MTRR characteristics to determine the true characteristics. In practice, the address of the memory location of the next level entry is combined with information from the current level (PCT, etc.) to determine whether the location of the next level entry is strictly ordered. Additional information on MTTR and PAT mechanisms is known in the art, and reference may be made to publicly available information (such as software developer manuals from Intel (registered trademark) (e.g., Addendum-Intel Architecture Software Developer's Manual, Vol. 3: system Programming Guide, incorporated herein by reference). In addition, a given table lookup load operation may also be strictly ordered if paging information (e.g., accessed bits or dirty bits in paging entries) needs to be updated or if the resulting physical page is global. Further information on these situations may be found in the aforementioned '650 patent.

[0026] As mentioned above, a table lookup takeover can also occur when there is no serialization condition. For example, there may be a scenario where there is an earlier store to the same location, or there is a memory fencing operation, which does not always require the table lookup engine to be the earliest serialization case. The store / fencing must eventually complete first, or the table lookup engine will be taken over by an earlier instruction than the store / fencing.

[0027] In view of the foregoing description, the table lookup takeover method 144 is Figure 2 1 and described below without reference to the serialized case, and it is understood that the takeover may or may not involve the serialized case. In addition, for the sake of illustration, the table lookup takeover method 144 is described in the context of two exemplary instructions, which are dispatched in reverse order and may be separated by several clock cycles. These instructions, also referred to below as the earlier or first micro-operation and the newer or second micro-operation, are dispatched in reverse order (e.g., the newer micro-operation is dispatched into the pipeline first). Note that the reference to the first and the second has no particular relevance and is particularly not necessarily equivalent to similar terms used in the claims.

[0028] At block 146 , the microprocessor 100 receives a memory access instruction 146 (eg, a load / store instruction), also referred to hereinafter as a second micro-operation, as described in the previous paragraph. Flow proceeds to block 148 .

[0029] At block 148, the microprocessor 100 detects that the virtual page address of the memory access instruction executed in the load unit 132 or the store unit 134 is in Figure 1 The process proceeds to block 150.

[0030] At block 150 , the table lookup engine 142 initiates a table lookup operation. That is, the table lookup engine 142 updates a state within the microprocessor 100 to indicate that a table lookup is required for the memory page accessed by the memory access instruction. Flow proceeds to block 152 .

[0031] At block 152 , the second micro-operation determines whether there is an active table lookup. For purposes of this example, it is assumed that there is no active table lookup, so the flow proceeds to block 154 .

[0032] At block 154 , the second micro-operation initiates a new speculative table lookup.

[0033] Now assume that an earlier memory access instruction or first micro-operation is dispatched into the pipeline. As similarly explained above in blocks 146, 148 and 150, a similar flow is performed for the first micro-instruction.

[0034] At block 152, the first micro-operation determines whether there is an active table lookup. If not, flow proceeds to block 154. However, for this example, it is assumed that the second micro-operation has not yet completed the (speculative) table lookup operation, so it is determined that there is an active table lookup. Flow proceeds to block 156.

[0035] At block 156, the first micro-operation determines whether it is older than the second micro-operation that is performing an ongoing table lookup. If not, flow proceeds to block 146 (e.g., after a possible idle period), where the first micro-operation is replayed into the pipeline (e.g., because there may or may not be a TLB miss that ensues at block 148). If the first micro-operation is older than the second micro-operation (as is the case in this illustrative example), flow proceeds to block 160.

[0036] At box 160, the first micro-operation compares its page and attributes with the page and attributes of the second micro-operation currently performing table lookup. In other words, the first micro-operation determines whether its page address (e.g., a virtual page such as a 4k region that is the same as an illustration) and attributes are the same as the page address and attributes of the second micro-operation. For example, attributes that can be matched include privilege levels (e.g., whether two memory access instructions are derived from the same programming code privilege level, where if both programming codes are user code or both are monitoring code, a match occurs). Another example of attributes to be matched includes whether the type of operation represented by the memory access instruction is the same, where if both are load operations or both are storage operations, a match occurs. Another example of matching of attributes is that both instructions set access bits or dirty bits, and for example, if one of the instructions sets the dirty bit and the other does not set the dirty bit, there is no match. Other types of attributes used for matching relate to behaviors related to implementing instructions. For example, if one of the instructions involves prefetching (prefetch) and the other does not involve prefetching, these are different behaviors, so there is no match. As another example, if both instructions involve writable operations, there is a match, while only one is writable is a mismatch. These and / or other attributes may be the subject of determination in block 160. Note that the attribute determination requires all attributes to match (e.g., a match is that both instructions involve writable or write-enabled operations (where the page is writable and the micro-operation attempts to write) and the setting of the access bit or dirty bit). If there is no match in the page address and attributes, then flow proceeds to block 162, otherwise flow proceeds to block 164.

[0037] At block 162 , the first micro-op causes eviction of the second (newer) micro-op, and flow proceeds to block 154 , where the first micro-op initiates a new speculative table lookup.

[0038] At block 164 , based on the match, the table lookup engine 142 is updated so that the second micro-operation table lookup now represents the first micro-operation. Flow proceeds to block 166 .

[0039] At block 166, at the processing stage left by the second micro-operation, the first micro-operation takes over the current speculative table lookup. In other words, unlike previous techniques, the first micro-operation does not initiate a new speculative table lookup after evicting the newer micro-operation. Instead, the first micro-operation utilizes the work performed during the current table lookup and continues from the current processing stage.

[0040] Note that variations in the amount and / or order of steps may be implemented in method 144, with some steps being performed simultaneously or in parallel. Figure 2 In some embodiments, a smaller or larger number of steps may be performed.

[0041] In view of the above description, it should be understood by those skilled in the art that Figure 3 One embodiment of another exemplary table lookup takeover method represented by method 168 and implemented by a microprocessor in one embodiment includes: initiating a first speculative table lookup (170) based on a miss in a translation lookaside buffer (TLB) of a first virtual page address via a first micro-operation corresponding to a first memory access instruction; and taking over the current first speculative table lookup (172) of the first micro-operation at a current processing stage of the first micro-operation based on a virtual page address and attributes that are earlier than the first micro-operation and also match the first virtual page address and attributes for the first memory access instruction via a second micro-operation corresponding to a second memory access instruction.

[0042] Any process description or block in the flowchart should be understood to represent a module, segment, logic or portion of code (which includes one or more executable instructions for implementing specific logical functions or steps in the process), and alternative implementations are included within the scope of the embodiments, where, as will be understood by those skilled in the art of the present invention, functions may not be performed in the order shown or discussed (including substantially simultaneously or in a different order), depending on the functions involved. In some embodiments, the functions of method 144 and / or 168 may be implemented in a computer program product including a non-transitory computer-readable storage medium having computer-readable code embodied therein for specifying a microprocessor configured to perform a speculative table lookup.

[0043] Although the present invention is shown and described in detail in the drawings and the foregoing description, such drawings and descriptions should be considered illustrative or exemplary rather than restrictive; the present invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure, and the appended claims.

[0044] Note that various combinations of the disclosed embodiments can be used, and therefore reference to an embodiment or one embodiment does not mean to exclude features of that embodiment from use of features of other embodiments. In the claims, the word "comprising" does not exclude other elements or steps.

Claims

1. A microprocessor, comprising: a translation lookaside buffer, or TLB, configured to indicate that a virtual page address corresponding to a physical page address of a memory page attempted to be accessed by a memory access instruction misses in the TLB; a first micro-operation corresponding to a first memory access instruction and configured to initiate a first speculative table lookup based on a miss of a first virtual page address in the TLB; as well as A second micro-operation corresponds to a second memory access instruction and is configured to take over an ongoing first speculative table lookup of the first micro-operation at a current processing stage of the first micro-operation based on the second micro-operation being earlier than the first micro-operation and also based on having a virtual page address and attributes that match the first virtual page address and attributes for the first memory access instruction.

2. The microprocessor according to claim 1, wherein: The second micro-operation facilitates a table lookup operation based on a TLB miss and after the first micro-operation has initiated the first speculative table lookup.

3. The microprocessor according to claim 2, wherein: The second micro-operation is configured to determine whether there is an active table lookup, and in response to there not being an active table lookup, initiate a new speculative table lookup.

4. The microprocessor according to claim 3, wherein: The second micro-operation is configured to determine whether the second micro-operation is earlier than the first micro-operation based on determining that there is an active first speculative table lookup, and to replay into the pipeline if the second micro-operation is not earlier.

5. The microprocessor according to claim 4, wherein: The second micro-operation is configured to determine whether a virtual page address and attributes corresponding to the second memory access instruction match the first virtual page address and attributes for the first memory access instruction based on the second micro-operation being earlier than the first micro-operation, and if not, evict the second micro-operation and initiate a new speculative table lookup.

6. The microprocessor according to claim 1, wherein: The attributes include permission level.

7. The microprocessor according to claim 6, wherein: The authority levels include user codes and monitor codes.

8. The microprocessor according to claim 1, wherein: The attributes include a memory access type.

9. The microprocessor according to claim 8, wherein: The memory access types include load and store instructions.

10. The microprocessor according to claim 1, wherein: The properties include whether writing is enabled.

11. The microprocessor according to claim 1, wherein: The attributes include whether the access bit or the dirty bit is set.

12. The microprocessor according to claim 1, wherein: A match to the first virtual page address corresponds to a page of the virtual memory space mapped to a memory page.

13. The microprocessor of claim 1 further comprising a table lookup engine, wherein: Based on the match, a table lookup engine for the first micro-operation is updated with the age of the second micro-operation.

14. A method implemented in a microprocessor, the method comprising: Initiating a first speculative table lookup based on a miss of a first virtual page address in a translation lookaside buffer (TLB) via a first micro-operation corresponding to a first memory access instruction; as well as Taking over the ongoing first speculative table lookup of the first micro-operation at a current processing stage of the first micro-operation by a second micro-operation corresponding to a second memory access instruction, based on the second micro-operation being earlier than the first micro-operation and also based on having a virtual page address and attributes that match the first virtual page address and attributes for the first memory access instruction.

15. The method according to claim 14, further comprising: A table lookup operation is facilitated, by the second micro-operation, based on a TLB miss and after the first speculative table lookup has been initiated by the first micro-operation.

16. The method according to claim 15, further comprising: Through the second micro-operation, it is determined whether there is an active table lookup, and in response to there not being an active table lookup, a new speculative table lookup is initiated.

17. The method according to claim 16, further comprising: By the second micro-operation, it is determined whether the second micro-operation is earlier than the first micro-operation based on the determination that there is an ongoing first speculative table lookup, and if the second micro-operation is not earlier, it is replayed into the pipeline.

18. The method according to claim 17, further comprising: Through the second micro-operation, it is determined whether the virtual page address and attributes corresponding to the second memory access instruction match the first virtual page address and attributes for the first memory access instruction, and if not, the second micro-operation is evicted and a new speculative table lookup is initiated.

19. The method according to claim 14, wherein: The attributes include one or more of a privilege level, a memory access type, whether writing is enabled, whether an access bit or a dirty bit is set.

20. The method of claim 14, further comprising updating a table lookup engine of the first micro-operation with an age of the second micro-operation based on the match.

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