Chip for convolution calculation and control method thereof, electronic device

Abstract

The application relates to a chip for convolution calculation, comprising a memory, a processor and a convolution calculation module, wherein the memory is used for storing convolution parameter data and convolution calculation results; the processor is connected with the memory and is used for receiving a self-customized instruction of a user, generating a control instruction based on the self-customized instruction based on a RISC-V open source instruction set architecture; the convolution calculation module is connected with the processor and the memory and is used for receiving the control instruction and the convolution parameter data, performing calculation based on the control instruction and the convolution parameter data, and outputting convolution calculation results. The chip for convolution calculation adopts the most simple architecture RISC-V, can discard a large number of redundant instructions, makes the kernel design simple, and reduces power consumption. Meanwhile, the convolution acceleration calculation is realized by the convolution calculation module instead of a software application in the kernel, so that the convolution acceleration calculation speed is greatly improved.

Description

Technical Field

[0001] The present application relates to the field of pulse modulation, and in particular to a chip for convolution calculation, a control method thereof, and an electronic device. Background Art

[0002] With the popularity of deep neural networks, the number and variety of neural network accelerator products has grown dramatically. Dedicated chips for neural network acceleration have become key components in many consumer, communications, medical, and industrial products. These products use a variety of hardware methods to implement specific types of computations. Convolution is one of the most common. This operation accounts for a significant portion of neural network computations, consuming a significant amount of computing time and power. Furthermore, the parameters and types of convolutions are complex, making a single computational architecture inadequate for accelerating all convolutions. Therefore, convolution accelerators require a degree of configurability to enable field reconfiguration to meet evolving computing needs. These accelerator chips often require an embedded processor to configure chip functions and execute code.

[0003] However, in today's processor field, the mainstream architectures are x86 and ARM architectures. Although these two architectures are technologically mature, they retain many backward instructions for compatibility, resulting in a large number of instructions and serious instruction redundancy. Using them to design new processors will inevitably result in larger area and power consumption.

[0004] In addition, the use of commercial x86 and ARM architectures also involves high patent and licensing fees, which makes later designers pay high learning costs and requires them to make many concessions in processor design. Summary of the Invention

[0005] Based on this, it is necessary to address the problems in the above-mentioned background technology and provide a chip for convolution calculation and its control method and electronic device. Based on the RISC-V open source instruction set architecture, users can customize operations, effectively improve the speed of convolution calculation, achieve power consumption optimization, and reduce costs.

[0006] One aspect of the present application provides a chip for convolution calculation, including a memory, a processor and a convolution calculation module, wherein the memory is used to store convolution parameter data and convolution calculation results; the processor is connected to the memory, based on the RISC-V open source instruction set architecture, and is used to receive user customized instructions and generate control instructions based on the customized instructions; the convolution calculation module is connected to both the processor and the memory, and is used to receive the control instructions and the convolution parameter data, and perform calculations based on the control instructions and the convolution parameter data, and output the convolution calculation results.

[0007] In the chip for convolution calculation in the above embodiment, by setting a memory for storing convolution parameter data and convolution calculation results, the processor and convolution calculation module connected to the memory can extract data from the memory at any time, and based on the instructions given by the user to the processor, complex convolution calculations can be achieved. The chip for convolution calculation in this application adopts the most streamlined architecture RISC-V, which can discard a lot of redundant instructions, making the core design simple and reducing power consumption. At the same time, the convolution acceleration calculation is implemented by the convolution calculation module, rather than the software application in the kernel, which greatly improves the calculation speed of convolution acceleration.

[0008] In one embodiment, the processor includes a basic instruction submodule and an extended instruction submodule, wherein the basic instruction submodule is used to implement the standard instruction set defined by the RISC-V standard; the extended instruction submodule is used to implement a user-defined custom instruction set.

[0009] In one embodiment, the convolution calculation module includes a register group and a matrix module, wherein the register group is connected to the extended instruction sub-module to realize information interaction between the extended instruction sub-module and the calculation module; the matrix module is connected to the extended instruction sub-module via the register group and the memory to receive the control instruction and the convolution parameter data, and perform convolution calculation based on the control instruction and the convolution parameter data, and output the convolution calculation result.

[0010] In one embodiment, the register group includes a command register and a response register, wherein the command register is connected to both the extended instruction sub-module and the matrix module, and is used to receive the control instruction and generate a control signal based on the control instruction; the response register is connected to both the extended instruction sub-module and the calculation module, and is used to obtain the convolution calculation result and generate a response signal based on the convolution calculation result.

[0011] In one embodiment, the control signal includes an operation control signal and a precision control signal, the matrix module includes a preset number of calculation units, and any of the calculation units includes a control register, a data register and a multiplier / adder, wherein the control register is connected to the command register group, and is used to send the received operation control signal and the precision control signal to the data register; the data register is connected to the control register and the memory, and is used to send the received operation control signal, the precision control signal and the convolution parameter data to the multiplier / adder; the multiplier / adder is connected to the data register, and is used to receive the operation control signal, the precision control signal and the convolution parameter data, calculate the convolution parameter data based on the operation control signal and the precision control signal, and output the calculation result.

[0012] In one embodiment, the convolution parameter data includes first convolution parameter data and second convolution parameter data, and the data register includes a first input data chain and a second input data chain, wherein the first input data chain is connected to the memory for storing and / or outputting the first convolution parameter data; the second input data chain is connected to the memory for storing and / or outputting the second convolution parameter data.

[0013] In one embodiment, the control signal also includes a displacement control signal, and the processor is further configured to: obtain the customized instruction and the convolution parameter data; generate the displacement control signal based on the customized instruction and the convolution parameter data; and control the displacement of the second convolution parameter data in the second input data chain based on the displacement control signal.

[0014] In one embodiment, the matrix module further includes an adder, which is used to obtain calculation results of each of the calculation units, perform sum operation on the calculation results of the calculation units, and output a convolution calculation result.

[0015] Another aspect of the present application provides an electronic device comprising a chip for convolution calculation as described in any one of the embodiments of the present application.

[0016] The electronic device in the above embodiment adopts the chip for convolution calculation in the embodiment of the present application. By setting up a memory for storing convolution parameter data and convolution calculation results, the processor and convolution calculation module connected to the memory can extract data from the memory at any time. Based on the instructions given by the user to the processor, complex convolution calculations can be achieved. Since RISC-V is an emerging open source instruction set, it does not have high patent licensing fees and supports designers to customize instructions. The use of chips based on the RISC-V framework allows designers to make special optimizations for the above electronic devices according to the application scenario, which not only reduces the energy consumption and cost of the electronic devices, but also makes their application range wider and more applicable.

[0017] Another aspect of the present application provides a control method for convolution calculation, comprising the following steps:

[0018] Get user-defined instructions;

[0019] A processor based on the RISC-V open source instruction set architecture generates control instructions according to the user-customized instructions;

[0020] The convolution calculation module obtains the convolution parameter data and the control instruction, performs calculation based on the control instruction and the convolution parameter data, and outputs the convolution calculation result.

[0021] The control method for convolution calculation in this application utilizes the characteristic of the RISC-V core's customizable instruction set to implement convolution calculation with only a small subset of instructions. Compared with ordinary x86 or ARM instruction set processors with hundreds of instruction sets, the processor based on the RISC-V core is much smaller in scale than other architectures, and therefore has lower power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0023] Figure 1 A schematic diagram of a chip structure for convolution calculation provided in one embodiment of the present application;

[0024] Figure 2 This is a schematic diagram of a chip structure for convolution calculation provided in another embodiment of the present application;

[0025] Figure 3 This is a schematic diagram of a chip structure for convolution calculation provided in another embodiment of the present application;

[0026] Figure 4 This is a schematic diagram of a chip structure for convolution calculation provided in yet another embodiment of the present application;

[0027] Figure 5 A schematic diagram of a convolution calculation process controlled by a control signal provided in one embodiment of the present application;

[0028] Figure 6 A schematic diagram of a data register provided in one embodiment of the present application;

[0029] Figure 7 This is a flow chart of a control method for convolution calculation provided in one embodiment of the present application;

[0030] Figure 8 A flow chart of a control method for convolution calculation provided in another embodiment of the present application. DETAILED DESCRIPTION

[0031] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0033] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.

[0034] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this application.

[0035] In this application, unless otherwise specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can refer to direct connection or indirect connection through an intermediate medium, internal communication between two elements, or interaction between two elements. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0036] In the processor world, the x86 and ARM architectures are currently the dominant architectures. After decades of development, modern x86 and ARM architecture documentation spans hundreds or thousands of pages, encompassing numerous versions. This is primarily due to the continuous evolution and maturation of modern processor architecture technology. Furthermore, as commercial architectures, maintaining backward compatibility necessitates retaining many outdated definitions, or integrating existing technologies into new architectural components, leading to significant verbosity over time. However, RISC-V, as an instruction set, offers a significant advantage over most other instruction sets in being freely usable for any purpose, allowing anyone to design, manufacture, and sell RISC-V chips and software. Its balanced approach to data throughput and speed makes it an ideal architecture for the heterogeneous IoT era, and the ecosystem it has fostered is rapidly evolving. RISC-V's advantages also lie in its open source nature, resulting in low CPU design costs and significant economic benefits from collaborative hardware innovations. Its simplicity, with a base instruction set of just over 40 instructions, meets the stringent code size requirements of embedded systems and the IoT. Its flexibility, with ample code space and four user instructions, allows for instruction set extensions. While not the first open source instruction set, RISC-V is significant because its design makes it suitable for modern computing devices. Its designers prioritized performance and power efficiency for these applications. It also boasts extensive software support, addressing a common weakness of new instruction sets.

[0037] In one embodiment of the present application, Figure 1 As shown, a chip 100 for convolution calculation is provided, including a memory 10, a processor 20 and a convolution calculation module 30, wherein the memory 10 is used to store convolution parameter data and convolution calculation results; the processor 20 is connected to the memory 10, and is used to receive user customized instructions based on the RISC-V open source instruction set architecture, and generate control instructions based on the customized instructions; the convolution calculation module 30 is connected to both the processor 20 and the memory 10, and is used to receive the control instructions and the convolution parameter data, and perform calculations based on the control instructions and the convolution parameter data, and output convolution calculation results.

[0038] In the chip for convolution calculation in the above embodiment, by setting a memory for storing convolution parameter data and convolution calculation results, the processor and convolution calculation module connected to the memory can extract data from the memory at any time, and based on the instructions given by the user to the processor, complex convolution calculations can be achieved. The chip for convolution calculation in this application adopts the most streamlined architecture RISC-V, which can discard a lot of redundant instructions, making the core design simple and reducing power consumption. At the same time, the convolution acceleration calculation is implemented by the convolution calculation module, rather than the software application in the kernel, which greatly improves the calculation speed of convolution acceleration.

[0039] In one embodiment, Figure 2 As shown, the processor 20 includes a basic instruction submodule 21 and an extended instruction submodule 22, wherein the basic instruction submodule 21 is used to implement the standard instruction set defined by the RISC-V standard; the extended instruction submodule 22 is used to implement a user-defined custom instruction set.

[0040] Specifically, the biggest difference between the RISC-V architecture and other mature commercial architectures is that it is a modular architecture. In this application, the processor that complies with the RISC-V ISA standard includes a basic instruction submodule 21, which is used to implement the standard instruction set defined by the RISC-V standard. The standard instruction set includes RV32I, RV32E, RV64I, and RV128I. Among them, RV32I is a 32-bit integer instruction set, RV32E is a subset of RV32I and is used in small embedded scenarios, RV64I is a 64-bit integer instruction set compatible with RV32I, and RV128I is a 128-bit integer instruction set compatible with RV64I and RV32I. The processor 20 that complies with the RISC-V ISA standard also includes an extended instruction submodule 22 for implementing user-defined custom instruction sets. The RISC-V architecture is not only compact and powerful, but its different parts can also be organized together in a modular manner, thereby attempting to meet a variety of different applications through a unified architecture. This modularity is not available in the x86 and ARM architectures. The open source nature of the RISC-V ISA means that corresponding chip architectures can be created for different application scenarios. With the help of corresponding customized instruction tools, application acceleration can be made more efficient, and the multi-core heterogeneous characteristics also promote power consumption optimization.

[0041] In one embodiment, Figure 3 As shown, the convolution calculation module 30 includes a register group 31 and a matrix module 32, wherein the register group 31 is connected to the extended instruction sub-module 22 for realizing information interaction between the extended instruction sub-module 22 and the matrix module 32; the matrix module 32 is connected to the extended instruction sub-module 22 via the register group 30 and the memory 10 for receiving the control instruction and the convolution parameter data, and performing convolution calculation based on the control instruction and the convolution parameter data, and outputting the convolution calculation result.

[0042] Specifically, by setting up a register group to receive and store the control instructions of the extended instruction sub-module and sending them to the matrix module, the signal interaction of the extended instruction sub-module controlling the matrix module to perform operations is completed. In addition, the matrix module receives the control instruction to generate a response signal and sends it to the extended instruction sub-module through the register group, completing the signal interaction of the matrix module feedback to the extended instruction sub-module.

[0043] In one embodiment, Figure 4 As shown, the register group includes a command register and a response register, wherein the command register is connected to both the extended instruction submodule and the matrix module, and is used to receive the control instruction and generate a control signal based on the control instruction; the response register is connected to both the extended instruction submodule and the calculation module, and is used to obtain the convolution calculation result and generate a response signal based on the convolution calculation result.

[0044] Specifically, by setting the command register to receive and store the control instructions of the extended instruction sub-module and sending them to the matrix module, the signal interaction of the extended instruction sub-module controlling the matrix module to perform operations is completed. In addition, by setting the response register to receive and store the calculation results of the matrix module and sending them to the extended instruction sub-module, the signal interaction of the matrix module feeding back the extended instruction sub-module is completed.

[0045] In one of the embodiments, please refer to Figure 4 , the control signal includes an operation control signal and a precision control signal, the matrix module includes a preset number of calculation units, any of the calculation units includes a control register, a data register and a multiplier / adder, wherein the control register is connected to the command register group, and is used to send the received operation control signal and the precision control signal to the data register; the data register is connected to the control register and the memory, and is used to send the received operation control signal, the precision control signal and the convolution parameter data to the multiplier / adder; the multiplier / adder is connected to the data register, and is used to receive the operation control signal, the precision control signal and the convolution parameter data, calculate the convolution parameter data based on the operation control signal and the precision control signal, and output the calculation result.

[0046] Specifically, the convolution calculation module includes multiple sets of different command registers and response registers. The format and meaning of these registers can be freely customized to correspond to the extended instructions defined by the processor's extended instruction submodule. This means that the processor has dedicated instructions, and a single instruction can access and control the convolution calculation module. Furthermore, the convolution calculation module provides communication between the computational unit and the processor, handling load / store requests from the matrix module. Both the processor and the convolution calculation module can initiate read and write requests to the shared memory, which the two modules share. The memory controller arbitrates the read and write order, greatly improving control efficiency.

[0047] Furthermore, the control signal includes an operation control signal and a precision control signal. For example, Figure 5As shown, the arithmetic control signal is a 2-bit OP code, and the precision control signal is a 1-bit OP code. The computing unit performs the following operations based on the arithmetic control signal OP code: 00 → Z = X × Y + 0 = X × Y (multiplication), 10 → Z = 1 × Y + X = X + Y (addition), and 11 → Z = -1 × Y + X = XY (subtraction). Based on the precision control signal OP code, the computing unit performs the following operations: 0 → 16-bit precision, 1 → 8-bit precision. In other words, the control signal can control the convolution calculation module's computational process through simple coding.

[0048] In one embodiment, Figure 6 As shown, the convolution parameter data includes first convolution parameter data and second convolution parameter data, and the data register includes a first input data chain and a second input data chain, wherein the first input data chain is connected to the memory for storing and / or outputting the first convolution parameter data; the second input data chain is connected to the memory for storing and / or outputting the second convolution parameter data.

[0049] Specifically, by setting a first input data chain and a second input data chain connected to the memory, the computing unit can read the convolution parameter data in the memory.

[0050] As an example, in a one-dimensional convolution calculation, the 64-order one-dimensional convolution formula is as follows:

[0051]

[0052] Using the convolution calculation chip in the embodiment of the present application, it is only necessary to change the coefficient a k The data is loaded into the memory and stored as the first convolution parameter data, and the sampling point x(nk) is loaded into the memory and stored as the second convolution parameter data. The first input data chain and the second input data chain read the first convolution parameter data and the second convolution parameter data respectively, and transmit them to the calculation unit to complete the convolution calculation process.

[0053] In one embodiment, the control signal also includes a displacement control signal, and the processor is further configured to: obtain the customized instruction and the convolution parameter data; generate the displacement control signal based on the customized instruction and the convolution parameter data; and control the displacement of the second convolution parameter data in the second input data chain based on the displacement control signal.

[0054] As an example, two-dimensional convolution is used for image spatial domain processing. Image smoothing and sharpening are obtained by convolving an image pixel matrix B(n×n) with a specific mask matrix W(m×m). For example, when m=3, a new pixel point can be calculated as follows:

[0055]

[0056] Using the convolution chip described in the embodiments of the present application, the first input data chain is used to store the coefficients in the mask W. As in a one-dimensional convolution, a pixel window can be extracted from a single data stream. Image pixels are input row by row, starting from the point where the convolution window is located, until two complete rows and the three pixels in the third row of the convolution window are stored in the second input data chain. At this point, a 3×3 convolution can be performed, where the data in the first data chain is multiplied and summed element by element with the data in the second data chain. Furthermore, from this point on, the convolution window shifts one position each time a new pixel is inserted into the second input data chain. Specifically, the displacement of the second convolution parameter data in the second input data chain is controlled by a shift control signal. Because the second input data chain can store a maximum of 64 pixels, the image must be cut vertically with a width of 30 pixels. Both image processing at the cut point and repositioning of the convolution window are controlled by the shift control signal.

[0057] In one embodiment, the matrix module further includes an adder, which is used to obtain calculation results of each of the calculation units, perform sum operation on the calculation results of the calculation units, and output a convolution calculation result.

[0058] For details, please refer to Figure 6 ,The matrix module also includes an adder, which sums the outputs of the 64 computing units, and the final output is the convolution ,computation result.

[0059] Another aspect of the present application provides an electronic device comprising a chip for convolution calculation as described in any one of the embodiments of the present application.

[0060] The electronic device in the above embodiment adopts the chip for convolution calculation in the embodiment of the present application. By setting up a memory for storing convolution parameter data and convolution calculation results, the processor and convolution calculation module connected to the memory can extract data from the memory at any time. Based on the instructions given by the user to the processor, complex convolution calculations can be achieved. Since RISC-V is an emerging open source instruction set, it does not have high patent licensing fees and supports designers to customize instructions. The use of chips based on the RISC-V framework allows designers to make special optimizations for the above electronic devices according to the application scenario, which not only reduces the energy consumption and cost of the electronic devices, but also makes their application range wider and more applicable.

[0061] Another aspect of the present application provides a control method for convolution calculation, such as Figure 7 As shown, the following steps are included:

[0062] Step S202: Obtain user customized instructions;

[0063] Step S204: The processor based on the RISC-V open source instruction set architecture generates a control instruction based on the user-customized instruction;

[0064] Step S206: Obtain convolution parameter data and the control instruction based on the convolution calculation module, perform calculation based on the control instruction and the convolution parameter data, and output the convolution calculation result.

[0065] The control method for convolution calculation in this application utilizes the characteristic of the RISC-V core's customizable instruction set to implement convolution calculation with only a small subset of instructions. Compared with ordinary x86 or ARM instruction set processors with hundreds of instruction sets, the processor based on the RISC-V core is much smaller in scale than other architectures, and therefore has lower power consumption.

[0066] Specifically, a processor based on the RISC-V open source instruction set architecture generates control instructions based on the user-customized instructions, driving the convolution calculation module to perform the following tasks: setting the calculation accuracy of the convolution calculation by setting the register configured by the convolution calculation module to 0 or 1, setting the operation rule of the product calculation by setting the register configured by the convolution calculation module to 00, 01 and 11, executing the enable / disable of the load shift register through the control instruction, passing the calculation array to read the starting address and range of the memory, loading the data of the memory into the calculation unit, and the convolution calculation module performs calculation after reading the calculation instruction and stores the result in the memory.

[0067] As an example, Figure 8 As shown, the instructions first configure the precision and operation type of the convolution calculation module (PE), as well as the shift control (shift or not, and how many times to shift). Then the coefficients for the convolution calculation are read in and loaded into group a registers. Then the image data to be calculated is read in and loaded into group b registers. The calculation begins. If there is a lot of data, new data is continuously shifted into group b registers to complete the convolution. After one set of data is used up, the accumulator outputs the result, completing the one-dimensional convolution. If you want to calculate multi-dimensional convolution, loop back to the "read coefficients, load into group a registers" step. After looping N times, the N-dimensional convolution is completed. The results of each time are accumulated, and finally the convolution result is output.

[0068] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0069] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present invention.

[0070] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A chip for convolution calculation, characterized in that: include: A memory, configured to store convolution parameter data and convolution calculation results; the convolution parameter data including second convolution parameter data; A processor, connected to the memory, based on the RISC-V open source instruction set architecture, configured to receive user-defined instructions and generate control instructions based on the user-defined instructions; wherein the processor includes an extended instruction submodule, the extended instruction submodule being configured to implement the user-defined custom instruction set; a convolution calculation module connected to both the processor and the memory, configured to receive the control instruction and the convolution parameter data, perform calculations based on the control instruction and the convolution parameter data, and output a convolution calculation result; wherein the convolution calculation module includes a register group and a matrix module; the register group is connected to the extended instruction submodule to implement information exchange between the extended instruction submodule and the calculation module; the matrix module is connected to the extended instruction submodule to receive the control instruction and the convolution parameter data, perform convolution calculations based on the control instruction and the convolution parameter data, and output a convolution calculation result; The register group includes a command register, which is connected to both the extended instruction submodule and the matrix module, and is used to receive the control instruction and generate a control signal based on the control instruction; the control signal includes a displacement control signal; The matrix module includes a preset number of calculation units; any of the calculation units includes a data register, and the data register includes a second input data chain; the second input data chain is connected to the memory for storing and / or outputting second convolution parameter data; The processor is further configured to: obtain the custom instruction and the convolution parameter data; generate the displacement control signal based on the custom instruction and the convolution parameter data; and control the displacement of the second convolution parameter data in the second input data chain based on the displacement control signal.

2. The chip according to claim 1, characterized in that The processor further includes: The basic instruction submodule is used to implement the standard instruction set defined by the RISC-V standard.

3. The chip according to claim 1, characterized in that The register set also includes: A response register is connected to both the extended instruction submodule and the calculation module, and is used to obtain the convolution calculation result and generate a response signal based on the convolution calculation result.

4. The chip according to claim 3, characterized in that The control signal includes an operation control signal and a precision control signal, and the calculation unit includes: a control register connected to the command register group, and configured to send the received operation control signal and the precision control signal to the data register; The data register is connected to the control register and the memory, and is used to send the received operation control signal, the precision control signal and the convolution parameter data to the multiplier-accumulator; A multiplier-accumulator is connected to the data register, and is used to receive the operation control signal, the precision control signal and the convolution parameter data, calculate the convolution parameter data based on the operation control signal and the precision control signal, and output the calculation result.

5. The chip according to claim 4, characterized in that The convolution parameter data further includes first convolution parameter data, and the data register further includes: The first input data chain is connected to the memory and is used to store and / or output first convolution parameter data.

6. The chip according to claim 1, characterized in that The matrix module further includes an adder, which is used to obtain calculation results of each of the calculation units, perform a sum operation on the calculation results of the calculation units, and output a convolution calculation result.

7. An electronic device, characterized in that: include: The chip according to any one of claims 1 to 6.

8. A control method for convolution calculation, characterized in that: The method comprises: Get user-defined instructions; A processor based on the RISC-V open source instruction set architecture generates control instructions according to the user-customized instructions; Acquire convolution parameter data and the control instruction based on a convolution calculation module, perform calculation based on the control instruction and the convolution parameter data, and output a convolution calculation result; wherein the convolution parameter data includes second convolution parameter data; The processor includes an extended instruction submodule, and the extended instruction submodule is used to implement a user-defined custom instruction set; The convolution calculation module includes a register group and a matrix module. The register group is connected to the extended instruction submodule to realize information exchange between the extended instruction submodule and the calculation module; the matrix module is connected to the extended instruction submodule to receive the control instruction and the convolution parameter data, and perform convolution calculation based on the control instruction and the convolution parameter data, and output the convolution calculation result; The register group includes a command register, which is connected to both the extended instruction submodule and the matrix module, and is used to receive the control instruction and generate a control signal based on the control instruction; the control signal includes a displacement control signal; The matrix module includes a preset number of calculation units, any of the calculation units includes a data register, the data register includes a second input data chain, the second input data chain is connected to the memory, and is used to store and / or output second convolution parameter data; The processor is further configured to: Obtaining the customized instruction and the convolution parameter data; generating the displacement control signal based on the customized instruction and the convolution parameter data; Based on the shift control signal, the shift of the second convolution parameter data in the second input data chain is controlled.

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