Collar for under bump metallization and associated systems and methods

Abstract

The present application relates to a collar for an under bump metal structure and associated systems and methods. A semiconductor die includes: a semiconductor material having a solid state component; and an interconnect extending at least partially through the semiconductor material. An under bump metal (UBM) structure is formed above the semiconductor material and electrically coupled to a corresponding interconnect. The collar surrounds at least a portion of a side surface of the UBM structure, and a solder material is disposed above a top surface of the UBM structure.

Description

[0001] This application is a divisional application of the Chinese invention patent application with the invention name of “Ring for Under Bump Metal Structure and Associated Systems and Methods”, application number 201680053250.9 and application date of August 3, 2016. Technical Field

[0002] The present invention relates generally to semiconductor devices, and more particularly, in several embodiments, the present invention relates to under bump metallurgy (UBM) structures for inter-die and / or inter-package interconnects. Background Art

[0003] Microelectronic devices such as memory devices, microprocessors, and light emitting diodes typically include one or more semiconductor die mounted to a substrate and encased in a plastic protective covering. The semiconductor die includes functional features such as memory cells, processor circuits, and interconnect circuits. The semiconductor die also typically includes bonding pads electrically coupled to the functional features. The bonding pads are electrically connected to pins or other types of terminals extending outside the protective covering to connect the semiconductor die to a bus, circuit, or other assembly.

[0004] Semiconductor die manufacturers are under increasing pressure to reduce the volume occupied by a die and to increase the capacity and / or speed of the resulting encapsulated assembly. To meet these demands, semiconductor die manufacturers typically stack multiple die on top of each other to increase the capacity or performance of the device within the limited volume of a circuit board or other component to which the die is mounted. In many applications, the die are stacked on top of each other before being encapsulated to form a three-dimensional package.

[0005] Stacked semiconductor die are usually electrically connected by solder bumps or other electrical connectors attached to an under-bump metal (UBM) structure. The UBM structure is usually formed by depositing a copper seed structure onto a wafer, forming a mask having an opening aligned with a bonding pad on the die on the copper seed structure, plating copper onto the seed structure, and then plating one or more other materials over the copper to form the UBM structure. The uppermost material of the UBM structure is usually selected to promote wetting for subsequently forming an interconnect on the uppermost material. After forming the UBM structure, microbumps of solder material are formed over the uppermost material of the UBM structure to serve as interconnects. After forming the UBM structure and the microbumps, the mask is removed and a suitable wet etch is used to remove the exposed portion of the seed structure to form an isolated UBM structure and microbumps. The present invention relates to an improved UBM structure and a method for manufacturing a UBM structure. Summary of the invention

[0006] On the one hand, the present application provides a semiconductor die, which includes: a semiconductor material having a solid-state component; an interconnect that at least partially extends through the semiconductor material; an under-bump metal (UBM) structure that is electrically coupled to the interconnect, wherein the UBM structure has a top surface, a bottom surface, and a sidewall extending between the top surface and the bottom surface, and wherein the UBM structure includes a first conductive material and a second conductive material disposed above the first conductive material; a collar that surrounds at least a portion of the sidewall of the UBM structure so that the collar contacts at least a portion of the first conductive material, wherein the collar is recessed below the top surface of the UBM structure; and a solder material disposed above the top surface of the UBM structure, wherein the collar includes an anti-wetting material that is not easily wetted by the solder material in a liquid phase.

[0007] On the other hand, the present application further provides a semiconductor die, which includes: a semiconductor material having a solid-state component; an interconnect that extends at least partially through the semiconductor material; an under-bump metal (UBM) structure that is electrically coupled to the interconnect, wherein the UBM structure has a top surface, a bottom surface, and a sidewall extending between the top surface and the bottom surface, and wherein the UBM structure includes a first conductive material and a second conductive material disposed above the first conductive material; a collar that surrounds at least a portion of the sidewall of the UBM structure so that the collar contacts at least a portion of the first conductive material but does not contact the second conductive material; and a solder material disposed above the top surface of the UBM structure.

[0008] On the other hand, the present application further provides a semiconductor die, which includes: a semiconductor material; an interconnect that at least partially extends through the semiconductor material; a pillar structure that is electrically coupled to the interconnect, wherein the pillar structure includes a lower portion and an upper portion, the lower portion includes a first conductive material and has a first side, the upper portion includes a second conductive material formed above the lower portion, and the upper portion has a second side; a ring that surrounds at least a portion of the pillar structure so that the ring contacts at least a portion of the first side and is recessed from the top surface of the pillar; and a welding material disposed above the top surface of the pillar structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Many aspects of the invention can be better understood with reference to the following drawings, wherein the components in the drawings are not necessarily drawn to scale, emphasis instead being placed upon clearly illustrating the principles of the invention.

[0010] Figure 1 is a cross-sectional view schematically showing a substrate assembly of multiple semiconductor dies according to an embodiment of the invention.

[0011] Figures 2A to 2H is a cross-sectional view schematically illustrating a portion of a semiconductor die at various stages of a method according to an embodiment of the invention.

[0012] Figures 3A to 3G is a cross-sectional view schematically illustrating a portion of a semiconductor die at various stages of a method according to another embodiment of the invention.

[0013] Figure 4 is a flow chart of a method according to an embodiment of the present invention.

[0014] Figure 5 is a flow chart of a method according to an embodiment of the present invention.

[0015] Figure 6 is a block diagram illustrating a system incorporating a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Specific details of several embodiments of methods for manufacturing semiconductor devices and related devices and systems thereof are described herein. The term "semiconductor device" generally refers to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, microprocessors, and diodes, among others. In addition, the term "semiconductor device" may refer to a manufactured device or to an assembly or other structure in various processing stages before becoming a manufactured device. Depending on the context of its use, the term "substrate" may refer to a wafer-level substrate or a singulated die-level substrate. A person of ordinary skill in the relevant art will recognize that the appropriate steps of the methods described herein may be performed at the wafer level or the die level. In addition, unless the context indicates otherwise, conventional semiconductor manufacturing techniques may be used to form the structures disclosed herein. Materials may be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, and / or other suitable techniques. Similarly, materials may be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0017] Many embodiments of the present invention will be described below in the context of UBM structures electrically coupled to TSVs (e.g., through silicon vias, which have conductive plugs or connectors that extend completely through a substrate and / or packaging material when completed). Persons of ordinary skill in the relevant art will also appreciate that the present invention may include embodiments for forming UBM structures on a first side or a second side of a substrate assembly, and may use UBM structures in the context of other electrical connectors associated with semiconductor assemblies. Thus, the present invention may be described without reference to the UBM structures herein. Figures 1 to 6The present invention is practiced without reference to several details of the embodiments described herein. For ease of reference, the same element numbers are used to identify similar or analog components or features in the present invention, but the use of the same element numbers does not imply that the features should be interpreted as the same. In fact, in many examples described herein, features with the same element numbers have multiple embodiments that are different in structure and / or function from each other. In addition, the same shading can be used to indicate cross-sectional materials that can have similar compositions, but unless otherwise specified herein, the use of the same shading does not imply that the materials should be interpreted as the same.

[0018] The UBM structure and microbumps use a reflow process to attach to adjacent dies. During the reflow of the microbumps disposed on the top of the UBM structure, some materials of the microbumps (e.g., tin) may react with materials of the UBM structure (e.g., copper), which may adversely affect the interconnection between the UBM structure and the adjacent die. For example, some materials from the microbumps may flow out due to wetting along the sidewalls of the UBM structure. This may result in the formation of intermetallic compounds on the sidewalls of the microbumps. In addition, some microbump materials (e.g., tin) may diffuse until they reach the UBM structure material (e.g., copper) and react with the UBM structure material (e.g., copper), thereby causing the molar volume of available tin in the microbumps to shrink, also known as solder deficiency. These two effects may result in the depletion of unreacted solder material available at the center of the microbumps, thereby causing voids in the solder joints and reducing electromigration reliability.

[0019] Several embodiments of the present invention significantly reduce the likelihood that the solder material of the microbump will react with the material of the UBM structure during reflow of the microbump. For example, several embodiments of the present invention form a collar around at least a portion of the first material and / or the second material of the UBM structure (which protects the UBM sidewalls from reacting with the solder from the microbump). Thus, several embodiments of the present invention reduce the reaction between the microbump and the UBM sidewalls during reflow of the microbump, as will be explained in more detail below.

[0020] Figure 1 1 is a cross-sectional view schematically illustrating a substrate assembly 100 having a semiconductor material 110 having a first side 112 and a second side 114. The substrate assembly 100 further includes a dielectric material 116 located on the second side 114 of the semiconductor material 110. A plurality of semiconductor dies 120 are formed at discrete regions of the substrate assembly 100. Although Figure 1 Two semiconductor dies 120 are illustrated in FIG. 1 , but in reality, semiconductor assembly 100 typically has hundreds or even more than 1,000 individual semiconductor dies. Individual semiconductor dies 120 may include an integrated circuit 122 and a plurality of interconnects 124 electrically coupled to the integrated circuit 122. Figure 1In the embodiment shown, the interconnect 124 is a TSV including a dielectric liner 126 and a conductive plug 128 within the dielectric liner 126. Thus, the interconnect 124 may extend completely through the substrate assembly 100.

[0021] The semiconductor die 120 further includes a plurality of UBM structures 130, and individual UBM structures 130 are electrically coupled to corresponding interconnects 124. In several embodiments, the individual UBM structures 130 include a first material 132 electrically coupled to one of the interconnects 124 and a second material 134 located over the first material 132. An anti-wetting material 136 forms a collar 138 surrounding at least a portion of the first material 132 and the second material 134. The semiconductor die 120 may also include a microbump 140 located over the second material 134 of the individual UBM structures 130.

[0022] In a particular embodiment, the first material 132 includes copper, the second material 134 includes nickel, the microbump 140 includes a tin-silver solder material, and the collar 138 includes an oxide, such as tetraethyl orthosilicate (TEOS) or another oxide. This embodiment forms: a Cu / Ni UBM structure 130 having a microbump 140 formed thereon; and an oxide collar that surrounds the exposed sidewalls of the Ni and at least a portion of the Cu and does not cover the top surface of the UBM structure 130 (e.g., the top surface of the second material 134). In other embodiments, the first material 132 and the second material 134 may include any conductive material, such as gold, silicon, tungsten, etc. The shape and size of the UBM structure 130 may vary. For example, in some embodiments, the UBM structure 130 is generally cylindrical, thereby forming a columnar structure, but in other embodiments, the UBM structure 130 may have other cross-sectional shapes, such as rectangular, regular polygonal, irregular polygonal, elliptical, etc. The UBM structure 130 may have a thickness between about 1 micron and about 100 microns and may have a height between about 1 micron and about 100 microns.

[0023] The microbump 140 may include a solder material, such as tin-silver, indium, or another solder material suitable for forming an electrical connection and a mechanical connection between the UBM structure 130 and an adjacent die. In some embodiments, the anti-wetting material 136 forming the collar 138 may include a material that prevents wetting of the microbump 140 on the sidewalls of the first material 132 and the second material 134 (e.g., the anti-wetting material 136 provides a non-wettable surface to the material of the microbump 140). The anti-wetting material 136 may have very low or negligible diffusivity to the solder material of the microbump 140. For example, in some embodiments, the anti-wetting material 136 includes an oxide, a nitride, or a polyimide. In some embodiments, the anti-wetting material 136 has about To date or, in some embodiments, have a thickness of about To date In some embodiments, the anti-wetting material 136 completely surrounds at least a portion of the circumference of the first material 132 and / or the second material 134, but in other embodiments, the anti-wetting material 136 does not cover the entire circumference. The anti-wetting material 136 also extends along at least a portion of the height of the UBM structure 130; for example, the anti-wetting material 136 covers at least 80% of the height of the UBM structure 130. The inclusion of the anti-wetting material 136 in the collar 138 eliminates or reduces solder wetting from the microbump 140 along the sidewalls of the first material 132 and the second material 134 of the UBM structure 130. Reference will be made to Figures 2A to 3G Further embodiments and aspects of forming UBM structures, collars, and micro-bumps according to the present invention are described.

[0024] Figures 2A to 2H is a cross-sectional view of a semiconductor die 120 schematically illustrating portions of a substrate assembly 100 during different stages of a method for forming a UBM structure, a collar, and microbumps. Figure 2A , at this stage of the method, the semiconductor die 120 has a seed structure 240 formed on the dielectric material 116 and the portion of the interconnect 124 proximate to the second side 114 of the substrate 110, and a mask 250 on the seed structure 240. The seed structure 240 may have a first region 242 associated with the location of the interconnect 124 and a second region 244 between the first region 242. The seed structure 240 may be a single material suitable for plating the base material or the first material of the UBM structure. In several embodiments, the seed structure 240 includes a barrier material and a seed material on the barrier material. The barrier material may be tantalum, tantalum nitride, titanium, titanium-tungsten, or another material that prevents the UBM material from diffusing into the dielectric material 116 and the substrate 100. The seed material may be copper, a copper alloy, nickel, or a suitable material for plating the first material 132 ( Figure 1 ) Other materials plated onto the seed material. In practice, the seed structure 240 may be integrated with the conductive plug 128 of the interconnect 124.

[0025] The mask 250 may be a resist material or other suitable mask material having a plurality of openings 252 aligned with the first regions 242 of the seed structure 240. As will be explained in more detail below, the UBM structure is formed in the openings 252 of the mask 250. Figure 2A , the opening 252 of the mask 250 has a T-shaped cross-section, with an upper portion 254 having a wider opening than a lower portion 256. Such a T-shaped opening 252 in the mask 250 may be formed using a leaky chrome mask during photolithography or other suitable technique.

[0026] Figure 2B2 is a schematic diagram showing that the first material 132 has been formed in the exposed first region 242 ( Figure 2A ). In one embodiment, the seed structure 240 includes a copper seed material deposited using a physical vapor deposition process, and the first material 132 includes copper deposited onto the copper seed material using an electroplating or electroless plating process known in the art. Thus, the first material 132 may define a base material for the UBM structure. In one embodiment, the first material 132 has a first diameter (e.g., 30 μm) and a height (30 μm) at this stage of the process, but the diameter and the height of the first material 132 may have any other suitable dimensions depending on the specific configuration of the specific semiconductor die 120.

[0027] Figure 2C 2 is a cross-sectional view schematically illustrating the semiconductor die 120 after the second material 134 has been deposited into the opening 252 such that the second material 134 is located over the first material 132. The second material 134 may include nickel or other suitable material that provides a good wetting surface for forming interconnects on the second material 134. The first material 132 and the second material 134 may define the UBM structure 130. At this stage of the process, the semiconductor die 120 has a plurality of UBM structures 130 that are electrically coupled to each other through the seed structure 240. In some embodiments, the second material may be omitted entirely, and the UBM structure may include only the first material.

[0028] Figure 2D 2 is a cross-sectional view schematically illustrating semiconductor die 120 after portions of mask 250 have been removed to define collar opening 258 in accordance with one embodiment of the present invention. Mask 250 may be etched using anisotropic dry etching and dry cleaning. The dry etching may substantially uniformly remove mask 250 across semiconductor die 120 until mask 250 adjacent to UBM structure 130 in collar opening 258 is completely removed. Collar opening 258 may define collar 138 ( Figure 1 ) having a thickness of, for example, about To date Between or about To date The parameters of the dry etch (eg, chemistry, power, temperature, etc.) may be adapted to harden the mask 250 during etching to prepare the mask 250 for subsequent deposition steps.

[0029] Figure 2E 1 is a cross-sectional view schematically illustrating a semiconductor die 120 after a moisture resistant material 136 has been formed according to one embodiment of the present invention. The moisture resistant material 136 may be a micro bump 140 ( Figure 1) does not easily wet (eg, cover) its material in the liquid phase and / or has a solder material for microbump 140 ( Figure 1 ) has low or negligible diffusion of solder materials. The anti-wetting material 136 may be an oxide, a nitride, a polyimide, or other suitable material. In one embodiment, the anti-wetting material 136 is tetraethyl orthosilicate (TEOS) formed by low temperature (e.g., less than 150° C.) plasma enhanced chemical vapor deposition or other suitable process. The anti-wetting material 136 is formed as a blanket layer over the mask 250 and the opening 252, including covering the UBM structure 130 and filling the collar opening 258 ( Figure 2D ).

[0030] Figure 2F 1 is a cross-sectional view schematically illustrating semiconductor die 120 after portions of anti-wetting material 136 have been removed in accordance with one embodiment of the present invention. Portions of anti-wetting material 136 may be removed using a buffered oxide etch or a spacer etch followed by a wet wash. Figure 2F , most of the anti-wetting material 136 has been removed until the remaining portion of the anti-wetting material 136 is only located at the collar opening 258 ( Figure 2D ) to form a collar 138. In some embodiments, the collar 138 can be substantially coplanar with the second material 134, while in other embodiments, the collar 138 can be recessed relative to the second material 134.

[0031] Figure 2G 1 is a cross-sectional view schematically illustrating semiconductor die 120 after microbumps 140 have been formed according to one embodiment of the present invention. Microbumps 140 may be formed of a solder material, such as tin-silver or indium solder, plated into openings 252 on top of UBM structure 130 and collar 138. In some embodiments, microbumps 140 may have a height between about 3 microns and about 50 microns.

[0032] Figure 2H 1 is a cross-sectional view schematically illustrating semiconductor die 120 after portions of mask 250 and seed structure 240 have been removed to electrically isolate UBM structure 130. Mask 250 may be removed using wet resist stripping or other suitable techniques, and then second region 244 of seed structure 240 may be removed using a wet etch suitable for removing the material of the seed structure. At this point, the UBM structures are electrically isolated from each other.

[0033] Figures 3A to 3G 1 is a cross-sectional view of a semiconductor die 120 at a portion of a substrate assembly 100 schematically illustrating different stages of fabrication of a UBM structure, a collar, and microbumps according to another embodiment of the present invention. Figure 3A, at this stage of the method, the semiconductor die 120 has a seed structure 240 on the dielectric material 116 and the portion of the interconnect 124 proximate to the second side 114 of the substrate 110, and a mask 250 is located on the seed structure 240. The seed structure 240 has a first region 242 associated with the location of the interconnect 124 and a second region 244 between the first regions 242. The mask 250 can be a resist material or other suitable mask material having a plurality of openings 252 aligned with the first regions 242 of the seed structure 240. As will be explained in more detail below, the UBM structure is formed in the openings 252 of the mask 250.

[0034] Figure 3B 1 is a cross-sectional view schematically illustrating a semiconductor die 120 after a moisture resistant material 136 has been formed according to one embodiment of the present invention. The moisture resistant material 136 may be a micro bump 140 ( Figure 1 ) does not easily wet (eg, cover) its material in the liquid phase and / or has a tendency to resist microbumps 140 ( Figure 1 ) has low or negligible diffusion of solder materials. The anti-wetting material 136 may be an oxide (e.g., tetraethyl orthosilicate (TEOS) or other oxides), a nitride, a polyimide, or other suitable material. In one embodiment, the anti-wetting material 136 is tetraethyl orthosilicate (TEOS) formed by low temperature (e.g., less than 150° C.) plasma enhanced chemical vapor deposition or other suitable process. The anti-wetting material 136 is formed as a blanket layer over the mask 250 and the opening 252.

[0035] Figure 3C 1 is a cross-sectional view schematically illustrating semiconductor die 120 after portions of anti-wetting material 136 have been removed in accordance with an embodiment of the present invention. Portions of anti-wetting material 136 may be removed using a spacer oxide etch followed by a wet wash. Figure 3C , the overlying portions of the anti-wetting material 136 have been removed until the remaining portions of the anti-wetting material 136 are only along the sidewalls of the opening 252.

[0036] Figure 3D Schematically illustrates that the first material 132 has been formed in the exposed first region 242 ( Figure 3C) and after a second material 134 has been formed over the first material 132. In one embodiment, the seed structure 240 includes a copper seed material deposited using a physical vapor deposition process, and the first material 132 includes copper deposited onto the copper seed material using an electroplating or electroless plating process known in the art. The first material 132 and the second material 134 may define a UBM structure 130 surrounded by a moisture resistant material 136. At this stage of the process, the semiconductor die 120 has a plurality of UBM structures 130 electrically coupled to each other through the seed structure 240. In some embodiments, the second material may be omitted entirely, and the UBM structure may include only the first material.

[0037] Figure 3E 1 is a cross-sectional view schematically illustrating the semiconductor die 120 after a portion of the anti-wetting material 136 has been further removed to form the collar 138. Figure 3B The process described may use a spacer oxide etch followed by a wet clean to remove additional portions of the moisture resistant material 136. Figure 3E , the anti-wetting material 136 has been removed until only the remaining anti-wetting material 136 along the sidewalls of the opening 252 is substantially coplanar with the second material 134 and thereby forms a collar 138 .

[0038] Figure 3F 1 is a cross-sectional view schematically illustrating semiconductor die 120 after microbumps 140 have been formed. Microbumps 140 may be formed of a solder material, such as tin-silver or indium solder, plated into openings 252 on top of UBM structure 130 and collar 138. In some embodiments, microbumps 140 may have a height between about 3 microns and about 50 microns.

[0039] Figure 3G 2 is a cross-sectional view schematically illustrating semiconductor die 120 after mask 250 and seed structure 240 have been removed to electrically isolate UBM structures 130. Mask 250 may be removed using wet resist stripping or other suitable techniques, and then a suitable wet etch may be used to remove second region 244 of seed structure 240 to electrically isolate UBM structures 130 from each other.

[0040] Figure 4is a flow chart of an embodiment of a method 400 for forming a UBM structure on a semiconductor die according to an embodiment of the present invention. In this embodiment, the method 400 includes: forming a mask on a seed structure (box 402) and plating a first material onto an exposed area of ​​the seed structure (box 404). For example, the mask has an opening exposing an area of ​​the seed structure, the area being electrically coupled to an interconnect extending at least partially through a semiconductor substrate. In several embodiments, the opening of the mask is superimposed over a TSV. The method 400 further includes: depositing a second material over the first material in the opening to thereby form a UBM structure (box 406), and etching a collar area around the UBM structure (box 408). The method then proceeds to: forming a moisture-resistant material over the UBM structure and into the collar area (box 410), and then etching the moisture-resistant material until the moisture-resistant material is substantially coplanar with the second material in the collar area (box 412). This step forms a collar surrounding the UBM structure. The method 400 then proceeds by forming microbumps over the UBM structures (block 414). The mask may then be removed, followed by removing the exposed portions of the seed structure between the UBM structures by wet etching.

[0041] Figure 5 is a flow chart of an embodiment of a method 500 for forming a UBM structure on a semiconductor die according to an embodiment of the present invention. In this embodiment, the method 500 includes: forming a mask on a seed structure (block 502) and forming a moisture resistant material over the mask and exposed portions of the seed material (block 504). For example, the mask has an opening exposing an area of ​​the seed structure, the area electrically coupled to an interconnect extending at least partially through a semiconductor substrate. In several embodiments, the opening of the mask is superimposed over a TSV. The method 500 further includes: etching the moisture resistant material until the seed structure is exposed and the remaining moisture resistant material defines a collar in the opening (block 506). For example, the moisture resistant material may be etched using a buffered oxide etch or a spacer etch followed by a wet wash. The method 500 then proceeds to: plating a first material over the seed material in the opening (block 508) and forming a second conductive material over the first conductive material in the opening, thereby forming a UBM structure (block 510). Next, the method 500 removes the moisture resistant material until the collar is substantially coplanar with the second conductive material in the opening (block 512). The method 500 then proceeds to: forming microbumps over the UBM structures (block 514). Next, the mask may be removed, followed by removing the exposed portions of the seed structure between the UBM structures by wet etching.

[0042] With above reference Figures 1 to 5Any of the semiconductor devices of the described features may be incorporated into any of a number of larger and / or more complex systems, a representative example of which is Figure 6 Schematically shown in the system 600. The system 600 may include a processor 602, a memory 604 (such as SRAM, DRAM, flash memory and / or other memory devices), an input / output device 606 and / or other subsystems or components 608. Figures 1 to 5 The semiconductor device 100 described may be included in Figure 6 . The resulting system 600 may be configured to perform any of a variety of suitable computing, processing, storage, sensing, imaging, and / or other functions. Thus, representative examples of system 600 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptop computers, Internet appliances, handheld devices (such as palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of system 600 include lights, cameras, vehicles, and the like. With respect to these and other examples, system 600 may be housed in a single unit or distributed over multiple interconnected units, such as through a communications network. Thus, components of system 600 may include any of local and / or remote storage storage devices and a variety of suitable computer-readable media.

[0043] It will be appreciated from the foregoing that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without departing from the scope of the invention. Accordingly, the present invention is limited only by the appended claims.

Claims

1. A semiconductor die, comprising: Semiconductor materials, which have solid-state components; an interconnect extending at least partially through the semiconductor material; an under bump metallurgy (UBM) structure electrically coupled to the interconnect, wherein the UBM structure has a top surface, a bottom surface, and sidewalls extending between the top surface and the bottom surface, and wherein the UBM structure includes a first conductive material and a second conductive material disposed over the first conductive material; a collar surrounding at least a portion of the sidewall of the UBM structure such that the collar contacts at least a portion of the first conductive material, wherein the collar is recessed below the top surface of the UBM structure; and a solder material disposed over the top surface of the UBM structure, wherein the collar comprises an anti-wetting material, the solder material not readily wettable in a liquid phase, The collar has a constant thickness defined by an outer side and an inner side thereof, and the outer side of the collar is substantially coplanar with a side of the welding material. 2 . The semiconductor die of claim 1 , wherein the collar comprises at least one of an oxide, a nitride, or a polyimide.

3. The semiconductor die of claim 1 , wherein the collar has arrive The thickness between. 4 . The semiconductor die of claim 1 , wherein the UBM structure is a pillar, and wherein the collar only partially covers the sidewall of the pillar. The semiconductor die of claim 1 , wherein the collar does not contact the second conductive material. 6 . The semiconductor die of claim 1 , wherein the UBM structure has a height between 1 micron and 100 microns, and wherein the UBM structure has a thickness between 1 micron and 100 microns. 7 . The semiconductor die of claim 1 , wherein the first conductive material comprises copper and the second conductive material comprises nickel.

8. The semiconductor die of claim 1 , wherein the UBM structure comprises a pillar, the pillar comprising: a lower portion comprising copper and having a first side; as well as An upper portion includes nickel formed over the lower portion, the upper portion having a second side, wherein the first side is substantially coplanar with the second side. 9 . The semiconductor die of claim 8 , wherein the collar contacts the first side but does not contact the second side.

10. A semiconductor die, comprising: Semiconductor materials, which have solid-state components; an interconnect extending at least partially through the semiconductor material; an under bump metallurgy (UBM) structure electrically coupled to the interconnect, wherein the UBM structure has a top surface, a bottom surface, and sidewalls extending between the top surface and the bottom surface, and wherein the UBM structure includes a first conductive material and a second conductive material disposed over the first conductive material; a collar surrounding at least a portion of the sidewall of the UBM structure such that the collar contacts at least a portion of the first conductive material but does not contact the second conductive material; and a solder material disposed over the top surface of the UBM structure, The collar has a constant thickness defined by an outer side and an inner side thereof, and the outer side of the collar is substantially coplanar with a side of the welding material.

11. The semiconductor die of claim 10, wherein the collar comprises an anti-wetting material, the solder material not readily wettable by the anti-wetting material in a liquid phase.

12. The semiconductor die of claim 10, wherein the collar comprises at least one of an oxide, a nitride, or a polyimide.

13. The semiconductor die of claim 10, wherein the UBM structure comprises a pillar, the pillar comprising: a lower portion comprising copper and having a first side; as well as An upper portion includes nickel formed over the lower portion, the upper portion having a second side, wherein the first side is substantially coplanar with the second side.

14. The semiconductor die of claim 13, wherein the collar is in contact with the first side but not in contact with the second side.

15. A semiconductor die, comprising: Semiconductor materials; an interconnect extending at least partially through the semiconductor material; a pillar structure electrically coupled to the interconnect, wherein the pillar structure includes a lower portion and an upper portion, the lower portion including a first conductive material and having a first side, the upper portion including a second conductive material formed over the lower portion, the upper portion having a second side, a collar surrounding at least a portion of the column structure such that the collar contacts at least a portion of the first side and is recessed from a top surface of the column; and a welding material disposed above the top surface of the column structure, The collar has a constant thickness defined by an outer side and an inner side thereof, and the outer side of the collar is substantially coplanar with a side of the welding material.

16. The semiconductor die of claim 15, wherein the collar comprises an anti-wetting material, the solder material not readily wettable by the anti-wetting material in a liquid phase.

Images