Composite substrate and method for manufacturing the same

Abstract

This invention provides a composite substrate and its fabrication method, comprising: a III-V group substrate having a III-V polar facet and a V-V polar facet; and an ohmic contact layer located on the V-V polar facet of the III-V group substrate. The fabrication method includes: providing a III-V group substrate having a III-V polar facet and a V-V polar facet; and forming an ohmic contact layer on the V-V polar facet of the III-V group substrate. Another fabrication method provided by this invention includes: providing a supporting substrate; forming an ohmic contact layer on the surface of the supporting substrate; forming a III-V group substrate on the surface of the ohmic contact layer, the III-V group substrate having a III-V polar facet and a V-V polar facet, with the V-V polar facet directly contacting the ohmic contact layer; and removing the supporting substrate. This invention, by incorporating an ohmic contact layer, increases the carrier concentration of the composite substrate, reduces contact resistance, improves the thermal stability of the ohmic contact, and enhances the performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a composite substrate and its preparation method. Background Technology

[0002] Gallium nitride (GaN) is a direct bandgap semiconductor material with advantages such as a large bandgap, strong breakdown electric field, and good chemical stability. ， GaN is an ideal substrate material for fabricating GaN-based optoelectronic and microelectronic devices. Currently, Ga-polar GaN-based devices have achieved rapid development and are widely used in semiconductor lighting, laser displays, power electronics, and microwave radio frequency fields.

[0003] The ohmic contact of the N-polar surface is an important issue for GaN-based devices, mainly because: (1) In recent years, GaN-based vertical structure devices have received widespread attention because vertical structure devices can avoid the problems of edge electric field concentration faced by conventional planar devices and reduce the influence of surface states on device performance, which is an important direction for the development of GaN-based devices. One electrode of the vertical structure device must be fabricated on the N-polar surface of the gallium nitride single crystal substrate. (2) Compared with Ga polar GaN, N-polar GaN has different polarities, surface dangling bonds and surface reconstruction methods, which can realize many new device structures and obtain performance that Ga polar devices do not have. N-polar high electron mobility transistor (HEMT) devices can reduce short-channel effects and improve the high-frequency characteristics of the device. The incorporation efficiency of impurities such as In and Al is higher during the growth of N-polar materials, and it is easier to control the composition of GaN-based ternary and quaternary compounds. In solar cells, the polarization electric field inside the N-polar device can promote the separation of photogenerated electrons and holes and improve the efficiency of the solar cell. One electrode of the N-polar device must also be fabricated on the N-polar surface of the gallium nitride single crystal substrate.

[0004] However, N-polar ohmic contacts face problems such as high contact resistance and poor thermal stability. Generally, ohmic contacts on N-polar surfaces deteriorate or even fail after annealing at temperatures above 300 degrees Celsius. This is mainly because Al in the electrode material at the interface easily diffuses into GaN to form AlN, which then creates two-dimensional cavitation gas near the interface due to piezoelectric polarization, leading to a deterioration in ohmic properties. Since high-temperature processes are frequently used in device fabrication, such as annealing and wire bonding, it is essential to improve the thermal stability of N-polar ohmic contacts to avoid performance degradation caused by high temperatures. Summary of the Invention

[0005] The technical problem to be solved by this invention is to address the poor ohmic contact of the N-polar surface of GaN-based devices, improve the thermal stability of the ohmic contact of the N-polar surface, reduce the contact resistance, effectively suppress the formation of two-dimensional cavitation gas at the interface, improve the reliability of the device, and provide a composite substrate and its preparation method.

[0006] To address the aforementioned problems, the present invention provides a composite substrate comprising: a III-V group substrate having a III-V polar facet and a V-V polar facet; and an ohmic contact layer located on the V-V polar facet of the III-V group substrate.

[0007] To address the aforementioned problems, the present invention provides a method for preparing a composite substrate, comprising: providing a III-V group substrate, the III-V group substrate having a III-polar surface and a V-polar surface; and forming an ohmic contact layer on the V-polar surface of the III-V group substrate.

[0008] The present invention provides another method for preparing a composite substrate, comprising: providing a support substrate; forming an ohmic contact layer on the surface of the support substrate; forming a III-V group substrate on the surface of the ohmic contact layer, the III-V group substrate having a III-V polar facet and a V-V polar facet, wherein the V-V polar facet is in direct contact with the ohmic contact layer; and removing the support substrate.

[0009] The present invention also provides another method for preparing a composite substrate, comprising: providing an ohmic contact layer, wherein the ohmic contact layer is made of a III-V group material and has a III-V polar face and a V-V polar face; and forming a III-V group substrate on the III-V polar face of the ohmic contact layer.

[0010] This invention improves the carrier concentration of the composite substrate and reduces the contact resistance by forming an ohmic contact layer on the V-polar surface of the III-V substrate. This effectively alleviates the problem of poor ohmic contact on the N-polar surface of the GaN substrate, and improves the thermal stability of the ohmic contact and the performance of the device. Attached Figure Description

[0011] Appendix Figure 1 The diagram shown is a schematic representation of a specific embodiment of the present invention.

[0012] Appendix Figure 2A-2B The attached image shows... Figure 1 Schematic diagram of process steps S10-S11.

[0013] Appendix Figure 3 The diagram shown is a schematic representation of a specific embodiment of the present invention.

[0014] Appendix Figures 4A-4D The attached image shows... Figure 3Schematic diagram of steps S30-S33 in the middle section.

[0015] Appendix Figure 5 The diagram shown is a schematic representation of a specific embodiment of the present invention.

[0016] Appendix Figures 6A-6B The attached image shows... Figure 5 Schematic diagram of process steps S50-S51. Detailed Implementation

[0017] The specific embodiments of the composite substrate and its preparation method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0018] Appendix Figure 1 The diagram shown is a schematic diagram of a specific embodiment of the present invention, including: step S10, providing a III-V group substrate, the III-V group substrate having a III-V polar surface and a V-V polar surface; step S11, forming an ohmic contact layer on the V-V polar surface of the III-V group substrate.

[0019] Appendix Figure 2A-2B The attached image shows... Figure 1 Schematic diagram of process steps S10-S11.

[0020] Appendix Figure 2A Referring to step S10, a III-V substrate 201 is provided, wherein the III-V substrate 201 has a III-polar surface and a V-polar surface. In a specific embodiment of the present invention, the III-V substrate 201 is made of undoped GaN material or semi-insulating GaN material, and has a thickness of 1 μm-1000 μm.

[0021] Appendix Figure 2B Referring to step S11, an ohmic contact layer 202 is formed on the group V polar surface of the group III-V substrate 201. In a specific embodiment of the present invention, the ohmic contact layer 202 is made of a high carrier concentration GaN material with a thickness of 10 nm-1000 μm. The high carrier concentration GaN material is doped with shallow-level donor impurities such as Si, Ge, and O, and has a carrier concentration higher than 1 × 10⁻⁶. 19 cm -3 The GaN material is used. In this specific embodiment, the ohmic contact layer 202 is a 1μm high carrier concentration GaN material layer, and the carrier concentration is higher than 1×10⁻⁶. 19 cm -3 The ohmic contact layer 202 is formed using a metal-organic chemical vapor deposition method. In other specific embodiments of the present invention, the method for forming the ohmic contact layer 202 may be selected from one or a combination of several methods, including hydride vapor phase epitaxy, metal-organic chemical vapor deposition, molecular beam epitaxy, ammonothermal method, and Na flux method.

[0022] The III-V substrate 201 and the ohmic contact layer 202 are made of binary III-V semiconductor materials, ternary, quaternary, and multi-component III-V semiconductor materials formed by multiple group III elements and multiple group V elements, such as GaN, AlN, InN, GaAs, InP, etc., or binary, ternary, and multi-component III-V semiconductor materials with different bandgap widths formed by group III and group V elements. Furthermore, the III-V substrate 201 and the ohmic contact layer 202 can be made of the same III-V compound or different III-V compounds.

[0023] Upon completion of the above technical solution, the attached document will be obtained. Figure 2B The composite substrate shown includes: a III-V substrate 201, which has a III-V polar facet and a V-V polar facet; and an ohmic contact layer 202, which is located on the V-V polar facet of the III-V substrate 201. In a specific embodiment of the present invention, the III-V substrate 201 is made of undoped GaN material or semi-insulating GaN material, with a thickness of 1 μm-1000 μm. The ohmic contact layer 202 is made of high carrier concentration GaN material, with a thickness of 10 nm-1000 μm. The high carrier concentration GaN material is doped with shallow-level donor impurities such as Si, Ge, and O, and has a carrier concentration higher than 1 × 10⁻⁶. 19 cm -3 The GaN material exhibits this characteristic. When the annealing temperature does not exceed the critical temperature, the higher the carrier concentration at the same annealing temperature, the lower the contact resistance. Due to the high carrier concentration in the ohmic contact layer 202, a large number of electrons neutralize the two-dimensional hole gas near the interface, reducing the contact resistance of the ohmic contact and improving its thermal stability.

[0024] The III-V substrate 201 and the ohmic contact layer 202 are made of binary III-V semiconductor materials, ternary, quaternary, and multi-component III-V semiconductor materials formed by multiple group III elements and multiple group V elements, such as GaN, AlN, InN, GaAs, InP, etc., or binary, ternary, and multi-component III-V semiconductor materials with different bandgap widths formed by group III and group V elements. Furthermore, the III-V substrate 201 and the ohmic contact layer 202 can be made of the same III-V compound or different III-V compounds.

[0025] Semiconductor materials with large band gaps possess high transition energies, resulting in high breakdown electric field strength, high saturated electron drift velocity, high thermal conductivity, low dielectric constant, and good chemical stability. These characteristics make them suitable for fabricating high-frequency, high-power, and high-density integrated electronic devices, exhibiting excellent high-temperature and high-pressure resistance and radiation resistance. Furthermore, by adjusting the band gap and using semiconductors with different band gaps to form heterojunctions, high electron mobility transistors (HEMTs) can be fabricated. Because they utilize heterojunctions and the highly mobile two-dimensional electron gas within them, these devices and their integrated circuits can operate in ultra-high frequency (millimeter-wave) and ultra-high-speed applications.

[0026] Appendix Figure 3 The diagram shown is a schematic representation of another specific embodiment of the present invention, including: step S30, providing a support substrate; step S31, forming an ohmic contact layer on the surface of the support substrate; step S32, forming a III-V group substrate on the surface of the ohmic contact layer, the III-V group substrate having a III-V polar surface and a V-V polar surface, and the V-V polar surface being in direct contact with the ohmic contact layer; step S33, removing the support substrate.

[0027] Appendix Figures 4A-4D The attached image shows... Figure 3 Schematic diagram of steps S30-S33 in the middle section.

[0028] Appendix Figure 4A Referring to step S30, a support substrate 40 is provided. In a specific embodiment of the present invention, the support substrate includes substrate materials such as GaN single crystal substrate, sapphire substrate, Si substrate, and SiC substrate.

[0029] Appendix Figure 4B Referring to step S31, an ohmic contact layer 402 is formed on the surface of the supporting substrate 40. In a specific embodiment of the present invention, the ohmic contact layer 402 is made of a high carrier concentration GaN material with a thickness of 10 nm-1000 μm. The high carrier concentration GaN material is doped with shallow-level donor impurities such as Si, Ge, and O, and has a carrier concentration higher than 1 × 10⁻⁶. 19 cm -3 The GaN material is used. In this specific embodiment, the ohmic contact layer 402 is a 10 μm high carrier concentration GaN material layer, and the carrier concentration is higher than 1 × 10⁻⁶. 19 cm -3 The ohmic contact layer 402 is formed using a hydride vapor phase epitaxy method. In other specific embodiments of the present invention, the method for forming the ohmic contact layer 402 may be selected from one or a combination of several methods, including hydride vapor phase epitaxy, metal-organic chemical vapor deposition, molecular beam epitaxy, ammonothermal method, and Na flux method.

[0030] Appendix Figure 4C Referring to step S32, a III-V substrate 401 is formed on the surface of the ohmic contact layer 402. The III-V substrate 401 has a III-polar surface and a V-polar surface, and the V-polar surface is in direct contact with the ohmic contact layer 402. In one specific embodiment of the present invention, the III-V substrate 401 is made of undoped GaN material with a thickness of 1 μm-1000 μm. In this specific embodiment, the III-V substrate 401 is a 300 μm undoped GaN material layer, formed by hydride vapor phase epitaxy. In other specific embodiments of the present invention, the method for forming the III-V substrate 401 is selected from one or a combination of several of the following methods: hydride vapor phase epitaxy, metal-organic chemical vapor deposition, molecular beam epitaxy, ammonothermal method, and Na flux method.

[0031] Appendix Figure 4D Referring to step S33, the support substrate 40 is removed. In one specific embodiment of the present invention, the support substrate is removed by laser lift-off or polishing.

[0032] Upon completion of the above technical solution, the attached document will be obtained. Figure 4D The composite substrate shown includes: a III-V substrate 401, which has a III-V polar surface and a V-V polar surface; and an ohmic contact layer 402, which is located on the V-V polar surface of the III-V substrate 401. In a specific embodiment of the present invention, the III-V substrate 401 is made of undoped GaN material or semi-insulating GaN material, with a thickness of 1 μm-1000 μm. The ohmic contact layer 402 is made of high carrier concentration GaN material, with a thickness of 10 nm-1000 μm. The high carrier concentration GaN material is doped with shallow-level donor impurities such as Si, Ge, and O, and has a carrier concentration higher than 1 × 10⁻⁶. 19 cm -3 The GaN material exhibits this characteristic. When the annealing temperature does not exceed the critical temperature, the higher the carrier concentration at the same annealing temperature, the lower the contact resistance. Due to the high carrier concentration in the ohmic contact layer 402, a large number of electrons neutralize the two-dimensional hole gas near the interface, reducing the contact resistance of the ohmic contact and improving its thermal stability.

[0033] The materials of the III-V substrate 401 and the ohmic contact layer 402 are respectively binary III-V semiconductor materials, ternary, quaternary, and multi-component III-V semiconductor materials formed by multiple group III elements and multiple group V elements, such as GaN, AlN, InN, GaAs, InP, etc., or binary, ternary, and multi-component III-V semiconductor materials with different band gaps formed by group III and group V elements. Furthermore, the materials of the III-V substrate 401 and the ohmic contact layer 402 can be the same III-V compound or different III-V compounds.

[0034] Appendix Figure 5 The diagram shown is a schematic diagram of another specific embodiment of the present invention, including: step S50, providing an ohmic contact layer, the ohmic contact layer being made of a III-V group material and having a III-V polar surface and a V-V polar surface; step S51, forming a III-V group substrate on the III-V polar surface of the ohmic contact layer.

[0035] Appendix Figures 6A-6B The attached image shows... Figure 5 Schematic diagram of process steps S50-S51.

[0036] Appendix Figure 6A Referring to step S50, an ohmic contact layer 602 is provided. The ohmic contact layer 602 is made of a III-V group material and has a III-V polar facet and a V-V polar facet. In a specific embodiment of the present invention, the ohmic contact layer 602 is made of a high-conductivity GaN single-crystal material with a thickness of 1 μm-1000 μm. In this specific embodiment, the carrier concentration of the ohmic contact layer 602 is higher than 1 × 10⁻⁶. 18 cm -3 The conductivity of the high-conductivity GaN single crystal material is higher than 5 × 10⁻⁶. 3 S / m.

[0037] Appendix Figure 6B Referring to step S51, a III-V substrate 601 is formed on the III-V polar surface of the ohmic contact layer 602. That is, the ohmic contact layer 602 is located on the V-V polar surface of the III-V substrate 601. In a specific embodiment of the present invention, the III-V substrate 601 is a low-impurity epitaxial layer with a thickness of 1 μm-1000 μm and a carrier concentration lower than 1 × 10⁻⁶. 17 cm -3 In this specific embodiment, the low-impurity epitaxial layer is made of low-impurity GaN material. The method for forming the III-V substrate 601 is selected from one or a combination of several of the following methods: hydride vapor phase epitaxy, metal-organic chemical vapor deposition, molecular beam epitaxy, ammonothermal method, and Na flux method.

[0038] Upon completion of the above technical solution, the attached document will be obtained. Figure 6B The composite substrate shown includes: a III-V group substrate 601, which has a III-V polar facet and a V-V polar facet; and an ohmic contact layer 602, which is located on the V-V polar facet of the III-V group substrate 601. In one specific embodiment of the present invention, the ohmic contact layer 602 is made of a III-V group material and has a III-V polar facet and a V-V polar facet. In another specific embodiment of the present invention, the ohmic contact layer 602 is made of a high-conductivity GaN single crystal material with a thickness of 1 μm-1000 μm. In this specific embodiment, the carrier concentration of the ohmic contact layer 602 is higher than 1 × 10⁻⁶. 18 cm -3 The conductivity of the high-conductivity GaN single crystal material is higher than 5 × 10⁻⁶. 3 S / m. The III-V group substrate 601 employs a low-impurity epitaxial layer with a thickness of 1μm-1000μm and a carrier concentration below 1×10⁻⁶. 17 cm -3 In this specific embodiment, the low-impurity concentration epitaxial layer is made of low-impurity concentration GaN material. When the annealing temperature does not exceed the critical temperature, the higher the carrier concentration at the same annealing temperature, the lower the contact resistance. Due to the high carrier concentration in the ohmic contact layer 602, a large number of electrons neutralize the two-dimensional hole gas near the interface, reducing the contact resistance of the ohmic contact and improving its thermal stability.

[0039] The above technical solution improves the carrier concentration of the composite substrate and reduces the contact resistance by forming an ohmic contact layer on the V-polar surface of the III-V substrate. This effectively alleviates the problem of poor ohmic contact on the N-polar surface of the GaN substrate, and improves the thermal stability of the ohmic contact and the performance of the device.

[0040] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A composite substrate, characterized in that, include: The III-V group substrate has a III polar facet and a V polar facet. The III-V group substrate is made of undoped GaN material or semi-insulating GaN material, with a thickness of 1 μm-1000 μm and a carrier concentration of less than 1 × 10⁻⁶. 17 cm -3 ; An ohmic contact layer is located on the group V polar facet of the group III-V substrate. The ohmic contact layer is made of high carrier concentration GaN material, with a thickness of 10 nm-1000 μm. The high carrier concentration GaN material is doped with shallow-level donor impurities, and the carrier concentration is higher than 1 × 10⁻⁶. 19 cm -3 The GaN material, wherein the shallow-level donor impurity is Si, Ge or O.

2. The composite substrate according to claim 1, characterized in that, The ohmic contact layer is made of high-conductivity GaN single crystal material with a thickness of 1μm-1000μm.

3. The composite substrate according to claim 1, characterized in that, The III-V group substrate employs a low-impurity epitaxial layer with a thickness of 1 μm-1000 μm and a carrier concentration below 1 × 10⁻⁶. 17 cm -3 .

4. The composite substrate according to claim 1, characterized in that, The materials of the III-V substrate and the ohmic contact layer are respectively binary III-V semiconductor materials, ternary, quaternary and multi-element III-V semiconductor materials formed by multiple III elements and multiple V elements, or binary, ternary and multi-element III-V semiconductor materials with different band gaps formed by III elements and V elements.

5. A method for preparing a composite substrate, characterized in that, include: A group III-V substrate is provided, wherein the group III-V substrate has a group III polar facet and a group V polar facet, the group III-V substrate is made of undoped GaN material or semi-insulating GaN material, the thickness is 1 μm-1000 μm, and its carrier concentration is less than 1 × 10⁻⁶. 17 cm -3 ; An ohmic contact layer is formed on the group V polar surface of the group III-V substrate. The ohmic contact layer is made of high carrier concentration GaN material, and its thickness is 10 nm-1000 μm. The high carrier concentration GaN material is doped with shallow-level donor impurities, and its carrier concentration is higher than 1 × 10⁻⁶. 19 cm -3 The GaN material, wherein the shallow-level donor impurity is Si, Ge or O.

6. The method according to claim 5, characterized in that, The materials of the III-V substrate and the ohmic contact layer are respectively binary III-V semiconductor materials, ternary, quaternary and multi-element III-V semiconductor materials formed by multiple III elements and multiple V elements, or binary, ternary and multi-element III-V semiconductor materials with different band gaps formed by III elements and V elements.

7. The method according to claim 5, characterized in that, The method for forming the ohmic contact layer is selected from one or a combination of several of the following methods: hydride vapor phase epitaxy, metal-organic chemical vapor deposition, molecular beam epitaxy, ammonothermal method, and Na flux method.

8. A method for preparing a composite substrate, characterized in that, include: Provide a supporting substrate; An ohmic contact layer is formed on the surface of the supporting substrate. The ohmic contact layer is made of a high carrier concentration GaN material, and its thickness is 10 nm-1000 μm. The high carrier concentration GaN material is doped with shallow-level donor impurities, and its carrier concentration is higher than 1 × 10⁻⁶. 19 cm -3 The GaN material wherein the shallow-level donor impurity is Si, Ge, or O; A III-V group substrate is formed on the surface of the ohmic contact layer. The III-V group substrate has a III-group polar facet and a V-group polar facet, and the V-group polar facet is in direct contact with the ohmic contact layer. The III-V group substrate is made of undoped GaN material or semi-insulating GaN material, with a thickness of 1 μm-1000 μm and a carrier concentration of less than 1 × 10⁻⁶. 17 cm -3 ; Remove the supporting substrate.

9. The method according to claim 8, characterized in that, The materials of the III-V substrate and the ohmic contact layer are respectively binary III-V semiconductor materials, ternary, quaternary and multi-element III-V semiconductor materials formed by multiple III elements and multiple V elements, or binary, ternary and multi-element III-V semiconductor materials with different band gaps formed by III elements and V elements.

10. The method according to claim 8, characterized in that, The methods for forming the ohmic contact layer and the III-V substrate are all selected from one or a combination of several of the following methods: hydride vapor phase epitaxy, metal-organic chemical vapor deposition, molecular beam epitaxy, ammonothermal method, and Na flux method.

11. The method according to claim 8, characterized in that, The supporting substrate includes a GaN single crystal substrate, a sapphire substrate, a Si substrate, or a SiC substrate.

12. The method according to claim 8, characterized in that, The supporting substrate is removed by laser peeling or grinding.

13. A method for preparing a composite substrate, characterized in that, include: An ohmic contact layer is provided, wherein the ohmic contact layer is made of a group III-V material and has a group III polar facet and a group V polar facet. The ohmic contact layer is made of a high carrier concentration GaN material, and the thickness of the ohmic contact layer is 10 nm-1000 μm. The high carrier concentration GaN material is doped with shallow-level donor impurities, and the carrier concentration is higher than 1 × 10⁻⁶. 19 cm -3 The GaN material wherein the shallow-level donor impurity is Si, Ge, or O; A III-V substrate is formed on the III-V polar surface of the ohmic contact layer. The III-V substrate is a low-impurity epitaxial layer with a thickness of 1 μm-1000 μm and a carrier concentration of less than 1 × 10⁻⁶. 17 cm -3 .

14. The method according to claim 13, characterized in that, The ohmic contact layer is made of high-conductivity GaN single crystal material with a thickness of 1μm-1000μm.

15. The method according to claim 13, characterized in that, The method for forming III-V group substrates is selected from one or a combination of several of the following methods: hydride vapor phase epitaxy, metal-organic chemical vapor deposition, molecular beam epitaxy, ammonothermal method, and Na flux method.

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