Output buffer circuit with non-target ODT function

Abstract

A device is disclosed herein, comprising: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power supply potential; a first tri-state circuit comprising an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tri-state circuit comprising an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up transistor and the pull-down transistor have threshold voltages different from those of the first pull-up transistor and the pull-down transistor.

Description

Background Art

[0001] Semiconductor devices such as DRAM have an ODT function that causes an output buffer to function as a termination resistor. In recent years, there are cases where a transistor having a low threshold is used in a circuit in a preceding stage of an output buffer to increase the speed of a data path to the output buffer. Therefore, when such semiconductor devices perform a non-target ODT operation that causes an output buffer to function as a termination resistor when the semiconductor device is in an unselected state, there is a problem that a leakage current increases when the semiconductor device is in an unselected state. Summary of the invention

[0002] According to at least one example disclosed herein, a device may include a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power supply potential; a first tri-state circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tri-state circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level, wherein the second pull-up transistor and the pull-down transistor have threshold voltages different from those of the first pull-up transistor and the pull-down transistor.

[0003] According to at least one example disclosed herein, a device may include a data terminal; an output transistor connected between the data terminal and a first power line supplying a first power supply potential; a first tri-state circuit including an output node connected to a control electrode of the output transistor; a second tri-state circuit including an output node connected to the control electrode of the output transistor; and a third tri-state circuit including an output node connected to the control electrode of the output transistor, wherein the first tri-state circuit is activated when a speed mode signal indicates a high-speed mode, wherein the second tri-state circuit is activated when the speed mode signal indicates a low-speed mode, and wherein the third tri-state circuit is activated when a non-target ODT signal is activated regardless of the speed mode signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram showing a configuration of a semiconductor device according to the present disclosure.

[0005] Figure 2A is a block diagram showing a circuit of a data output system included in an I / O circuit.

[0006] Figure 2B is a block diagram showing the configuration of a pull-up circuit.

[0007] Figure 2C is a block diagram showing the configuration of a pull-down circuit.

[0008] Figure 2D is a block diagram showing the configuration of a pull-up pre-emphasis circuit.

[0009] Figure 2E is a block diagram showing the configuration of a pull-down pre-emphasis circuit.

[0010] Figure 3 is a diagram for explaining the flow of pull-up data and pull-down data.

[0011] Figure 4 is a circuit diagram showing the signal path in the pull-down circuit in more detail.

[0012] Figure 5A and 5B This is a circuit diagram of the adjustment circuit.

[0013] Figure 6 This is a circuit diagram of the pre-emphasis circuit on the pull-down side.

[0014] Figure 7 is a circuit diagram showing the signal path in the pull-up circuit in more detail.

[0015] Figure 8 This is a circuit diagram of the pre-emphasis circuit on the pull-up side.

[0016] Fig. 9 is a timing chart for explaining the operation of the semiconductor device according to an embodiment of the present disclosure.

[0017] Fig.10 is a timing chart showing the relationship between the power gating operation and the reset signal.

[0018] Fig.11 : is a timing chart showing an example in which the change timing of the reset signal changes according to the potential.

[0019] Fig.12 is a timing chart showing the change timing of the reset signal when the mode of the speed mode signal is switched. DETAILED DESCRIPTION

[0020] Various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that illustrate specific aspects and embodiments of the present invention that can be practiced by means of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be used and structural, logical and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0021] For example, Figure 1 The semiconductor device 10 shown in FIG. 1 is a low power double data rate 5 (LPDDR5) DRAM, and has a memory cell array 11, an access control circuit 12 that accesses the memory cell array 11, and an I / O circuit 13 that inputs data to and outputs data from the memory cell array 11. The access control circuit 12 accesses the memory cell array 11 based on a command address signal CA input from an external controller via a command address terminal 14. In a read operation, data DQ read out from the memory cell array 11 is output to a data terminal 15 via the I / O circuit 13. In a write operation, data DQ input to the data terminal 15 from an external controller is supplied to the memory cell array 11 via the I / O circuit 13. In addition, in an ODT operation, an output buffer included in the I / O circuit 13 acts as a termination resistor.

[0022] Figure 2A FIG. 1 shows a circuit block of a data output system included in the I / O circuit 13, which is associated with one data terminal 15. Figure 2A As shown in FIG. 1 , the I / O circuit 13 includes a serializer 20 that converts parallel data DATA read out from the memory cell array 11 into serial data. The serial data output from the serializer 20 includes pull-up data DATAu and pull-down data DATAd. The pull-up data DATAu and the pull-down data DATAd are signals complementary to each other.

[0023] The pull-up data DATAu is supplied to the pull-up circuit 21 and the pre-emphasis circuit 23. In the pull-up operation, that is, when the high-level read data DQ is output from the data terminal 15, the pull-up circuit 21 is activated. Figure 2BAs shown in , the pull-up circuit 21 includes three pull-up drive circuits 30H to 32H belonging to the high-speed path and three pull-up drive circuits 30L to 32L belonging to the low-speed path. Whether to use the high-speed path or the low-speed path is selected based on the speed mode signal Hs input to the drive circuit 330. In the case where the high-speed path is selected, one or two or more of the pull-up drive circuits 30H to 32H are selected based on the drive strength selection signal DS. In the case where the low-speed path is selected, one or two or more of the pull-up drive circuits 30L to 32L are selected based on the drive strength selection signal DS. The driver sizes of the pull-up drive circuits 30H to 32H may be different from each other. Similarly, the driver sizes of the pull-up drive circuits 30L to 32L may be different from each other. Each of the pull-up drive circuits 30H to 32H and 30L and 32L includes an output impedance calibration circuit 50 to 53. These output impedance calibration circuits equally and selectively drive the adjustment MOS transistors having impedances equal to each other included in a plurality of output stage circuits based on the impedance selection signal ZQ, and the driving manner is such that the impedance of each output stage circuit is calibrated to a desired value. The number of associated output stage circuits is different among the pull-up driving circuits 30H / L to 32H / L. For example, the circuit 30H / L is associated with three output stage circuits, the circuit 31H / L is associated with two output stage circuits, and the circuit 32H / L is associated with one output stage circuit. In this case, each of the output impedance calibration circuits 50 to 53 in the circuit 30H / L drives the adjustment MOS transistors of three output stage circuits, each of the output impedance calibration circuits 50 to 53 in the circuit 31H / L drives the adjustment MOS transistors of two output stage circuits, and each of the output impedance calibration circuits 50 to 53 in the circuit 32H / L drives the adjustment MOS transistor of one output stage circuit. Therefore, it is possible to select the output impedance in the pull-up operation as an accurate impedance having a desired driving strength. In addition, the speed mode signal Hs and the slew rate selection signal SR are also commonly supplied to the output impedance calibration circuits 50 to 53.

[0024] The pull-down data DATAd is supplied to the pull-down circuit 22 and the pre-emphasis circuit 24. In the pull-down operation, that is, when the low-level read data DQ is output from the data terminal 15, the pull-down circuit 22 is activated. In addition, the driving circuit 120 included in the pull-down circuit 22 is activated when the non-target ODT operation is performed. Figure 2C As shown in FIG. 1 , the pull-down circuit 22 includes three pull-down driving circuits 40H to 42H belonging to a high-speed path and three pull-down driving circuits 40L to 42L belonging to a low-speed path. Figure 2CAlso shown is a driving circuit 120 that performs a non-target ODT operation. Whether to use a high-speed path or a low-speed path is selected based on a speed mode signal Hs input to the driving circuit 130. In the case where the high-speed path is selected, one or two or more of the pull-down driving circuits 40H to 42H are selected based on the drive strength selection signal DS. In the case where the low-speed path is selected, one or two or more of the pull-down driving circuits 40L to 42L are selected based on the drive strength selection signal DS. The driver sizes of the pull-down driving circuits 40H to 42H may be different from each other. Similarly, the driver sizes of the pull-down driving circuits 40L to 42L may be different from each other. Each of the pull-down driving circuits 40H to 42H and 40L and 42L includes output impedance calibration circuits 60 to 63. These output impedance calibration circuits selectively drive the adjustment MOS transistors having equal impedances contained in a plurality of output stage circuits equally based on the impedance selection signal ZQ, and the driving method is such that the impedance of each output stage circuit is calibrated to a desired value. The number of associated output stage circuits is different among the pull-down driving circuits 40H / L to 42H / L. For example, the circuit 40H / L is associated with three output stage circuits, the circuit 41H / L is associated with two output stage circuits, and the circuit 42H / L is associated with one output stage circuit. In this case, each of the output impedance calibration circuits 60 to 63 in the circuit 40H / L drives the adjustment MOS transistors of three output stage circuits, each of the output impedance calibration circuits 60 to 63 in the circuit 41H / L drives the adjustment MOS transistors of two output stage circuits, and each of the output impedance calibration circuits 60 to 63 in the circuit 42H / L drives the adjustment MOS transistor of one output stage circuit. Therefore, it is possible to select the output impedance in the pull-down operation as an accurate impedance with the desired driving strength. In addition, the speed mode signal Hs and the slew rate selection signal SR are also supplied to the output impedance calibration circuits 60 to 63 in common.

[0025] The pull-down circuit 22 includes a driving circuit 120 for performing a non-target ODT operation. The driving circuit 120 is configured by a portion of the pull-down driving circuits 40H / L to 42H / L and a portion of the output impedance calibration circuits 60 to 63, and is activated when performing a non-target ODT operation regardless of the speed mode signal Hs. Which of the pull-down driving circuits 40H / L to 42H / L is activated in the non-target ODT operation is selected based on the driving strength selection signal DSnt not included for the non-target ODT operation. The impedance of the output impedance calibration circuits 60 to 63 in the non-target ODT operation is specified by the impedance selection signal ZQ.

[0026] Each of the pre-emphasis circuits 23 and 24 temporarily reduces its output resistance only during the data period transition, thereby compensating for the loss caused by the skin effect and the dielectric loss generated in the high frequency operation. Therefore, it is possible to allow the data transition to occur at an appropriate slew rate even in the high frequency operation and drive the data terminal 15 with the set resistance in the stable state.

[0027] When the read data DQ changes to a high level, the pre-emphasis circuit 23 is activated, thereby making the rising edge of the read data DQ steeper. Figure 2D As shown in FIG. 1 , the pre-emphasis circuit 23 includes a one-shot pulse generating circuit 420, pull-up driving circuits 33H and 34H belonging to a high-speed path, and a pull-up driving circuit 33L belonging to a low-speed path. Each of the pull-up driving circuits 33H and 33L includes three driving circuits 54 to 56 selected by the pre-emphasis operation start signal / PEmpStr.

[0028] When the read data DQ changes to a low level, the pre-emphasis circuit 24 is activated, thereby making the falling edge of the read data DQ steeper. Figure 2E As shown in FIG. 1 , the pre-emphasis circuit 24 includes a one-shot pulse generating circuit 220, pull-down driving circuits 43H and 44H belonging to a high-speed path, and a pull-down driving circuit 43L belonging to a low-speed path. Each of the pull-down driving circuits 43H and 43L includes three driving circuits 64 to 66 selected by the pre-emphasis operation start signal / PEmpStr.

[0029] Figure 3 1 is a schematic diagram for explaining the flow of pull-up data DATAu and pull-down data DATAd. Figure 3 As shown, the pull-up data DATAu is supplied to the gate electrode of the output transistor 71 via the high-speed path 80 or the low-speed path 81. In the fan-out, the high-speed path 80 is smaller than the low-speed path 81. The output transistor 71 is an N-channel MOS transistor. Whether to use the high-speed path 80 or the low-speed path 81 is selected based on the speed mode signal. The outputs of the high-speed path 80 and the low-speed path 81 are supplied to the gate electrode of the output transistor 71 via the multiplexer 91. The pull-down data DATAd is supplied to the gate electrode of the output transistor 72 via the high-speed path 82 or the low-speed path 83. In the fan-out, the high-speed path 82 is smaller than the low-speed path 83. The output transistor 72 is an N-channel MOS transistor. Whether to use the high-speed path 82 or the low-speed path 83 is selected based on the speed mode signal. The outputs of the high-speed path 82, the low-speed path 83 and the non-target ODT path 84 are supplied to the gate electrode of the output transistor 72 via the multiplexer 92. As shown Figure 3As shown, both high-speed paths 80 and 82 include gate circuits arranged in six stages, while both low-speed paths 81 and 83 include gate circuits arranged in four stages. The non-target ODT path 84 is selected when the non-target ODT enable signal NTe is activated. The non-target ODT enable signal NTe is kept active at a high level except during a read operation and a write operation in which the output circuit is activated. When the non-target ODT enable signal NTe is active, all other paths 80 to 83 are inactive.

[0030] In the case where the speed mode signal indicates the high-speed mode, the high-speed paths 80 and 82 are activated in the read operation, and the ODT path 82T in the high-speed path 82 is activated in the target ODT operation. On the other hand, in the case where the speed mode signal indicates the low-speed mode, the low-speed paths 81 and 83 are activated in the read operation, and the ODT path 83T in the low-speed path 83 is activated in the target ODT operation. The target ODT paths 82T and 83T are selected when the target ODT enable signal Te is activated. The target ODT enable signal Te is activated in the write operation. When the target ODT enable signal Te is activated, the parts of the pull-up side paths 80 and 81 and the pull-down side paths 82 and 83 other than the target ODT paths 82T and 83T are inactive.

[0031] The switching transistor 70, the output transistor 71, and the output transistor 72 are connected in series with each other between the high potential side power line and the low potential side power line. The switching transistor 70 is an N-channel MOS transistor in which a gate insulating film is formed thick, and a reset signal / SCr is supplied to its gate electrode. The reset signal / SCr is an inverted signal of the reset signal SCr that becomes low in the read operation. The data terminal 15 is connected to the connection point between the output transistor 71 and the output transistor 72. At Figure 3 In and subsequent figures, a transistor in which a straight line opposite to its gate electrode is indicated by a bold line is a transistor in which its gate insulating film is formed thick.

[0032] Figure 4 2 is a circuit diagram showing the signal path in the pull-down circuit 22 in more detail. Figure 2C As described, the pull-down circuit 22 includes three pull-down drive circuits 40H to 42H and three pull-down drive circuits 40L to 42L. Each of the pull-down drive circuits 40H to 42H and 40L to 42L includes four output impedance calibration circuits 60 to 63. The pull-down drive circuits 40H / L to 42H / L have the same circuit configuration as each other, and the output impedance calibration circuits 60 to 63 have the same circuit configuration as each other. Therefore, the parts having the same circuit configuration are Figure 4 Shown together.

[0033] The output impedance calibration circuits 60 to 63 each include three tri-state buffer circuits 100, 110, and 120. The output nodes of the tri-state buffer circuits 100, 110, and 120 are commonly connected to the gate electrode of the output transistor 72A. That is, the output nodes of the tri-state buffer circuits 100, 110, and 120 are connected in a wired OR connection and configured. Figure 3 The multiplexer 92 is shown in FIG. The output transistor 72A is Figure 3 , which is included in the pull-down driving circuits 40H / L to 42H / L. The leakage current in the output transistor 72A is increased to an appropriate level, so that the output transistor 72A has an improved driving capability.

[0034] The tri-state buffer circuit 100 belongs to the high-speed path 82 and includes transistors 101 to 106 connected in series with each other between the high-potential side power line and the low-potential side power line. Transistors 101 and 106 are N-channel MOS transistors, each of which has a gate insulating film formed to be thick, and a control signal / SCw*Hs is supplied to its gate electrode. The control signal / SCw*Hs is an AND signal of an inverted signal of a reset signal SCw that becomes low during a read operation and a write operation and a speed mode signal Hs, and uses a boost potential VCCP. The speed mode signal Hs becomes high in the high-speed mode and becomes low in the low-speed mode. Transistor 102 is configured as an adjustment circuit that is activated when a corresponding one of the output impedance calibration circuits 60 to 63 is selected. As Figure 5A As shown in FIG. 1 , the transistor 102 is composed of three P-channel MOS transistors 102 connected in parallel to each other. 0 To 102 2 Configuration. Control signals / (SR0*ZQ* / PD) to / (SR2*ZQ*PD) are respectively supplied to transistor 102 0 To 102 2 The control signals SR0 to SR2 are bit signals for configuring the slew rate selection signal SR. The control signal ZQ is a signal for selecting whether the corresponding output impedance calibration circuit among the output impedance calibration circuits 60 to 63 is in action or inactive. The control signal / PD is an inverted signal of the power-down signal PD which becomes high when the power drops. The transistor 105 also configures the adjustment circuit. Figure 5B As shown in FIG. 1 , the transistor 105 is composed of three N-channel MOS transistors 105 connected in parallel to each other. 0 To 105 2 Configuration. Bit signals SR0 to SR2 configuring the slew rate selection signal SR are supplied to transistors 105, respectively. 0 To 105 2The transistor 103 is a P-channel MOS transistor that receives the output of the NAND gate circuit 151 included in the logic circuit 150 at the previous stage. The transistor 104 is an N-channel MOS transistor that receives the output of the NOR gate circuit 152 included in the logic circuit 150 at the previous stage. The transistors 102 to 105 each have a reduced threshold voltage, and thus can perform high-speed switching. Figure 4 In the following figures, transistors whose both ends are marked with bold lines are transistors with reduced threshold voltages. In addition, among inverter circuits, NAND gate circuits, and NOR gate circuits, circuits with input nodes marked with bold lines are circuits using transistors with reduced threshold voltages.

[0035] The pull-down data DATAd is input to the tri-state buffer circuit 100 via the logic circuits 130 and 150 and the logic circuit 140 included in the highway path 82. The logic circuit 130 includes inverter circuits 131 and 132 connected to each other in a cascade manner, transistors 133 and 134 that reset the highway path 82, and transistors 135 and 136 that activate the inverter circuits 131 and 132. The control signal / RSr*Hs is supplied to the gate electrodes of the transistors 133 and 135. The control signal / SCr*Hs is supplied to the gate electrodes of the transistors 134 and 136. The reset signal / RSr is an inverted signal of the reset signal RSr that becomes low during the read operation. The logic circuit 140 includes NAND gate circuits 141 and 142 connected to each other in a cascade manner, transistors 143 and 144 that reset the highway path 82, and transistors 145 and 146 that activate the NAND gate circuits 141 and 142. The output signal of the logic circuit 130 and the drive strength selection signal DSd are input to the NAND gate circuit 141. The drive strength selection signal DSd is a signal for selecting whether the corresponding pull-down drive circuit among the pull-down drive circuits 40H / L to 42H / L is in action or inaction. The output signal of the NAND gate circuit 141 and the inverted signal of the target ODT enable signal Te are input to the NAND gate circuit 142. The control signal / RSr*Hs is supplied to the gate electrodes of the transistors 143 and 145. The control signal / SCw*Hs is supplied to the gate electrodes of the transistors 144 and 146. The logic circuit 150 includes a NAND gate circuit 151, a NOR gate circuit 152, a transistor 153 that fixes the gate electrode of the transistor 103 at a high level, a transistor 154 that fixes the gate electrode of the transistor 104 at a low level, a transistor 155 that activates the NAND gate circuit 151, and transistors 156 and 157 that activate the NOR gate circuit 152. The output signal of the logic circuit 140 and the inverted signal of the non-target ODT enable signal NTe are input to the NAND gate circuit 151. The output signal of the logic circuit 140 and the non-target ODT enable signal NTe are input to the NOR gate circuit 152. The control signal / SCw*Hs is supplied to the gate electrodes of the transistors 153 and 155 to 157. The inverted signal / ( / SCw*Hs) of the control signal / SCw*Hs is supplied to the gate electrode of the transistor 154. Since N-channel MOS transistors each including a gate insulating film formed thick are used as the transistors 155 to 157, the influence of process variation, especially on the transistor 156, can be reduced, and the occupied area can also be reduced, compared with the case of using a standard P-channel MOS transistor whose ability to supply current is low.The power supply potential VDD2 lower than the boost potential VCCP is used only for the control signals / SCr*Hs and / SCw*Hs used in the logic circuits 130 and 140, while the boost potential VCCP is used for the control signal / SCw*Hs used in the logic circuit 150 and the subsequent circuit for driving the thick film transistor. By this configuration, in the case where the speed mode signal Hs indicates the high-speed mode, any one of the transistors 103 and 104 is turned on based on the pull-down data DATAd in the read operation, and the transistor 103 is turned on in the target ODT operation. Therefore, the output node of the tri-state buffer circuit 100 is driven to a high level or a low level. On the other hand, in the case where the speed mode signal Hs indicates the low-speed mode or during the non-target ODT operation, the output node of the tri-state buffer circuit 100 is placed in a high impedance state. The high impedance state of the tri-state buffer circuit 100 is achieved by turning off the transistors 103 and 104 for access or turning off the transistors 101 and 106 for switching. When the transistors 103 and 104 for access are turned off, the parasitic capacitance of the output node of the tri-state buffer circuit 100 is reduced. When the transistors 106 and 101 for switching are turned off, the subthreshold leakage in the inactive state is reduced. In addition, since N-channel MOS transistors each including a gate insulating film formed thick are used as the transistors 101 and 106 for switching, the influence of process variation, especially on the transistor 101, can be reduced, the occupied area can be reduced, and charge injection can be prevented when ESD occurs, compared with the case of using a standard P-channel MOS transistor with a low supply current capability.

[0036] The tri-state buffer circuit 110 belongs to the low-speed path 83 and includes transistors 111 to 116 connected in series with each other between the high potential side power supply line and the low potential side power supply line. The tri-state buffer circuit 110 has the same circuit configuration as the tri-state buffer circuit 100. The same signal as the signal input to the gate electrodes of the transistors 101, 102, 105, and 106 is input to the gate electrodes of the transistors 111, 112, 115, and 116, except that the speed mode signal HS is inverted.

[0037] The pull-down data DATAd is input to the tri-state buffer circuit 110 via the logic circuits 160 and 170 included in the low-speed path 83. The logic circuit 160 includes NAND gate circuits 161 and 162 connected to each other in a cascade manner, transistors 163 and 164 that reset the low-speed path 83, and transistors 165 and 166 that activate the NAND gate circuits 161 and 162. The pull-down data DATAd and the drive strength selection signal DSd are input to the NAND gate circuit 161. The output signal of the NAND gate circuit 161 and the inverted signal of the target ODT enable signal Te are input to the NAND gate circuit 162. The control signal / RSr* / Hs is supplied to the gate electrodes of the transistors 163 and 165. The control signal / SCw* / Hs is supplied to the gate electrodes of the transistors 164 and 166. The logic circuit 170 includes a NAND gate circuit 171, a NOR gate circuit 172, a transistor 173 that fixes the gate electrode of the transistor 113 at a high level, a transistor 174 that fixes the gate electrode of the transistor 114 at a low level, a transistor 175 that activates the NAND gate circuit 171, and transistors 176 and 177 that activate the NOR gate circuit 172. The output signal of the logic circuit 160 and the inverted signal of the non-target ODT enable signal NTe are input to the NAND gate circuit 171. The output signal of the logic circuit 160 and the non-target ODT enable signal NTe are input to the NOR gate circuit 172. The control signal / SCw* / Hs is supplied to the gate electrodes of the transistors 173 and 175 to 177. The inverted signal of the control signal / SCw* / Hs is supplied to the gate electrode of the transistor 174. Only the power supply potential VDD2 lower than the boost potential VCCP is used for the control signal / SCw* / Hs used in the logic circuit 160, and the boost potential VCCP is used for the control signal / SCw* / Hs used in the logic circuit 170 and the subsequent circuit for driving the thick film transistor. By this configuration, in the case where the speed mode signal Hs indicates the low speed mode, either one of the transistors 113 and 114 is turned on based on the pull-down data DATAd during the read operation, and the transistor 113 is turned on during the target ODT operation. Therefore, the output node of the tri-state buffer circuit 110 is driven to a high level or a low level. On the other hand, in the case where the speed mode signal Hs indicates the high speed mode or during the non-target ODT operation, the output node of the tri-state buffer circuit 110 is placed in a high impedance state.

[0038] The tri-state buffer circuit 120 belongs to the non-target ODT path 84 and includes transistors 121 to 125 connected in series with each other between the high potential side power line and the low potential side power line. Transistors 121 and 125 are N-channel MOS transistors, each of which has a gate insulating film formed as a thick layer, and a control signal PwUp is supplied to its gate electrode. The control signal PwUp maintains a low level during the transition period of the power-on operation after the power is turned on, and becomes high when the power-on operation is completed. Transistor 122 is a P-channel MOS transistor with a normal threshold voltage, and a control signal / ZQ is supplied to its gate electrode. Transistor 123 is a P-channel MOS transistor that receives the output of the NAND gate circuit 181 included in the logic circuit 180 at the previous stage. Transistor 124 is an N-channel MOS transistor that receives the output of the NOR gate circuit 182 included in the logic circuit 180 at the previous stage. Both transistors 123 and 124 have normal thresholds. The non-target ODT path 84 is activated in a plurality of periods including a power-off period other than the period in which the high-speed path 82 or the low-speed path 83 is in effect. Therefore, the subthreshold current is reduced by using the transistors 123 and 124 each having a normal threshold voltage. In addition, since N-channel MOS transistors each including a gate insulating film formed thick are used as the transistors 121 and 125, charge injection can be prevented when ESD occurs.

[0039] The non-target ODT enable signal NTe and the AND signal of the drive strength selection signal DSnt and the non-target ODT mode signal NT are supplied to the NAND gate circuit 181. The inverted signal of the non-target ODT enable signal NTe and the AND signal of the drive strength selection signal DSnt and the non-target ODT mode signal NT are supplied to the NOR gate circuit 182. The drive strength selection signal DSnt is a signal for selecting the drive strength in the non-target ODT operation. The non-target ODT mode signal NT is a mode signal for selecting whether to perform the non-target ODT operation. Through this configuration, in the case where the non-target ODT operation is allowed, the transistor 123 is turned on when the non-target ODT enable signal NTe is activated. Therefore, the output node of the tri-state buffer circuit 120 is driven to a high level. However, because the transistors 122 to 124 have normal threshold voltages, respectively, the leakage current during the non-target ODT operation is reduced. On the other hand, in the case where the non-target ODT operation is not allowed or the non-target ODT enable signal NTe is not activated, the output node of the tri-state buffer circuit 120 is placed in a high impedance state.

[0040] In addition, the output impedance calibration circuits 60 to 63 each include N-channel MOS transistors 191 to 194 that reset the gate electrode of the output transistor 72A to a low level. Control signals / PwUp and / NT*SCw, control signal / ZQ, and control signal / ( / NT*SCw) are supplied to the gate electrodes of transistors 191 to 194, respectively. Transistors 191, 192, and 194 are N-channel MOS transistors, each of which has a gate insulating film formed to be thick. Because the N-channel MOS transistors each include a gate insulating film formed to be thick as transistors 191, 192, and 194, charge injection can be prevented when ESD occurs. In addition, the amplitude of the control signal / PwUp input to the transistor 191 is not the boost potential VCCP but the external power supply potential VDD1. Therefore, immediately after the power is turned on, the gate electrode of the output transistor 72A is surely fixed at a low level. On the other hand, the amplitudes of the control signals / NT*SCw and / ( / NT*SCw) are VCCP, and the amplitude of the control signal / ZQ is VDD2. When the current mode is not the non-target ODT mode and the reset signal SCw is in effect, the transistor 192 is turned on. In the non-target ODT mode or when the reset signal SCw is inactive and the corresponding output impedance calibration circuit in the output impedance calibration circuits 60 to 63 is not selected, the reset circuit configured by the transistors 193 and 194 is turned on.

[0041] Figure 6 2 is a circuit diagram of the pre-emphasis circuit 24. The pre-emphasis circuit 24 includes two tri-state buffer circuits 200 and 210. The output nodes of the tri-state buffer circuits 200 and 210 are commonly connected to the gate electrode of the output transistor 72B. That is, the output nodes of the tri-state buffer circuits 200 and 210 are connected in a wired OR connection and configured. Figure 3 The multiplexer 92 is shown in FIG. 1 . The output transistor 72B is Figure 3 One of the output transistors 72 shown in FIG. 1 , which is included in the pre-emphasis circuit 24 .

[0042] The tri-state buffer circuit 200 belongs to the high-speed path 82 and includes transistors 201 to 205 connected in series with each other between the high potential side power supply line and the low potential side power supply line. Transistors 201 and 205 are N-channel MOS transistors, each of which has a gate insulating film formed to be thick, and a control signal / SCw*Hs is supplied to its gate electrode. The pre-emphasis operation start signal / PEmpStr is input to the gate electrode of transistor 202. Transistor 203 is a P-channel MOS transistor that receives the output of the NAND gate circuit 251 included in the logic circuit 250 in the previous stage. Transistor 204 is an N-channel MOS transistor that receives the output of the NOR gate circuit 252 included in the logic circuit 250 in the previous stage. Transistors 202 to 204 have a reduced threshold value, respectively, and thus can perform high-speed switching.

[0043] The pull-down data DATAd is supplied to a one-shot pulse generating circuit 220. The one-shot pulse generating circuit 220 includes a NAND gate circuit 221 receiving the pull-down data DATAd and a pull-down pre-emphasis enable signal PEmpEnPd, a NAND gate circuit 222 receiving an output signal of the NAND gate circuit 221 and the pull-down pre-emphasis enable signal PEmpEnPd, an inverter circuit 223 cascade-connected as a subsequent stage of the NAND gate circuit 222, wherein the number of the inverter circuits 223 is an odd number, and an N-channel MOS transistor 224 supplying power to the NAND gate circuits 221 and 222 and the inverter circuit 223. A reset signal / SCr is supplied to a gate electrode of the transistor 224. The pull-down pre-emphasis enable signal PEmpEnPd selects whether to perform a pre-emphasis operation at a falling edge of the read data DQ. Therefore, in the case where the pull-down pre-emphasis enable signal PEmpEnPd is in effect at a high level, the one-shot signal EmpPd is generated in synchronization with the rising edge of the pull-down data DATAd from the one-shot pulse generating circuit 220. The one-shot pulse generating circuit 220 does not use a NOR gate circuit requiring a plurality of P-channel MOS transistors connected in series, but is configured by using a NAND gate circuit requiring no plurality of P-channel MOS transistors connected in series, and thus it is suitable for high-speed operation.

[0044] The one-shot signal EmpPd and the pull-down data DATAd are input to the tri-state buffer circuit 200 via the logic circuits 230 and 240 and the logic circuit 250 included in the highway 82. The logic circuit 230 includes a NAND gate circuit 231 receiving the one-shot signal EmpPd and the pull-down data DATAd, an inverter circuit 232, transistors 233 and 234 that reset the highway 82, and transistors 235 and 236 that activate the NAND gate circuit 231 and the inverter circuit 232. The control signal / RSr*Hs is supplied to the gate electrodes of the transistors 233 and 235. The control signal / SCr*Hs is supplied to the gate electrodes of the transistors 234 and 236. The logic circuit 240 includes inverter circuits 241 and 242 that are cascade-connected to each other, transistors 243 and 244 that reset the highway 82, and transistors 245 and 246 that activate the inverter circuits 241 and 242. The control signal / RSr*Hs is supplied to the gate electrodes of the transistors 243 and 245. The control signal / SCw*Hs is supplied to the gate electrodes of the transistors 244 and 246. The logic circuit 250 includes a NAND gate circuit 251, a NOR gate circuit 252, a transistor 253 that fixes the gate electrode of the transistor 203 at a high level, a transistor 254 that fixes the gate electrode of the transistor 204 at a low level, a transistor 255 that activates the NAND gate circuit 251, and transistors 256 and 257 that activate the NOR gate circuit 252. The output signal of the logic circuit 240 and the fixed high level signal are input to the NAND gate circuit 251. The output signal of the logic circuit 240 and the control signal / ( / SCw*Hs) are input to the NOR gate circuit 252. The control signal / SCw*Hs is supplied to the gate electrodes of the transistors 253 and 255 to 257. The inverted signal / ( / SCw*Hs) of the control signal / SCw*Hs is supplied to the gate electrode of the transistor 254. By this configuration, in the case where the speed mode signal Hs indicates the high-speed mode, the transistor 203 is temporarily turned on when the pull-down data DATAd changes to a high level in the read operation. Therefore, the output transistor 72B is temporarily turned on, so that the pre-emphasis operation in the pull-down state is performed. On the other hand, in the case where the speed mode signal Hs indicates the low-speed mode, the output node of the tri-state buffer circuit 200 is placed in a high-impedance state.

[0045] The tri-state buffer circuit 210 belongs to the low speed path 83 and includes transistors 211 to 215 connected in series with each other between the high potential side power supply line and the low potential side power supply line. The tri-state buffer circuit 210 has the same circuit configuration as the tri-state buffer circuit 200. The same signal as the signal input to the gate electrodes of the transistors 201, 202, and 205 is input to the gate electrodes of the transistors 211, 212, and 215, except that the speed mode signal HS is inverted.

[0046] The one-shot signal EmpPd and the pull-down data DATAd are input to the tri-state buffer circuit 210 via logic circuits 260 and 270 included in the low-speed path 83. The logic circuit 260 includes a NAND gate circuit 261 that receives the one-shot signal EmpPd and the pull-down data DATAd, an inverter circuit 262, transistors 263 and 264 that reset the low-speed path 83, and transistors 265 and 266 that activate the NAND gate circuit 261 and the inverter circuit 262. The control signal / RSr* / Hs is supplied to the gate electrodes of the transistors 263 and 265. The control signal / SCw*Hs is supplied to the gate electrodes of the transistors 264 and 266. The logic circuit 270 includes a NAND gate circuit 271, a NOR gate circuit 272, a transistor 273 that fixes the gate electrode of the transistor 213 at a high level, a transistor 274 that fixes the gate electrode of the transistor 214 at a low level, a transistor 275 that activates the NAND gate circuit 271, and transistors 276 and 277 that activate the NOR gate circuit 272. The output signal of the logic circuit 260 and the fixed high level signal are input to the NAND gate circuit 271. The output signal of the logic circuit 260 and the control signal / ( / SCw* / Hs) are input to the NOR gate circuit 272. The control signal / SCw* / Hs is supplied to the gate electrodes of the transistors 273 and 275 to 277. The inverted signal / ( / SCw* / Hs) of the control signal / SCw* / Hs is supplied to the gate electrode of the transistor 274. By this configuration, in the case where the speed mode signal Hs indicates the low speed mode, when the pull-down data DATAd changes to a high level in the read operation, the transistor 213 is temporarily turned on. Therefore, the output transistor 72B is temporarily turned on, so that the pre-emphasis operation in the pull-down state is performed. On the other hand, in the case where the speed mode signal Hs indicates the high speed mode, the output node of the tri-state buffer circuit 210 is placed in a high impedance state.

[0047] In addition, the pre-emphasis circuit 24 includes N-channel MOS transistors 291 to 294 that reset the gate electrode of the output transistor 72B to a low level. Control signals / PwUp, SCw, and / PEmpStr and the control signal / SCw are supplied to the gate electrodes of the transistors 291 to 294, respectively. The transistors 291, 292, and 294 are N-channel MOS transistors, each of which has a gate insulating film formed to be thick. In addition, the amplitude of the control signal / PwUp input to the transistor 291 is not the boost potential VCCP but the external power supply potential VDD1. At the same time, the amplitudes of the control signals SCw and / SCw are VCCP, and the amplitude of the control signal / PEmpStr is VDD2.

[0048] In the pre-emphasis circuit 24, driving circuits 64 to 66 are provided in parallel.

[0049] Figure 72 is a circuit diagram showing the signal path in the pull-up circuit 21 in more detail. Figure 2B As described, the pull-up circuit 21 includes three pull-up drive circuits 30H to 32H and three pull-up drive circuits 30L to 32L. Each of the pull-up drive circuits 30H to 32H and 30L to 32L includes four output impedance calibration circuits 50 to 53. The pull-up drive circuits 30H / L to 32H / L have the same circuit configuration as each other, and the output impedance calibration circuits 50 to 53 have the same circuit configuration as each other. Therefore, in Figure 7 Parts with the same configuration are shown together.

[0050] The output impedance calibration circuits 50 to 53 each include two tri-state buffer circuits 300 and 310. The output nodes of the tri-state buffer circuits 300 and 310 are commonly connected to the gate electrode of the output transistor 71A. That is, the output nodes of the tri-state buffer circuits 300 and 310 are connected in a wired OR connection and configured. Figure 3 The multiplexer 91 shown in FIG. 71A is an output transistor. Figure 3 One of the output transistors 71 shown in FIG. 1A is included in the pull-up driving circuits 30H / L to 32H / L. In the output transistor 71A, the amount of ion implantation is adjusted to improve linearity and operating voltage margin so that the threshold voltage is lowered.

[0051] The tri-state buffer circuit 300 belongs to the high-speed path 80 and includes transistors 301 to 306 connected in series with each other between the high potential side power supply line and the low potential side power supply line. The transistors 301 and 306 are N-channel MOS transistors, each of which has a gate insulating film formed thick, and a control signal / SCr*Hs is supplied to its gate electrode. The level of the control signal / SCr*Hs input to the transistors 301 and 306 is the boost potential VCCP. The transistors 302 and 305 correspond to Figure 4 302 and 305, and the same signal as the control signal input to the transistors 102 and 105 is input to the transistors 302 and 305. The transistor 303 is a P-channel MOS transistor that receives the output of the NAND gate circuit 351 included in the logic circuit 350 at the previous stage. The transistor 304 is an N-channel MOS transistor that receives the output of the NOR gate circuit 352 included in the logic circuit 350 at the previous stage. The transistors 302 to 305 have a lowered threshold voltage, respectively, and thus can perform high-speed switching.

[0052] The pull-up data DATAu is input to the tri-state buffer circuit 300 via the logic circuits 330 and 340 and the logic circuit 350 included in the highway 80. The logic circuit 330 includes inverter circuits 331 and 332 connected in cascade to each other, transistors 333 and 334 for resetting the highway 80, and transistors 335 and 336 for activating the inverter circuits 331 and 332. The control signal / RSr*Hs is supplied to the gate electrodes of the transistors 333 and 335. The control signal / SCr*Hs is supplied to the gate electrodes of the transistors 334 and 336. The logic circuit 340 includes NAND gate circuits 341 and 342 connected in cascade to each other, transistors 343 and 344 for resetting the highway 80, and transistors 345 and 346 for activating the NAND gate circuits 341 and 342. The output signal of the logic circuit 330 and the drive strength selection signal DSu are input to the NAND gate circuit 341. The driving strength selection signal DSu is a signal for selecting whether the corresponding pull-up driving circuit among the pull-up driving circuits 30H / L to 32H / L is in action or inaction. The output signal of the NAND gate circuit 341 and the fixed high level signal are input to the NAND gate circuit 342. The control signal / RSr*Hs is supplied to the gate electrodes of the transistors 343 and 345. The control signal / SCr*Hs is supplied to the gate electrodes of the transistors 344 and 346. The logic circuit 350 includes a NAND gate circuit 351, a NOR gate circuit 352, a transistor 353 that fixes the gate electrode of the transistor 303 at a high level, a transistor 354 that fixes the gate electrode of the transistor 304 at a low level, a transistor 355 that activates the NAND gate circuit 351, and transistors 356 and 357 that activate the NOR gate circuit 352. The output signal of the logic circuit 340 and the fixed high level signal are input to the NAND gate circuit 351. The output signal of the logic circuit 340 and the control signal / ( / SCr*Hs) are input to the NOR gate circuit 352. The control signal / SCr*Hs is supplied to the gate electrodes of the transistors 353 and 355 to 357. The inverted signal / ( / SCr*Hs) of the control signal / SCr*Hs is supplied to the gate electrode of the transistor 354. The power supply potential VDD2 lower than the boost potential VCCP is used for the control signal / SCr*Hs used in the logic circuits 330 and 340, and the boost potential VCCP is used for the control signal / SCr*Hs used in the logic circuit 350 and the subsequent circuit for driving the thick film transistor. By this configuration, in the case where the speed mode signal Hs indicates the high-speed mode, any one of the transistors 303 and 304 is turned on based on the pull-up data DATAu in the read operation. Therefore, the output node of the tri-state buffer circuit 300 is driven to a high level or a low level. On the other hand, in the case where the speed mode signal Hs indicates the low-speed mode, the output node of the tri-state buffer circuit 300 is placed in a high impedance state.

[0053] The tri-state buffer circuit 310 belongs to the low speed path 81 and includes transistors 311 to 316 connected in series with each other between the high potential side power supply line and the low potential side power supply line. The tri-state buffer circuit 310 has the same circuit configuration as the tri-state buffer circuit 300. The same signal as the signal input to the gate electrodes of the transistors 301, 302, 305, and 306 is input to the gate electrodes of the transistors 311, 312, 315, and 316, except that the speed mode signal Hs is inverted.

[0054] The pull-up data DATAu is input to the tri-state buffer circuit 310 via the logic circuits 360 and 370 included in the low-speed path 81. The logic circuit 360 includes NAND gate circuits 361 and 362 connected in cascade to each other, transistors 363 and 364 for resetting the low-speed path 81, and transistors 365 and 366 for activating the NAND gate circuits 361 and 362. The pull-up data DATAu and the drive strength selection signal DSu are input to the NAND gate circuit 361. The output signal of the NAND gate circuit 361 and the fixed high level signal are input to the NAND gate circuit 362. The control signal / RSr* / Hs is supplied to the gate electrodes of the transistors 363 and 365. The control signal / SCr* / Hs is supplied to the gate electrodes of the transistors 364 and 366. The logic circuit 370 includes a NAND gate circuit 371, a NOR gate circuit 372, a transistor 373 that fixes the gate electrode of the transistor 313 at a high level, a transistor 374 that fixes the gate electrode of the transistor 314 at a low level, a transistor 375 that activates the NAND gate circuit 371, and transistors 376 and 377 that activate the NOR gate circuit 372. The output signal of the logic circuit 360 and the fixed high level signal are input to the NAND gate circuit 371. The output signal of the logic circuit 360 and the control signal / ( / SCr* / Hs) are input to the NOR gate circuit 372. The control signal / SCr* / Hs is supplied to the gate electrodes of the transistors 373 and 375 to 377. The inverted signal of the control signal / SCr* / Hs is supplied to the gate electrode of the transistor 374. The power supply potential VDD2 lower than the boost potential VCCP is used for the control signal / SCr* / Hs used in the logic circuit 360, and the boost potential VCCP is used for the control signal / SCr* / Hs used in the logic circuit 370 and the subsequent circuit for driving the thick film transistor. With this configuration, in the case where the speed mode signal Hs indicates the low speed mode, any one of the transistors 313 and 314 is turned on based on the pull-up data DATAu in the read operation. Therefore, the output node of the tri-state buffer circuit 310 is driven to a high level or a low level. On the other hand, in the case where the speed mode signal Hs indicates the high speed mode, the output node of the tri-state buffer circuit 310 is placed in a high impedance state.

[0055] In addition, the output impedance calibration circuits 50 to 53 each include N-channel MOS transistors 391 to 394 that reset the gate electrode of the output transistor 71A to a low level. Control signals / PwUp, Scr, / ZQ, and / SCr are supplied to the gate electrodes of the transistors 391 to 394, respectively. The transistors 391, 392, and 394 are N-channel MOS transistors, each of which has a gate insulating film formed to be thick. In addition, the amplitude of the control signal / PwUp input to the transistor 391 is not the boost potential VCCP but the external power supply potential VDD1. At the same time, the amplitudes of the control signals Scr and / SCr are VCCP, and the amplitude of the control signal / ZQ is VDD2.

[0056] Figure 8 2 is a circuit diagram of the pre-emphasis circuit 23. The pre-emphasis circuit 23 includes two tri-state buffer circuits 400 and 410. The output nodes of the tri-state buffer circuits 400 and 410 are commonly connected to the gate electrode of the output transistor 71B. That is, the output nodes of the tri-state buffer circuits 400 and 410 are connected in a wired OR connection and configured. Figure 3 The multiplexer 91 shown in FIG. 71B is an output transistor. Figure 3 One of the output transistors 71 shown in FIG. 1 , which is included in the pre-emphasis circuit 23 .

[0057] The tri-state buffer circuit 400 belongs to the high-speed path 80 and includes transistors 401 to 405 connected in series to each other between the high potential side power supply line and the low potential side power supply line. Transistors 401 and 405 are N-channel MOS transistors, each of which has a gate insulating film formed to be thick, and a control signal / SCw*Hs is supplied to its gate electrode. The pre-emphasis operation start signal / PEmpStr is input to the gate electrode of transistor 402. Transistor 403 is a P-channel MOS transistor that receives the output of the NAND gate circuit 451 included in the logic circuit 450 in the previous stage. Transistor 404 is an N-channel MOS transistor that receives the output of the NOR gate circuit 452 included in the logic circuit 450 in the previous stage. Transistors 402 to 404 have a reduced threshold voltage, respectively, and thus can perform high-speed switching.

[0058] The pull-up data DATAu is supplied to a one-shot pulse generating circuit 420. The one-shot pulse generating circuit 420 includes a NAND gate circuit 421 receiving the pull-up data DATAu and the pull-up pre-emphasis enable signal PEmpEnPu, a NAND gate circuit 422 receiving an output signal of the NAND gate circuit 421 and the pull-up pre-emphasis enable signal PEmpEnPu, an inverter circuit 423 cascade-connected as a subsequent stage of the NAND gate circuit 422, wherein the number of the inverter circuits 423 is an odd number, and an N-channel MOS transistor 424 supplying power to the NAND gate circuits 421 and 422 and the inverter circuit 423. A reset signal / SCr is supplied to a gate electrode of the transistor 424. The pull-up pre-emphasis enable signal PEmpEnPu selects whether to perform a pre-emphasis operation at a rising edge of the read data DQ. Therefore, in the case where the pull-up pre-emphasis enable signal PEmpEnPu is in effect at a high level, the one-shot signal EmpPu is generated in synchronization with the rising edge of the pull-up data DATAu from the one-shot pulse generating circuit 420. The one-shot pulse generating circuit 420 does not use a NOR gate circuit requiring a plurality of P-channel MOS transistors connected in series, but is configured by using a NAND gate circuit not requiring a plurality of P-channel MOS transistors connected in series, and therefore it is suitable for high-speed operation.

[0059] The one-shot signal EmpPu and the pull-up data DATAu are input to the tri-state buffer circuit 400 via the logic circuits 430 and 440 and the logic circuit 450 included in the highway 80. The logic circuit 430 includes a NAND gate circuit 431 receiving the one-shot signal EmpPu and the pull-up data DATAu, an inverter circuit 432, transistors 433 and 434 that reset the highway 80, and transistors 435 and 436 that activate the NAND gate circuit 431 and the inverter circuit 432. The control signal / RSr*Hs is supplied to the gate electrodes of the transistors 433 and 435. The control signal / SCr*Hs is supplied to the gate electrodes of the transistors 434 and 436. The logic circuit 440 includes inverter circuits 441 and 442 that are cascade-connected to each other, transistors 443 and 444 that reset the highway 80, and transistors 445 and 446 that activate the inverter circuits 441 and 442. The control signal / RSr*Hs is supplied to the gate electrodes of the transistors 443 and 445. The control signal / SCr*Hs is supplied to the gate electrodes of the transistors 444 and 446. The logic circuit 450 includes a NAND gate circuit 451, a NOR gate circuit 452, a transistor 453 that fixes the gate electrode of the transistor 403 at a high level, a transistor 454 that fixes the gate electrode of the transistor 404 at a low level, a transistor 455 that activates the NAND gate circuit 451, and transistors 456 and 457 that activate the NOR gate circuit 452. The output signal of the logic circuit 440 and the fixed high level signal are input to the NAND gate circuit 451. The output signal of the logic circuit 440 and the control signal / ( / SCr*Hs) are input to the NOR gate circuit 452. The control signal / SCr*Hs is supplied to the gate electrodes of the transistors 453 and 455 to 457. The inverted signal / ( / SCr*Hs) of the control signal / SCr*Hs is supplied to the gate electrode of the transistor 454. The power supply potential VDD2 lower than the boost potential VCCP is used for the control signal / SCr*Hs used in the logic circuits 430 and 440, and the boost potential VCCP is used for the control signal / SCr* / Hs used in the logic circuit 450 and the subsequent circuit for driving the thick film transistor. By this configuration, in the case where the speed mode signal Hs indicates the high-speed mode, the transistor 403 is temporarily turned on when the pull-up data DATAu changes to a high level in the read operation. Therefore, the output transistor 71B is temporarily turned on, so that the pre-emphasis operation in the pull-up state is performed. On the other hand, in the case where the speed mode signal Hs indicates the low-speed mode, the output node of the tri-state buffer circuit 400 is placed in a high impedance state.

[0060] The tri-state buffer circuit 410 belongs to the low speed path 81 and includes transistors 411 to 415 connected in series with each other between the high potential side power supply line and the low potential side power supply line. The tri-state buffer circuit 410 has the same circuit configuration as the tri-state buffer circuit 400. The same signal as the signal input to the gate electrodes of the transistors 401, 402, and 405 is input to the gate electrodes of the transistors 411, 412, and 415, except that the speed mode signal Hs is inverted.

[0061] The one-shot signal EmpPu and the pull-up data DATAu are input to the tri-state buffer circuit 410 via logic circuits 460 and 470 included in the low-speed path 81. The logic circuit 460 includes a NAND gate circuit 461 that receives the one-shot signal EmpPu and the pull-up data DATAu, an inverter circuit 462, transistors 463 and 464 that reset the low-speed path 81, and transistors 465 and 466 that activate the NAND gate circuit 461 and the inverter circuit 462. The control signal / RSr* / Hs is supplied to the gate electrodes of the transistors 463 and 465. The control signal / SCr* / Hs is supplied to the gate electrodes of the transistors 464 and 466. The logic circuit 470 includes a NAND gate circuit 471, a NOR gate circuit 472, a transistor 473 that fixes the gate electrode of the transistor 413 at a high level, a transistor 474 that fixes the gate electrode of the transistor 414 at a low level, a transistor 475 that activates the NAND gate circuit 471, and transistors 476 and 477 that activate the NOR gate circuit 472. The output signal of the logic circuit 460 and the fixed high level signal are input to the NAND gate circuit 471. The output signal of the logic circuit 460 and the control signal / ( / SCr* / Hs) are input to the NOR gate circuit 472. The control signal / SCr* / Hs is supplied to the gate electrodes of the transistors 473 and 475 to 477. The inverted signal / ( / SCr* / Hs) of the control signal / SCr* / Hs is supplied to the gate electrode of the transistor 474. By this configuration, in the case where the speed mode signal Hs indicates the low speed mode, the transistor 413 is temporarily turned on when the pull-up data DATAu changes to a high level in the read operation. Therefore, the output transistor 71B is temporarily turned on, so that the pre-emphasis operation in the pull-up state is performed. On the other hand, in the case where the speed mode signal Hs indicates the high speed mode, the output node of the tri-state buffer circuit 410 is placed in a high impedance state.

[0062] In addition, the pre-emphasis circuit 23 includes N-channel MOS transistors 491 to 494 that reset the gate electrode of the output transistor 71B to a low level. Control signals / PwUp, Scr, / PEmpStr, and / SCr are supplied to the gate electrodes of the transistors 491 to 494, respectively. The transistors 491, 492, and 494 are N-channel MOS transistors, each of which has a gate insulating film formed to be thick. In addition, the amplitude of the control signal / PwUp input to the transistor 491 is not the boost potential VCCP but the external power supply potential VDD1. At the same time, the amplitudes of the control signals SCr, / PEmpStr, and / SCr are VCCP.

[0063] In the pre-emphasis circuit 23, driving circuits 54 to 56 are provided in parallel.

[0064] Fig. 9 is a timing chart for explaining the operation of the semiconductor device 10 according to the embodiment of the present disclosure.

[0065] exist Fig. 9 In the example shown in FIG. 1 , a read command and a write command are issued at times t1 and t2, respectively, and a read command and a write command are issued at times t3 and t4, respectively. Times t1 and t2 are included in a time period T1 during which an operation is performed in a low-speed mode, and times t3 and t4 are included in a time period T2 during which an operation is performed in a high-speed mode. Fig. 9 As shown, when the read command has been issued, the reset signals RSr and SCr, the reset signal RSw and the reset signal SCw are inactive at a low level. At the same time, when the write command has been issued, the reset signals RSw and SCw are inactive at a low level. The falling timing of the reset signals RSr and RSw is different from the falling timing of the reset signals SCr and SCw. Similarly, the rising timing of the reset signals RSr and RSw is different from the rising timing of the reset signals SCr and SCw. The reset signal RSr is at a high level in the dormant state, becomes low when the read operation starts, and returns to a high level when the read operation ends. The reset signal SCr becomes low when the read operation starts, slightly earlier than the reset signal RSr, and returns to a high level when the read operation ends, much later than the reset signal RSr. The reset signal RSw becomes low when the read operation or the write operation starts, and returns to a high level when the read operation or the write operation ends. The reset signal SCw goes low when a read operation or a write operation starts, slightly earlier than the reset signal RSw, and returns to a high level when a read operation or a write operation ends, much later than the reset signal RSw.

[0066] When a read command has been issued, read data DQ is output from the data terminal 15. When a write command has been issued, write data DQ is input to the data terminal 15. In addition, in a write operation, the target ODT enable signal Te is activated so that a target ODT operation is performed. In addition, when neither a read operation nor a write operation is performed, a non-target ODT enable signal NTe is activated so that a non-target ODT operation is performed.

[0067] Fig.10 is a waveform diagram showing the relationship between the reset signals RSr and RSw and the reset signals SCr and SCw. Fig.10 As shown, the reset signals SCr and SCw each define the timing of ending the power gating operation and causing the corresponding logic circuit to transition from the inactive state to the active state. At the same time, the reset signals RSr and RSw each define the timing of resuming the power gating operation and causing the corresponding logic circuit to transition from the active state to the inactive state. In each logic circuit, the reset signals RSr and RSw are input to the previous stage and the reset signals SCr and SCw are input to the next stage. Therefore, when the power gating operation ends, the signal output from the logic level of each logic circuit is fixed. At the same time, because the reset signals SCr and SCw are input to the transistor using the boost potential VCCP, the reset signal remains at a low level for a relatively long time even after the power gating operation is resumed, so as to avoid increased power consumption and hot carrier degradation due to repeated switching on and off in a short period of time.

[0068] like Figure 4 and 6 As shown in FIG. 8 , the control signal / RSr*Hs and the control signal / SCr*Hs activate the high-speed paths 80 and 82 in the read operation, and are used to pull up the data DATAu in the high-speed path 80 and to pull down the data DATAd in a portion of the high-speed path 82, which portion does not involve the target ODT operation. The control signal / RSr* / Hs and the control signal / SCr* / Hs activate the low-speed paths 81 and 83 in the read operation, and are used to pull up the data DATAu in the low-speed path 81 and to pull down the data DATAd in a portion of the low-speed path 83, which portion does not involve the target ODT operation. The control signal / SCw*Hs activates the high-speed path 82 in the read operation or the write operation, and is used to pull down the data DATAd in a portion of the high-speed path 82, which portion involves the target ODT operation. The control signal / SCw* / Hs activates the low-speed path 83 in the read operation or the write operation, and is used to pull down the data DATAd in a portion of the low-speed path 83, which portion involves the target ODT operation.

[0069] The reset signal SCr can be divided into a signal input to the transistor using the boost potential VCCP and a signal input to the transistor using the power supply potential VDD2. Fig.11 As shown in , when the control signal / SCr* / Hs is generated based on the reset signal SCr, the rise of the control signal / SCr* / Hs_VCCP input to the transistor using the boost potential VCCP can be delayed from the rise of the control signal / SCr* / Hs_VDD2 input to the transistor using the power supply potential VDD2, and the fall of the control signal / SCr* / Hs_VCCP can be delayed from the fall of the control signal / SCr* / Hs_VDD2. By this setting, unknown data is prevented from being output from the data terminal 15 when the power gating operation ends.

[0070] In addition, when the low speed mode is switched to the high speed mode or when the high speed mode is switched to the low speed mode, the transition timings of the reset signals SCr and SCw and the various control signals generated by the speed mode signal Hs may be sequenced. Fig.12 As shown in FIG. 1 , when the low-speed mode is switched to the high-speed mode, the control signal / SCr*Hs_VDD2 may be changed to a high level, after which the control signal / SCr*Hs_VCCP and the control signal / SCw* / Hs_VCCP may be changed to a high level and a low level, respectively, and after which the control signal / SCw* / Hs_VDD2 may be changed to a low level. In this order, unknown data is prevented from being output from the data terminal 15 when switching from the low-speed mode to the high-speed mode or when switching from the high-speed mode to the low-speed mode.

[0071] Although the present invention has been disclosed in the context of certain preferred embodiments and examples, it will be appreciated by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the present invention and its obvious modifications and use of equivalents. In addition, based on this disclosure, other modifications within the scope of the present invention will be apparent to those skilled in the art. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be performed and still fall within the scope of the present invention. It will be appreciated that the various features and aspects of the disclosed embodiments can be combined with each other or replace each other to form a variation pattern of the present invention. Therefore, it is desirable that at least some of the scope of the present invention disclosed herein should not be limited by the specific disclosed embodiments described above.

Claims

1. A device comprising: Data terminal; a first output transistor connected between the data terminal and a first power supply line supplying a first power supply potential; a first tri-state circuit comprising an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tri-state circuit comprising an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level, wherein the second pull-up transistor and the pull-down transistor have threshold voltages different from those of the first pull-up transistor and the pull-down transistor, wherein the output node of the first tri-state circuit enters a high impedance state when a first mode signal is activated, wherein the output node of the second tri-state circuit enters a high impedance state when the first mode signal is deactivated, wherein the first mode signal is a non-target ODT signal, and The threshold voltages of the second pull-up transistor and the pull-down transistor are higher than the threshold voltages of the first pull-up transistor and the pull-down transistor.

2. The apparatus of claim 1, wherein the first tri-state circuit further comprises a first switching transistor connected in series with the first pull-up transistor, and a second switching transistor connected in series with the first pull-down transistor. 3 . The device according to claim 2 , wherein gate insulating films of the first and second switching transistors are thicker than gate insulating films of the first pull-up and pull-down transistors. 4 . The apparatus of claim 3 , wherein the first switching transistor and the second switching transistor have the same conductivity type as each other. 5 . The apparatus of claim 1 , wherein one of the first pull-up transistor and the pull-down transistor enters an on state based on a first data signal during a read operation. The apparatus of claim 5 , wherein the first pull-up transistor enters an on-state during a write operation.

7. The apparatus of claim 5, further comprising a third tri-state circuit comprising an output node connected to the control electrode of the first output transistor, a third pull-up transistor configured to drive the output node to the first logic level, and a third pull-down transistor configured to drive the output node to the second logic level, wherein the third pull-up transistor and the pull-down transistor have the same threshold voltage as the first pull-up transistor and the pull-down transistor, and One of the first tri-state circuit and the third tri-state circuit is activated based on a second mode signal. The apparatus of claim 7 , wherein the second mode signal indicates a frequency of the first data signal.

9. The apparatus of claim 5, further comprising: a second output transistor connected between the data terminal and a second power supply line supplying a second power supply potential; and a fourth tri-state circuit comprising an output node connected to the control electrode of the second output transistor, a fourth pull-up transistor configured to drive the output node to the first logic level, and a fourth pull-down transistor configured to drive the output node to the second logic level, The threshold voltages of the second pull-up transistor and the pull-down transistor are higher than the threshold voltages of the fourth pull-up transistor and the pull-down transistor. 10 . The apparatus of claim 9 , wherein one of the fourth pull-up transistor and the pull-down transistor enters an on state based on a second data signal, the second data signal being an inverted signal of the first data signal.

11. A device comprising: Data terminal; a first output transistor connected between the data terminal and a first power supply line supplying a first power supply potential; a first tri-state circuit comprising an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tri-state circuit comprising an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level, wherein the second pull-up transistor and the pull-down transistor have threshold voltages different from those of the first pull-up transistor and the pull-down transistor, wherein the first tri-state circuit further comprises a first switch transistor connected in series with the first pull-up transistor, and a second switch transistor connected in series with the first pull-down transistor, The first tri-state circuit further includes a first adjustment circuit connected between the first pull-up transistor and the first switch transistor, and a second adjustment circuit connected between the first pull-down transistor and the second switch transistor.

12. The apparatus of claim 11, wherein each of the first adjustment circuit and the second adjustment circuit comprises a plurality of adjustment transistors connected in parallel.

13. The apparatus of claim 12, wherein the plurality of adjustment transistors are controlled by a slew rate code signal.

14. An apparatus comprising: Data terminal; an output transistor connected between the data terminal and a first power line supplying a first power potential; a first tri-state circuit comprising an output node connected to a control electrode of the output transistor; a second tri-state circuit including an output node connected to the control electrode of the output transistor; and a third tri-state circuit including an output node connected to the control electrode of the output transistor, wherein the first tri-state circuit is activated when the speed mode signal indicates a high speed mode, wherein the second tri-state circuit is activated when the speed mode signal indicates a low speed mode, and Wherein when the non-target ODT signal is activated, the third tri-state circuit is activated regardless of the speed mode signal.

15. The device according to claim 14, wherein each of the first tri-state circuit and the second tri-state circuit comprises a first transistor, a second transistor and a third transistor connected in series between the control electrode of the output transistor and the first power line, The first transistor is controlled by a first signal, wherein the second transistor is controlled by a second signal, wherein the third transistor is controlled by a third signal, and The gate insulating film of the third transistor is thicker than the gate insulating films of the first transistor and the second transistor.

16. The device according to claim 15, wherein each of the first three-state circuit and the second three-state circuit further comprises a fourth transistor, a fifth transistor and a sixth transistor connected in series between the control electrode of the output transistor and a second power supply line supplying a second power supply potential, wherein the fourth transistor is controlled by the first signal, wherein the fifth transistor is controlled by the second signal, wherein the sixth transistor is controlled by the third signal, and The gate insulating film of the sixth transistor is thicker than the gate insulating films of the fourth transistor and the fifth transistor.

17. The device according to claim 16, wherein the first, second, third and sixth transistors are of N-channel type, and Wherein the fourth transistor and the fifth transistor are of P-channel type.

18. The device according to claim 17, wherein the third tri-state circuit comprises a seventh transistor of an N-channel type and an eighth transistor of a P-channel type, wherein the drains of the seventh transistor and the eighth transistor are connected to the control electrode of the output transistor, and The threshold voltages of the seventh transistor and the eighth transistor are higher than the threshold voltages of the first transistor and the fourth transistor.

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