Filter Circuit and Semiconductor Device

Abstract

Provided is a filter circuit and a semiconductor device that have a simple structure and can prevent malfunction of a circuit even when the power supply voltage changes. A latch circuit and a rising adjustment unit are provided. The latch circuit latches a set signal input to a first input terminal and a reset signal input to a second input terminal, respectively. The rising adjustment unit makes the rising time of the set signal or the reset signal when the power supply is turned on shorter than the time specified by a time constant circuit disposed in the previous stage of the latch circuit.

Description

Technical Field

[0001] The present invention relates to a filter circuit and a semiconductor device equipped with the filter circuit. Background Art

[0002] In recent years, a HVIC (High Voltage IC) technology has been developed to achieve high efficiency, energy saving, miniaturization, and high reliability of IDC (Internet Data Center) power supply systems such as servers and UPSs (Uninterruptible Power Supplies). HVIC refers to a high breakdown voltage IC that drives the gates of power devices in a bridge circuit structure (for example, Patent Document 2).

[0003] In Patent Document 2, a HVIC is used to drive a high-side power MOS transistor and a low-side power MOS transistor that are connected in a half-bridge configuration, respectively.

[0004] In addition, in the above-mentioned HVIC, a set pulse and a reset pulse are used to control, for example, a high-side power MOS transistor to be turned on and off. However, when the power supply voltage fluctuates, an RS flip-flop circuit that controls the set pulse and the reset pulse sometimes malfunctions. Therefore, the high-side power MOS transistor and the low-side power MOS transistor sometimes conduct simultaneously, affecting the stability of the system.

[0005] In addition, a structure in which two low-potential side power supplies (VDD, VBAT) are provided is proposed in Patent Document 1. In addition, Patent Document 2 proposes a configuration in which a capacitor is inserted between the set side and ground (GND) and a capacitor is inserted between the reset side and the power supply to form a time constant circuit. In addition, Patent Document 3 proposes a configuration in which a capacitor is connected to the output of an RS flip-flop to eliminate the indeterminate period of the RS flip-flop when the power is turned on. And Patent Document 4 proposes a structure in which a pull-up circuit or a pull-down circuit is provided between the output of the RS flip-flop and the power supply.

[0006] Prior Art Documents

[0007] Patent Documents

[0008] Patent Document 1: Japanese Patent Application Laid-Open No. 2012-9982

[0009] Patent Document 2: Japanese Patent Application Laid-Open No. 2004-260730

[0010] Patent Document 3: Japanese Patent Application Laid-Open No. 2003-152515

[0011] Patent Document 4: Japanese Patent Laid-Open No. 5-235705 Summary of the Invention

[0012] Problems to be Solved by the Invention

[0013] In addition, in the above Patent Document 1, an additional power supply needs to be prepared, increasing the circuit scale. In the above Patent Document 2, although the connection method of the capacitor is changed to prevent malfunction, it is not applied to the malfunction of the RS flip-flop. In the above Patent Document 3, an additional control circuit for determining the initial value is provided on the input side of the RS flip-flop, resulting in a large circuit scale. In the above Patent Document 4, an additional control circuit for determining the initial value needs to be provided on the input side of the RS flip-flop.

[0014] The present invention has been completed in view of the above problems, and an object thereof is to provide a filter circuit and a semiconductor device having a simple structure and capable of preventing malfunction of the circuit even when the power supply voltage fluctuates.

[0015] Means for Solving the Problems

[0016] To solve the above problems, the gist of one aspect of the present invention is to include: a latch circuit that latches a set signal input to a first input terminal and a reset signal input to a second input terminal; and a rising adjustment unit that makes the rising time of the set signal or the reset signal when the power is turned on shorter than the time specified by a time constant circuit disposed in the previous stage of the latch circuit.

[0017] Effects of the Invention

[0018] According to the present invention, it is possible to provide a filter circuit and a semiconductor device having a simple structure and capable of preventing malfunction of the circuit even when the power supply voltage fluctuates. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a block diagram showing a structural example of a semiconductor device equipped with a filter circuit according to a first embodiment of the present invention.

[0020] Figure 2 It is a block diagram showing an internal structural example of the filter circuit according to the first embodiment of the present invention.

[0021] Figure 3 It is a circuit diagram showing a specific structure of the filter circuit according to the first embodiment of the present invention.

[0022] Figure 4 It is a timing chart showing the operation of the filter circuit when the pull-up circuit and the pull-down circuit are not provided.

[0023] Figure 5It is a timing chart showing the operation of the filter circuit according to the first embodiment of the present invention.

[0024] Figure 6 It is a circuit diagram showing the specific structure of the filter circuit according to a modification of the first embodiment of the present invention.

[0025] Figure 7 It is a circuit diagram showing the specific structure of the filter circuit according to the second embodiment of the present invention.

[0026] Figure 8 It represents Figure 2 The circuit diagram of the detailed structural example of the RC time constant circuit of.

[0027] Figure 9 It represents Figure 8 The timing chart of the operation of the RC time constant circuit shown in. Specific embodiments

[0028] The embodiments of the invention will be described below. In the description of the following drawings, the same or similar parts are denoted by the same or similar reference numerals, and duplicate descriptions are omitted.

[0029] (First embodiment)

[0030] Figure 1 It is a block diagram showing a structural example of a semiconductor device equipped with a filter circuit according to the first embodiment of the present invention.

[0031] The semiconductor device 1 includes an HVIC 10 and a half-bridge circuit 20. The half-bridge circuit 20 includes a high-side power MOS transistor (not shown) and a low-side power MOS transistor (not shown) that are half-bridge connected. The HVIC 10 outputs a signal to the gate terminal of the high-side power MOS transistor to drive the high-side power MOS transistor, for example, at the timing when the input signal switches from "L (low)" to "H (high)", and outputs a signal to the gate terminal of the low-side power MOS transistor to drive the low-side power MOS transistor at the timing when the input signal switches from "H" to "L". The high-side power MOS transistor and the low-side power MOS transistor are alternately turned on by the HVIC 10 to supply power to a load (not shown).

[0032] The HVIC 10 includes an input detection circuit 11, a filter circuit 12, a pulse generation circuit 13, a low-side drive circuit 14, a level shift circuit 15, and a high-side drive circuit 16. The input detection circuit 11 has a function of detecting the timing for driving the high-side power MOS transistor according to the signal level of the input signal. The filter circuit 12 has a function of removing minute pulse noise from the output signal of the input detection circuit 11 and a function of delaying for a specified time and latching. The pulse generation circuit 13 has the following functions: generating a set pulse for turning on the high-side power MOS transistor corresponding to the rising edge of the output signal of the filter circuit 12, and generating a reset pulse for turning off the high-side power MOS transistor corresponding to the falling edge of the output signal of the filter circuit 12. The low-side drive circuit 14 has a function of driving the low-side power MOS transistor corresponding to the output signal of the filter circuit 12. The level shift circuit 15 has the following functions: using the set pulse and the reset pulse output from the pulse generation circuit 13, shifting the output signal of the filter circuit 12 from the ground potential GND reference level to a high-side reference potential signal. The high-side drive circuit 16 has a function of driving the high-side power MOS transistor corresponding to the output signal of the level shift circuit 15.

[0033] The input detection circuit 11 inputs an input signal IN that switches between "H (high)" and "L (low)" at a specified timing, and outputs an output signal IN1 to the filter circuit 12. Here, it is assumed that the high-side power MOS transistor is turned on when the input signal input to the input detection circuit 11 rises from "L" to "H", and the high-side power MOS transistor is turned off when the input signal input to the input detection circuit 11 falls from "H" to "L".

[0034] The output signal IN2 of the filter circuit 12 is supplied to the pulse generation circuit 13 and the low-side drive circuit 14. The pulse generation circuit 13 takes the output signal IN2 of the filter circuit 12 as an input, and outputs a set pulse for turning on the high-side power MOS transistor corresponding to the rising edge of the output signal IN2, and outputs a reset pulse for turning off the high-side power MOS transistor corresponding to the falling edge of the output signal IN2. The level shift circuit 15 uses the set pulse and the reset pulse output from the pulse generation circuit 13, shifts the output signal of the filter circuit 12 from the ground potential GND reference level to a high-side reference potential signal, and outputs the signal of the high-side reference potential to the high-side drive circuit 16.

[0035] The high-side drive circuit 16 selectively outputs a signal to the gate terminal of the high-side power MOS transistor corresponding to the set pulse and the reset pulse output from the slave level shift circuit 15, so as to switch the high-side power MOS transistor between conduction and non-conduction. The low-side drive circuit 14 selectively outputs a signal to the gate terminal of the low-side power MOS transistor corresponding to the output signal IN2 of the filter circuit 12, so as to switch the low-side power MOS transistor between conduction and non-conduction.

[0036] Figure 2 Shows the internal structure of the above filter circuit 12.

[0037] The signal IN1 output from the input detection circuit 11 is supplied to the RC time constant circuit 101, and the signal IN1 is inverted in signal level by the inverter circuit 103 and the inverted signal ZIN1 is supplied to the RC time constant circuit 102. The RC time constant circuit 101 outputs a set signal to the RS latch circuit 100A according to the input signal IN1. The RC time constant circuit 102 outputs a reset signal to the RS latch circuit 100A according to the ZIN1 signal obtained by inverting the signal IN1.

[0038] The RS latch circuit 100A is used to latch the set signal and the reset signal. The output of the RS latch circuit 100A is output after passing through the inverter circuit 104.

[0039] Figure 8 Shows the internal structures of the RC time constant circuits 101 and 102.

[0040] The RC time constant circuits 101 and 102 are composed of inverter circuits 31 and 32 and a buffer circuit 33. The inverter circuit 32 includes a CMOS inverter circuit composed of a PMOS transistor MP1 and an NMOS transistor MN1, and an RC delay circuit composed of a resistor R1 and a capacitor C1. As Figure 9 shown, the RC delay circuit gradually changes the rising edge of the node voltage RCV ( Figure 9 (b)) along the transition phenomenon curve determined by the RC time constant based on the resistor R1 and the capacitor C1, and outputs the output signal RC_OUT of the buffer circuit 33 ( Figure 9 (c)) when the threshold Vth of the buffer circuit 33 is reached, thereby removing the tiny pulse noise of the input signal RC_IN ( Figure 9 (a)) and delaying for a specified time.

[0041] Figure 3 Shows a circuit structure example of the filter circuit 12.

[0042] The RS latch circuit 100A includes NOR circuits 111 and 112. A pull - down resistor 151 is connected between the S terminal of the RS latch circuit 100A and the ground (GND). In addition, a pull - up resistor 152 is connected between the R terminal of the RS latch circuit 100A and the power supply voltage line.

[0043] A set signal is output from the RC time - constant circuit 101. A reset signal is output from the RC time - constant circuit 102. The RC time - constant circuits 101 and 102, the pull - down resistor 151, and the pull - up resistor 152 constitute a rising adjustment unit.

[0044] Next, the operation of the filter circuit 12 constituted by the Figure 2 structure will be described.

[0045] In Figure 4 , when the power supply voltage VDD rises (during t2 - t3 in (a) of Figure 4 ), the node voltage RCV of the RC time - constant circuit 102 (in (b) of Figure 4 ) rises along the transient curve determined by the RC time - constant until it reaches the threshold voltage Vth, and the RC time - constant circuit 102 outputs an output signal RC_OUT (in (c) of Figure 4 ). At this time, the voltages applied to the S terminal and R terminal of the RS latch circuit 100A (in (d) of Figure 4 , in (e) of Figure 4 ) are at the L level and H level respectively. Therefore, at time point t4, the voltage obtained at the output terminal Q of the RS latch circuit 100A is at the L level.

[0046] However, when the power supply voltage VDD rises (during t2 - t4), the voltages applied to the S terminal and R terminal of the RS latch circuit 100A are in a transition state from the state of L level and L level to the state of L level and H level. Therefore, the following situation is also considered: Immediately after the power is turned on, as shown in (f) of Figure 4 , the output terminal Q of the RS latch circuit 100A becomes an unexpected H level. When falling into such a state, a false turn - on pulse is generated from the RS latch circuit 100A (in (g) of Figure 4 ), causing the high - side power MOS transistor and the low - side power MOS transistor to conduct simultaneously.

[0047] Therefore, in this first embodiment, a pull - down resistor 151 is connected between the S terminal of the RS latch circuit 100A and the ground (GND), and a pull - up resistor 152 is connected between the R terminal of the RS latch circuit 100A and the power supply voltage line. Thus, even when the output voltage of the RC time - constant circuit 102 has not reached the threshold voltage Vth, by using the pull - down resistor 151 to suppress the rise of the power supply voltage VDD Figure 5During the period from t2 to t3 in (a)), the rising edge of the set signal that temporarily changes while in an indeterminate state Figure 5 in (e)), and makes the rising edge of the reset signal faster than the rising edge of the output of the RC time constant circuit 102 Figure 5 in (d)), it is also possible to set the set signal to the L level and the reset signal to the H level. That is, the rising time of the reset signal is set to a time shorter than the time specified by the RC time constant circuit 102.

[0048] Therefore, the voltage obtained at the output terminal IN2 of the RS latch circuit 100A remains at the L level Figure 5 in (f)), and no false turn-on pulse is generated from the RS latch circuit 100A Figure 5 in (g)).

[0049] As described above, according to the first embodiment, even when the output voltage of the RC time constant circuit 102 that outputs the reset signal has not reached the threshold value Vth, by the effects of the pull-down resistor 151 and the pull-up resistor 152, the set signal can be reliably determined to be at the L level and the reset signal can be reliably determined to be at the H level, thereby preventing the output of the RS latch circuit 100A from malfunctioning.

[0050] In addition, according to the first embodiment, by using the pull-down resistor 151 and the pull-up resistor 152, it can be configured inexpensively, and by simply adding a resistor element with a small circuit scale, the generation of false pulses after a power supply interruption is eliminated.

[0051] (Modification example)

[0052] Figure 6 is a circuit diagram showing the specific structure of the filter circuit 12 according to the modification example of the first embodiment of the present invention. In Figure 6 , the same parts as those in the above Figure 3 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0053] The RS latch circuit 100B includes NAND circuits 211 and 212 and an inverter circuit 104. A pull-down resistor 251 is connected between the S terminal of the RS latch circuit 100B and the ground (GND). In addition, a pull-up resistor 252 is connected between the R terminal of the RS latch circuit 100B and the power supply voltage line.

[0054] Further, the output of the NOR circuit 260 is supplied to the RC time constant circuit 102. The RC time constant circuits 101 and 102, the pull-down resistor 251, and the pull-up resistor 252 constitute the rising adjustment unit. The signal IN1 and the reset signal for initialization at power-on are input to the NOR circuit 260. The NOR circuit 260 generates the signal ZIN1 based on the logical OR of the signal IN1 and the reset signal, and outputs this signal ZIN1 to the RC time constant circuit 102.

[0055] As described above, the above-described modification can also achieve the same effects as those of the above-described first embodiment.

[0056] (Second Embodiment)

[0057] Figure 7 FIG. is a circuit diagram showing a specific structure of the filter circuit 12 according to the second embodiment of the present invention. In Figure 7 the same parts as those in the above Figure 3 are denoted by the same reference numerals, and detailed description thereof is omitted.

[0058] A MOS-FET 351 constituting a pull-down circuit is connected between the S terminal of the RS latch circuit 100A and the ground (GND). Further, a MOS-FET 352 constituting a pull-up circuit is connected between the R terminal of the RS latch circuit 100A and the power supply voltage line. The gates of the MOS-FETs 351 and 352 are connected to constant voltage biases (BIAS1, BIAS2). The RC time constant circuits 101 and 102 and the MOS-FETs 351 and 352 constitute the rising adjustment unit.

[0059] The above-described second embodiment can also achieve the same effects as those of the above-described first embodiment, and can be manufactured at low cost when manufacturing the HVIC 10.

[0060] (Other Embodiments)

[0061] As described above, the present invention has been described by way of embodiments, but it should not be construed that the descriptions and the drawings forming a part of this disclosure are used to limit the present invention. Based on this disclosure, those skilled in the art will clearly understand various alternative embodiments and modifications.

[0062] In the above-described embodiments, an example in which pull-up circuits and pull-down circuits are provided for both the S terminals and the R terminals of the RS latch circuits 100A and 100B has been described. However, it is not limited thereto, and a structure in which either a pull-up circuit or a pull-down circuit is provided as the rising adjustment unit may be used.

[0063] Also, in each of the above-described embodiments, an example in which the filter circuit 12 is mounted on the HVIC 10 and used has been described. However, the present invention is not limited to this, and the filter circuit 12 can also be applied to other semiconductor devices.

[0064] Description of Reference Numerals

[0065] 1: Semiconductor device; 10: HVIC; 11: Input detection circuit; 12: Filter circuit; 13: Pulse generation circuit; 14: Low-side drive circuit; 15: Level shift circuit; 16: High-side drive circuit; 20: Half-bridge circuit; 31, 32: Inverter circuit; 33: Buffer circuit; 100A, 100B: RS latch circuit; 101, 102: RC time constant circuit; 103, 104: Inverter circuit; 111, 112, 260: NOR circuit; 151, 251: Pull-down resistor; 152, 252: Pull-up resistor; 211, 212: NAND circuit; 351, 352: MOS-FET.

Claims

1. A filter circuit, comprising: A latch circuit that latches a set signal input to a first input terminal and a reset signal input to a second input terminal, respectively; and A rising adjustment unit configured to suppress the rising of the set signal when the power supply voltage rises and to make the rising of the reset signal faster than the rising of the output of a time constant circuit arranged at the front stage of the latch circuit. Among them, The rising adjustment unit includes: A pull-up circuit that pulls up one of the inputs of the first input terminal and the second input terminal; and A pull-down circuit that pulls down the other of the inputs of the first input terminal and the second input terminal.

2. The filter circuit according to claim 1, wherein The reset signal of the latch circuit is generated based on the logical OR of an input signal input to the rising adjustment unit and a reset signal for initialization at power-on.

3. The filter circuit according to claim 1, wherein The pull-up circuit and the pull-down circuit are constituted by resistance elements.

4. The filter circuit according to claim 1, wherein The pull-up circuit and the pull-down circuit are constituted by on-resistances.

5. A semiconductor device incorporating the filter circuit according to any one of claims 1 to 4.

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