De-embedding Method for On-Wafer Test Structure of RF MOS Devices

Abstract

The present invention provides a de-embedding method for an on-wafer test structure of an RF MOS device, comprising the following steps: forming a device to be tested, and corresponding pin structures, open circuit structures, short circuit structures, and through structures on the same substrate at the same time; performing S parameter tests on the device to be tested, the pin structures, the open circuit structures, the short circuit structures, and the through structures respectively; simulating the impedance of a metal strip using an electromagnetic simulation model to calculate the impedance introduced by the actual short circuit structure; and converting the S parameters into Y parameters using the impedance introduced by the actual short circuit structure obtained. The present invention simulates the impedance of the part of the metal block used for common ground interconnection in the short circuit structure actually used for de-embedding by performing electromagnetic simulation on a metal strip, and removes the impedance during the de-embedding process, thereby obtaining better de-embedding accuracy at higher frequencies.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a de-embedding method for an on-wafer test structure of an RF MOS device. Background Art

[0002] As the characteristic size of MOS transistors continues to decrease, the power consumption of devices is also decreasing, and the RF performance has also been greatly improved. The cutoff frequency and maximum oscillation frequency have reached several hundred GHz. The improvement of RF performance has made the application fields of MOS devices more extensive, such as 60GHz local area network, radar (77GHz), etc. Therefore, in order to better characterize the characteristics of devices in the higher frequency range and improve the design speed of integrated circuits, the device testing methodology and MOS electrical model need to be improved.

[0003] On-wafer transistor testing requires connecting the device under test to the pins through metal interconnects, and then measuring the device's S parameters through RF probes and related instruments. However, the pins and metal interconnects will introduce parasitic impedance, affecting the actual performance of the DUT, so they must be removed, i.e., de-embedded.

[0004] The most commonly used de-embedding method in the prior art is open-short de-embedding, but the accuracy of this method decreases when the frequency is greater than 50 GHz. Moreover, as the frequency increases, especially in the millimeter wave range, the gain of the device decreases, and the parasitic effect of the interconnection line becomes greater, so a more accurate de-embedding method is needed.

[0005] The parasitics caused by the pins and interconnects are mainly manifested as the parallel parasitic admittance from the pins to the substrate and the series parasitic impedance caused by the interconnects. The equivalent model is as follows: Figure 1 As shown. The implementation of the commonly used de-embedding method open short requires an overall structure, an open circuit structure and a short circuit structure. The overall structure includes the device under test, interconnects and pins, while the open circuit structure removes the device under test from the overall structure. The short circuit structure usually removes the device under test and then uses a metal layer to connect the two signal input terminals and the ground (i.e., short circuit). Its equivalent model is as follows Figure 2 As shown, the metal layer used for interconnection is an additional impedance introduced, that is, Figure 2 In the Zs, in the higher frequency range, the impedance effect cannot be ignored. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a de-embedding method for an on-wafer test structure of an RF MOS device, which can ensure the de-embedding accuracy in the high frequency field.

[0007] In order to solve the above problems, the present invention provides a de-embedding method for an on-wafer test structure of an RF MOS device, comprising the following steps: forming a device to be tested, and corresponding pin structures, open circuit structures, short circuit structures, and through structures on the same substrate at the same time; performing S parameter tests on the device to be tested, the pin structures, the open circuit structures, the short circuit structures, and the through structures respectively to obtain S parameters; simulating a metal strip impedance using an electromagnetic simulation model, the metal strip being used to simulate the metal impedance used for common ground interconnection in the short circuit structure, to obtain the Z parameter of the metal strip and the impedance value Z of the metal strip having a length L. L , calculate the impedance Z introduced by the actual short-circuit structure s =L1 / L*Z L ; The impedance Z introduced by the actual short-circuit structure obtained s , convert S parameters into Y parameters.

[0008] Optionally, the S parameter S of the device under test mea , S parameter S of the pin structure pad , S parameter S of the open circuit structure open , S parameter S of the short-circuit structure short , and the S parameter S of the through structure thru .

[0009] Optional, the Y parameter Y of the device under test mea 、Y parameter Y of the pin structure pad , and the Y parameter Y of the short-circuit structure short .

[0010] The present invention simulates the impedance of a metal block used for common ground interconnection in a short-circuit structure actually used for de-embedding by electromagnetically simulating the impedance of a metal strip, and removes the impedance during the de-embedding process, thereby obtaining better de-embedding accuracy at higher frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Attached Figure 1 It is an equivalent model of the complete structure of the parallel parasitic admittance from the pin to the substrate and the series parasitic impedance caused by the interconnection line in the prior art.

[0012] Attached Figure 2 It is an equivalent model of the de-embedded short-circuit structure of the parallel parasitic admittance from the pin to the substrate and the series parasitic impedance caused by the interconnection line in the prior art.

[0013] Attached Figure 3A It is a complete device under test structure provided by a specific implementation manner of the present invention.

[0014] Attached Figure 3B A de-embedding pin structure corresponding to a device under test is provided in a specific embodiment of the present invention.

[0015] Attached Figure 3C It is a de-embedded open circuit structure corresponding to the device under test provided by a specific implementation manner of the present invention.

[0016] Attached Figure 3D A de-embedding short-circuit structure corresponding to a device under test is provided in a specific embodiment of the present invention.

[0017] Attached Figure 3E A through structure for calibrating an electromagnetic simulation model corresponding to a device under test is provided in a specific embodiment of the present invention.

[0018] Attached Figure 3F It is an equivalent model of a complete device under test provided by a specific implementation manner of the present invention.

[0019] Attached Figure 3G is an equivalent model of the de-embedded short-circuit structure provided by a specific embodiment of the present invention

[0020] Attached Figure 4 It is a metal strip structure used for electromagnetic simulation according to a specific embodiment of the present invention.

[0021] Attached Figure 5 A specific embodiment of the present invention is to test the S mea Convert to Y mea , S pad Convert to Y pad , S short Convert to Y short The transformation process model. DETAILED DESCRIPTION

[0022] The specific implementation of the de-embedding method of the on-wafer test structure of the RF MOS device provided by the present invention is described in detail below with reference to the accompanying drawings.

[0023] 1. It is necessary to form the device under test, as well as the corresponding pin structure, open circuit structure, short circuit structure and straight-through structure on the same substrate at the same time. The device under test includes a transistor under test, interconnects and pins, and the pin structure only includes pins. The open circuit structure is to remove the transistor under test from the device under test, the short circuit structure is to remove the transistor under test from the device under test, and then use a metal layer to connect the two signal input terminals to the ground, and the straight-through structure is to connect the two signal terminals of the device to the ground through the top metal layer. Figure 3A To Attachment Figure 3G , which are respectively a complete device under test structure, a de-embedded pin structure corresponding to the device under test, a de-embedded open circuit structure corresponding to the device under test, a de-embedded short circuit structure corresponding to the device under test, a through structure corresponding to the device under test for electromagnetic simulation model calibration, an equivalent model of the complete device under test, and an equivalent model of the de-embedded short circuit structure.

[0024] 2. Perform S parameter tests on the above-mentioned device under test, pin structure, open circuit structure, short circuit structure, and straight-through structure respectively to obtain the S parameter S of the device under test. mea , S parameter S of the pin structure pad , S parameter S of the open circuit structure open , S parameter S of the short-circuit structure short , and the S parameter S of the through structure thru .

[0025] 3. Use the electromagnetic simulation model to simulate the impedance of a metal strip, which is used to simulate the metal impedance used for common ground interconnection in the above short-circuit structure, and obtain the Z parameter of the metal strip and the impedance value Z of the metal strip with a length of L. L , calculate the impedance Z introduced by the actual short-circuit structure s =L1 / L*Z L . Figure 4 Shown is the metal strip structure used for electromagnetic simulations.

[0026] The specific process of the above electromagnetic simulation model is as follows:

[0027] In the electromagnetic simulation software, a structure identical to the above-mentioned through-structure is prepared, that is, the material, preparation process and size are ensured to be the same; and the S parameter test is performed on the structure to establish a corresponding electromagnetic simulation model; and a comparative analysis is performed with the S parameters measured with the actual through-structure, and the simulation parameters in the electromagnetic simulation model (such as the conductivity of the pins, interconnects of each layer and the substrate, as well as the dielectric constant of each dielectric layer and the selection of the simulation grid size, etc.) are corrected, and finally the optimal electromagnetic simulation model is obtained; and the S parameters are compared with those measured with the actual through-structure. Figure 4 The structure in the figure (the length of the structure is consistent with the length of the straight-through part in the straight-through structure, that is, it is marked as L in the figure, the width and thickness of the structure are consistent with the part of the metal block used for common ground interconnection in the actual short-circuit structure, and the length of the metal block is marked as L1, and the material of the structure is consistent with the part of the metal block used for common ground interconnection in the actual short-circuit structure) replaces the metal strips connecting the two signals in the straight-through structure; and uses the above-mentioned electromagnetic simulation model to simulate and test it.

[0028] Convert the S parameters obtained in step 2 into Y parameters, including the Y parameters Y of the device under test. mea 、Y parameter Y of the pin structure pad , and the Y parameter Y of the short-circuit structure short . S mea Convert to Y mea , S pad Convert to Y pad , S short Convert to Y short .

[0029]

[0030] in

[0031]

[0032]

[0033]

[0034]

[0035] The conversion process is as follows Figure 5 shown.

[0036] Specific de-embedding calculation process: Z”=[Y shor Y pad ]-1-Z';

[0037] Y dut =[(Y mea -Y pad )-1-Z”]-1-[(Y open -Y pad )-1-Z”]-1

[0038] The above technical solution simulates the impedance of a metal strip by electromagnetically simulating its impedance to simulate the impedance of the metal block used for common ground interconnection in the short-circuit structure actually used for de-embedding, and removes the impedance during the de-embedding process, thereby obtaining better de-embedding accuracy at higher frequencies.

[0039] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for de-embedding an on-wafer test structure of an RF MOS device, characterized in that: The steps include: Simultaneously forming a device under test, and corresponding pin structures, open circuit structures, short circuit structures, and through structures on the same substrate; Performing S parameter tests on the device under test, the pin structure, the open circuit structure, the short circuit structure, and the through structure to obtain S parameters; The electromagnetic simulation model is used to simulate the impedance of a metal strip, which is used to simulate the metal impedance used for common ground interconnection in the short-circuit structure, and the Z parameter of the metal strip and the impedance value Z of the metal strip with a length of L are obtained. L , calculate the impedance Z introduced by the actual short-circuit structure s =L1 / L*Z L ; The impedance Z introduced by the actual short-circuit structure is obtained s , convert S parameters to Y parameters, Y parameter Y of the device under test mea 、Y parameter Y of the pin structure pad , and the Y parameter Y of the short-circuit structure short； S mea Convert to Y mea , S pad Convert to Y pad , S short Convert to Y short； in Specific de-embedding calculation process: Z”=[Y shor Y pad ]-1-Z'; AND dut =[(And mea -AND pad )-1-Z”]-1-[(Y open -AND pad )-1-Z”]-1 The S parameter of the device under test is S mea , the S parameter of the pin structure is S pad , the S parameter of the open circuit structure is S open , the S parameter of the short-circuit structure is S short , and the S parameter of the through structure is S thru， The Y parameter of the device under test is Y mea , the Y parameter of the pin structure is Y pad , and the Y parameter of the short-circuit structure is Y short .

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