Capacitive sensing

Abstract

The present invention relates generally to capacitive sensing. As disclosed herein, a circuitry and method for providing digitized voltage values of a capacitive sensor, wherein a second capacitive sensor is used for charge equalization. After charge equalization, an analog-to-digital converter (ADC) provides a digital value representing the voltage of one sensor.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to capacitive sensing. BACKGROUND

[0002] Capacitive sensing uses capacitive technology to detect a stimulus or provide a measurement. A capacitive sensor is a device that is capacitively coupled to a conductive or dielectric external object, whose capacitance varies with movement of the external object relative to the capacitive sensor. SUMMARY

[0003] According to one embodiment, a method of capacitive sensing comprises:

[0004] charging a first capacitive sensor with a first voltage and charging a second capacitive sensor with a second voltage, the first voltage being different from the second voltage;

[0005] after the charging, removing the first voltage from the first capacitive sensor and removing the second voltage from the second capacitive sensor, and thereafter equalizing charge on the first capacitive sensor and the second capacitive sensor;

[0006] after the equalizing, providing a digital indication of a sensed voltage level of the first capacitive sensor with an analog-to-digital converter.

[0007] In one or more embodiments, the first capacitive sensor and the second capacitive sensor are part of a touch screen array.

[0008] In one or more embodiments, the first voltage is lower than the second voltage.

[0009] In one or more embodiments, the first voltage is a system ground.

[0010] In one or more embodiments, the first voltage is higher than the second voltage.

[0011] In one or more embodiments, the providing the digital indication comprises providing a voltage of the first capacitive sensor through a multiplexer.

[0012] In one or more embodiments, the method additionally comprises:

[0013] charging the second capacitive sensor with the first voltage and charging the first capacitive sensor with the second voltage;

[0014] after the charging, removing the first voltage from the second capacitive sensor and removing the second voltage from the first capacitive sensor, and thereafter equalizing charge on the first capacitive sensor and the second capacitive sensor;

[0015] After the equalization, a digital indication of a sensed voltage level of the second capacitive sensor is provided.

[0016] In one or more embodiments, the method additionally includes comparing the sensed voltage level of the first capacitive sensor to a threshold to determine whether the first capacitive sensor is activated.

[0017] In one or more embodiments, the sensed voltage level of the first capacitive sensor is compared to a second threshold to determine whether the second capacitive sensor is activated.

[0018] In one or more embodiments, the method additionally includes comparing the sensed voltage level of the first capacitive sensor to a threshold to determine whether the second capacitive sensor is activated.

[0019] In one or more embodiments, the sensed voltage level of the first capacitive sensor is indicative of a proximity of an object relative to the first capacitive sensor.

[0020] In one or more embodiments, the sensed voltage level of the first capacitive sensor is indicative of a proximity of an object relative to the second capacitive sensor.

[0021] In one or more embodiments, the equalization is performed by a resistive circuit coupled in a path between the first capacitive sensor and the second capacitive sensor.

[0022] In one or more embodiments, the first capacitive sensor and the second capacitive sensor are part of a plurality of capacitive sensors, the method additionally including:

[0023] periodically providing a digital indication of a sensed voltage level indicative of a capacitance of each capacitive sensor of the plurality of capacitive sensors.

[0024] According to another embodiment, a circuit includes:

[0025] a plurality of external terminals;

[0026] a plurality of switching circuits;

[0027] at least one analog-to-digital converter;

[0028] control circuitry to configure the circuit to perform a capacitance sensing routine to sense a capacitive sensor coupled to the plurality of external terminals, the control circuitry configured to control a first one of the plurality of switch circuits to charge a first one of the plurality of external terminals to a first voltage and to control a second one of the plurality of switch circuits to charge a second one of the plurality of external terminals to a second voltage, the first voltage being different than the second voltage, control the first switch circuit to remove the first voltage from the first external terminal and the second switch circuit to remove the second voltage from the second external terminal after the charging such that a capacitive sensor coupled to the first external terminal can equalize charge with a capacitive sensor coupled to the second external terminal, and control a digital indication of a sensed voltage level of the first external terminal to be provided by an analog-to-digital converter of the at least one analog-to-digital converter after the equalizing.

[0029] In one or more embodiments, the first voltage is lower than the second voltage.

[0030] In one or more embodiments, the circuit is configured to use the digital indication to determine whether a capacitive sensor coupled to the first external terminal has been activated.

[0031] In one or more embodiments, the circuit is configured to use the digital indication to determine whether a capacitive sensor coupled to the second external terminal has been activated.

[0032] In one or more embodiments,

[0033] wherein the control circuitry is configured to control the circuit to periodically provide a digital indication of a sensed voltage level of each of the plurality of external terminals by the at least one analog-to-digital converter.

[0034] According to another embodiment, an electronic system includes a circuit as previously described and additionally includes:

[0035] a plurality of capacitive sensors, wherein each capacitive sensor is coupled to an external terminal of the plurality of external terminals.

[0036] In one or more embodiments, the electronic system additionally includes at least one resistor, wherein a resistor of the at least one resistor is connected to a capacitive sensor coupled to the first external terminal and to a capacitive sensor coupled to the second external terminal. BRIEF DESCRIPTION OF DRAWINGS

[0037] The application can be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0038] Figure 1 is a circuit diagram of an electronic system according to one embodiment of the application.

[0039] Figure 2 is a flowchart illustrating operation of an electronic system according to one embodiment of the application. Figure 1

[0040] Figure 3 is a circuit diagram of a portion of an electronic system according to one embodiment of the application during a pre-charge phase. Figure 1

[0041] Figure 4 is a circuit diagram of a portion of an electronic system according to one embodiment of the application during a charge redistribution phase. Figure 1

[0042] Figure 5 is a circuit diagram of a portion of an electronic system according to one embodiment of the application during a digitization phase. Figure 1

[0043] Figure 6 is a circuit diagram of an electronic system according to another embodiment of the application.

[0044] Unless otherwise indicated, like drawing reference numerals indicate like items in different figures. The various figures are not necessarily drawn to scale. DETAILED DESCRIPTION

[0045] A detailed description of models for carrying out the application is set forth herein. The description is intended to be illustrative, and not to be limiting.

[0046] As disclosed herein, a circuit system and method for providing digitized voltage values of one capacitive sensor, where a second capacitive sensor is used for charge equalization. After charge equalization, an analog-to-digital converter (ADC) provides a digital value representing a voltage of one sensor indicative of a capacitance of the sensor. In the case of some embodiments, providing such a system can allow for a reduction in the number of external terminals (e.g., pins, pads, bumps) of an integrated circuit, where only one terminal is needed for each capacitive sensor. Also, some embodiments can allow for simultaneous execution of multiple phases of a routine for multiple pairs of capacitive sensors with a multiplexed ADC. Also, in the case of some embodiments, the digitized values can be used to determine whether either of the two capacitive sensors has been activated.

[0047] Figure 1 ​​​​is a circuit diagram of an electronic system 101 according to one embodiment of the present application. In the illustrated embodiment, system 101 includes a capacitive sensor array 110, which includes a number N of capacitive sensors (105, 107, 109, and 111). In some embodiments, array 110 is part of a touch screen. In one embodiment, each capacitive sensor can represent a "button" location on a touch screen, such as a particular number, letter, or device command button that a user activates by touching the location. For example, a touch screen can be implemented on a household appliance (e.g., a refrigerator, microwave, washing machine), a car, an HVAC controller, or a self-service terminal (e.g., an ATM). When a finger or stylus is in close proximity to or touches a capacitive sensor, the sensor's capacitance changes to indicate that the function of the sensor needs to be activated. However, in other embodiments, array 110 can be implemented in other types of systems, such as in a measurement device where each electrode represents a level detector that measures a delta, for example.

[0048] Different types of capacitive sensors can be used in different embodiments. In one embodiment, a capacitive sensor is a self-capacitance or absolute capacitance sensor, in which an object (e.g., a finger or stylus) loads the sensor or adds capacitance to ground. In other embodiments, an object in close proximity to a sensor decreases the parasitic capacitance to ground. In other embodiments, a capacitive sensor is a mutual-capacitance sensor, in which an object changes the mutual coupling between a row electrode and a column electrode.

[0049] System 101 also includes electronic circuitry for determining whether a capacitive sensor has been activated, which in one embodiment is implemented in an integrated circuit 103. In one embodiment, integrated circuit 103 is a microprocessor that includes a processor 129, an analog-to-digital converter (ADC) 133, and a plurality of external terminals, where terminals 102, 104, 106, and 108 are connected to sensors 105, 107, 109, and 111, respectively. Circuit 103 also includes switch circuits 119, 121, 123, and 125, which are connected to terminals 102, 104, 106, and 108, respectively, for controlling the coupling of the terminals to either a voltage terminal VREF, a voltage terminal ground, or a channel of ADC 133. In the illustrated embodiment, switch circuits 119, 121, 123, and 125 are three-position switches. In some embodiments, the switch circuits can be implemented with transistors (e.g., NFETs, PFETs) and / or one or more pass gates.

[0050] In the illustrated embodiment, the ADC 133 includes a multiplexer 131 having an input connected to each of the switch circuits 199, 121, 123, and 125. The output of the multiplexer 131 is connected to a switch 137. In the illustrated embodiment, the ADC 133 includes a sample and hold capacitor 139 for sampling the voltage at the output of the multiplexer 131 when the switch 137 is closed. The ADC 133 includes a digitizer 134 for providing a digital representation of the sampled analog voltage on the capacitor 139. The digitizer 134 can implement one of a variety of types of digitizing converters, such as a successive approximation converter, a delta-sigma converter, a dual-slope converter, an integrating converter, a direct conversion converter, or a flash converter. In some embodiments, the ADC 133 does not include the sample and hold capacitor 139.

[0051] The integrated circuit 103 includes a controller 127 for controlling the operation of the ADC 133 and the switch circuits 119, 121, 123, and 125 during a routine to determine the capacitances of the capacitive sensors 105, 107, 109, and 111 by generating digitized values of the voltage levels of the capacitive sensors 105, 107, 109, and 111. The controller generates switch signals (SC1, SC2, SCN-1, and SCN) for controlling the switch circuits (119, 121, 123, and 125), a multiplexer control signal for controlling the multiplexer 131, and a control signal (ADCC) for controlling the switch 137. In some embodiments, the functions of the controller 127 are performed by the processor 129.

[0052] During the voltage determination routine, each capacitive sensor is coupled through a resistor (113, 115) to another capacitive sensor of the array 110 to perform a charge equalization of the sensor with another sensor to equalize the charge on the sensor. For example, the capacitive sensor 105 is coupled through the resistor 113 to the capacitive sensor 107. In one embodiment, the resistors 113 and 115 are each 4.7 K ohms, but can be other values in other embodiments. In one embodiment, the conductive electrode of the capacitive sensor (105) is connected to the resistor (113) and to the external terminal (102). In one embodiment, the pair of capacitive sensors coupled by the resistors are adjacent to each other in the array 110. In other embodiments, the capacitive sensors of the pair are located at positions that are not adjacent to each other so that two pairs of capacitive sensors are not activated at the same time. In some embodiments, a pair of sensors will be in different sensor arrays. In one embodiment, a pair of sensors are on different touchscreens.

[0053] Figure 2is a flowchart showing the stages of a measurement routine for providing a digital voltage value indicative of the capacitance of capacitor sensor 107. In pre-charge stage 201, capacitor sensor 105 is charged to a reference voltage VREF, and capacitor sensor 107 is charged to VSS (discharged to ground in the illustrated embodiment).

[0054] Figure 3 is a circuit diagram showing portions of system 101 during the pre-charge stage for digitizing the voltage of sensor 107. As shown in Figure 3 , switch circuit 119 is in a position to provide voltage VREF to sensor 105 through external terminal 102. Switch circuit 121 is in a position to ground capacitor sensor 107 through external terminal 104. In one embodiment, using these switch circuit configurations, the electrodes of sensor 105 and sensor 107 are pulled to VREF and ground, respectively.

[0055] In one embodiment, VREF is the same voltage as VDD, which is the system supply voltage (e.g., 5 volts) supplied to integrated circuit 103 and array 110. In other embodiments, VREF is different from VDD. In some cases, VREF is higher than VDD (e.g., with a charge pump used to provide VREF). In some embodiments, the higher VREF is, the greater the electromagnetic field of the sensor is, and the better the sensitivity is. In some embodiments, the switch circuits (119 and 121) are connected to a negative charge pump instead of system ground to provide a negative voltage to one of the sensors (e.g., sensor 107 in Figure 3 In some embodiments, the voltage range supplied to the capacitor sensors during the pre-charge stage will match the voltage range supplied to ADC 133.

[0056] Referring back to Figure 2 , in charge redistribution stage 203, the charge is equalized between sensor 105 and sensor 107 through resistor 113. As used herein, "equalized" means that the charge is the same or nearly the same on both capacitor sensors as a result of the charge redistribution.

[0057] Figure 4is a circuit diagram showing portions of system 101 in the charge redistribution phase 203. During the charge redistribution phase, charge from sensor 105 flows through resistor 113 to sensor 107 until the charge on both is equalized. During this time, switch circuits 119 and 121 are shown in positions that provide current paths from terminals 102 and 104 to inputs of multiplexer 131. However, at this time, the inputs of multiplexer 131 connected to switch circuits 119 and 121 are not selected to be provided to the output of multiplexer 131, and / or switch 137 is open such that terminals 102 and 104 see a high impedance in integrated circuit 103. Thus, during the charge redistribution phase 201, little charge from sensor 105 flows into integrated circuit 103.

[0058] Referring back to Figure 2 During the digitization phase 205, ADC 133 provides a digital indication of the voltage level of capacitive sensor 107.

[0059] Figure 5 is a circuit diagram showing portions of system 101 in the digitization phase 205. During this phase, switch circuit 121 is in a position to provide a current path between external terminal 104 and an input of multiplexer 131. Also, in a state such that multiplexer 131 will connect the multiplexer input coupled to capacitive sensor 107 to the output of multiplexer 131, controller 127 places a control signal to multiplexer 131. Controller 127 also closes switch 137 such that the output of multiplexer 131 can be provided to sample and hold capacitor 139 and digitizer 134 can produce a digital indication of the voltage level of capacitive sensor 107 at its output DO. In one embodiment, processor 129 receives the digital representation of the voltage of sensor 107 and uses the digital representation to calculate the capacitance of sensor 107.

[0060] In some embodiments, processor 129 only determines whether voltage VI is below an activation threshold that indicates whether sensor 107 is activated. In some of these embodiments, processor 129 does not use the particular capacitance value in further processing beyond determining whether the threshold has been met. In yet other embodiments, processor 129 determines whether the voltage of VI is above an activation threshold that indicates sensor 105 is activated. In other embodiments, processor 129 determines whether the measured voltage is changing that indicates a change in capacitance.

[0061] During the charge redistribution phase 201, the amount of charge that flows from the capacitive sensor 105 into the capacitive sensor 107 depends on the capacitance of the sensor 105 at that time. In one embodiment, if the sensor 105 is activated (e.g., a conductive object is touching or very close to the area of the array 110 corresponding to the sensor 105, as when a user wants to select the "button" corresponding to the sensor 105), then the capacitance of the sensor 105 will increase. Because of its increased capacitance, the sensor 105 will be able to hold more charge during the pre-charge phase 201. Therefore, more charge will flow into the sensor 107 during the charge redistribution phase. If the sensor 105 is not activated, then less charge will flow into the sensor 107.

[0062] In one embodiment, the voltage of a sensor after charge redistribution is a function of the capacitance of the sensor and the amount of charge stored in the capacitor. In one embodiment, the closer a conductive object is to a capacitive sensor, the higher the capacitance of the sensor. The higher the capacitance of a capacitive sensor, the more charge is required to raise the voltage of the sensor due to charge equalization. The smaller the capacitance, the less charge is required to raise the voltage.

[0063] Therefore, in one embodiment for the case where Figure 2 the lower voltage of the sensor 107 after equalization means that the capacitance of the sensor 107 is higher due to an object being close to the sensor (e.g., when the sensor 107 is activated). Conversely, a higher voltage on the sensor 107 after equalization means that the capacitance of the sensor 107 is lower because no object is close to the sensor (it is not activated) (assuming that the sensor 105 is also not activated).

[0064] In one embodiment, during the pre-charge phase 201, the amount of charge (Q) applied to the sensor 105 due to pre-charging to the voltage VREF is as follows, where C105 is the capacitance of the sensor 105:

[0065] (Equation 1) Q = C105 * VREF;

[0066] During the charge redistribution phase 203, the charge (Q) is equalized with the sensor 107, which has a capacitance shown as C107, and the measured voltage after equalization is shown as V1eq:

[0067] (Equation 2) Q = (C105 + C107) * V1eq;

[0068] By substituting the above two equations and performing mathematical operations, the equation for the capacitance of the sensor 107 (C107) can be found:

[0069] (Equation 3) C105*VREF = (C105+C107)*V1eq;

[0070] (Equation 4) C107*V1eq = C105*(VREF-V1eq);

[0071] (Equation 5) C107 = C105*(VREF-V1eq) / V1eq;

[0072] In some embodiments, the processor 129 implements Equation 5 to measure the absolute capacitance of a sensor (e.g., 107) (assuming the other sensor in the pair (e.g., 105) is not activated during the time). The capacitance C105 of sensor 105 can be determined by a startup routine, where the capacitance of each sensor of the array 110 can be measured when no object is in proximity to the sensor array 110. In other embodiments, C105 can be stored in memory 140 during system manufacture. Those capacitance values can be used by the processor 129 along with the measured voltage V1eq to calculate C107 during operation to determine the capacitance of sensor 107. In some embodiments, the processor 129 uses the measured voltage to derive the capacitance from a table stored in memory 140.

[0073] Because in some embodiments the voltage of a pair of sensors is equivalent after equalization, a measurement of the voltage of one sensor (e.g., sensor 107) by a routine of Figure 2 The measurement of the voltage of one sensor (e.g., sensor 107) by a routine of

[0074] (Equation 6) C105 = (C107*V1eq) / (VREF-V1eq);

[0075] In some embodiments, the voltage on each sensor in a pair of sensors is equivalent after equalization, and the capacitance of the sensors when not activated is similar, Figure 2 The routine of

[0076] (Equation 7) V1eq = (C105*VREF) / (C105+C107);

[0077] As shown from Equation 7, if in Figure 2During the routine, if neither sensor 105 nor sensor 107 is activated, then C1 will be approximately equal to C0, and the measured voltage V1EQ will be approximately equal to VREF / 2. If sensor 105 is activated and sensor 107 is not activated, then capacitor C105 is greater than capacitor C107, and (according to Equation 7 above), the measured voltage V1EQ will be greater than VREF / 2. If sensor 107 is activated and sensor 105 is not activated, then the measured voltage V1EQ will be less than VREF / 2. If both sensors are activated to the same degree, then V1EQ will be approximately VREF / 2. However, in some systems, such as via a numeric touchpad, activating both sensors at once is an erroneous condition.

[0078] Therefore, in some embodiments described herein, the measured voltages Veq1 with thresholds higher than VREF / 2 and thresholds lower than VREF / 2 are compared to allow for the use of Figure 2 The routine determines whether any sensor in the sensor pair has been activated.

[0079] Figure 6 This is a circuit diagram of an electronic system according to another embodiment of the present invention. Figure 6 Implementation examples and Figure 1 The implementation is similar, except that only one capacitive sensor in each capacitive sensor pair is connected to the ADC (ADC 635). Although Figure 6 Not shown, but the ADC 635 includes a multiplexer, switches, sample and hold capacitors, and related components. Figure 1 The ADC133 includes a multiplexer 131, a switch 137, a sample-and-hold capacitor 139, and a digitizer 134, similar to the digitizer in the ADC133. Array 602 includes several capacitive sensors, of which sensors 605, 607, 609, and 611 are shown in... Figure 6 Integrated circuit 603 includes switching circuits 619, 621, 623, and 625, which are similar to switching circuits 119, 121, 123, and 125. However, switching circuits 619 and 623 are not connected to the ADC. Integrated circuit 603 includes a processor 629 and a memory 640. Integrated circuit 603 includes a controller 627, similar to the controller 127 of integrated circuit 103, for controlling the operation of switching circuits 619, 621, 623, and 625 and the ADC 635 during voltage measurement routines. The signal output by controller 627 is not... Figure 6 As shown in the figure. Integrated circuit 603 may have different configurations in other embodiments.

[0080] In the illustrated embodiment, integrated circuit 603 performs operations for each sensor pair (e.g., sensors 605 and 607). Figure 2the routine of FIG. 6B, and reads the voltage of the sensor (607) connected to the pair of ADC 635. The processor 629 then compares the measured voltage to 1) an activation threshold above VREF / 2 to indicate that one sensor in the pair is activated, 2) an activation threshold below VREF / 2 to indicate that the other sensor in the pair is activated, or 3) between the two activation thresholds to indicate that neither sensor is activated.

[0081] In some embodiments, the capacitance of the current path and the capacitance of the sample and hold capacitor (139) can affect the value of the measured voltage read during the routine of FIG. 6B. Thus, in some embodiments, the measured voltage (VEQ) indicating that both sensors in a pair are not activated can be different from VREF / 2. In these embodiments, the processor 629 will compare the measured voltage to an activation threshold above VEQ to indicate that one sensor in the pair is activated or an activation threshold below VEQ to indicate that the other sensor in the pair is activated. In some embodiments, VEQ is determined during system manufacturing and stored in memory 640 or determined during the system startup routine when no sensors are activated. Figure 2

[0082] In some embodiments, the activation thresholds are based on a percentage of VREF or VEQ (e.g., in one embodiment, the activation threshold voltages are approximately 1.25VEQ and.75VEQ). In other embodiments, the activation thresholds are fixed values above and below VEQ or VREF (e.g., VEQ-30mV, VEQ 30mV). In some embodiments, the activation threshold amount will depend on the thickness of the plastic or glass covering the sensor, the value of VREF, the capacitance of the non-activated sensor, and the granularity of the ADC.

[0083] Figure 6 One advantage of the circuit of FIG. 6B over the circuit of FIG. 6A is that, for some embodiments, only half of the ADC channels of the ADC 635 are needed to determine whether a capacitive sensor of the array 602 has been activated to the desired half of the time because Figure 1 One advantage of the system of FIG. 6B over the system of FIG. 6A is that, for some embodiments, only half of the ADC channels of the ADC 635 are needed for sensor activation detection. Figure 2 One advantage of the system of FIG. 6B over the system of FIG. 6A is that, for some embodiments, only half of the ADC channels of the ADC 635 are needed for sensor activation detection. Figure 6 Referring back to FIG. 6B, the processor 629 can determine whether the measured voltage is above or below the activation threshold to determine which sensor in the pair is activated. In some embodiments, the processor 629 can determine which sensor in the pair is activated by comparing the measured voltage to a second activation threshold. The second activation threshold can be a fixed value above or below the first activation threshold. In some embodiments, the second activation threshold is a fixed value above or below VREF / 2. In other embodiments, the second activation threshold is a fixed value above or below VEQ. In some embodiments, the second activation threshold is a fixed value above or below VREF / 2 or VEQ that is determined during system manufacturing and stored in memory 640 or determined during the system startup routine when no sensors are activated.

[0084] Referring back to FIG. 6B, the processor 629 can determine whether the measured voltage is above or below the activation threshold to determine which sensor in the pair is activated. In some embodiments, the processor 629 can determine which sensor in the pair is activated by comparing the measured voltage to a second activation threshold. The second activation threshold can be a fixed value above or below the first activation threshold. In some embodiments, the second activation threshold is a fixed value above or below VREF / 2. In other embodiments, the second activation threshold is a fixed value above or below VEQ. In some embodiments, the second activation threshold is a fixed value above or below VREF / 2 or VEQ that is determined during system manufacturing and stored in memory 640 or determined during the system startup routine when no sensors are activated. Figure 2 ​In the illustrated embodiment, sensor 105 is charged to VREF and sensor 107 is grounded during the pre-charge phase 201 and the voltage of sensor 107 is read during the digitization phase to determine the capacitance of sensor 107. However, in other embodiments, sensor 107 can be charged to VREF and sensor 105 can be grounded during the pre-charge phase. Also, in some embodiments, the voltage of sensor 105 can be read during the digitization phase to determine the capacitance of sensor 107.

[0085] In some embodiments of system 101, after the routine of Figure 2 is executed to obtain a digitized voltage indicative of the capacitance of sensor 107, the circuit 103 uses the routine of Figure 2 to obtain digitized voltages indicative of the capacitances of other capacitive sensors in array 110. For example, after the routine of Figure 2 is run for sensor 107, a routine can be run to obtain a voltage indicative of the capacitance of sensor 105. In this routine, sensor 107 would be pre-charged to VREF and sensor 105 would be grounded in phase 201. In phase 205, the voltage level of sensor 105 would be digitized.

[0086] For system 101, after the voltage of sensor 105 has been measured with the routine of Figure 2 the routine of Figure 2 is used to measure the capacitance indicative voltage of other capacitive sensors (e.g., 109 and 111). For example, to measure the voltage of sensor 111, during the pre-charge phase 201, sensor 109 would be charged to VREF and sensor 111 would be charged to VSS. After all of the sensors have been checked, the controller 127 would loop back to the sensors of array 110 to check the capacitance indicative voltage level to determine if any of the sensors have been activated in the routine of Figure 2 In some embodiments, each pair of sensors would be checked consecutively in order. However, in other embodiments, each pair of sensors would not be checked consecutively in order.

[0087] For embodiments of Figure 6 after the routine of Figure 2 is run to check if any of sensors 605 or 607 are activated, the routine would be run for other pairs of sensors (e.g., 609 and 611). After all of the pairs of sensors have been checked, each pair of sensors would be checked again.

[0088] One advantage that may arise in the embodiments shown or described herein is that, since the system does not use the ADC's sample-and-hold capacitor (139) during the pre-charge and equalization phases, the ADC (133, 635) can perform the digitization phase 201 for one sensor in the sensor pair while the other sensor pairs are in the pre-charge phase 203 and / or equalization phase 205. For example, when ADC 133 provides a digital value of the voltage of sensor 107 in the digitization phase 205, the sensor pair of sensors 109 and 111 is in the pre-charge phase 201, and another sensor pair (not shown) of array 110 is in the charge redistribution phase 203. However, if the system uses the sample-and-hold capacitor 139 for charge equalization, it is not possible to perform both simultaneously. Figure 2 This is a stage in the routine used for other sensors. Therefore, in some cases, a system using sample-and-hold circuitry for charge equalization may take three times longer to determine whether any of the sensors has been activated.

[0089] Another potential advantage compared to systems using the sample-and-hold capacitor (139) of the ADC for charge equalization is that the effectiveness of the system can depend less on the potential capacitance of the capacitive sensors relative to the size of the capacitor in the sample-and-hold circuit. In some embodiments, the array of capacitive sensors typically has the same size, compared to cases where the capacitance values ​​in the inactive state would be relatively identical. Because the sensors have relatively uniform capacitance, charge equalization can be performed more efficiently, allowing the integrated circuit 103 to be used effectively with arrays of capacitive sensor sizes over a wide range. The effectiveness of circuits using the sample-and-hold capacitor of the ADC for charge equalization would be limited by the array having sensors of a certain size. However, other embodiments of the invention can operate with arrays of capacitive sensors with different capacitance sizes.

[0090] In addition, relative to Figure 6 Implementation examples, Figure 2 A single instance of the routine can be used to determine whether either of the two sensors is activated. On the other hand, a system using the ADC's sample-and-hold capacitors (139) for charge equalization would require running a read routine for each sensor to determine whether a sensor has been read. Therefore, in Figure 6 In the case of this embodiment, the time required to determine the sensor activation of the array can be reduced by half.

[0091] although Figure 2The routine is shown charging the sensors to be read to a ground voltage during the pre-charge phase 201, but in other embodiments, the sensors to be read can be charged to other voltages (e.g., VDD, ½ VREF, a negative voltage) during pre-charge. In some embodiments, the sensors to be read (e.g., sensors 107 in Figure 2 VREF, and the other sensor in the pair (e.g., sensor 105) can be grounded.

[0092] In other embodiments, the electronic system can have other configurations. For example, in some embodiments, each sensor will have its own ADC (where the ADC will not include a multiplexer). In other embodiments, some of the circuitry of the integrated circuit 103 or 603 can be located in a different integrated circuit. In some embodiments, charge can be balanced among a greater number of capacitive sensors, where each capacitive sensor will be coupled to more than one sensor with a resistor. Also, in other embodiments, the switching circuit (119) can have a different configuration. In some embodiments, a determination of whether a sensor is activated can be made by logic circuitry coupled to the ADC.

[0093] In some embodiments described herein, the electronic system can be implemented to allow each capacitive sensor to have one external terminal, allowing the integrated circuit to sense the voltage of a greater number of capacitive sensors.

[0094] In one embodiment, a method of capacitive sensing includes charging a first capacitive sensor with a first voltage and charging a second capacitive sensor with a second voltage. The first voltage is different from the second voltage. The method includes, after charging, removing the first voltage from the first capacitive sensor and removing the second voltage from the second capacitive sensor, and then balancing charge on the first capacitive sensor and the second capacitive sensor. The method includes, after balancing, providing a digital indication of a sensed voltage level of the first capacitive sensor with an analog-to-digital converter.

[0095] In another embodiment, a circuit includes a plurality of external terminals, a plurality of switch circuits, at least one analog-to-digital converter, and control circuitry to configure the circuit to perform a capacitance sensing routine for sensing a capacitive sensor coupled to the plurality of external terminals. The control circuitry is configured to control, during a pre-charge phase, a first switch circuit of the plurality of switch circuits to charge a first external terminal of the plurality of external terminals to a first voltage and to control a second switch circuit of the plurality of switch circuits to charge a second external terminal of the plurality of external terminals to a second voltage, the first voltage being different from the second voltage. The control circuitry is configured to control, after charging, the first switch circuit to remove the first voltage from the first external terminal and the second switch circuit to remove the second voltage from the second external terminal, enabling the capacitive sensor coupled to the first external terminal to equalize charge with the capacitive sensor coupled to the second external terminal. The control circuitry is configured to control, after equalizing, to provide, by an analog-to-digital converter of the at least one analog-to-digital converter, a digital indication of a sensed voltage level of the first external terminal.

[0096] While particular embodiments of the present application have been shown and described, it will be understood, of course, that, based on the teachings herein, changes and modifications can be made to the application without departing from the true spirit and scope of the application, and it is therefore intended to cover in the appended claims all such changes and modifications that are within the true spirit and scope of this application.

Claims

1. A method of capacitive sensing, characterized by, comprises: charging a first capacitive sensor with a first voltage and a second capacitive sensor with a second voltage, the first voltage being different from the second voltage; after the charging, removing the first voltage from the first capacitive sensor and the second voltage from the second capacitive sensor, and thereafter equalizing charge on the first capacitive sensor and the second capacitive sensor; after the equalizing, providing a digital indication of a sense voltage level of the first capacitive sensor with an analog-to-digital converter; wherein a comparison of the sense voltage level of the first capacitive sensor to a threshold is used to determine whether the first capacitive sensor is activated; and a comparison of the sense voltage level of the first capacitive sensor to a second threshold is used to determine whether the second capacitive sensor is activated.

2. The method of claim 1, wherein, further comprising: charging the second capacitive sensor with the first voltage and the first capacitive sensor with the second voltage; after the charging, removing the first voltage from the second capacitive sensor and the second voltage from the first capacitive sensor, and thereafter equalizing charge on the first capacitive sensor and the second capacitive sensor; after the equalizing, providing a digital indication of a sense voltage level of the second capacitive sensor.

3. The method of claim 1, wherein, the equalizing is performed by a resistive circuit coupled in a path between the first capacitive sensor and the second capacitive sensor.

4. The method of claim 1, wherein, the first capacitive sensor and the second capacitive sensor are part of a plurality of capacitive sensors, the method further comprising: periodically providing a digital indication of a sense voltage level indicative of a capacitance of each capacitive sensor of the plurality of capacitive sensors.

5. A circuit, characterized by comprises: a plurality of external terminals; a plurality of switch circuits; at least one analog-to-digital converter; control circuitry for configuring the circuitry to perform a capacitive sensing routine to sense a capacitive sensor coupled to the plurality of external terminals, the control circuitry configured to control a first switch circuit of the plurality of switch circuits to charge a first external terminal of the plurality of external terminals to a first voltage and to control a second switch circuit of the plurality of switch circuits to charge a second external terminal of the plurality of external terminals to a second voltage, the first voltage being different from the second voltage, control the first switch circuit to remove the first voltage from the first external terminal and control the second switch circuit to remove the second voltage from the second external terminal after the charging, so that a capacitive sensor coupled to the first external terminal can equalize charge with a capacitive sensor coupled to the second external terminal, and control a digital indication of a sense voltage level of the first external terminal to be provided by an analog-to-digital converter of the at least one analog-to-digital converter after the equalizing; wherein a comparison of the sense voltage level of the first external terminal to a threshold is used to determine whether a capacitive sensor coupled to the first external terminal is activated; and a comparison of the sense voltage level of the first external terminal to a second threshold is used to determine whether a capacitive sensor coupled to the second external terminal is activated.

6. The circuit of claim 5, wherein: wherein the control circuitry is configured to control the circuit to periodically provide, by the at least one analog-to-digital converter, a digital indication of a sensed voltage level of each of the plurality of external terminals.

7. An electronic system, characterized by comprising the circuit of claim 5 and further comprising: a plurality of capacitive sensors, wherein each capacitive sensor is coupled to an external terminal of the plurality of external terminals.

8. The electronic system of claim 7, wherein, further comprising at least one resistor, wherein a resistor of the at least one resistor is connected to a capacitive sensor coupled to the first external terminal and a capacitive sensor coupled to the second external terminal.

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