An Interrupt Verification Method and System Based on the RISC-V Architecture

Abstract

The present invention relates to the technical field of interrupt verification, and specifically relates to an interrupt verification method and system based on the RISCV architecture, including: an RTL design module, connected to a status register, which realizes randomly injecting different types of interrupts and randomly configuring the privilege mode for handling interrupts through operations on the status register; a cache module, which is used to return through the corresponding xret instruction and store instructions of different privilege modes after processing interrupt exceptions; a check module, which is used to mask the check when inserting an interrupt and adjust the check after inserting a random interrupt; an interrupt signal generating device, which is used to connect and interact with the RTL design module, the cache module and the check module. In the module verification stage of the present invention, complex interrupt scenarios are verified by means of force, the verification scenarios of interrupts are comprehensively covered, and the verification of interrupts converges faster.

Description

Technical Field

[0001] The present invention relates to the technical field of interrupt verification, and particularly to an interrupt verification method and system based on the RISC-V architecture. Background Art

[0002] Current interrupts are random, diverse, and uncertain. There are the following numerous types of interrupts based on the RISC-V architecture:

[0003] Machine mode: machine timer interrupt; machine software interrupt; machine external interrupt;

[0004] Supervisor mode: supervisor timer interrupt; supervisor software interrupt; supervisor external interrupt;

[0005] User mode: user timer interrupt; user software interrupt; user external interrupt;

[0006] Hypervisor supervisor mode (no virtual): supervisor guest external interrupt; hypervisor guest interrupt (multiple interrupt sources with IDs 0 to N can be configured);

[0007] Hypervisor supervisor mode (virtual): virtual supervisor timer interrupt; virtual supervisor software interrupt; virtual supervisor external interrupt;

[0008] Hypervisor user mode (virtual): virtual user timer interrupt; virtual user software interrupt; virtual user external interrupt;

[0009] For different types of interrupts, the privilege modes that can be processed are also different. Taking the virtual supervisor timer interrupt as an example:

[0010] If the current working mode is Machine mode, the privilege mode for handling interrupt exceptions can be M mode; if the current working mode is supervisor mode, the privilege modes for handling interrupt exceptions can be M mode and S mode; if the current working mode is virtual supervisor mode, the privilege modes for handling interrupt exceptions can be M mode, S mode, and VS mode.

[0011] Since interrupt verification generally starts relatively late and is basically carried out in a relatively top-level environment, the top-level verification is relatively cumbersome. In modular verification, it is difficult to cover the numerous scenarios of interrupts, and bugs are often missed and passed on to software-level verification. Software programs are relatively large and complex, and debugging is relatively unintuitive. Summary of the Invention

[0012] Aiming at the deficiencies of the prior art, the present invention discloses an interrupt verification method and system based on the RISCV architecture, which is used to solve the problems that interrupt verification generally starts relatively late and is basically carried out in a relatively top-level environment, and the top-level verification is relatively cumbersome. In modular verification, it is difficult to cover the numerous scenarios of interrupts, and bugs are often missed and passed on to software-level verification. Software programs are relatively large and complex, and debugging is relatively unintuitive.

[0013] The present invention is realized through the following technical solutions:

[0014] In a first aspect, the present invention discloses an interrupt verification system based on the RISCV architecture, including:

[0015] An RTL design module, connected to the status register, realizes randomly injecting different types of interrupts and randomly configuring the privilege mode for handling interrupts through operations on the status register;

[0016] A cache module, used to return through the corresponding xret instruction and store instructions of different privilege modes after processing interrupt exceptions;

[0017] An inspection module, used to mask the check when inserting an interrupt and make adjustments to the check after inserting a random interrupt;

[0018] An interrupt signal generating device, used to connect and interact with the RTL design module, the cache module, and the inspection module.

[0019] Furthermore, the RTL design module simultaneously monitors whether the RTL module has an anomaly and whether it has processed a randomly injected interruption.

[0020] Furthermore, the different privilege modes include machine mode, supervisor mode, and user mode; the xret instructions include machine mode MRET, supervisor mode SRET, and user mode URET.

[0021] Furthermore, in a single interruption trigger of the system, two random counters are used to cyclically control the high-level time and the low-level time holding time of the single interruption.

[0022] Furthermore, during multiple interruption triggers of the system, an interruption interval counter is used to randomly generate the generation interval between interruptions.

[0023] Furthermore, during the interruption pull-down counting process of the system, wait for the counter to trigger the interruption pull-down moment; during the interruption interval pull-down counting process, wait for the counter to trigger the interruption recovery and pull-up moment.

[0024] In a second aspect, the present invention discloses an interruption verification method based on the RISC-V architecture. When the method is executed, the interruption verification system based on the RISC-V architecture as described in the first aspect is used, including the following steps:

[0025] Step1: Check whether there is an anomaly refresh. If there is an anomaly refresh, go to step2; if there is no anomaly refresh, go to step3;

[0026] Step2: Clear the interruption interval counter and the interruption flag; randomly pull down the interruption counter and the interruption interval counter; at the same time, according to the state of the stored CPU status register, restore the value of the CPU status register or end the current interruption processing flow;

[0027] Step3: Determine whether there is a random interruption in flight. If there is, determine whether the interruption has been processed. If it is completed, directly go to step2; if the interruption is not completed, go to step6 again; if there is no triggered interruption in flight, then according to whether the interruption interval counter reaches the trigger value, end the current interruption processing flow or go to step4;

[0028] Step 4: Randomly trigger a valid interrupt number, record this number, then based on the interrupt corresponding to this number and the current CPU working mode, randomly select a reasonable interrupt exception handling privilege mode, save the status registers related to the interrupt of the current CPU, set the interrupt flag, the interrupt status bits and enable bits for forced response; at the same time, set the flag for the interrupt pull-down process;

[0029] Step 5: During the process of handling the interrupt pull-down, further determine whether the interrupt flag is valid and reaches the trigger value of the interrupt pull-down counter. If not satisfied, increment the interrupt pull-down counter and end the current interrupt handling process; if satisfied, jump to step 6; if not in the process of handling the interrupt pull-down, go to step 7;

[0030] Step 6: Perform the corresponding random interrupt pull-down, clear the random interrupt pull-down counter to 0, clear the flag for the random interrupt pull-down process, set the flag for the random interrupt pull-down interval, and end the current interrupt handling process.

[0031] Step 7: During the process of handling the interrupt pull-down interval, further determine whether the interrupt flag is valid and reaches the trigger value of the interrupt pull-down interval counter, and then end the current interrupt handling process or go to step 8. If not in the process of handling the interrupt pull-down interval, directly end the current interrupt handling process;

[0032] Step 8: Perform the corresponding random interrupt pull-up, clear the interrupt pull-down interval counter to 0, clear the flag for the interrupt pull-down interval, set the flag for the random interrupt pull-down process, and end the current interrupt handling process.

[0033] Furthermore, in the method, determine whether there is a stored status of the CPU status register. If there is, restore the value of the CPU status register; if not, end the current interrupt handling process.

[0034] Furthermore, in the method, determine whether the interrupt interval counter reaches the trigger value. If not, increment the interrupt interval counter and end the current interrupt handling process. If it reaches the trigger value of the interrupt interval counter, go to step 4.

[0035] Furthermore, in the method, determine whether the interrupt flag is valid and reaches the trigger value of the interrupt pull-down interval counter. If the condition is not satisfied, increment the interrupt pull-down interval counter and end the current interrupt handling process. If the condition is satisfied, go to step 8.

[0036] The beneficial effects of the present invention are:

[0037] In the module verification stage of the present invention, complex interrupt scenarios are verified by means of force, covering the verification scenarios of interrupts comprehensively, so that the verification of interrupts converges faster. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0039] Figure 1 is a schematic block diagram of an interrupt verification system based on the RISCV architecture;

[0040] Figure 2 is a single-interrupt simulation behavior diagram of an embodiment of the present invention;

[0041] Figure 3 is a multi-interrupt simulation behavior diagram of an embodiment of the present invention;

[0042] Figure 4 is a flowchart of an interrupt verification method based on the RISCV architecture. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the scope of protection of the present invention. Embodiment 1

[0044] This embodiment discloses a Figure 1 shown interrupt verification system based on the RISCV architecture, including:

[0045] The RTL design module is connected to the status register, and by operating the status register, it realizes randomly injecting different types of interrupts and randomly configuring the privilege mode for handling interrupts;

[0046] The cache module is used to return through the corresponding xret instruction and store instructions of different privilege modes after processing the interrupt exception;

[0047] The check module is used to mask the check when inserting an interrupt and adjust the check after inserting a random interrupt;

[0048] An interrupt signal generating device for connecting and interacting with the RTL design module, cache module, and check module.

[0049] In the design module of this embodiment, the device is mainly connected to the status registers of the design module, including (mstatus, mie, mip, mideleg, sideleg). By operating on the status registers, different types of interrupts can be randomly injected, and the privilege mode for handling interrupts can be randomly configured.

[0050] In the cache module of this embodiment, for different privilege modes (machine mode, supervisor mode, user mode), after handling interrupt exceptions, they are returned through the corresponding xret (machine mode MRET; supervisor mode SRET; user mode URET). Since our interrupts are randomly generated, the xret instruction needs to be placed at a specific address in the memory so that the random interrupts can return normally.

[0051] In one implementation of this embodiment, here we stipulate that if it is the machine privilege mode, we force the exception address of the machine to be 0x90009000 and place the MRET instruction at the address 0x90009000 in the cache module; similarly, for the supervisor privilege mode, we place the SRET instruction at the address 0x90000000; for the user privilege mode, we place the URET instruction at the address 0x90008000.

[0052] In the check module of this embodiment, since the interrupts are randomly injected, in order not to affect the normal program instruction flow, some checks need to be masked when inserting interrupts, and some check adjustments, such as the number of instructions, need to be made after inserting the random interrupts. Embodiment 2

[0053] This embodiment discloses a privileged mode for generating and handling interrupt exceptions. In the RISC-V architecture, there are generally three privileged modes: machine mode, supervisor mode, and user mode, and the privilege of machine mode is greater than that of supervisor mode which is greater than that of user mode. After enabling the hypervisor feature, there are generally machine mode, hypervisor supervisor mode, virtual supervisor mode, and virtual user mode. Similarly, the privilege of machine mode is greater than that of hypervisor supervisor mode which is greater than that of virtual supervisor mode which is greater than that of virtual user mode.

[0054] The interrupts in each existing working mode and the privileged modes that can handle these interrupts are listed in the following table:

[0055]

[0056] In this embodiment, to randomly generate the privileged mode for handling interrupts, it is necessary to be random based on the specific interrupt type and in combination with the current working mode.

[0057] In one implementation of this embodiment, if a Machine timer interrupt is randomly generated, then the privileged mode for handling the exception can only be Machine mode, regardless of the current working mode.

[0058] In one implementation of this embodiment, if a User timer interrupt is randomly generated, the privileged mode for handling the exception can be Machine mode, Supervisor mode, or User mode. In combination with the current working mode, if it is Machine mode, the interrupt exception can be selected to be taken to Machine mode; if it is Supervisor mdoe, the interrupt can be randomly selected to be taken to Machine mode or Supervisor mode. To go to Supervisor mode, the corresponding interrupt bit in the Mideleg system register needs to be configured, and the authority to handle the interrupt is delegated from Machine mode to Supervisor mode; if it is User mode, the interrupt can be randomly selected to be taken to Machine mode, Supervisor mode, or User mode. Similarly, to go to the low-privilege Supervisor mode, the Mideleg register needs to be configured, and to go to the low-privilege User mode, both the Mideleg and Sideleg registers need to be configured. Example 3

[0059] This embodiment discloses Figure 2 The single interrupt simulation behavior shown in the figure uses two random counter cycles to control the high level time and low level time of the single interrupt during the single interrupt trigger.

[0060] This embodiment discloses Figure 3 The multiple interrupt simulation behaviors shown in the figure use an interrupt interval counter to randomly generate the intervals between interrupts during the multiple interrupt triggering process.

[0061] This embodiment discloses the life cycle of an interrupt, triggering an interrupt; setting the interrupt flag; saving the relevant scene before the interrupt; judging whether there is an abnormal refresh other than the interrupt; if so, the interrupt life ends, the interrupt flag is cleared, the scene before the interrupt is restored, and the next interrupt interval count is waited for to be triggered; if there is no abnormal refresh, checking whether the current process is the interrupt lowering count process or the interrupt interval lowering count process.

[0062] In this embodiment, during the interrupt low counting process, the counter is waited for to trigger the interrupt low moment; during the interrupt interval low technical process, the counter is waited for to trigger the interrupt recovery high moment.

[0063] This embodiment also checks the RTL aspect to see if the interrupt processing has been completed. If so, the interrupt life cycle ends, the interrupt flag is cleared, and the scene before the interrupt is restored. Otherwise, the interrupt life cycle is looped. Example 4

[0064] This example discloses a method for interrupt verification based on the RISCV architecture as shown in Figure 4 and includes the following processes:

[0065] Step1: Check if there is an abnormal refresh. If there is an abnormal refresh, go to step2; if there is no abnormal refresh, go to step3.

[0066] Step2: Clear the interrupt interval counter to 0, randomly pull down the interrupt counter to 0, randomly pull down the interrupt interval counter to 0, and clear the interrupt flag; at the same time, determine whether there is the status of the stored CPU status register. If so, restore the value of the CPU status register; if not, end the current interrupt handling process.

[0067] Step3: Determine whether there is a triggered interrupt in flight. If so, determine whether the interrupt has been processed. If it has been completed, directly go to step2; if the interrupt has not been completed, go to step6. If there is no triggered interrupt in flight, determine whether the interrupt interval counter has reached the trigger value. If it has not reached, increment the interrupt interval counter and end the current interrupt handling process. If the trigger value of the interrupt interval counter is reached, go to step4.

[0068] Step4: Randomly trigger a valid interrupt number and record this number. Then, based on the interrupt of this number and the current CPU working mode, randomly select a reasonable interrupt exception handling privilege mode and go to step5.

[0069] Step5: Save the status of the current CPU status register related to the interrupt; set the interrupt flag; force the corresponding random interrupt number; at the same time, set the flag for the interrupt pull-down process; go to step6.

[0070] Step6: Determine whether it is in the process of pulling down the random interrupt? If so, go to step7; if not, go to step9.

[0071] Step7: Determine whether the interrupt flag is valid and has reached the trigger value of the randomly pulled-down interrupt counter. If not, increment the randomly pulled-down interrupt counter and end the current interrupt handling process; if the condition is met, jump to step8.

[0072] Step8: Pull down the corresponding random interrupt, clear the randomly pulled-down interrupt counter to 0, clear the flag for the randomly pulled-down interrupt process, set the flag for the randomly pulled-down interrupt interval, and end the current interrupt handling process.

[0073] Step9: Determine whether it is in the process of handling the pull-down interval of the random interruption? If not, directly end the current interruption handling process; if yes, go to step10.

[0074] Step10: Determine whether the interruption flag is valid and reaches the trigger value of the random pull-down interruption interval counter? If not, increment the random pull-down interruption interval counter and end the current interruption handling process. If the condition is met, go to step11.

[0075] Step11: Pull up the corresponding random interruption, clear the random pull-down interruption interval counter to 0, clear the random interruption pull-down interval flag, set the random interruption pull-down process flag, and end the current interruption handling process.

[0076] In summary, the present invention solves the problems that the interruption verification generally starts relatively late and is basically carried out in a relatively top-level environment, and the top-level verification is relatively cumbersome. In modular verification, it is difficult to cover the numerous scenarios of interruptions, and bugs are often missed in the software-level verification. The software program is relatively large and complex, and the debugging is relatively not intuitive.

[0077] In the module verification stage of the present invention, complex interruption scenarios are verified by the force method, and the verification scenarios of interruptions are comprehensively covered, so that the verification of interruptions converges faster.

[0078] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An interrupt verification method based on the RISCV architecture, characterized in that, The method includes the following steps: Step1: Check for abnormal refresh. If there is abnormal refresh, go to Step2; if there is no abnormal refresh, go to Step3; Step2: Clear the interrupt interval counter to 0, randomly reset the interrupt counter to 0, randomly reset the interrupt interval counter to 0, and clear the interrupt flag; at the same time, according to the status of the stored CPU status register, restore the value of the CPU status register or end the current interrupt handling process; Step3: Determine whether there is a triggered interrupt in progress. If there is, determine whether the interrupt has been processed. If it has been completed, directly go to Step2; if the interrupt has not been completed, go to Step5 again; if there is no triggered interrupt in progress, then according to whether the interrupt interval counter has reached the trigger value, end the current interrupt handling process or go to Step4; Step4: Randomly trigger a valid interrupt number and record the number. Then, according to the interrupt corresponding to this number and the current CPU working mode, randomly select an interrupt exception handling privilege mode, save the status of the CPU status register related to the interrupt, set the interrupt flag and the force corresponding to the random interrupt number; at the same time, set the flag for the interrupt pull-down process; go to Step5 Step5: During the process of handling the random interrupt pull-down, further determine whether the interrupt flag is valid and has reached the trigger value of the random pull-down interrupt counter. If not, increment the value of the random pull-down interrupt counter by 1 and end the current interrupt handling process; if satisfied, jump to Step6; during the process of handling the random interrupt pull-down, go to Step7; Step6: Pull down the corresponding random interrupt, clear the random pull-down interrupt counter to 0, clear the flag for the random interrupt pull-down process, set the random interrupt pull-down interval flag, and end the current interrupt handling process; Step7: During the process of handling the random interrupt pull-down interval, further determine whether the interrupt flag is valid and has reached the trigger value of the random pull-down interrupt interval counter, and then end the current interrupt handling process or go to Step8; Step8: Raise the corresponding random interrupt, clear the random pull-down interrupt interval counter to 0, clear the interrupt pull-down interval flag, set the flag for the random interrupt pull-down process, and end the current interrupt handling process.

2. The interrupt verification method based on the RISC-V architecture according to claim 1, characterized in that In the method, determine whether there is the status of the stored CPU status register. If there is, restore the value of the CPU status register; if not, end the current interrupt handling process.

3. The interrupt verification method based on the RISC-V architecture according to claim 1, wherein In the method, determine whether the interrupt interval counter has reached the trigger value. If not, increment the value of the interrupt interval counter by 1 and end the current interrupt handling process; if the interrupt interval counter has reached the trigger value, go to Step4.

4. The interrupt verification method based on the RISC-V architecture according to claim 1, characterized in that, In the method, determine whether the interrupt flag is valid and has reached the trigger value of the random pull-down interrupt interval counter. If the condition is not met, increment the value of the random pull-down interrupt interval counter by 1 and end the current interrupt handling process; if the condition is met, go to Step8.

5. An interrupt verification system based on the RISC-V architecture, using the interrupt verification method based on the RISC-V architecture according to any one of claims 1-4, characterized in that, It includes: RTL design module, connected to the status register, realizes randomly injecting different types of interrupts and randomly configuring the privilege mode for handling interrupts by operating on the status register; Cache module, used to return and store instructions in different privilege modes through the corresponding xret instruction after handling interrupt exceptions; Check module, used to mask check when inserting an interrupt and adjust check after inserting a random interrupt; Interrupt signal generating device, used to connect and interact with the RTL design module, cache module and check module.

6. The interrupt verification system based on the RISC-V architecture according to claim 5, wherein The RTL design module simultaneously monitors whether the RTL module has an exception and whether a randomly injected interrupt has been processed.

7. The interrupt verification system based on the RISC-V architecture according to claim 5, wherein The different privilege modes include machine mode, supervisor mode and user mode; the xret instructions include machine mode MRET, supervisor mode SRET and user mode URET.

8. The interrupt verification system based on the RISC-V architecture according to claim 5, characterized in that, In a single interrupt trigger of the system, two random counters are used to cycle and control the holding time of the high level time and low level time of the single interrupt.

9. The interrupt verification system based on the RISC-V architecture according to claim 8, wherein In the process of multiple interrupt triggers of the system, an interrupt interval counter is used to randomly generate the generation interval between interrupts.

10. The interrupt verification system based on the RISC-V architecture according to claim 5, wherein, In the process of interrupt pull-down counting of the system, wait for the random pull-down interrupt counter to trigger the interrupt pull-down moment; in the process of interrupt interval pull-down counting, wait for the random pull-down interrupt interval counter to trigger the interrupt recovery and pull-up moment.

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