A planar cross array structure resistive random access memory and preparation method thereof

Abstract

The present invention discloses a planar cross array structure resistive random access memory and a preparation method thereof, wherein the bottom electrode, the first resistance conversion layer and the second resistance conversion layer are placed in the groove of the insulating substrate, thereby solving the edge effect problem existing in a resistive random access device using an ordinary cross array. By patterning the bottom electrode and relying on the first resistance conversion layer and the second resistance conversion layer, the electrical performance of the device can be effectively improved compared to a single-layer resistive random access layer, the on / off threshold voltage is significantly reduced, the voltage value distribution is significantly concentrated, and the data retention capability and the resistance switching speed are relatively improved, thereby improving reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of memristors, and in particular to a resistive random access memory with a planar cross array structure and a preparation method thereof. Background Art

[0002] In the 21st century, with the advent of the era of big data, the advancement and application of science and technology have generated an amount of data that is unimaginable to ordinary people in human society. At the same time, the amount of data in human society is increasing day by day. The surging demand for data storage is in conflict with the current limited storage device capabilities. Therefore, scientists have begun to seek new materials, new mechanisms, and new structures of storage technology to resolve this current contradiction. In this social context, semiconductor memory devices such as ferroelectric random access memory, phase change random access memory, magnetoresistive random access memory, and resistive random access memory have emerged.

[0003] As a strong competitor of the next generation of memory, RRAM has lower power consumption and miniaturization potential compared to other memories. The cross array integration method can reduce the storage unit area to 4F2 (F is the characteristic size), which will greatly improve the integration density of RRAM and reduce the cost. At the same time, the cross array structure can further realize three-dimensional multi-layer stacking integration, so that the area of ​​each storage unit can be reduced to 4F2 / N (N is the number of layers of the cross array).

[0004] However, the use of ordinary cross arrays will inevitably have edge effect problems in practical applications. The preparation of ordinary cross arrays is to first deposit a strip bottom electrode on a flat insulating substrate, then plate an intermediate dielectric film layer, and finally deposit a strip top electrode that crosses the bottom electrode perpendicularly. The so-called edge effect: the edge of the bottom electrode in the cross array prepared by the above method has a stronger electric field concentration effect, so the dielectric material on the edge and corner of the bottom electrode will undergo resistance transformation before the dielectric above the bottom electrode, and may also cause hazards such as heat concentration. Therefore, the edge effect is one of the problems faced in realizing high-density resistive random access memory.

[0005] In order to solve the problem of edge effect that is inevitable in ordinary cross arrays in practical applications, the present invention prepares a planar cross array structure resistive random access memory in which the bottom electrode is plated into the groove of the substrate, and the double-layer storage medium layer is also placed in the groove to obtain a flat surface, so there is no edge effect. The bottom electrode is patterned to improve the performance parameters of the device. Summary of the invention

[0006] The object of the present invention is to provide a planar cross array structured resistive random access memory and a preparation method thereof, in order to solve the problem of edge effect existing in resistive random access memories using ordinary cross arrays in the prior art.

[0007] The present invention provides a method for preparing a planar cross array structure resistive random access memory, comprising the following steps:

[0008] Spin-coating a photoresist on an insulating substrate to obtain a first sample;

[0009] The first sample is subjected to photolithography and etching processing, so that a plurality of grooves are formed on the first sample;

[0010] Depositing a bottom electrode in each of the grooves to obtain a second sample;

[0011] Depositing a nanostructure on the second sample through a porous film so that each bottom electrode is patterned to obtain a third sample;

[0012] Using adhesive tape to remove the porous film plate on the third sample to obtain a fourth sample;

[0013] sequentially depositing a first resistance conversion layer and a second resistance conversion layer on the fourth sample to obtain a fifth sample;

[0014] removing the photoresist in the fifth sample to obtain a sixth sample;

[0015] A top electrode was deposited on the sixth sample.

[0016] Wherein, in the step of depositing a bottom electrode in each of the grooves:

[0017] The bottom electrode layer is deposited by magnetron sputtering, the bottom electrode is Pt, Al, Au, Ti, TiN or Cu, and the thickness of the bottom electrode is 20nm to 300nm.

[0018] The step of depositing metal on the second sample through the porous film comprises:

[0019] placing a porous film on the second sample;

[0020] By adopting the oblique deposition technology, a layer of nanostructure with a conical sidewall profile is deposited on the surface of each bottom electrode by magnetron sputtering oblique deposition.

[0021] Wherein, in the step of sequentially depositing the first resistance transition layer and the second resistance transition layer on the fourth sample:

[0022] The first resistance conversion layer is a metal oxide, a two-dimensional material, a chalcogenide solid electrolyte, a nitride or an organic matter, and the thickness of the first resistance conversion layer is 5nm to 100nm;

[0023] The second resistance conversion layer is a metal oxide, a two-dimensional material, a chalcogenide solid electrolyte, a nitride or an organic matter, and the thickness of the second resistance conversion layer is 5nm to 100nm;

[0024] The top of the second resistance conversion layer is flush with the top of the insulating substrate.

[0025] Wherein, in the step of depositing a top electrode on the sixth sample:

[0026] The top electrode is Pt, Al, Ag, Zn, Au, Ti, TiN, ITO or Cu, and the thickness of the bottom electrode is 20nm to 300nm.

[0027] The present invention also provides a resistive random access memory prepared by the resistive random access memory preparation method of the planar cross array structure described above, comprising the insulating substrate and a plurality of dielectric structures, the insulating substrate having a plurality of the grooves, each of the dielectric structures being fixedly connected to the corresponding grooves and being located inside the corresponding grooves, each of the dielectric structures comprising the bottom electrode, the nanostructure, the first resistance transition layer, the second resistance transition layer and the top electrode, the bottom electrode being fixedly connected to the groove and being located on the inner bottom wall of the groove, the first resistance transition layer being fixedly connected to the bottom electrode and being located on the top of the bottom electrode, the second resistance transition layer being fixedly connected to the first resistance transition layer and being located on the top of the first resistance transition layer, the nanostructure being fixedly connected to the top of the bottom electrode and being embedded in the first resistance transition layer, and the top electrode being fixedly connected to the top of the insulating substrate and being located on the top of the second resistance transition layer.

[0028] The beneficial effects of the present invention are:

[0029] 1. The bottom electrode, the first resistance conversion layer and the second resistance conversion layer are placed in the groove of the insulating substrate to obtain a flat substrate without edge effect problems, thus solving the edge effect problem caused by the resistive random access memory using an ordinary cross array.

[0030] 2. Moreover, by patterning the bottom electrode, due to the presence of the conical tip at the bottom, the effective thickness of the resistive layer is reduced, and the electric field at the tip is stronger, which can accelerate the migration of oxygen vacancies or metal ions, thereby accelerating the formation and breakage of conductive filaments, and also reducing the operating voltage and device power consumption; at the same time, the electric field is stronger at the tip, which not only makes it easy to generate conductive filaments at the tip, but also suppresses the probability of random generation of conductive filaments outside the tip, thereby reducing randomness and improving reliability.

[0031] 3. Compared with a single-layer resistance change layer, the first resistance change layer and the second resistance change layer can effectively improve the electrical performance of the device, reduce the operating voltage, significantly concentrate the voltage value distribution, and relatively improve the data retention capability and resistance switching speed, thereby improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 It is a flow chart of the steps of the method for preparing a resistive random access memory with a planar cross array structure of the present invention.

[0034] Figure 2 It is a cross-sectional view of a resistive random access memory prepared by the method for preparing a resistive random access memory with a planar cross array structure of the present invention.

[0035] Figure 3 It is a cross-sectional view of the first sample of the present invention.

[0036] Figure 4 It is a cross-sectional view of the second sample of the present invention.

[0037] Figure 5 It is a cross-sectional view of the third sample of the present invention.

[0038] Figure 6 It is a cross-sectional view of the fourth sample of the present invention.

[0039] Figure 7 It is a cross-sectional view of the fifth sample of the present invention.

[0040] Figure 8 It is a cross-sectional view of the sixth sample of the present invention.

[0041] 1-insulating substrate, 2-bottom electrode, 3-first resistance transition layer, 4-second resistance transition layer, 5-top electrode, 6-groove, 7-nanostructure, 11-medium structure. DETAILED DESCRIPTION

[0042] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0043] In the description of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, in the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0044] See also Figures 1 to 8 The present invention provides a method for preparing a planar cross array structure resistive random access memory, comprising the following steps:

[0045] S1: Spin-coat photoresist on an insulating substrate to obtain the first sample;

[0046] S2: performing photolithography and etching on the first sample to form a plurality of grooves on the first sample;

[0047] S3: depositing a bottom electrode in each of the grooves to obtain a second sample;

[0048] S4: depositing a nanostructure on the second sample through a porous film so that each bottom electrode is patterned to obtain a third sample;

[0049] S5: using an adhesive tape to remove the porous film plate on the third sample to obtain a fourth sample;

[0050] S6: sequentially depositing a first resistance transition layer and a second resistance transition layer on the fourth sample to obtain a fifth sample;

[0051] S7: removing the photoresist in the fifth sample to obtain a sixth sample;

[0052] S8: depositing a top electrode on the sixth sample.

[0053] Specifically, in the step of depositing the bottom electrode in each of the grooves:

[0054] The bottom electrode layer is deposited by magnetron sputtering, the bottom electrode is Pt, Al, Au, Ti, TiN or Cu, and the thickness of the bottom electrode is 20nm to 300nm.

[0055] Specifically, the step of depositing metal on the second sample through the porous film includes:

[0056] placing a porous film on the second sample;

[0057] By adopting the oblique deposition technology, a layer of nanostructure with a conical sidewall profile is deposited on the surface of each bottom electrode by magnetron sputtering oblique deposition.

[0058] Specifically, in the step of removing the porous film plate on the third sample sheet using an adhesive tape:

[0059] The use of the tape may be combined with wet etching to remove the porous film more cleanly.

[0060] Specifically, in the step of sequentially depositing the first resistance transition layer and the second resistance transition layer on the fourth sample:

[0061] The first resistance transition layer is made of metal oxide, two-dimensional material, chalcogenide solid electrolyte, nitride or organic matter, and the thickness of the first resistance transition layer is 5nm to 100nm.

[0062] The second resistance conversion layer is a metal oxide, a two-dimensional material, a chalcogenide solid electrolyte, a nitride or an organic matter, and the thickness of the second resistance conversion layer is 5nm to 100nm;

[0063] The top of the second resistance conversion layer is flush with the top of the insulating substrate.

[0064] Specifically, in the step of depositing the top electrode on the sixth sample:

[0065] The top electrode is Pt, Al, Ag, Zn, Au, Ti, TiN, ITO or Cu, and the thickness of the bottom electrode is 20nm to 300nm.

[0066] The present invention also provides a resistive random access memory prepared by the resistive random access memory preparation method of the planar cross array structure described above, comprising the insulating substrate 1 and a plurality of dielectric structures 11, the bottom electrode 2, the first resistance change layer 3, the second resistance change layer 4 and the top electrode 5, the insulating substrate 1 having a plurality of grooves 6, each of the dielectric structures 11 being fixedly connected to the corresponding grooves 6 respectively and being located inside the corresponding grooves 6, each of the dielectric structures 11 comprising the bottom electrode 2, the nanostructure 7, the first resistance change layer 3, the second resistance change layer 4 and the top electrode 5, the bottom electrode 2 being fixedly connected to the groove 6 and being located on the inner bottom wall of the groove 6, the first resistance change layer 3 being fixedly connected to the bottom electrode 2 and being located at the top of the bottom electrode 2, the second resistance change layer 4 being fixedly connected to the first resistance change layer 3 and being located at the top of the first resistance change layer 3, the nanostructure 7 being fixedly connected to the top of the bottom electrode 2 and being embedded in the first resistance change layer 3, the top electrode 5 being fixedly connected to the top of the insulating substrate 1 and being located at the top of the second resistance change layer 4.

[0067] The preparation of an ordinary cross array is to first deposit a strip bottom electrode on a flat insulating substrate, then plate an intermediate dielectric film layer, and finally deposit a strip top electrode that crosses the bottom electrode perpendicularly. The edge of the bottom electrode in the cross array prepared by this method has a stronger electric field concentration effect, and the dielectric material on the edge and corner of the bottom electrode will undergo resistance transformation before the dielectric above the bottom electrode, and may also cause hazards such as heat concentration. The cross array structure adopted by the present invention is to place the bottom electrode, the first resistance transformation layer and the second resistance transformation layer in the groove of the insulating substrate, which solves the edge effect problem of the resistor using an ordinary cross array. By patterning the bottom electrode and relying on the first resistance transformation layer and the second resistance transformation layer, compared with a single-layer resistance transformation layer, the electrical performance of the device can be effectively improved, the on / off threshold voltage is significantly reduced, the voltage value distribution is significantly concentrated, and the data retention capability and resistance switching speed are relatively improved, thereby improving reliability. Specific embodiment one:

[0069] The silicon substrate is processed, and a plurality of grooves 6 are formed on the silicon substrate by photolithography and etching, and the depth of the grooves 6 is 120 nm, thereby obtaining a first sample. The photoresist retained on the first sample is used for subsequent processes.

[0070] On the groove 6 of the silicon substrate, a strip of metal Pt with a thickness of 80 nm was deposited by magnetron sputtering as the bottom electrode 2 to obtain the second sample.

[0071] The porous film is placed on the second sample, and Au is deposited on the surface of each bottom electrode 2 by magnetron sputtering in an oblique deposition manner. The height of the structure depends on the sputtering time, and each nanostructure 7 is not necessarily as shown in the cross section of the sample. Figure 1 The bottom electrodes are generally separated, but may also be connected at the bottom, which is related to controllable parameters such as sputtering time, tilt angle, working gas pressure, substrate rotation and power. The bottom electrode patterning is completed to obtain the third sample.

[0072] The porous film is removed by using an adhesive tape and wet etching to completely remove the porous film, thereby obtaining the fourth sample.

[0073] RF magnetron sputtering is used to deposit 20 nm of MoS2 on the bottom electrode 2 as the first resistance transition layer 3. Argon is used as the sputtering gas, and the target material is a high-purity MoS2 target (99.99%), wherein the sputtering power is 300 W, the deposition temperature is 25° C., and the deposition pressure is 1 Pa.

[0074] The fifth sample was obtained by depositing 20 nm of ZrO2 on the first resistance transition layer 3 as the second resistance transition layer 4 using radio frequency sputtering, wherein the target material was 99.99% pure ZrO2, the sputtering power was 80 W, the ratio of argon to oxygen was 2:1, and the working pressure was 10 mTorr.

[0075] The fifth sample was immersed in acetone to remove the photoresist, thereby obtaining a sixth sample.

[0076] Finally, magnetron sputtering was used, with the target material selected as Ag with a purity of 99.99%, the DC sputtering power of 10 W, and the ambient pressure of 2×10 -4 Pa, and the ambient pressure is 3 Pa. A strip-shaped metal Ag is deposited on the sixth sample as the top electrode 5 to complete the preparation.

[0077] What is disclosed above is only a preferred embodiment of the present invention, and it certainly cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiment and equivalent changes made according to the claims of the present invention still fall within the scope of the invention.

Claims

1. A method for preparing a planar cross array structure resistive random access memory, characterized in that: The steps include: Spin-coating a photoresist on an insulating substrate to obtain a first sample; The first sample is subjected to photolithography and etching processing, so that a plurality of grooves are formed on the first sample; Depositing a bottom electrode in each of the grooves to obtain a second sample; Depositing a nanostructure on the second sample through a porous film so that each bottom electrode is patterned to obtain a third sample; Using adhesive tape to remove the porous film plate on the third sample to obtain a fourth sample; sequentially depositing a first resistance conversion layer and a second resistance conversion layer on the fourth sample to obtain a fifth sample; removing the photoresist in the fifth sample to obtain a sixth sample; depositing a top electrode on the sixth sample; The step of depositing metal on the second sample through the porous film comprises: placing a porous film on the second sample; By adopting the oblique deposition technology, a layer of nanostructure with a conical sidewall profile is deposited on the surface of each bottom electrode by magnetron sputtering oblique deposition.

2. The method for preparing a planar cross array structure resistive random access memory according to claim 1, characterized in that: In the step of depositing a bottom electrode in each of the grooves: The bottom electrode layer is deposited by magnetron sputtering, the bottom electrode is Pt, Al, Au, Ti, TiN or Cu, and the thickness of the bottom electrode is 20nm to 300nm.

3. The method for preparing a planar cross array structure resistive random access memory according to claim 1, characterized in that: In the step of sequentially depositing a first resistance conversion layer and a second resistance conversion layer on the fourth sample: The first resistance conversion layer is a metal oxide, a two-dimensional material, a chalcogenide solid electrolyte, a nitride or an organic matter, and the thickness of the first resistance conversion layer is 5nm to 100nm; The second resistance conversion layer is a metal oxide, a two-dimensional material, a chalcogenide solid electrolyte, a nitride or an organic matter, and the thickness of the second resistance conversion layer is 5nm to 100nm; The top of the second resistance conversion layer is flush with the top of the insulating substrate.

4. The method for preparing a planar cross array structure resistive random access memory according to claim 1, wherein: In the step of depositing a top electrode on the sixth sample: The top electrode is Pt, Al, Ag, Zn, Au, Ti, TiN, ITO or Cu, and the thickness of the bottom electrode is 20nm to 300nm.

5. A resistive random access memory manufactured by the method for manufacturing a resistive random access memory having a planar cross array structure as claimed in any one of claims 1 to 4, characterized in that: The invention comprises an insulating substrate and a plurality of dielectric structures, wherein the insulating substrate has a plurality of grooves, each of the dielectric structures is fixedly connected to the corresponding grooves and is located inside the corresponding grooves, each of the dielectric structures comprises the bottom electrode, the nanostructure, the first resistance transition layer, the second resistance transition layer and the top electrode, the bottom electrode is fixedly connected to the groove and is located on the inner bottom wall of the groove, the first resistance transition layer is fixedly connected to the bottom electrode and is located on the top of the bottom electrode, the second resistance transition layer is fixedly connected to the first resistance transition layer and is located on the top of the first resistance transition layer, the nanostructure is fixedly connected to the top of the bottom electrode and is embedded in the first resistance transition layer, and the top electrode is fixedly connected to the top of the insulating substrate and is located on the top of the second resistance transition layer.

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