Method and apparatus for saving microcontroller power

Abstract

Embodiments of the present disclosure relate to methods and devices for saving power in a microcontroller. A power saving system includes a persistence memory element for a persistence peripheral device, the persistence memory element being set to a logic state during an operating power mode and maintaining the logic state during an enhanced power saving mode. The power saving system also includes a non-persistent memory element for a non-persistent peripheral device, the non-persistent memory element being set to a logic state during an operating power mode of the power saving system; and a controller that instructs the persistence memory element to maintain its logic state when in the enhanced power saving mode.

Description

Technical Field

[0001] The present application relates to microcontrollers, and in particular to methods and apparatus for saving power for a microcontroller. Background Art

[0002] During periods of inactivity or low usage, the operation of the microcontroller may consume power resources. Undesirable power consumption can be limited during periods of inactivity or low usage by reducing the power supply to internal peripherals (which may consume power in low-power modes). Many microcontrollers can switch to one or more low-power consumption modes to try to save power. However, there is a trade-off between reduced power consumption, user experience, and application complexity. Summary of the invention

[0003] According to one embodiment of the present invention, a power saving system includes a retention trigger of a retention peripheral device and a non-retention trigger of a non-retention peripheral device. The power saving system also includes a controller that communicates with the retention trigger and the non-retention trigger, wherein the controller is configured to transmit a save signal to the retention trigger to instruct the retention trigger to maintain the logic state of the retention peripheral device during an enhanced power saving mode of the power saving system, and to transmit a reset signal to the non-retention trigger when the power saving system enters the enhanced power saving mode of the power saving system to instruct the non-retention trigger to reset the non-retention trigger.

[0004] According to one embodiment of the present invention, a microcontroller includes: a main power regulator coupled to a main voltage source and configured to provide main power; a low power regulator coupled to a main voltage source and configured to provide low power; a first switch device configured to couple and decouple the main power regulator with a retention trigger and a non-retention trigger; and a second switch device configured to couple and decouple the low power regulator with the retention trigger. The microcontroller also includes a power mode controller that communicates with the first switch device and the second switch device, the power mode controller being configured to operate the first power switch device to couple the main power regulator to the retention trigger and the non-retention trigger during the operation power mode; and wherein the power mode controller is configured to operate the second switch device to couple the low power regulator to the retention trigger during the enhanced power saving mode, and to operate the first switch device to decouple the retention trigger and the non-retention trigger from the main power regulator during the enhanced power saving mode.

[0005] According to one embodiment of the present invention, a method for saving power includes: having a microcontroller; during an operating power mode, setting a retention trigger to a logic state of a retention peripheral device; during an operating power mode, setting a non-retention trigger to a logic state of a non-retention peripheral device; during an enhanced power saving mode, decoupling a main power source from the retention trigger and the non-retention trigger; and during the enhanced power saving mode, providing a low power source to the retention trigger to maintain the logic state of the retention peripheral device in a low power position of the retention trigger. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0007] Figure 1 A block diagram of a microcontroller having a power saving system in an operating power mode is illustrated;

[0008] Figure 2 A block diagram of a microcontroller in a low power mode with a power saving system is illustrated;

[0009] Figure 3 A block diagram of a microcontroller in a low power mode with a power saving system is illustrated;

[0010] Figure 4 One embodiment of an enhanced microcontroller is illustrated;

[0011] Figure 4A One embodiment of an enhanced microcontroller is illustrated;

[0012] Figure 5 One embodiment of a persistent memory element and a non-persistent memory element of an enhanced microcontroller is illustrated;

[0013] Figure 6 One embodiment of an always-on storage element of an always-on domain of an enhanced microcontroller is illustrated;

[0014] Figure 7 depicts a flow chart illustrating a method for waking up an enhanced microcontroller according to one embodiment;

[0015] Figure 8 A memory controller and memory elements are illustrated; and

[0016] Fig. 9 A flow chart illustrating a method of conserving power according to one embodiment is depicted. DETAILED DESCRIPTION

[0017] In the following description, one or more specific details are illustrated to provide a deeper understanding of the examples of the embodiments of the present description. The embodiments can be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not illustrated or described in detail so that some aspects of the embodiments are not covered.

[0018] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0019] In many electronic devices, excess power consumption is undesirable. Designers may try to reduce power consumption. Microcontrollers can limit power consumption by utilizing one or more low-power modes that are entered during periods of inactivity.

[0020] Figure 1 A block diagram of a microcontroller in an operating power mode with a power saving system is illustrated.

[0021] The microcontroller 100 has two modes of operation. During standard operation, the first switch 102 is closed. When the first switch 102 is closed, power is supplied to the various components of the microcontroller 100 by the main regulator 104.

[0022] The main regulator (MR) 104 is coupled to provide a supply voltage V DD During standard power mode, the main regulator 104 distributes sufficient power to the components of the microcontroller 100 to allow them to operate.

[0023] During periods of inactivity or low usage, the microcontroller 100 limits power supply to certain components or internal peripherals.

[0024] Figure 2 A block diagram of a microcontroller with a power saving system in a low power mode is shown. This low power mode is referred to herein as a stop mode.

[0025] In the stop mode, the second switch 110 couples the low power regulator (LP) 112 to some peripherals of the microcontroller 100 to provide low power to the peripherals. The first switch 102 decouples the main regulator 104 from the peripherals. During the operating power mode, the power provided by the low power regulator 112 is less than the power provided by the main regulator 104. This allows power to be saved for the microcontroller 100 when the microcontroller 100 is in the stop mode.

[0026] The microcontroller 100 includes a first retained peripheral 106A, a second retained peripheral 106B, and a third retained peripheral 106C. The logic state of the first retained peripheral 106A is stored in a flip-flop or other volatile memory element of the first retained peripheral 106A. The logic state of the second retained peripheral 106B is stored in a flip-flop or other volatile memory element of the second retained peripheral 106B. The logic state of the third retained peripheral 106C is stored in a flip-flop or other volatile memory element of the third retained peripheral 106C.

[0027] The logic states of the first, second, and third surviving peripherals 106A, 106B, and 106C may be retained during the stop mode. The surviving peripherals may be grouped into a surviving peripheral domain 107. When the microcontroller 100 is in the stop mode, the power supplied by the low power regulator 112 may provide sufficient power to save the logic states of the first, second, and third surviving peripherals 106A, 106B, and 106C.

[0028] Figure 3 A block diagram of a microcontroller in low power mode with a power saving system is shown.

[0029] This mode may be referred to as a standby mode. In various embodiments, when in standby mode, the first switch 102 may be disconnected. This may decouple the main regulator 104 from the first retained peripheral 106A, the second retained peripheral 106B, and the third retained peripheral 106C. The second switch 110 may also be disconnected in standby mode. In addition, the low-power regulator 112 may be decoupled from the first retained peripheral 106A, the second retained peripheral 106B, and the third retained peripheral 106C. The first retained peripheral 106A, the second retained peripheral 106B, and the third retained peripheral 106C, which are isolated from the main regulator 104 and the low-power regulator 112, may have no power during standby mode, and may consume little or no power.

[0030] This may cause the flip-flops or other volatile memory elements storing the digital logic states of the first, second, and third retained peripherals 106A, 106B, and 106C to lose their digital logic settings. Furthermore, the states of the first, second, and third retained peripherals 106A, 106B, and 106C may also be lost along with the digital logic settings of their associated flip-flops or other memory elements.

[0031] When exiting the standby mode, the first, second, and third surviving peripherals 106A, 106B, and 106C of the microcontroller 100 may be initialized. Also, transitioning the microcontroller 100 from the standby mode back to the operating power mode may take more time than may be desired in some cases. From a user's perspective, exiting the standby mode and re-entering the operating power mode (which may be referred to as waking up) may look like a system restart.

[0032] In various embodiments, a microcontroller with enhanced power saving modes allows for further reduction of power consumption and limits user interrupts, software complexity, and transition time between power modes.

[0033] Figure 4 One embodiment of an enhanced microcontroller 400 is illustrated.

[0034] In various embodiments, the enhanced microcontroller 400 may include a voltage input 403 to receive a power supply voltage V DD . Supply voltage V DD can be delivered directly or indirectly to the components of the enhanced microcontroller 400. In various embodiments, the power supply voltage V DD An external voltage source may be included. In various embodiments, V DD can be 3 volts. However, in other embodiments, V DD Larger or smaller voltages may be included.

[0035] In various embodiments, the enhanced microcontroller 400 may include components or peripherals that are not subject to the power reduction of the enhanced power saving mode. When the enhanced microcontroller 400 is in the power saving mode, the peripherals that are not subject to the power reduction of the enhanced power saving mode may continue to receive the same amount of power, or substantially the same amount of power. In various embodiments, this may include any peripherals or components that may need to operate at full power to keep the microcontroller running, to initialize a wake-up routine, or both. Some embodiments of peripherals that are not subject to the power reduction of the enhanced power saving mode may be directly coupled to the V DD .

[0036] In various embodiments, the enhanced microcontroller 400 may include a real time clock 405. In various embodiments, the real time clock 405 is subject to power reduction in the enhanced power saving mode.

[0037] In various embodiments, the real-time clock 405 can be connected to V DD The coupling allows the real time clock 405 to continue to receive full power and continue to operate during various embodiments of the enhanced power save mode.

[0038] In various embodiments, the enhanced microcontroller 400 may include additional full-power peripherals 408 that may not be subject to the power reduction of the enhanced power saving mode. In some embodiments, the additional full-power peripherals 408 may include an independent watchdog.

[0039] In various embodiments, additional full-power peripherals 408 may be connected to V DD The coupling allows the additional full-power peripheral device 408 to continue to receive full power and operate during various embodiments of the enhanced power saving mode. In various embodiments, the enhanced microcontroller 400 may include one or more additional peripheral devices that are not subject to the power reduction of the enhanced power saving mode.

[0040] In various embodiments, the enhanced microcontroller 400 may include an additional voltage supply input 411 to receive a secondary voltage source. In one embodiment, the secondary voltage source received at the additional voltage supply input 411 may include a battery that outputs a battery voltage VBAT. In various embodiments, the enhanced microcontroller 400 may include a battery in which an additional voltage is stored. In some embodiments, the battery supplying the voltage VBAT may provide a backup voltage supply for the enhanced microcontroller 400.

[0041] The enhanced microcontroller 400 may include a backup voltage supply switch 415 that can be opened when the main power supply VDD is present and closed when the main power supply VDD is not present. In various embodiments, a battery supplying voltage VBAT can provide a backup voltage for the real-time clock 405 or the backup registers or both. If the power supply voltage V DD If the external voltage supply is removed, a backup voltage supply VBAT provided by a battery may be required.

[0042] In various embodiments, the enhanced microcontroller 400 may include a main regulator 404 and a low power regulator 412. The low power regulator 412 may include a buck regulator. The enhanced microcontroller 400 may also include a first switching device 402 and a second switching device 410.

[0043] In various embodiments, the first switch device 402 may include a single switch. The first switch device 402 may include two or more switches. In various embodiments, the second switch device 410 may include a single switch. In various embodiments, the second switch device 410 may include two or more switches.

[0044] In various embodiments, the first switch device 402 may include a first end 402A coupled to the main regulator 404, a second end 402B coupled to one or more persistent memory elements 500, and a second end coupled to one or more non-persistent memory elements 506. The persistent memory elements 500 and the non-persistent memory elements 506 are at least partially referred to elsewhere in this disclosure. Figure 5 In various embodiments, the second switch device 410 may include a first end 410A coupled to the low power regulator 412 and a second end 410B coupled to the one or more retention memory elements 500 .

[0045] In various embodiments, the enhanced microcontroller 400 may include one or more retained peripherals. The retained peripherals may include any internal peripherals of the enhanced microcontroller 400, which are disconnected from the high power supply and connected to the low power supply during the enhanced power saving mode. This may allow the logic states of the retained peripherals to be preserved with less power consumption during the enhanced low power mode. The logic states of the retained peripherals may be maintained by storing their states in a retained memory element or a trigger that receives power from the low power supply during the enhanced power saving mode.

[0046] For purposes of description, the retained peripherals may be grouped into a retained peripheral domain 407. In various embodiments, the retained peripherals of the retained peripheral domain 407 are physically grouped in the enhanced microcontroller 400. In various embodiments, the retained peripherals of the retained peripheral domain 407 are not physically grouped together in the enhanced microcontroller 400.

[0047] In various embodiments, CPU 406A may be in retention peripherals domain 407. In various embodiments, SRAM 406C may be in retention peripherals domain 407. In various embodiments, retention peripherals domain 407 may include additional retention peripherals 406B. Retention peripherals domain 407 may include multiple additional retention peripherals or fewer retention peripherals.

[0048] In various embodiments, the enhanced microcontroller 400 may include one or more non-persistent peripherals. The non-persistent peripherals may include any peripherals that lose their power during the enhanced power saving mode. For the purpose of description, the non-persistent peripherals may be grouped into a non-persistent peripheral domain 414. In various embodiments, the non-persistent peripherals of the non-persistent peripheral domain 414 may be physically grouped together in the enhanced microcontroller 400. In various embodiments, the non-persistent peripherals of the non-persistent peripheral domain 414 are not physically grouped together in the enhanced microcontroller 400. The non-persistent peripheral domain 414 may include a first persistent peripheral 413A and a second persistent peripheral 413B. In various embodiments, the non-persistent peripheral domain 414 may include more or fewer non-persistent peripherals.

[0049] During the operating power mode of the enhanced microcontroller 400, the first switching device 402 can be closed. When the first switching device 402 is closed, the retained peripheral device can be coupled to the main regulator 404. The main regulator 404 can be coupled to provide V DD When the first switch device 402 is closed, the main regulator 404 can provide a high power source for the remaining peripheral devices of the remaining peripheral device domain 407.

[0050] In various embodiments, if there is no supply voltage V DD , the main regulator 404 can be connected to the battery voltage V BAT Coupling. V DD can be used as the main voltage supply for the enhanced microcontroller 400, while V BAT Can be used as a backup voltage supply. When V DD When not present or disconnected from the enhanced microcontroller 400, the battery voltage V BAT It can be used as a main voltage source for the enhanced microcontroller 400. The main regulator 404 can be configured to receive a voltage from the main voltage source.

[0051] When the first switch device 402 is closed, the non-persistent peripherals of the non-persistent peripheral domain 414 may also be coupled to the main regulator 404, which may be used as a high power source for the non-persistent peripherals of the non-persistent peripheral domain 414. During the operational power mode, the persistent peripherals of the persistent peripheral domain 407 are allocated sufficient power for full operation. This may include the CPU 406A, SRAM 406C, additional persistent peripherals 406B, and any additional persistent peripherals of the persistent peripheral domain 107. During the operational power mode, the non-persistent peripherals of the non-persistent peripheral domain 414 may also be allocated sufficient power for full operation.

[0052] The enhanced power saving mode of the enhanced microcontroller 400 can allow the enhanced microcontroller 400 to save power. In various embodiments, the first switch device 402 can be turned off in the enhanced power saving mode of the enhanced microcontroller 400. This can isolate the surviving peripherals of the surviving peripheral domain 407 and the non-surviving peripherals of the non-surviving peripheral domain 414 from the high power source provided by the main regulator 404.

[0053] In various embodiments, the main regulator 404 may be turned off when not in use. For example, there may be embodiments where the main regulator 404 is not in use during an enhanced power saving mode of the enhanced microcontroller 400, and the main regulator 404 may be turned off during such an enhanced power saving mode. The main regulator 404 may be powered on by internal circuitry or Figure 4 The circuit is turned on and off by a switch not depicted.

[0054] In various embodiments, when the low power regulator 412 is not used, it can be turned off. For example, there may be embodiments in which the low power regulator 412 is not used in an operating power mode of the enhanced microcontroller 400, and the low power regulator 412 can be turned off during such an operating power mode. The low power regulator 412 can be turned off by internal circuit devices or Figure 4 The circuit is turned on and off by a switch not depicted.

[0055] In the enhanced power saving mode of the enhanced microcontroller 400, the second switch device 410 can be closed to couple the low power regulator 412 of the enhanced microcontroller 400 with the retained peripherals of the retained peripheral device domain 407. The low power regulator 412 can be configured to receive a voltage from the main voltage source to provide low power. When the second switch device 410 is closed, the low power regulator 412 can provide low power to the retained peripheral device domain 407. In various embodiments, the low power regulator 412 can provide 1.2V. The low power regulator 412 can provide a voltage greater than or less than 1.2V but less than the power supply voltage V DD voltage.

[0056] The low power provided by the low power regulator in the enhanced power saving mode may provide sufficient power to maintain (e.g., in volatile memory) the logic states of the retained peripherals of the retained peripheral domain 407. However, in various embodiments, the low power may not provide sufficient power for the retained peripherals of the retained peripheral domain to perform standard operations. This allows for reduced power consumption because less power may be required to maintain the logic states of the retained peripherals of the retained peripheral domain 407 than to perform standard operations.

[0057] During the enhanced power saving mode, the non-persistent peripherals of the non-persistent peripheral domain 414 can be isolated from the main regulator 404 and the power source. Power can be saved because when the non-persistent peripherals of the non-persistent peripheral domain 414 are isolated from the main regulator 404, they will not consume power.

[0058] The enhanced microcontroller 400 with an enhanced power saving mode can provide many advantages. Compared with the stop mode or standby mode, the enhanced power saving mode can provide greater flexibility. Compared with the stop mode, because fewer peripheral devices can be retained, it can save more power. Since the logic state of certain peripheral devices can be retained during the enhanced power saving mode, it can also enhance the user experience. Because the logic state of certain retained peripheral devices will not be lost during the enhanced power saving mode, it can also wake up faster than the standby mode. In addition, the enhanced power saving mode may lose less power due to the leakage of its components, because in various embodiments, fewer internal peripheral devices may require leaking memory elements. The enhanced power mode can also reduce software complexity.

[0059] The enhanced microcontroller 400 with enhanced power saving mode can also provide design flexibility for determining which peripherals can be retained and which peripherals are not retained. Peripherals can also be classified as retained peripherals or non-retained peripherals based on the indicators of the enhanced microcontroller 400.

[0060] For example, in various embodiments, frequently used peripherals may be included in the retained peripherals domain 407. Peripherals that consume a small amount of power may be included in the retained peripherals domain 407. In various embodiments, peripherals that require fast recovery after exiting the enhanced power saving mode may be included in the retained peripherals domain 407.

[0061] In various embodiments, peripherals that are not frequently used may be grouped in the non-persistent peripheral domain 414. Peripherals that consume a lot of power may be included in the non-persistent peripheral domain 414. Peripherals that do not require fast recovery after exiting the enhanced power saving mode may be included in the non-persistent peripheral domain 414. The peripherals of the microcontroller 400 may be divided into the persistent peripheral domain 407 and the non-persistent peripheral domain 414 to maximize power savings, user experience, or any other desired approach.

[0062] In various embodiments, the enhanced microcontroller 400 may include an always-on domain 416. The always-on domain 416 may include an always-on peripheral 416A. The always-on domain 416 may include additional peripherals. In some embodiments, an I2C peripheral may be included in the always-on domain 416. The peripherals or components of the always-on domain 416 may be configured to perform standard operations using a power source that is smaller than the high power source provided by the main regulator 404. The peripherals or components of the always-on domain 416 may be configured to perform full operations using a low power source provided by the low power regulator 412.

[0063] In various embodiments, the always-on domain 416 can be coupled to the low power regulator 412 during the enhanced power saving mode. During the enhanced power saving mode, the second switching device 410 can couple the always-on domain 416 to the low power regulator 412. During the operating power mode, the second switching device 410 can decouple the always-on domain from the low power regulator 412. During the standby mode of the enhanced microcontroller 400, the second switching device 410 can decouple the always-on domain from the low power regulator 412.

[0064] In various embodiments, the first switching device 402 may couple the always-on domain 416 to the main regulator 404 during the operational power mode. The first switching device 402 may decouple the always-on domain from the main regulator 404 during the enhanced power saving mode.

[0065] In various embodiments, the enhanced microcontroller 400 may include a power mode controller 418 in communication with the first switch device 402 and the second switch device 410. The power mode controller 418 may transmit control signals to the first switch device 402 and the second switch device 410. In various embodiments, the control signal transmitted to the first switch device 402 may open and close one or more switches in the first switch device 402. In various embodiments, the control signal transmitted to the second switch device 410 may open and close one or more switches in the second switch device 410.

[0066] In various embodiments of the enhanced microcontroller 400, the power mode controller 418 may operate the first switch device to couple the main regulator 404 to the retention peripherals domain 407 and the non-retention peripherals domain 414 during an operating power mode of the microcontroller 400. The power mode controller 418 may be configured to operate the second switch device 410 to couple the low power regulator 412 to the retention peripherals domain 407 during an enhanced power saving mode. The power mode controller 418 may be configured to operate the first switch device 402 to decouple the non-retention peripherals of the retention peripherals domain 407 and the non-retention peripherals domain 414 from the main regulator 404 during an enhanced power saving mode.

[0067] In various embodiments, the power mode controller 418 may also transmit control signals to operate the first switch device 402 to couple and decouple the always-on domain 416 to and from the main regulator 404 during the operating power mode and the enhanced power saving mode. In various embodiments, the power mode controller 418 may also transmit control signals to operate the second switch device 410 to couple and decouple the low power regulator 412 to and from the always-on domain 416 during the operating power mode and the enhanced power saving mode.

[0068] In various embodiments, the enhanced microcontroller 400 may also operate in a standby mode as previously described in the present disclosure. The power mode controller 418 may transmit a control signal to the first switch device 402 during the standby mode to operate the first switch device 402 to decouple the main regulator 404 from the retention peripheral device domain 407 and the non-retention peripheral device domain 414. The power mode controller 418 may transmit a signal to the second switch device 410 during the standby mode to operate the second switch device 410 to decouple the low power regulator 412 from the retention peripheral device domain 407. In various embodiments, the operation of the first switch device 402 and the second switch device 410 during the standby mode as by the power mode controller 418 may also cause the always-on domain 416 to be decoupled from the main regulator 404 and the low power regulator 412. In various embodiments, the enhanced microcontroller 400 may also operate in additional power saving modes.

[0069] Figure 4A An enhanced power controller is depicted.

[0070] In various embodiments of the enhanced microcontroller 400, the first switch device 402 may include a first switch 420 and a second switch 422. The second switch device 410 may include a first switch 424 and a second switch 426. The first switch 420 of the first switch device 402, the second switch 422 of the first switch device 402, the first switch 424 of the second switch device 410, and the second switch 426 of the second switch device 410 may be opened and closed by a control signal received from the power mode controller 418.

[0071] In the enhanced power saving mode of the enhanced microcontroller 400, the first switch 420 of the first switch device 402 and the second switch 422 of the first switch device 402 may be opened. The first switch 424 of the second switch device 410 and the second switch 426 of the second switch device may be closed. In the operating power mode of the enhanced microcontroller 400, the first switch 420 of the first switch device 402 and the second switch 422 of the first switch device 402 may be closed. The first switch 424 of the second switch device 410 and the second switch 426 of the second switch device may be opened. In the standby mode of the enhanced microcontroller 400, the first switch 420 of the first switch device 402 and the second switch 422 of the first switch device 402 may be opened. The first switch 424 of the second switch device 410 and the second switch 426 of the second switch device may also be opened.

[0072] The first switch device 402 including more than one switch and the second switch device 410 including more than one switch can allow the enhanced microcontroller 400 to select different domains to receive power in different operating modes. For example, in one embodiment, the second switch 426 of the second switch device 410 can be closed, while the first switch 420 of the first switch device 402, the second switch 422 of the first switch device 402, and the first switch 424 of the second switch device 410 are open. This can provide a low power supply to the always-on domain 416, while no power is provided to the surviving peripheral device domain 407 and the non-surviving peripheral device domain 414.

[0073] The logic states of the persistent peripherals of the persistent peripherals domain 407 may be set in a plurality of persistent memory elements. Also, in various embodiments, the logic states of the non-persistent peripherals of the non-persistent peripherals domain 414 may be set in a plurality of non-persistent memory elements.

[0074] Figure 5 One embodiment of a persistent memory element and a non-persistent memory element of an enhanced microcontroller is disclosed.

[0075] In various embodiments, the retention memory element 500 may include a trigger. The digital logic of the retention peripheral device of the retention peripheral device domain 407 may include the retention memory element 500. The retention memory element 500 may include an input for receiving a clock pulse CP. In various embodiments, the retention memory element 500 may include an input for receiving a data value D. The retention memory element 500 may include an input for receiving a reset signal CDN. In various embodiments, the retention memory element 500 may include an input for receiving a save signal SAVE. The retention memory element 500 may include an input for receiving a restore signal NRESTORE. In various embodiments, the retention memory element 500 may include an output Q. The retention memory element 500 element may also include a first power input 502. And, in various embodiments, the retention memory element may include a second power input 504.

[0076] In various embodiments, non-persistent memory element 506 may include a flip-flop. Non-persistent memory element 506 may include an input for receiving a clock pulse CP. Non-persistent memory element 506 may include an input for receiving a data value D. Non-persistent memory element 506 may include an input for receiving a reset signal CDN. In various embodiments, non-persistent memory element 506 may include an output Q. Non-persistent memory element 506 may also include a power input 508.

[0077] In various embodiments, the persistence memory element 500 can be configured to be set to the logic state of the corresponding persistence peripheral device of the persistence peripheral device domain 407 during the operating power mode of the enhanced microcontroller 400. The persistence memory element 500 can be used as a digital logic memory element of its corresponding persistence peripheral device during the operating power mode of the enhanced microcontroller 400. In various embodiments, the persistence memory element 500 can be set and reset to the persistence peripheral device of the persistence peripheral device domain 407 to perform its corresponding function during the operating power mode. In various embodiments, the full digital logic complement of one or more persistence peripheral devices of the persistence peripheral device domain 407 can include the persistence memory element 500.

[0078] In various embodiments, the persistence memory element 500 may be configured to retain the logic state of its corresponding persistence peripheral device during the enhanced power saving mode of the enhanced microcontroller 400. In various embodiments, this may allow the logic state of the persistence peripheral devices of the persistence peripheral device domain 407 to be retained during the enhanced power saving mode of the enhanced microcontroller 400.

[0079] In various embodiments, the non-persistent memory elements 506 of the associated non-persistent peripherals of the non-persistent peripherals domain 414 may be configured to be set to the logic state of the non-persistent peripherals during an operational power mode of the enhanced microcontroller 400 .

[0080] During the operating power mode of the enhanced microcontroller 400, the non-persistent memory element 506 can be used as a digital logic memory element of its corresponding non-persistent peripheral device. In various embodiments, the non-persistent memory element 506 element can be set and reset during the operating power mode when the non-persistent peripheral devices of the non-persistent peripheral device domain perform their corresponding functions. The full digital logic complement of one or more non-persistent peripheral devices of the non-persistent peripheral device domain 414 can include the non-persistent memory element 506.

[0081] In various embodiments, the controller 510 can communicate with the retention memory elements 500 of the retention peripheral devices of the retention peripheral device domain 407 and the non-retention memory elements 506 of the non-retention peripheral devices of the non-retention peripheral device domain 414. The controller 510 can be referred to as a memory controller. The controller 510 may include a reset and clock controller. The controller 510 can transmit a save signal to one or more retention memory elements 500, indicating that the retention memory elements 500 maintain the logic state that has been set during the operating power mode. The controller 510 can transmit the save signal before the enhanced microcontroller 400 enters the enhanced power saving mode of the enhanced microcontroller 400. The save signal can be received at the input to receive the save signal SAVE of the retention memory element 500.

[0082] In various embodiments, the controller 510 may transmit a reset signal to the non-persistent memory element 506 of the non-persistent peripheral device of the non-persistent domain to indicate that the non-persistent memory element 506 is reset when the enhanced microcontroller 400 enters the enhanced power saving mode. The reset signal may be received at the input to receive the reset signal CDN.

[0083] In various embodiments, the retention memory element 500 can be coupled to a high power source during an operating power mode of the enhanced microcontroller 400 and decoupled from the high power source during an enhanced power saving mode of the enhanced microcontroller 400. The retention memory element 500 can receive the high power source at a first power input 502.

[0084] In various embodiments, the non-persistent memory element 506 can be coupled to a high power source during an operating power mode of the enhanced microcontroller 400 and can be decoupled from the high power source during an enhanced power saving mode of the enhanced microcontroller 400. The non-persistent memory element 506 can receive a high power source at a power input 508.

[0085] In various embodiments, the persistence memory element 500 may be coupled to a low power source during an enhanced power saving mode of the enhanced microcontroller 400. The persistence memory element 500 may receive the low power source at a second power input 504.

[0086] As described elsewhere, in various embodiments, when the high power source delivered to the surviving peripherals of the surviving peripherals domain 407 and the non-surviving peripherals of the non-surviving domain 407 is removed, the enhanced microcontroller 400 can enter an enhanced power saving mode, and the low power source is delivered to the surviving peripherals of the surviving peripherals domain 407. In various embodiments, the main regulator 404 can be used as a high power source, and the low power regulator 412 can be used as a low power source. In various embodiments, the low power source and the high power source can be delivered to the surviving peripherals, non-surviving peripherals, and always-on peripherals via the bus. In various embodiments, the enhanced microcontroller 400 can be triggered to enter the enhanced power saving mode by a user input or a triggering event such as a period of inactivity.

[0087] The persistence memory element 500 and the non-persistence memory element 506 can be coupled to the main regulator 404 and thus to the high power source through the first switch device 402. In various embodiments, when the first switch device 402 couples or decouples the persistence peripherals of the persistence peripheral device domain 407 with the main regulator 404, the persistence memory element 500 of the persistence peripheral device can also be coupled or decoupled with the main regulator 404. In various embodiments, when the first switch device 402 couples or decouples the non-persistence peripherals of the non-persistence peripheral device domain 414 with the main regulator 404, the non-persistence memory element 506 of the non-persistence peripheral device can also be coupled or decoupled with the main regulator 404.

[0088] In various embodiments, the first switch device 402 may include a single switch. In various embodiments, the first switch device 402 may include a switch device that couples and decouples the one or more resident memory elements 500 and the one or more non-resident memory elements 506 to a high power source.

[0089] The retention memory element 500 can be coupled to the low power regulator 412 and thus coupled to the low power source through the second switch device 410. In various embodiments, the second switch device 410 may include a single switch. In various embodiments, the second switch device 410 may include a switch device that couples and decouples one or more retention memory elements 500 from the low power source. In various embodiments, when the second switch device 410 couples or decouples the retention peripherals of the retention peripheral device domain 407 with the low power regulator 412, the retention memory element 500 of the retention peripheral device may also be coupled or decoupled from the low power regulator 412.

[0090] In various embodiments of the enhanced microcontroller 400, the persistence memory element 500 may include a low power memory location 512 where logic states of the persistence peripherals may be maintained during an enhanced power saving mode of the enhanced microcontroller 400. The low power memory location 512 may include a balloon latch.

[0091] The low power memory location 512 can be coupled to a low power source that can provide sufficient power to save the logic state of the retained peripheral device. This can allow the retained memory element 500 to save the logic state of the peripheral device while saving power in an enhanced power saving mode. In various embodiments, after the controller 510 transmits a save signal to the retained memory element 500, the logic state is saved in the low power memory location 512.

[0092] In various embodiments of the enhanced microcontroller 400, the logic states of the persistent peripherals of the persistent peripherals domain 407 stored in the persistent memory element 500 may be set at the first memory location 514 of the persistent memory element 500 during the operating power mode of the enhanced microcontroller 400. In various embodiments, the first memory location 514 may require high power delivered from the main regulator 404. When the enhanced microcontroller 400 enters the enhanced power saving mode and the persistent memory element 500 is decoupled from the main regulator 404, the settings in the first memory location 514 may be lost.

[0093] In various embodiments, before the enhanced microcontroller 400 exits the enhanced power saving mode, the controller 510 may transmit a restore signal to the retention memory element 500. This may be received by the retention memory element 500 at the input for the restore signal NRESTORE. In various embodiments, this may occur after the wake-up event has triggered the enhanced microcontroller 400 to restore the operating power mode. Once the restore signal is received by the retention memory element 500, it may retrieve the logic state of the retention peripheral device from the low power memory location 512 and reset the logic state of the retention peripheral device to the first memory location 514.

[0094] In various embodiments, the enhanced microcontroller 400 may include a memory that is always on. The memory that is always on may store a flag indicating when the microcontroller 400 is in the enhanced power saving mode. In various embodiments, the memory element that is always on may be coupled to the low power regulator 412 during the enhanced power saving mode of the microcontroller 400. This may allow the memory element that is always on to be accessible during the enhanced power saving mode. In various embodiments, the memory element that is always on may be included in the always on domain 416.

[0095] Figure 6 One embodiment of an always-on memory 602 in the always-on domain 416 is illustrated.

[0096] The always-on memory 602 may include registers. The always-on memory 602 may also communicate with the power control logic 604 in the always-on domain 416. The always-on memory 602 may be set by the power control logic 604 when the enhanced microcontroller 400 enters the enhanced power saving mode. The always-on memory 602 may also be accessed by the CPU 606, which may retrieve flags for processing.

[0097] In various embodiments, the power mode controller 418 may include control elements in the always-on domain 416 and the retained peripherals domain 407, depending on their functions. For example, control functions that control operations in the always-on domain 416 may also be in the always-on domain. Control functions that control operations in the retained peripherals domain 407 may also be in the retained peripherals domain. The power mode controller 418 may include power control logic 604.

[0098] It may be advantageous to store a flag indicating whether the enhanced microcontroller 400 is in the enhanced power saving mode so that software applications can initialize the peripherals of the enhanced microcontroller 400 upon wakeup. In various embodiments, the initialization process may vary for the surviving peripherals of the surviving peripherals domain 407 (whose states have been saved during the enhanced power saving mode) and the non-surviving peripherals of the non-surviving peripherals domain 414 (whose states may have been lost during the enhanced power saving mode).

[0099] The always-on memory element and the power control logic may be coupled to the low power regulator 412 via the second switch device 410 and to the main regulator 404 via the first switch device 402. In various embodiments, when the first switch device 402 couples or decouples the always-on domain to the main regulator 404, the always-on memory 602 may also be coupled or decoupled to the main regulator 404. In various embodiments, when the second switch device 410 couples or decouples the always-on domain to the low power regulator 412, the always-on memory 602 may also be coupled or decoupled to the low power regulator 412.

[0100] Figure 7 A flow chart illustrating a method 700 for waking up the enhanced microcontroller 400 is depicted.

[0101] At 702, the microcontroller 400 operates in an operational power mode. At step 704, an enhanced power saving mode is selected. This may be triggered by user input or certain programmed conditions (such as an inactive period). At 706, the microcontroller 400 enters the enhanced power saving mode. At 708, a wake-up event is detected. It should be understood that any number of various conditions may trigger a wake-up, such as a user input or a timed operation.

[0102] At step 710, a flag is checked to determine whether the microcontroller 400 is in an enhanced power saving mode or another power saving mode, such as a standby mode. If the flag indicates that the microcontroller 400 is in an enhanced power saving mode, then at step 712, the retained peripherals of the retained peripherals domain 407 and the non-retained peripherals of the non-retained peripherals domain 414 are initialized accordingly. At step 714, the flag is cleared and the system returns to the operating power mode. If the flag indicates that the microcontroller 400 is not in the enhanced power saving mode at 710, steps 712 and 714 are skipped. The method 700 can be part of an interrupt service routine (ISR) executed after an interrupt event generated due to wake-up. Initialization from standby mode can include standard system initialization performed at each CPU startup.

[0103] Figure 8Controller 510 , which may be referred to as a memory controller, and memory elements are illustrated.

[0104] In various embodiments of the enhanced microcontroller 400, the internal peripherals may be divided into resident peripherals and non-resident peripherals. During the operating power mode of the microcontroller 400, the logic state of the first non-resident peripheral of the non-resident peripheral domain 414 may be stored in the non-resident memory elements 506A, 506B, 506C, and 506D. In various embodiments, upon entering the enhanced power saving mode, the controller 510 may transmit a reset signal IP1 to the non-resident memory elements 506A, 506B, 506C, and 506D of the first internal peripheral to reset the logic states stored therein. Upon entering the enhanced power saving mode, the controller 510 may transmit a reset signal to the non-resident memory elements of each non-resident peripheral of the non-resident peripheral domain 414.

[0105] The logic states of the retained peripheral devices may be set in the retained memory elements 502A, 502B, 502C, and 502D. In various embodiments, the controller 510 does not transmit the reset signal IP2 to the retained memory elements 502A, 502B, 502C, and 502D because the logic states of the retained peripheral devices are preserved in the enhanced power saving mode and the logic states are not reset. The controller may transmit the save signal ( Figure 8 ), and when leaving the enhanced power saving mode, a resume signal is transmitted ( Figure 8 When the enhanced microcontroller 400 enters the standby mode, the controller 510 may also transmit a reset signal IP2 to the retention memory elements 502A, 502B, 502C, and 502D.

[0106] In various embodiments, the controller 510 may selectively transmit appropriate signals (which may be saved, restored, or reset) to all persistent memory elements as determined by the mode of the enhanced microcontroller 400. The controller 510 may selectively transmit appropriate signals (which may be saved or reset) to all non-persistent memory elements as determined by the mode of the enhanced microcontroller 400.

[0107] In various embodiments, the non-persistent memory elements and the persisting memory elements may be located in physical proximity to each other. In various embodiments, the non-persistent memory elements and the persisting memory elements are not located in physical proximity to each other.

[0108] In various embodiments, in addition to the operating power mode and the enhanced power saving mode, the enhanced microcontroller 400 can also operate in a standby mode. In various embodiments, when the enhanced microcontroller 400 enters the standby mode, the controller 510 can transmit a reset signal to the retention memory element and the non-retention memory element.

[0109] Fig. 9 A flow chart illustrating a method 900 for saving power according to one embodiment is depicted.

[0110] At step 902, the method 900 for saving power may include having a microcontroller. At step setting 904, the method 900 may also include setting the persistence memory element to the logic state of the persistence peripheral device during the operating power mode. In various embodiments, the method 900 may include, at step 906, setting the non-persistent memory element to the logic state of the non-persistent peripheral device during the operating power mode. The method 900 may also include, at step 908, decoupling the main power source from the persistence memory element and the non-persistent memory element during the enhanced power saving mode. The method 900 may also include, at step 910, providing a low power source to the persistence memory element during the enhanced power saving mode to maintain the logic state of the persistence peripheral device in the low power position of the persistence memory element.

[0111] In various embodiments, method 900 further includes restoring the primary power source to the surviving memory element and the non-surviving memory element when the enhanced power saving mode expires.

[0112] In various embodiments, the method 900 further includes: wherein the persistence memory element loses its settings during the enhanced power saving mode, and wherein the method 900 further includes restoring the settings of the persistence memory element from the low power position.

[0113] In various embodiments, method 900 further includes decoupling the main power source from the resident memory element and the non-resident memory element during the second power saving mode.

[0114] In various embodiments, method 900 further includes indicating when the microcontroller is in the enhanced power saving mode by saving a flag in a flag memory element, wherein the flag memory element is coupled to the low power source during the enhanced power saving mode.

[0115] Example 1. A power saving system includes a retention trigger of a retention peripheral device; a non-persistence trigger of a non-persistence peripheral device; and a controller that communicates with the retention trigger and the non-persistence trigger, wherein the controller is configured to transmit a save signal to the retention trigger to instruct the retention trigger to maintain the logical state of the retention peripheral device during an enhanced power saving mode of the power saving system, and to transmit a reset signal to the non-persistence trigger to instruct the non-persistence trigger to reset the non-persistence trigger when the power saving system enters the enhanced power saving mode of the power saving system.

[0116] Example 2. A power saving system according to Example 1, wherein the retention trigger is configured to be coupled to a high power source during an operating power mode of the power saving system, and to be decoupled from the high power source during an enhanced power saving mode of the power saving system; the non-retention trigger is configured to be coupled to the high power source during the operating power mode of the power saving system, and to be decoupled from the high power source during the enhanced power saving mode of the power saving system; and the retention trigger is configured to be coupled to a low power source during the enhanced power saving mode of the power saving system.

[0117] Example 3. The power saving system of example 1 or 2, wherein the retention trigger comprises a balloon latch, wherein a logic state of the retention peripheral device is maintained during an enhanced power saving mode of the power saving system.

[0118] Example 4. A power saving system according to Examples 1 to 3, wherein the logic state of the retained peripheral device is set in a retention trigger at a first memory location of the retention trigger during an operating power mode of the power saving system and is lost when the power saving system enters an enhanced power saving mode of the power saving system; and wherein the controller is configured to transmit a recovery signal to the retention trigger when the power saving system leaves the enhanced power saving mode to instruct the retention trigger to retrieve the logic state of the retained peripheral device from the balloon latch to reset the logic state of the retained peripheral device to the first memory location.

[0119] Example 5. A power saving system according to Examples 1 to 4, wherein the balloon latch is configured to be coupled to a low power source during an enhanced power saving mode of the power saving system to power the balloon latch during the enhanced power saving mode of the power saving system.

[0120] Example 6. The power saving system of Examples 1 to 5, wherein during an enhanced power saving mode of the power saving system, a low power source provides power to the balloon latch to maintain a logic state of the retained peripheral device.

[0121] Example 7. A power saving system according to Examples 1 to 6, wherein the retention trigger is coupled to a high power source through a first switch during an operating power mode of the power saving system, and is coupled to a low power source through a second switch during an enhanced power saving mode of the power saving system.

[0122] Example 8. The power saving system of Examples 1 to 7, wherein the non-retention flip-flop is coupled to the high power source through the first switch during an operating power mode of the power saving system.

[0123] Example 9. The power saving system according to Examples 1 to 8 further includes an always-on memory, which is configured to be coupled to a low power source during an enhanced power saving mode of the power saving system to store a flag indicating when the power saving system is in the enhanced power saving mode of the power saving system.

[0124] Example 10. A power saving system according to Examples 1 to 9, wherein the retention trigger is configured to decouple from the high power source and the low power source during a second power saving mode of the power saving system, and wherein the non-retention trigger is configured to decouple from the high power source during the second power saving mode of the power saving system.

[0125] Example 11. A microcontroller comprising: a main power regulator coupled to a main voltage source and configured to provide main power; a low power regulator coupled to the main voltage source and configured to provide low power; a first switching device configured to couple and decouple the main power regulator with a retention trigger and a non-retention trigger; a second switching device configured to couple and decouple the low power regulator with the retention trigger; a power mode controller communicating with the first switching device and the second switching device and configured to operate the first switching device to couple the main power regulator to the retention trigger and the non-retention trigger during an operating power mode; and wherein the power mode controller is configured to operate the second switching device to couple the low power regulator to the retention trigger during an enhanced power saving mode, and to operate the first switching device to decouple the retention trigger and the non-retention trigger from the main power regulator during the enhanced power saving mode.

[0126] Example 12. A microcontroller according to Example 11, wherein the power mode controller is configured to operate a first switching device to decouple a main power regulator from a retention trigger and a non-retention trigger during a second power saving mode, and to operate a second switching device to decouple a low power regulator from the retention trigger in the second power saving mode.

[0127] Example 13. A microcontroller according to Example 11 or 12, wherein the first switching device includes a first switch, the first switch including: a first end coupled to the main power regulator; and a second end coupled to the retention trigger and coupled to the non-retention trigger.

[0128] Example 14. A microcontroller according to Examples 11 to 13, wherein the second switch device includes a second switch, the second switch including a first end coupled to the low power regulator; and a second end coupled to the retention trigger.

[0129] Example 15. The microcontroller of Examples 11 to 14 further comprises an always-on memory configured to be coupled to the low power regulator during the enhanced power saving mode to store a flag indicating when the microcontroller is in the enhanced power saving mode.

[0130] Example 16. The microcontroller according to Examples 11 to 15 further includes: a memory controller that communicates with the retention trigger and the non-retention trigger, wherein the memory controller is configured to pass a save signal to the retention trigger to instruct the retention trigger to maintain the logical state of the retained peripheral device during the enhanced power saving mode, and pass a reset signal to the non-retention trigger to instruct the non-retention trigger to reset the non-retention trigger when the microcontroller enters the enhanced power saving mode.

[0131] Example 17. A microcontroller according to Examples 11 to 16, wherein the retention trigger includes a balloon latch, wherein the logic state of the retention peripheral device is maintained in the balloon latch during the enhanced power saving mode.

[0132] Example 18. A microcontroller according to Examples 11 to 17, wherein the logic state of the retained peripheral device is set in a retention trigger at a first memory location of the retention trigger during an operating power mode and is lost when the microcontroller enters an enhanced power saving mode; and wherein the memory controller is configured to transmit a resume signal to the retention trigger when the microcontroller leaves the enhanced power saving mode to retrieve the logic state of the retained peripheral device from the balloon latch to reset the logic state of the retained peripheral device to the first memory location.

[0133] Example 19. A microcontroller according to Examples 11 to 18, wherein the balloon latch is configured to be coupled to a low power regulator during an enhanced power saving mode to supply power to the balloon latch during the enhanced power saving mode.

[0134] Example 20. A method for saving power, comprising: having a microcontroller; during an operating power mode, setting a retention trigger to a logic state of a retention peripheral device; during an operating power mode, setting a non-retention trigger to a logic state of a non-retention peripheral device; during an enhanced power saving mode, decoupling a main power source from the retention trigger and the non-retention trigger; and during the enhanced power saving mode, providing a low power source to the retention trigger to maintain the logic state of the retention peripheral device in a low power position of the retention trigger.

[0135] Example 21. The method of saving power according to Example 20 further includes: when the enhanced power saving mode expires, restoring the main power source to the retention trigger and the non-retention trigger.

[0136] Example 22. A method of saving power according to example 20 or 21, wherein the persistence trigger loses its setting during the enhanced power saving mode, and wherein the method further comprises restoring the setting of the persistence trigger from the low power position.

[0137] Example 23. The method of saving power according to Examples 20 to 22 further includes: during the second power saving mode, decoupling the main power source from the retention trigger and the non-retention trigger.

[0138] Example 24. The method of saving power according to Examples 20 to 23 further includes: indicating when the microcontroller is in an enhanced power saving mode by saving a flag in a flag memory element, wherein the flag memory element is coupled to a low power source during the enhanced power saving mode.

[0139] Example 25. The method for saving power according to Examples 20 to 24 further includes: determining that the microcontroller is in an enhanced power saving mode when the main power source is decoupled from the retention trigger and the non-retention trigger, and the low power source is provided to the retention trigger.

[0140] References to the exemplary embodiments in this specification are not intended to be interpreted in a limiting sense. Various modifications and combinations of the exemplary embodiments and other embodiments will be apparent to those skilled in the art with reference to the description. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. A power saving system, comprising: Retention triggers for retention peripherals; Non-persistent triggers for non-persistent peripherals; a controller in communication with the retention flip-flop and the non-retention flip-flop, wherein the controller is configured to transmit a save signal to the retention flip-flop to instruct the retention flip-flop to maintain a logic state of the retention peripheral device during an enhanced power saving mode of the power saving system, and the controller is configured to transmit a reset signal to the non-retention flip-flop to instruct the non-retention flip-flop to reset the non-retention flip-flop when the power saving system enters the enhanced power saving mode of the power saving system from an operating power mode of the power saving system, and wherein the retention flip-flop is configured to be powered by a first voltage generated by a main power regulator during the operating power mode and by a second voltage generated by a low power regulator during the enhanced power saving mode, wherein the first voltage is higher than the second voltage; as well as A full-power peripheral device, wherein the surviving peripheral device and the non-surviving peripheral device are configured to be powered off in a standby mode of the power saving system, wherein the full-power peripheral device is configured to be powered by a power supply voltage in the standby mode, the operating power mode, and the enhanced power saving mode, wherein the power supply voltage is an input voltage of the main power regulator and the low power regulator and is used to power the main power regulator and the low power regulator, wherein the power supply voltage maintains the same voltage value during the operating power mode, the enhanced power saving mode, and the standby mode.

2. The power saving system according to claim 1, wherein: The retention trigger is configured to decouple from the main power regulator during the enhanced power saving mode of the power saving system; The non-retention flip-flop is configured to be coupled to the main power regulator during the operational power mode of the power saving system and to be decoupled from the main power regulator during the enhanced power saving mode of the power saving system.

3. The power saving system according to claim 2, wherein the retention trigger comprises: A balloon latch wherein the logic state of the retention peripheral device is maintained during the enhanced power saving mode of the power saving system.

4. A power saving system according to claim 3, wherein the logical state of the retained peripheral device is set in the retention trigger at the first memory location of the retention trigger during the operating power mode of the power saving system, and the logical state of the retained peripheral device is lost when the power saving system enters the enhanced power saving mode of the power saving system; and wherein the controller is configured to transmit a recovery signal to the retention trigger when the power saving system leaves the enhanced power saving mode to instruct the retention trigger to retrieve the logical state of the retained peripheral device from the balloon latch to reset the logical state of the retained peripheral device to the first memory location.

5. A power saving system according to claim 3, wherein the balloon latch is configured to be coupled to the low power regulator during the enhanced power saving mode of the power saving system to power the balloon latch during the enhanced power saving mode of the power saving system.

6. The power saving system of claim 5, wherein during the enhanced power saving mode of the power saving system, the low power regulator provides power to the balloon latch to maintain the logic state of the retention peripheral device.

7. A power saving system according to claim 2, wherein the retention trigger is coupled to the main power regulator through a first switch during the operating power mode of the power saving system, and is coupled to the low power regulator through a second switch during the enhanced power saving mode of the power saving system.

8. The power saving system of claim 7, wherein the non-retention flip-flop is coupled to the main power regulator through the first switch during the operating power mode of the power saving system.

9. The power saving system according to claim 2 further includes an always-on memory, which is configured to be powered by the second voltage provided by the low power regulator during the enhanced power saving mode of the power saving system to store a flag indicating when the power saving system is in the enhanced power saving mode of the power saving system.

10. A microcontroller comprising: a main power regulator powered by a main voltage source and configured to provide a first voltage; a low power regulator powered by the main voltage source and configured to provide a second voltage lower than the first voltage, wherein the second voltage has a constant voltage value; a first switching device configured to couple and decouple the main power regulator with a retention flip-flop and a non-retention flip-flop, wherein the retention flip-flop is in a retention peripheral of the microcontroller and the non-retention flip-flop is in a non-retention peripheral of the microcontroller, wherein the retention peripheral and the non-retention peripheral operate during an operating power mode of the microcontroller to perform normal operations of the microcontroller; a second switch device configured to couple and decouple the low power regulator from the retention trigger; a power mode controller in communication with the first switching device and the second switching device and configured to operate the first switching device to couple the main power regulator to the retention flip-flop and the non-retention flip-flop during the operating power mode; wherein the power mode controller is configured to operate the second switching device to couple the low power regulator to the retention flip-flop during an enhanced power saving mode of the microcontroller, and to operate the first switching device to decouple the retention flip-flop and the non-retention flip-flop from the main power regulator during the enhanced power saving mode, wherein the non-retention flip-flop is configured to be decoupled from the low power regulator during the enhanced power saving mode, wherein the retention flip-flop is powered by the first voltage during the operating power mode and powered by the second voltage during the enhanced power saving mode; and A full-power peripheral device, wherein the full-power peripheral device is powered by the main voltage source in the operating power mode and the enhanced power saving mode, wherein the power mode controller is configured to operate the first switching device and the second switching device so that in a standby mode of the microcontroller, the surviving peripheral device and the non-surviving peripheral device are powered off and the full-power peripheral device is powered by the main voltage source, wherein the main voltage source provides the same voltage during the operating power mode, the enhanced power saving mode and the standby mode.

11. The microcontroller of claim 10, further comprising an always-on memory configured to be coupled to the low power regulator during the enhanced power saving mode to store a flag indicating when the microcontroller is in the enhanced power saving mode.

12. The microcontroller according to claim 10, further comprising: a memory controller in communication with the retention trigger and the non-retention trigger, wherein the memory controller is configured to transmit a save signal to the retention trigger to instruct the retention trigger to maintain a logic state of a retained peripheral device during the enhanced power saving mode, and to transmit a reset signal to the non-retention trigger to instruct the non-retention trigger to reset the non-retention trigger when the microcontroller enters the enhanced power saving mode.

13. The microcontroller according to claim 12, wherein the retention trigger comprises: A balloon latch, wherein the logic state of the retention peripheral device is maintained in the balloon latch during the enhanced power saving mode.

14. A microcontroller according to claim 13, wherein the logic state of the retained peripheral device is set in the retention trigger at the first memory location of the retention trigger during the operating power mode, and the logic state of the retained peripheral device is lost when the microcontroller enters the enhanced power saving mode; and wherein the memory controller is configured to transmit a resume signal to the retention trigger when the microcontroller leaves the enhanced power saving mode to retrieve the logic state of the retained peripheral device from the balloon latch to reset the logic state of the retained peripheral device to the first memory location.

15. A microcontroller according to claim 13, wherein the balloon latch is configured to be coupled to the low power regulator during the enhanced power saving mode to supply power to the balloon latch during the enhanced power saving mode.

16. A method for saving power of a microcontroller, the method comprising: During an operational power mode, setting a retention flip-flop of a retention peripheral device of the microcontroller to a logic state of the retention peripheral device; during the operating power mode, setting a non-retention flip-flop of a non-retention peripheral device of the microcontroller to a logic state of the non-retention peripheral device; wherein the retention peripheral device and the non-retention peripheral device operate in the operating power mode to perform normal functions of the microcontroller, wherein the retention flip-flop and the non-retention flip-flop are powered by a first voltage provided by a main power regulator during the operating power mode; decoupling the main power regulator from the retention flip-flop and the non-retention flip-flop during an enhanced power saving mode; as well as a second voltage provided by a low power regulator to power the retention flip-flop during the enhanced power saving mode to maintain the logic state of the retention peripheral device in a low power position of the retention flip-flop, wherein the second voltage is lower than the first voltage; During the standby mode, powering off the surviving peripherals and the non-surviving peripherals by decoupling the main power regulator and the low power regulator from the surviving peripherals and the non-surviving peripherals; as well as In the standby mode, the operating power mode and the enhanced power saving mode, the full-power peripherals of the microcontroller are powered by a power supply voltage, wherein the power supply voltage has the same voltage value in the standby mode, the operating power mode and the enhanced power saving mode, wherein the main power regulator and the low power regulator are configured to be powered by the power supply voltage and convert the power supply voltage into the first voltage and the second voltage, respectively.

17. The method of saving power of a microcontroller according to claim 16, further comprising: When the enhanced power saving mode expires, the main power regulator is restored to the retention trigger and the non-retention trigger.

18. The method of saving power of a microcontroller according to claim 16, wherein the retention flip-flop loses its setting during the enhanced power saving mode, and wherein the method further comprises: The setting of the persistence trigger is restored from the low power position.

19. The method of saving power of a microcontroller according to claim 16, further comprising: During a second power saving mode, the main power regulator is decoupled from the retention flip-flop and the non-retention flip-flop.

20. The method of saving power of a microcontroller according to claim 16, further comprising: The microcontroller is indicated when it is in the enhanced power saving mode by saving a flag in a flag memory element, wherein the flag memory element is coupled to the low power regulator during the enhanced power saving mode.

21. The method of saving power of a microcontroller according to claim 16, further comprising: The microcontroller is determined to be in the enhanced power saving mode when the main power regulator is decoupled from the retention flip-flop and the non-retention flip-flop, and the low power regulator is provided to the retention flip-flop.

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