A ladder-shaped routing and testing method for FPGA

Abstract

This invention relates to a ladder-like routing and testing method for FPGAs, belonging to the field of chip testing technology. The method performs the following steps: 1) Defining the starting position; the first row, first column, last row, and last column CLBs of the FPGA are used as the starting positions for routing resources; 2) Completing routing; a. Forward routing; b. Reverse routing; 3) Connectivity testing. This invention can traverse all routing resources in both the horizontal and vertical directions. Compared with the traditional method of sequentially connecting horizontally connected routing interfaces, it overcomes the drawback of the single-source nature of routing resource testing, improves the coverage of FPGA routing resource testing, and provides a prerequisite for the reliable application of FPGAs.

Description

Technical Field

[0001] This invention relates to a ladder-shaped wiring and testing method for FPGAs, belonging to the field of chip testing technology. Background Technology

[0002] FPGA, a semi-custom circuit in the field of integrated circuits, consists of I / O modules (Input and Output Blocks) and CLBs (Configurable Logic Blocks), which are the basic building blocks of an FPGA. FPGAs offer advantages such as design flexibility, low cost, and abundant logic resources, and are now widely used in modern digital system design. Circuits designed using HDL are compiled into a binary code stream by FPGA EDA software. This code stream can be used to configure physical devices such as programmable switches within the FPGA chip, ultimately realizing the circuit function on the FPGA.

[0003] The FPGA EDA software flow includes circuit design, behavioral synthesis, process mapping, packaging, placement, and routing, with routing being one of the most time-consuming steps. Furthermore, routing connectivity issues frequently lead to FPGA application failures. Therefore, ensuring the connectivity of routing resources within the FPGA is crucial for improving the reliability of FPGA chips and the efficiency of EDA software compilation.

[0004] Currently, FPGA routing resource testing commonly uses the horizontal serial routing interface method. This testing method cannot cover situations where vertical routing resources are used or where horizontal and vertical routing resources are used simultaneously. It suffers from the problem of limited routing resources and low routing resource coverage. Summary of the Invention

[0005] The technical problem to be solved by this invention is to address the issues of low wiring coverage and incomplete wiring connectivity testing in FPGA chips.

[0006] To solve the above-mentioned technical problems, the technical solution proposed by this invention is: a ladder-shaped routing and testing method applied to FPGA, comprising the following steps:

[0007] 1) Define the starting position;

[0008] The first row, first column, last row, and last column of the FPGA are used as the starting positions for routing resources;

[0009] 2) Complete the wiring;

[0010] a. Begin forward wiring;

[0011] Start from any starting position and execute a unit step horizontally, then execute a unit step vertically, looping until the first / second / Rth / R-N+1th row or first / second / Cth / C-N+1th column of the FPGA, then stop forward routing;

[0012] b. Begin reverse routing;

[0013] Starting from the routing stop position in step a, route along a path that is mirror-symmetrical to the center point of the FPGA until returning to the starting position of step a;

[0014] Where R is the total number of rows in the FPGA, C is the total number of columns in the FPGA, and N is the length of the line being tested;

[0015] 3) Connectivity test;

[0016] The logic value is input into the CLB at the starting position of the wiring through the IO module, and XORed with the signal input to the starting position of the wiring after passing through the line segment under test in the LUT. The XOR result is input to the input of the D flip-flop in the CLB. The D flip-flop storing the XOR result of the LUT is then connected to form a shift register to shift and output the XOR result. The output result is checked to see if it is consistent with the expectation, and the connectivity of the line segment under test is determined accordingly.

[0017] The improvement of the above technical solution is as follows: In step 3), if the result of the shift output is consistent with the XOR result of the corresponding D flip-flop, then the corresponding line segment under test has normal connectivity; otherwise, the line segment under test has a fault.

[0018] The beneficial effects of this invention are: it can traverse all wiring resources in the horizontal and vertical directions, and compared with the traditional test method of sequentially connecting wiring interfaces horizontally, it solves the shortcomings of the singleness of wiring resource testing, improves the coverage of FPGA wiring resource testing, and provides a prerequisite for the reliable application of FPGA. Attached Figure Description

[0019] Figure 1a This is a flowchart of a ladder-shaped routing and testing method applied to FPGA according to Embodiment 1 of the present invention.

[0020] Figure 1b This is a flowchart of a test method for a ladder-shaped routing and testing method applied to FPGA, according to Embodiment 1 of the present invention.

[0021] Figure 2 This is a schematic diagram of the FPGA layout structure in a ladder-shaped routing and testing method applied to FPGA according to Embodiment 1 of the present invention.

[0022] Figure 3This is a schematic diagram of the CLB (Cellular Logic Module) in an FPGA, mentioned in the ladder-shaped wiring and testing method applied to an FPGA according to Embodiment 1 of the present invention.

[0023] Figure 4a yes Figure 3 A schematic diagram of the logic circuit of the LUT.

[0024] Figure 4b yes Figure 3 A schematic diagram of the logic circuit of the DFF.

[0025] Figure 5 This is a schematic diagram illustrating the definition of routing resource direction in a ladder-shaped routing and testing method applied to FPGA according to Embodiment 1 of the present invention.

[0026] Figure 6 This is a schematic diagram of different types of programmable routing resources for a ladder-like routing and testing method applied to FPGA according to Embodiment 1 of the present invention.

[0027] Figure 7 This is a schematic diagram of an X1-line routing method applied to a FPGA in Embodiment 1 of the present invention.

[0028] Figure 8 This is a schematic diagram of an X2-line routing method for a ladder-shaped routing and testing method applied to an FPGA according to Embodiment 1 of the present invention. Detailed Implementation

[0029] Example 1

[0030] like Figure 1a , 1b As shown, a ladder-shaped routing and testing method applied to FPGAs performs the following steps:

[0031] 1) Define the starting position;

[0032] The first row, first column, last row, and last column of the FPGA are used as the starting positions for routing resources;

[0033] 2) Complete the wiring

[0034] a. Begin forward wiring;

[0035] Start from any starting position and execute a unit step horizontally, then execute a unit step vertically, looping until the first / second / Rth / R-N+1th row or first / second / Cth / C-N+1th column of the FPGA, then stop forward routing;

[0036] b. Begin reverse routing;

[0037] Starting from the routing stop position in step a, route along a path that is mirror-symmetrical to the center point of the FPGA until returning to the starting position of step a;

[0038] Where R is the total number of rows in the FPGA, C is the total number of columns in the FPGA, and N is the length of the line being tested;

[0039] like Figure 6 As shown, for line types with different unit step lengths, X1 line type and X2 line type, routing with X1 line type will result in a similar outcome. Figure 7 The routing method in the diagram; if X2 routing is used, the result will be similar to... Figure 8 The wiring method will be discussed in detail later.

[0040] 3) Connectivity test;

[0041] The logic value is input into the CLB at the starting position of the wiring through the IO module, and XORed with the signal input to the starting position of the wiring after passing through the line segment under test in the LUT. The XOR result is input to the input of the D flip-flop in the CLB. The D flip-flop storing the XOR result of the LUT is then connected to form a shift register to shift and output the XOR result. The output result is checked to see if it is consistent with the expectation, and the connectivity of the line segment under test is determined accordingly.

[0042] In step 3), if the result of the shift output is consistent with the XOR result of the corresponding D flip-flop, then the connectivity of the corresponding line segment under test is normal; otherwise, the line segment under test is faulty.

[0043] like Figure 2 As shown, in this embodiment, the horizontal routing resources of the FPGA are named H, and the vertical routing resources are named V. Horizontal routing to the right is represented by E, horizontal routing to the left by W, vertical routing upwards by N, and vertical routing downwards by S, as shown. Figure 5 As shown. The length of the cabling resource (or the length N of the tested cable type) is the number of logic blocks (CLBs) it spans. X1 is a cabling resource spanning 1 CLB; X2 is a cabling resource spanning 2 CLBs; ... XN is a cabling resource spanning N CLBs, as shown. Figure 6 As shown. If the line type under test is X1, the unit step size of the line segment under test is 1, that is, it spans 1 CLB logic block; if the line type under test is X2, the unit step size of the line segment under test is 2, that is, it spans 2 CLB logic blocks; if the line type under test is XN, the unit step size of the line segment under test is N, that is, it spans N CLB logic blocks. This embodiment only uses 1 and 2 as examples, and the rest can be deduced by analogy.

[0044] Taking X1 as an example, such as Figure 7As shown, logic values ​​are input to the CLB at the first (R1C1) and second (R1C3) starting positions of the routing resources via the IO module. The unit step size for this line type is executed horizontally to the right (E), then vertically downwards (S), and so on, until the last row of the FPGA. Then, the routing operation is performed in the opposite direction until the starting position of the routing is reached. Other routing starting positions in the first row, last row, first column, and last column are all executed with unit steps sequentially in the "horizontal-vertical" routing operation. The logic value of the CLB at the starting position reaches the routing starting position via the "step-like" tested line segment. It undergoes an XOR operation in its LUT, and the XOR results of all starting positions are input to the corresponding D flip-flops. The XOR results are shifted and output through a shift register formed by the D flip-flops. The shift output is checked against the expectation. If the shift result matches the XOR result of the corresponding D flip-flop, the corresponding tested line segment has normal connectivity; otherwise, the tested line segment is faulty.

[0045] Taking X2 as an example again, such as Figure 7 As shown, the execution steps are similar to X1. Logic values ​​are input to the CLB at the starting positions (R2C8 and R8C8) of the routing resources via the IO module. The unit step size for this line type is executed horizontally to the right (E), and then vertically downwards (S). In this case, the unit step size is 2. This process continues until the last row or the second row of the FPGA. Then, the routing operation is performed in the opposite direction to the starting position, until the starting position is reached. The starting positions of other routing resources in the first row, last row, first column, and last column are all executed with unit steps sequentially in a "horizontal-vertical" routing operation. The logic value of the CLB at the starting position reaches the starting position via a "staircase" pattern of the tested line segment. An XOR operation is performed at the starting routing unit. The XOR results of all starting positions are then input to the corresponding D flip-flops. The XOR results are shifted and output through a shift register formed by connecting the D flip-flops. Based on the register result, the connectivity of the tested line segment is determined.

[0046] The LUT and D flip-flop in the above example, such as Figure 4a and 4b As shown.

[0047] In addition to the embodiments described above, the present invention may have other implementations. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for ladder-shaped routing and testing applied to FPGA, characterized in that... Perform the following steps: 1) Define the starting position; Use one of the CLBs in the first row or first column of the FPGA as the starting position of the routing resource; 2) Complete the wiring; a. Begin forward wiring; Start from any starting position and perform a horizontal unit step, then perform a vertical unit step, and repeat this cycle until routing reaches the FPGA boundary opposite the starting position; b. Begin reverse routing; Starting from the routing stop position in step a, route along a path that is mirror-symmetrical to the center point of the FPGA until returning to the starting position of step a; 3) Connectivity test; The logic value is input into the CLB at the starting position of the wiring through the IO module, and XORed with the signal input to the starting position of the wiring after passing through the line segment under test in the LUT. The XOR result is input to the input of the D flip-flop in the CLB. The D flip-flop storing the XOR result of the LUT is then connected to form a shift register to shift and output the XOR result. The output result is checked to see if it is consistent with the expectation, and the connectivity of the line segment under test is determined accordingly.

2. The ladder-shaped routing and testing method for FPGA as described in claim 1, characterized in that: In step 3), if the result of the shift output is consistent with the XOR result of the corresponding D flip-flop, then the connectivity of the corresponding line segment under test is normal; otherwise, the line segment under test is faulty.

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