Clock data recovery circuit, display device and driving method thereof

Abstract

The present invention relates to a clock data recovery circuit, a display device, and a driving method. The clock data recovery circuit includes: a phase-locked loop circuit that generates a multi-phase clock signal based on input data and includes a multi-rate phase detector capable of operating at multiple rates and operating at an initial rate that is a predetermined one of the multiple rates in an initial interval; a lock detector that detects the locked state of the phase-locked loop circuit to generate a lock enable signal; a dead zone calibration circuit that determines a final rate corresponding to the data rate of the input data among the multiple rates in response to the lock enable signal; and a digital block that controls the multi-rate phase detector to operate at the final rate, generates a calibration enable signal, the dead zone calibration circuit determines whether the multi-phase clock signal is locked within the dead zone in response to the calibration enable signal, and changes the phase of the multi-phase clock signal when the multi-phase clock signal is locked within the dead zone.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a clock data recovery circuit, a display device including the clock data recovery circuit, and a driving method of the clock data recovery circuit. Background Art

[0002] A data driver of a display device may use a clock data recovery (CDR) circuit to recover a clock signal and data based on input data received from a controller of the display device. In addition, the input data may be transmitted at one of a plurality of data rates according to the resolution and frame frequency of a display panel. Accordingly, it is required that the CDR circuit support multiple rates corresponding to the plurality of data rates.

[0003] Such a multi-rate CDR circuit may be classified into a multi-rate CDR circuit using a multi-rate phase detector and a multi-rate CDR circuit using a multi-rate voltage controlled oscillator. In addition, compared with the multi-rate CDR circuit using a multi-rate voltage controlled oscillator, the multi-rate CDR circuit using a multi-rate phase detector has advantages of small size and low power consumption. However, there is a problem that a clock signal may be locked in a dead zone in the multi-rate CDR circuit using a multi-rate phase detector. Summary of the Invention

[0004] An object of the present invention is to provide a clock data recovery circuit capable of preventing a clock signal from being locked in a dead zone.

[0005] Another object of the present invention is to provide a display device including a clock data recovery circuit capable of preventing a clock signal from being locked in a dead zone.

[0006] Still another object of the present invention is to provide a driving method of a clock data recovery circuit capable of preventing a clock signal from being locked in a dead zone.

[0007] However, the technical problems to be solved by the present invention are not limited to the above technical problems, and the present invention can be variously extended without departing from the spirit and concept of the present invention.

[0008] In order to achieve an object of the present invention, a clock data recovery circuit included in a data driver of a display device according to an embodiment of the present invention includes: a phase-locked loop circuit that generates a multi-phase clock signal from input data and includes a multi-rate phase detector capable of operating at multiple rates and operating at an initial rate that is a predetermined one of the multiple rates in an initial period; a lock detector that detects a locked state of the phase-locked loop circuit and generates a lock enable signal; a dead zone calibration circuit that determines a final rate corresponding to a data rate of the input data among the multiple rates in response to the lock enable signal; and a digital block that controls the multi-rate phase detector to operate at the final rate and generates a calibration enable signal. The dead zone calibration circuit determines whether the multi-phase clock signal is locked in a dead zone in response to the calibration enable signal, and changes a phase of the multi-phase clock signal when the multi-phase clock signal is locked in the dead zone.

[0009] In one embodiment, the multiple rates may include a full rate at which the multi-rate phase detector performs phase detection in each period of the multi-phase clock signal, a half rate at which the multi-rate phase detector performs the phase detection in each half period of the multi-phase clock signal, and a quarter rate at which the multi-rate phase detector performs the phase detection in each 1 / 4 period of the multi-phase clock signal, and the initial rate is the full rate.

[0010] In one embodiment, the data rate of the input data may be one of a first data rate, a second data rate that is twice the first data rate, and a third data rate that is twice the second data rate. When the data rate of the input data is the first data rate, the dead zone calibration circuit determines the final rate as the full rate in response to the lock enable signal. When the data rate of the input data is the second data rate, the dead zone calibration circuit determines the final rate as the half rate in response to the lock enable signal. When the data rate of the input data is the third data rate, the dead zone calibration circuit determines the final rate as the quarter rate in response to the lock enable signal.

[0011] In one embodiment, the phase range of the multi-phase clock signal corresponding to one period of the multi-phase clock signal may be divided into a first phase range, a second phase range, a third phase range, and a fourth phase range. The multi-phase clock signal is locked within the first phase range by the multi-rate phase detector operating at the initial rate. The dead zone calibration circuit detects a first edge of the input data within the second phase range and a second edge of the input data within the third phase range. In the case where neither the first edge nor the second edge is detected, the dead zone calibration circuit determines the final rate as the full rate in response to the lock enable signal. In the case where the first edge is not detected and the second edge is detected, the dead zone calibration circuit determines the final rate as the half rate in response to the lock enable signal. In the case where both the first edge and the second edge are detected, the dead zone calibration circuit determines the final rate as the quarter rate in response to the lock enable signal.

[0012] In one embodiment, the dead zone calibration circuit may further detect a third edge of the input data within the fourth phase range. In the case where the final rate is determined as the full rate, the dead zone calibration circuit determines that the multi-phase clock signal is locked within the dead zone when at least one of the first edge, the second edge, and the third edge is detected in response to the calibration enable signal. In the case where the final rate is determined as the half rate, the dead zone calibration circuit determines that the multi-phase clock signal is locked within the dead zone when at least one of the first edge and the third edge is detected in response to the calibration enable signal. In the case where the final rate is determined as the quarter rate, the dead zone calibration circuit determines that the multi-phase clock signal is not locked within the dead zone in response to the calibration enable signal.

[0013] In one embodiment, in the case where the multi-phase clock signal is determined to be locked within the dead zone, the dead zone calibration circuit may provide additional charge pump current to a loop filter included in the phase locked loop circuit to change the phase of the multi-phase clock signal.

[0014] In one embodiment, the phase range of the multi-phase clock signal corresponding to one period of the multi-phase clock signal may be divided into a first phase range, a second phase range, a third phase range, and a fourth phase range. The dead zone calibration circuit includes: an edge detection block that detects a first edge of the input data in the second phase range, a second edge of the input data in the third phase range, and a third edge of the input data in the fourth phase range; a rate determination block that determines the final rate based on the lock enable signal, the first edge, and the second edge; a dead zone detection block that determines whether the multi-phase clock signal is locked in the dead zone based on the calibration enable signal, the final rate, the first edge, the second edge, and the third edge; and a dead zone charge pump that provides additional charge pump current to a loop filter included in the phase locked loop circuit when the multi-phase clock signal is determined to be locked in the dead zone.

[0015] In one embodiment, the multi-phase clock signal includes a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal, and an eighth clock signal having different phases from each other. The edge detection block includes: a first flip-flop that samples the input data in response to the third clock signal; a second flip-flop that samples the input data in response to the fifth clock signal; a third flip-flop that samples the input data in response to the seventh clock signal; a fourth flip-flop that samples the input data in response to the first clock signal; a first exclusive-OR gate that performs an exclusive-OR operation on the output signal of the first flip-flop and the output signal of the second flip-flop to detect the first edge; a second exclusive-OR gate that performs an exclusive-OR operation on the output signal of the second flip-flop and the output signal of the third flip-flop to detect the second edge; and a third exclusive-OR gate that performs an exclusive-OR operation on the output signal of the third flip-flop and the output signal of the fourth flip-flop to detect the third edge.

[0016] In one embodiment, the edge detection block may further include: a fifth flip-flop located between the first flip-flop and the first exclusive-OR gate and sampling the output signal of the first flip-flop in response to the fourth clock signal; a sixth flip-flop located between the second flip-flop and the first exclusive-OR gate and sampling the output signal of the second flip-flop in response to the sixth clock signal; a seventh flip-flop located between the second flip-flop and the second exclusive-OR gate and sampling the output signal of the second flip-flop in response to the sixth clock signal; an eighth flip-flop located between the third flip-flop and the second exclusive-OR gate and sampling the output signal of the third flip-flop in response to the sixth clock signal; a ninth flip-flop located between the third flip-flop and the third exclusive-OR gate and sampling the output signal of the third flip-flop in response to the eighth clock signal; and a tenth flip-flop located between the fourth flip-flop and the third exclusive-OR gate and sampling the output signal of the fourth flip-flop in response to the eighth clock signal.

[0017] In one embodiment, the rate determination block may include: a first multiplexer selectively outputting the output signal of the first exclusive-OR gate or a low supply voltage in response to the lock enable signal; a second multiplexer selectively outputting the output signal of the second exclusive-OR gate or the low supply voltage in response to the lock enable signal; an eleventh flip-flop sampling a high supply voltage in response to the output signal of the first multiplexer to generate a first rate detection signal; and a twelfth flip-flop sampling the high supply voltage in response to the output signal of the second multiplexer to generate a second rate detection signal.

[0018] In one embodiment, when both the first rate detection signal and the second rate detection signal are at a low level, the digital block may control the multi-rate phase detector to operate at the full rate as the final rate. When the first rate detection signal is at the low level and the second rate detection signal is at a high level, the digital block controls the multi-rate phase detector to operate at the half rate as the final rate. When both the first rate detection signal and the second rate detection signal are at the high level, the digital block controls the multi-rate phase detector to operate at the quarter rate as the final rate.

[0019] In one embodiment, the dead zone detection block may include: a third multiplexer that selectively outputs an output signal of the first exclusive-OR gate or a low supply voltage as a first calibration signal in response to the calibration enable signal; a fourth multiplexer that selectively outputs an output signal of the second exclusive-OR gate or the low supply voltage as a second calibration signal in response to the calibration enable signal; a fifth multiplexer that selectively outputs an output signal of the third exclusive-OR gate or the low supply voltage as a third calibration signal in response to the calibration enable signal; a first OR gate that performs an OR operation on the first calibration signal, the second calibration signal, and the third calibration signal to output a full-rate calibration signal; a second OR gate that performs an OR operation on the first calibration signal and the third calibration signal to output a half-rate calibration signal; and a sixth multiplexer that selectively outputs the full-rate calibration signal, the half-rate calibration signal, or the low supply voltage as a dead zone detection signal in response to a final rate signal corresponding to the final rate.

[0020] In one embodiment, the dead zone charge pump may not provide the additional charge pump current to the loop filter when the dead zone detection signal has a low level, and may provide the additional charge pump current to the loop filter when the dead zone detection signal has a high level.

[0021] In one embodiment, the additional charge pump current may be a negative current, and the phase-locked loop circuit increases the phase of the multi-phase clock signal based on the additional charge pump current provided by the dead zone charge pump.

[0022] In one embodiment, the multi-rate phase detector may detect a phase difference between the input data and the multi-phase clock signal. The phase-locked loop circuit further includes: a charge pump that generates a charge pump current in response to the phase difference detected by the multi-rate phase detector; a loop filter that filters the charge pump current to generate a control voltage; and a voltage-controlled oscillator that generates the multi-phase clock signal based on the control voltage.

[0023] In one embodiment, the multi-phase clock signal includes a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal, and an eighth clock signal having different phases from each other. The multi-rate phase detector includes: a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop, a sixth flip-flop, a seventh flip-flop, and an eighth flip-flop, which sample the input data in response to the first clock signal to the eighth clock signal respectively; a first exclusive-OR gate, including a first input terminal, a second input terminal, and a first output terminal for outputting an up-signal; a second exclusive-OR gate, including a third input terminal, a fourth input terminal, and a second output terminal for outputting a down-signal; a first switch block, which provides the output signal of the first flip-flop, the output signal of the third flip-flop, the output signal of the fifth flip-flop, or the output signal of the seventh flip-flop to the first input terminal in response to a digital code received from the digital block; a second switch block, which provides the output signal of the second flip-flop, the output signal of the fourth flip-flop, the output signal of the sixth flip-flop, or the output signal of the eighth flip-flop to the second input terminal and the third input terminal in response to the digital code; and a third switch block, which provides the output signal of the third flip-flop, the output signal of the fifth flip-flop, the output signal of the seventh flip-flop, or the output signal of the first flip-flop to the fourth input terminal in response to the digital code.

[0024] In one embodiment, when the final rate is determined to be the full rate, the multi-rate phase detector may output the output signal of the sixth flip-flop as the recovered data. When the final rate is determined to be the half rate, the multi-rate phase detector outputs the output signals of the fourth flip-flop and the eighth flip-flop as the recovered data. When the final rate is determined to be the quarter rate, the multi-rate phase detector outputs the output signals of the first flip-flop, the third flip-flop, the fifth flip-flop, and the seventh flip-flop as the recovered data.

[0025] To achieve another object of the present invention, a display device according to an embodiment of the present invention includes: a display panel including a plurality of pixels; a data driver including a clock data recovery circuit that generates a multi-phase clock signal and recovered data based on input data, and provides a data signal corresponding to the recovered data to the plurality of pixels; and a controller that provides the input data to the data driver. The clock data recovery circuit includes: a phase-locked loop circuit that generates the multi-phase clock signal based on the input data, and includes a multi-rate phase detector that can operate at multiple rates and operates at an initial rate, which is a predetermined one of the multiple rates, in an initial period; a lock detector that detects a locked state of the phase-locked loop circuit to generate a lock enable signal; a dead zone calibration circuit that determines a final rate corresponding to a data rate of the input data among the multiple rates in response to the lock enable signal; and a digital block that controls the multi-rate phase detector to operate at the final rate and generates a calibration enable signal. The dead zone calibration circuit determines whether the multi-phase clock signal is locked within a dead zone in response to the calibration enable signal, and changes a phase of the multi-phase clock signal when the multi-phase clock signal is locked within the dead zone.

[0026] To achieve yet another object of the present invention, a driving method of a clock data recovery circuit included in a data driver of a display device according to an embodiment of the present invention includes the following steps: operating a multi-rate phase detector that can operate at multiple rates at an initial rate, which is a predetermined one of the multiple rates, in an initial period to generate a multi-phase clock signal based on input data; detecting a locked state of a phase-locked loop circuit including the multi-rate phase detector; determining a final rate corresponding to a data rate of the input data among the multiple rates; controlling the multi-rate phase detector to operate at the final rate; determining whether the multi-phase clock signal is locked within a dead zone; and changing a phase of the multi-phase clock signal when the multi-phase clock signal is locked within the dead zone.

[0027] In one embodiment, the multiple rates of the multi-rate phase detector may include a full rate, a half rate, and a quarter rate, and the initial rate is the full rate.

[0028] In a clock data recovery circuit, a display device, and a driving method of the clock data recovery circuit according to an embodiment of the present invention, a multi-rate phase detector may operate at a full rate in an initial interval, a dead zone calibration circuit determines a final rate corresponding to a data rate in response to a lock enable signal, the multi-rate phase detector operates at the final rate after the initial interval, and the dead zone calibration circuit performs a dead zone calibration operation of changing a phase of the multi-phase clock signal when it is determined that the multi-phase clock signal is locked in a dead zone in response to a calibration enable signal. Accordingly, it is possible to prevent the multi-phase clock signal from being locked in the dead zone, prevent an error in recovered data, and reduce the size and power consumption of the clock data recovery circuit.

[0029] However, the effects of the present invention are not limited to the above effects, and various expansions can be achieved without departing from the spirit and concept of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a block diagram showing a clock data recovery circuit according to an embodiment of the present invention.

[0031] Figure 2 is a block diagram showing an example of a phase-locked loop circuit included in the clock data recovery circuit according to an embodiment of the present invention.

[0032] Figure 3 is a diagram showing Figure 2 an example of a multi-rate phase detector included in the phase-locked loop circuit.

[0033] Figure 4 is a diagram showing an example of a digital code according to a phase detection rate.

[0034] Figure 5 is a timing diagram for explaining an example of phase detection of a multi-rate phase detector operating at a full rate, a half rate, and a quarter rate.

[0035] Figure 6 is a diagram showing an example of a locking point and a dead zone of a multi-phase clock signal of a clock data recovery circuit not including a dead zone calibration circuit.

[0036] Figure 7 is a timing diagram for explaining an operation of a multi-rate phase detector included in a clock data recovery circuit according to an embodiment of the present invention in an initial interval.

[0037] Figure 8 is a block diagram showing an example of a dead zone calibration circuit included in the clock data recovery circuit according to an embodiment of the present invention.

[0038] Figure 9It is a diagram showing an example of the final rate according to the first rate detection signal and the second rate detection signal.

[0039] Figure 10 It is a diagram for explaining an example of a dead zone detection signal according to a final rate signal, a first calibration signal, a second calibration signal, and a third calibration signal.

[0040] Figure 11 It is a diagram showing an example of a lock point and a dead zone of a multi-phase clock signal of a clock data recovery circuit according to an embodiment of the present invention.

[0041] Figure 12 It is a flowchart showing a driving method of a clock data recovery circuit according to an embodiment of the present invention.

[0042] Figure 13 It is a block diagram showing a display device according to an embodiment of the present invention.

[0043] Figure 14 It is a block diagram showing an electronic device including a display device according to an embodiment of the present invention.

[0044] Description of Reference Numerals

[0045] 100: Clock data recovery circuit 110: Phase-locked loop circuit

[0046] 120: Multi-rate phase detector 140: Charge pump

[0047] 150: Loop filter 160: Voltage-controlled oscillator

[0048] 170: Lock detector 180: Digital block

[0049] 200: Dead zone calibration circuit 210: Edge detection block

[0050] 230: Rate determination block 250: Dead zone detection block

[0051] 280: Dead zone charge pump 800: Display device

[0052] 810: Display panel 820: Gate driver

[0053] 830: Data driver 840: Clock data recovery circuit

[0054] 850: Controller Detailed Description of the Invention

[0055] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

[0056] Figure 1 is a block diagram showing a clock data recovery circuit according to an embodiment of the present invention, Figure 2 is a block diagram showing an example of a phase-locked loop circuit included in the clock data recovery circuit according to an embodiment of the present invention, Figure 3 is showing Figure 2 an example of a multi-rate phase detector included in the phase-locked loop circuit of Figure 4 is a diagram showing an example of a digital code according to a phase detection rate, Figure 5 is a timing diagram for explaining an example of phase detection of a multi-rate phase detector operating at full rate, half rate, and quarter rate, Figure 6 is a diagram showing an example of a lock point and a dead zone of a multi-phase clock signal of a clock data recovery circuit not including a dead zone calibration circuit, Figure 7 is a timing diagram for explaining the operation of a multi-rate phase detector included in a clock data recovery circuit according to an embodiment of the present invention in an initial section, Figure 8 is a block diagram showing an example of a dead zone calibration circuit included in the clock data recovery circuit according to an embodiment of the present invention, Figure 9 is a diagram showing an example of a final rate according to a first rate detection signal and a second rate detection signal, Figure 10 is a diagram for explaining an example of a dead zone detection signal according to a final rate signal, a first calibration signal, a second calibration signal, and a third calibration signal, Figure 11 is a diagram showing an example of a lock point and a dead zone of a multi-phase clock signal of a clock data recovery circuit according to an embodiment of the present invention.

[0057] Referring to Figure 1 , the clock data recovery circuit 100 included in the data driver of the display device according to an embodiment of the present invention may include: a phase-locked loop circuit 110 that generates a multi-phase clock signal MPCK based on input data DAT; a lock detector 170 that detects a locked state of the phase-locked loop circuit 110; a digital block 180 that provides a digital code DCODE to a multi-rate phase detector 120 included in the phase-locked loop circuit 110; and a dead zone calibration circuit 200 that performs a dead zone calibration operation on the multi-phase clock signal MPCK.

[0058] The phase-locked loop circuit 110 may receive input data DAT from a controller (e.g., a Timing Controller (TCON)) of the display device, generate a multi-phase clock signal MPCK based on the input data DAT, and sample the input data DAT in response to the multi-phase clock signal MPCK to generate recovered data RDAT. The multi-phase clock signal MPCK may include a plurality of clock signals having different phases from each other. For example, the multi-phase clock signal MPCK may include a first clock signal to an eighth clock signal, and the first clock signal to the eighth clock signal have edges at time points where one cycle is equally divided into 8 parts, that is, have phases where the phase corresponding to the 360 degrees of the one cycle is equally divided into 8 parts.

[0059] In one embodiment, the phase-locked loop circuit 110 may receive the input data DAT at one of multiple data rates DR1, DR2, DR3 according to the resolution and / or frame frequency of the display panel driven by the data driver. For example, the phase-locked loop circuit 110 may receive the input data DAT at a first data rate DR1 of about 1 Gbps when the display panel has a 4K Ultra High Definition (UHD) resolution and is driven at a frame frequency of about 60 Hz, receive the input data DAT at a second data rate DR2 of about 2 Gbps, which is twice the first data rate DR1, when the display panel has the 4K UHD resolution and is driven at a frame frequency of about 120 Hz, and receive the input data DAT at a third data rate DR3 of about 4 Gbps, which is twice the second data rate DR2, when the display panel has an 8K UHD resolution and is driven at the frame frequency of about 120 Hz. To support such multiple data rates DR1, DR2, DR3 of the input data DAT, the phase-locked loop circuit 110 may include a multi-rate phase detector 120 capable of operating at multiple rates.

[0060] In one embodiment, as Figure 2As shown, the phase-locked loop circuit 110 may include a multi-rate phase detector 120, a charge pump 140, a loop filter 150, and a voltage-controlled oscillator 160. The multi-rate phase detector 120 may detect the phase difference between the input data DAT and the multi-phase clock signal MPCK, and generate a signal corresponding to the phase difference (e.g., an up signal UP and / or a down signal DN). For example, the multi-rate phase detector 120 may generate an up signal UP when the input data DAT leads the multi-phase clock signal MPCK, and generate a down signal DN when the multi-phase clock signal MPCK leads the input data DAT. The charge pump 140 may generate a charge pump current ICP in response to the phase difference detected by the multi-rate phase detector 120. For example, the charge pump 140 may provide a positive charge pump current ICP to the loop filter 150 in response to the up signal UP, and provide a negative charge pump current ICP to the loop filter 150 in response to the down signal DN, i.e., draw the charge pump current ICP from the loop filter 150. The loop filter 150 may filter the charge pump current ICP to generate a control voltage VC. For example, the loop filter 150 may increase the control voltage VC in response to a positive charge pump current ICP, and decrease the control voltage VC in response to a negative charge pump current ICP. And, in one embodiment, the loop filter 150 may remove the high-frequency noise components of the multi-phase clock signal MPCK. The voltage-controlled oscillator 160 may generate the multi-phase clock signal MPCK based on the control voltage VC. For example, the voltage-controlled oscillator 160 may decrease the phase of the multi-phase clock signal MPCK when the control voltage VC increases, and increase the phase of the multi-phase clock signal MPCK when the control voltage VC decreases. In one embodiment, the voltage-controlled oscillator 160 may be an 8-phase voltage-controlled oscillator that generates a first clock signal CK0, a second clock signal CK45, a third clock signal CK90, a fourth clock signal CK135, a fifth clock signal CK180, a sixth clock signal CK225, a seventh clock signal CK270, and an eighth clock signal CK315 having different phases from each other as the multi-phase clock signal MPCK. For example, the first clock signal CK0 may have a phase of approximately 0 degrees, the second clock signal CK45 may have a phase of approximately 45 degrees, the third clock signal CK90 may have a phase of approximately 90 degrees, the fourth clock signal CK135 may have a phase of approximately 135 degrees, the fifth clock signal CK180 may have a phase of approximately 180 degrees, the sixth clock signal CK225 may have a phase of approximately 225 degrees, the seventh clock signal CK270 may have a phase of approximately 270 degrees, and the eighth clock signal CK315 may have a phase of approximately 315 degrees.

[0061] The multi-rate phase detector 120 can operate at one of multiple rates. In one embodiment, the multi-rate phase detector 120 can operate at a full rate FULL RATE corresponding to a first data rate DR1 of the input data DAT, a half rate HALF RATE corresponding to a second data rate DR2 that is twice the first data rate DR1, and a quarter rate QUARTER RATE corresponding to a third data rate DR3 that is twice the second data rate DR2. In one embodiment, in order to be able to operate at the full rate FULL RATE, the half rate HALF RATE, and the quarter rate QUARTER RATE, as Figure 3 shown, the multi-rate phase detector 120 can include a first flip-flop 121 to an eighth flip-flop 128, a first switch block 131, a second switch block 133, a third switch block 135, and a first exclusive-OR gate 137 and a second exclusive-OR gate 139.

[0062] The first flip-flop 121 to the eighth flip-flop 128 can sample the input data DAT in response to a first clock signal CK0, a second clock signal CK45, a third clock signal CK90, a fourth clock signal CK135, a fifth clock signal CK180, a sixth clock signal CK225, a seventh clock signal CK270, and an eighth clock signal CK315, respectively. For example, the first flip-flop 121 can sample the input data DAT in response to the first clock signal CK0 having a phase of approximately 0 degrees, the second flip-flop 122 samples the input data DAT in response to the second clock signal CK45 having a phase of approximately 45 degrees, the third flip-flop 123 samples the input data DAT in response to the third clock signal CK90 having a phase of approximately 90 degrees, the fourth flip-flop 124 samples the input data DAT in response to the fourth clock signal CK135 having a phase of approximately 135 degrees, the fifth flip-flop 125 samples the input data DAT in response to the fifth clock signal CK180 having a phase of approximately 180 degrees, the sixth flip-flop 126 samples the input data DAT in response to the sixth clock signal CK225 having a phase of approximately 255 degrees, the seventh flip-flop 127 samples the input data DAT in response to the seventh clock signal CK270 having a phase of approximately 270 degrees, and the eighth flip-flop 128 samples the input data DAT in response to the eighth clock signal CK315 having a phase of approximately 315 degrees.

[0063] The first switch block 131 can provide the output signal of the first flip-flop 121, the output signal of the third flip-flop 123, the output signal of the fifth flip-flop 125, or the output signal of the seventh flip-flop 127 to the first input terminal of the first exclusive-OR gate 137 in response to a digital code DCODE received from the digital block 180. For example, the digital code DCODE can include a first digital signal D1 to a fourth digital signal D4, and the first switch block 131 includes a first switch SW1 to a fourth switch SW4. The first switch SW1 can transmit the output signal of the first flip-flop 121 to the first input terminal in response to the first digital signal D1, the second switch SW2 transmits the output signal of the third flip-flop 123 to the first input terminal in response to the second digital signal D2, the third switch SW3 transmits the output signal of the fifth flip-flop 125 to the first input terminal in response to the third digital signal D3, and the fourth switch SW4 transmits the output signal of the seventh flip-flop 127 to the first input terminal in response to the fourth digital signal D4.

[0064] The second switch block 133 can provide the output signal of the second flip-flop 122, the output signal of the fourth flip-flop 124, the output signal of the sixth flip-flop 126, or the output signal of the eighth flip-flop 128 to the second input terminal of the first exclusive-OR gate 137 and the third input terminal of the second exclusive-OR gate 139 in response to the digital code DCODE. For example, the second switch block 133 can include a fifth switch SW5 to an eighth switch SW8. The fifth switch SW5 can transmit the output signal of the second flip-flop 122 to the second input terminal and the third input terminal in response to the first digital signal D1, the sixth switch SW6 transmits the output signal of the fourth flip-flop 124 to the second input terminal and the third input terminal in response to the second digital signal D2, the seventh switch SW7 transmits the output signal of the sixth flip-flop 126 to the second input terminal and the third input terminal in response to the third digital signal D3, and the eighth switch SW8 transmits the output signal of the eighth flip-flop 128 to the second input terminal and the third input terminal in response to the fourth digital signal D4.

[0065] The third switch block 135 can provide the output signal of the third flip-flop 123, the output signal of the fifth flip-flop 125, the output signal of the seventh flip-flop 127, or the output signal of the first flip-flop 121 to the fourth input terminal of the second exclusive-OR gate 139 in response to the digital code DCODE. For example, the third switch block 135 may include a ninth switch SW9 to a twelfth switch SW12. The ninth switch SW9 can transmit the output signal of the third flip-flop 123 to the fourth input terminal in response to a first digital signal D1, the tenth switch SW10 transmits the output signal of the fifth flip-flop 125 to the fourth input terminal in response to a second digital signal D2, the eleventh switch SW11 transmits the output signal of the seventh flip-flop 127 to the fourth input terminal in response to a third digital signal D3, and the twelfth switch SW12 transmits the output signal of the first flip-flop 121 to the fourth input terminal in response to a fourth digital signal D4.

[0066] The first exclusive-OR gate 137 can receive the output signal of the first switch block 131 at the first input terminal, receive the output signal of the second switch block 133 at the second input terminal, and perform an exclusive-OR operation on the output signal of the first switch block 131 and the output signal of the second switch block 133 to generate an up signal UP, and output the up signal UP at the first output terminal.

[0067] Moreover, the second exclusive-OR gate 139 can receive the output signal of the second switch block 133 at the third input terminal, receive the output signal of the third switch block 135 at the fourth input terminal, and perform an exclusive-OR operation on the output signal of the second switch block 133 and the output signal of the third switch block 135 to generate a down signal DN, and output the down signal DN at the second output terminal.

[0068] To drive the multi-rate phase detector 120 at a full rate FULL RATE corresponding to the first data rate DR1 of the input data DAT, as Figure 4As shown, the digital block 180 may provide a digital code DCODE of "1000" to the multi-rate phase detector 120. For example, the multi-rate phase detector 120 may receive a first digital signal D1 at a high level and second, third, and fourth digital signals D2, D3, and D4 at a low level. In response to the first digital signal D1 at the high level and the second, third, and fourth digital signals D2, D3, and D4 at the low level, the first switch block 131 may output the output signal of the first flip-flop 121 (i.e., the input data DAT sampled at a phase of approximately 0 degrees), the second switch block 133 may output the output signal of the second flip-flop 122 (i.e., the input data DAT sampled at a phase of approximately 45 degrees), and the third switch block 135 may output the output signal of the third flip-flop 123 (i.e., the input data DAT sampled at a phase of approximately 90 degrees). The first exclusive-OR gate 137 may perform an exclusive-OR operation on the output signal of the first switch block 131 (i.e., the input data DAT sampled at a phase of approximately 0 degrees) and the output signal of the second switch block 133 (i.e., the input data DAT sampled at a phase of approximately 45 degrees) to generate an up signal UP. Accordingly, the up signal UP may have a high level when the input data DAT has an edge within a phase range of approximately 0 degrees to approximately 45 degrees of the multi-phase clock signal MPCK. In addition, the up signal UP having the high level indicates that the input data DAT leads the multi-phase clock signal MPCK (i.e., the second clock signal CK45 having a phase of approximately 45 degrees), and the phase-locked loop circuit 110 may reduce the phase of the multi-phase clock signal MPCK in response to the up signal UP having the high level. Also, the second exclusive-OR gate 139 may perform an exclusive-OR operation on the output signal of the second switch block 133 (i.e., the input data DAT sampled at a phase of approximately 45 degrees) and the output signal of the third switch block 135 (i.e., the input data DAT sampled at a phase of approximately 90 degrees) to generate a down signal DN. Accordingly, the down signal DN may have a high level when the input data DAT has an edge within a phase range of approximately 45 degrees to approximately 90 degrees of the multi-phase clock signal MPCK. In addition, the down signal DN having the high level indicates that the multi-phase clock signal MPCK (i.e., the second clock signal CK45 having a phase of approximately 45 degrees) leads the input data DAT, and the phase-locked loop circuit 110 may increase the phase of the multi-phase clock signal MPCK in response to the down signal DN having the high level. In this way, as Figure 5As shown by the reference numeral 310 in the drawings, when the multi-rate phase detector 120 is driven at the full rate FULL RATE corresponding to the first data rate DR1 of about 1 Gbps of the input data DAT, the phase detection of the phase difference between the input data DAT and the multi-phase clock signal MPCK can be performed once per cycle PED of the multi-phase clock signal MPCK (e.g., the first clock signal CK0). And, in one embodiment, when the multi-rate phase detector 120 is driven at the full rate FULL RATE, for example, when the phase of the multi-phase clock signal MPCK is adjusted such that the input data DAT has an edge at a phase of about 45 degrees, the multi-rate phase detector 120 can output the output signal of the sixth flip-flop 126 (i.e., the input data DAT sampled at a phase of about 225 degrees) as the recovered data RDAT.

[0069] And, in order to drive the multi-rate phase detector 120 at the half rate HALF RATE corresponding to the second data rate DR2 of the input data DAT, as Figure 4 shown, the digital block 180 can provide the multi-rate phase detector 120 with a digital code DCODE that alternates between "1000" and "0010" within one cycle PED. For example, the multi-rate phase detector 120 can receive the high-level first digital signal D1 and the low-level second digital signal D2, third digital signal D3, and fourth digital signal D4 in the first half of the cycle PED, and receive the high-level third digital signal D3 and the low-level first digital signal D1, second digital signal D2, and fourth digital signal D4 in the second half of the cycle PED. In this case, the multi-rate phase detector 120 can output an up signal UP when the input data DAT has an edge within the phase range of about 0 degrees to about 45 degrees, output a down signal DN when the input data DAT has an edge within the phase range of about 45 degrees to about 90 degrees, output an up signal UP when the input data DAT has an edge within the phase range of about 180 degrees to about 225 degrees, and output a down signal DN when the input data DAT has an edge within the phase range of about 225 degrees to about 270 degrees. Accordingly, as Figure 5As shown by the reference numeral 330 in the drawings, when the multi-rate phase detector 120 is driven at a half rate HALF RATE corresponding to a second data rate DR2 of approximately 2 Gbps of the input data DAT, the phase detection may be performed every half period of the multi-phase clock signal MPCK, that is, the phase detection is performed twice per period PED of the multi-phase clock signal MPCK. Also, in one embodiment, when the multi-rate phase detector 120 is driven at the half rate HALF RATE, for example, when the phase of the multi-phase clock signal MPCK is adjusted such that the input data DAT has edges at phases of approximately 45 degrees and approximately 225 degrees, the multi-rate phase detector 120 may output the output signal of the fourth flip-flop 124 (i.e., the input data DAT sampled at a phase of approximately 135 degrees) and the output signal of the eighth flip-flop 128 (i.e., the input data DAT sampled at a phase of approximately 315 degrees) as the recovered data RDAT.

[0070] Also, to drive the multi-rate phase detector 120 at a quarter rate QUARTER RATE corresponding to a third data rate DR3 of the input data DAT, as Figure 4As shown, the digital block 180 can provide a digital code DCODE that alternates between "1000", "0100", "0010", and "0001" within one period PED to the multi-rate phase detector 120. For example, the multi-rate phase detector 120 can receive the high-level first digital signal D1 and the low-level second digital signal D2, third digital signal D3, and fourth digital signal D4 at the first 1 / 4 of the period PED, receive the high-level second digital signal D2 and the low-level first digital signal D1, third digital signal D3, and fourth digital signal D4 at the second 1 / 4 of the period PED, receive the high-level third digital signal D3 and the low-level first digital signal D1, second digital signal D2, and fourth digital signal D4 at the third 1 / 4 of the period PED, and receive the high-level fourth digital signal D4 and the low-level first digital signal D1, second digital signal D2, and third digital signal D3 at the fourth 1 / 4 of the period PED. In this case, the multi-rate phase detector 120 can output an up signal UP when the input data DAT has an edge within a phase range of approximately 0 degrees to approximately 45 degrees, output a down signal DN when the input data DAT has an edge within a phase range of approximately 45 degrees to approximately 90 degrees, output an up signal UP when the input data DAT has an edge within a phase range of approximately 90 degrees to approximately 135 degrees, output a down signal DN when the input data DAT has an edge within a phase range of approximately 135 degrees to approximately 180 degrees, output an up signal UP when the input data DAT has an edge within a phase range of approximately 180 degrees to approximately 225 degrees, output a down signal DN when the input data DAT has an edge within a phase range of approximately 225 degrees to approximately 270 degrees, output an up signal UP when the input data DAT has an edge within a phase range of approximately 270 degrees to approximately 315 degrees, and output a down signal DN when the input data DAT has an edge within a phase range of approximately 315 degrees to approximately 360 degrees. Accordingly, as Figure 5As shown by reference numeral 350 in the drawings, the multi-rate phase detector 120 can perform the phase detection at each 1 / 4 cycle of the multi-phase clock signal MPCK when driven at a quarter rate QUARTER RATE corresponding to a third data rate DR3 of approximately 4 Gbps of the input data DAT, that is, perform the phase detection four times per cycle PED of the multi-phase clock signal MPCK. Also, in one embodiment, when the multi-rate phase detector 120 is driven at a quarter rate QUARTER RATE, for example, when the phase of the multi-phase clock signal MPCK is adjusted such that the input data DAT has edges at phases of approximately 45 degrees, approximately 135 degrees, approximately 225 degrees, and approximately 315 degrees, the multi-rate phase detector 120 can output the output signal of the first flip-flop 121 (i.e., the input data DAT sampled at a phase of approximately 0 degrees), the output signal of the third flip-flop 123 (i.e., the input data DAT sampled at a phase of approximately 90 degrees), the output signal of the fifth flip-flop 125 (i.e., the input data DAT sampled at a phase of approximately 180 degrees), and the output signal of the seventh flip-flop 127 (i.e., the input data DAT sampled at a phase of approximately 270 degrees) as the recovered data RDAT.

[0071] In addition, Figure 2 FIG. shows an example of the configuration of the phase-locked loop circuit 110, but the configuration of the phase-locked loop circuit 110 according to an embodiment of the present invention is not limited to Figure 2 the example shown. And, Figure 3 FIG. shows an example of the configuration of the multi-rate phase detector 120, but the configuration of the multi-rate phase detector 120 according to an embodiment of the present invention is not limited to Figure 3 the example shown.

[0072] In addition, when the clock data recovery circuit 100 does not include the dead zone calibration circuit 200, as Figure 6 shown, the multi-phase clock signal MPCK can be locked within dead zones DZ1, DZ2 that are not the normal lock point NLP. For example, as Figure 6As shown by reference numeral 410 in the accompanying drawings, when the multi-rate phase detector 120 is driven at the full rate FULL RATE corresponding to the first data rate DR1, when the multi-phase clock signal MPCK (e.g., the second clock signal CK45) lags behind the input data DAT by approximately 0 unit intervals (UI: Unit Interval) to approximately 0.125 UI, that is, when it has a phase approximately 0 degrees to approximately 45 degrees greater than the input data DAT, the up signal UP can have a level higher than the down signal DN, and provide a positive charge pump current ICP, and reduce the phase of the multi-phase clock signal MPCK. Here, the UI (Unit Interval) can correspond to the width or time of each bit of the input data DAT. Also, when the second clock signal CK45 leads the input data DAT by approximately 0 UI to approximately 0.125 UI, that is, when it has a phase approximately 0 degrees to approximately 45 degrees smaller than the input data DAT, the down signal DN can have a level higher than the up signal UP, and provide a negative charge pump current ICP, and increase the phase of the multi-phase clock signal MPCK. Accordingly, when the second clock signal CK45 has a phase difference of approximately -0.125 UI to approximately 0.125 UI (i.e., approximately -45 degrees to approximately 45 degrees) with respect to the input data DAT (or a phase difference of approximately 0 UI to approximately 0.125 UI and approximately 0.875 UI to approximately 1 UI (i.e., approximately 0 degrees to approximately 45 degrees and approximately 315 degrees to approximately 360 degrees)) with respect to the input data DAT, the multi-phase clock signal MPCK can be adjusted so that the second clock signal CK45 has a phase difference of approximately 0 UI (i.e., approximately 0 degrees) with respect to the input data DAT, and is locked at the general lock point NLP. However, when the second clock signal CK45 has a phase difference of approximately 0.125 UI to approximately 0.875 UI (i.e., approximately 45 degrees to approximately 315 degrees) with respect to the input data DAT, the charge pump current ICP may not be generated, and the multi-phase clock signal MPCK will not be adjusted, and will not be locked at the general lock point NLP. Accordingly, when the multi-rate phase detector 120 is driven at the full rate FULL RATE, there can be a first dead zone DZ1 of approximately 45 degrees to approximately 315 degrees. And, as Figure 6As shown by reference numeral 430, when the multi-rate phase detector 120 is driven at a half rate HALFRATE corresponding to the second data rate DR2, the multi-phase clock signal MPCK (e.g., the second clock signal CK45) can be locked at the general lock point NLP when the multi-phase clock signal MPCK has a phase difference of about 0UI to about 0.25UI and about 0.75UI to about 1UI (i.e., about 0 degrees to about 90 degrees and about 270 degrees to about 360 degrees) with respect to the input data DAT. However, when the multi-rate phase detector 120 is driven at the half rate HALF RATE, there can be a second dead zone DZ2 of about 90 degrees to about 270 degrees. Additionally, as Figure 6 shown by reference numeral 450, when the multi-rate phase detector 120 is driven at a quarter rate QUARTER RATE corresponding to the third data rate DR3, the multi-phase clock signal MPCK can be locked at the general lock point NLP, and there can be no dead zone.

[0073] However, in the clock data recovery circuit 100 including the dead zone calibration circuit 200 according to an embodiment of the present invention, in order to prevent the multi-phase clock signal MPCK from being locked within the first dead zone DZ1 and the second dead zone DZ2, the multi-rate phase detector 120 can operate at a predetermined initial rate regardless of the data rate of the input data DAT in the initial interval. After the multi-phase clock signal MPCK is locked, the multi-rate phase detector 120 operates at a final rate corresponding to the data rate of the input data DAT, and the dead zone calibration circuit 200 performs a dead zone calibration operation to change the phase of the multi-phase clock signal MPCK locked within the first dead zone DZ1 and the second dead zone DZ2.

[0074] For example, as Figure 7 shown, the multi-rate phase detector 120 can operate at the full rate FULL RATE as the initial rate regardless of the data rates DR1, DR2, DR3 of the input data DAT in the initial interval. In one embodiment, the initial interval can be the interval from the time point when the input data DAT starts to be transmitted to the time point when the multi-phase clock signal MPCK is locked, but is not limited thereto. That is, in the initial interval, regardless of whether the input data DAT is received at the first data rate DR1 of about 1 Gbps, the second data rate DR2 of about 2 Gbps, or the third data rate DR3 of about 4 Gbps, the digital block 180 can provide the digital code DCODE of "1000" to the multi-rate phase detector 120. Accordingly, the multi-rate phase detector 120 can be as Figure 7Perform the phase detection on the input data DAT received at a first data rate DR1 of approximately 1 Gbps using the first clock signal CK0, the second clock signal CK45, and the third clock signal CK90 as shown by reference numeral 510, as Figure 7 Perform the phase detection on the input data DAT received at a second data rate DR2 of approximately 2 Gbps using the first clock signal CK0, the second clock signal CK45, and the third clock signal CK90 as shown by reference numeral 530, as Figure 7 Perform the phase detection on the input data DAT received at a third data rate DR3 of approximately 4 Gbps using the first clock signal CK0, the second clock signal CK45, and the third clock signal CK90 as shown by reference numeral 550. Accordingly, regardless of the data rates DR1, DR2, DR3 of the input data DAT, the multi-phase clock signal MPCK can be locked within a first phase range of approximately 0 degrees to approximately 90 degrees of the multi-phase clock signal MPCK.

[0075] Refer again to Figure 1 , if the multi-phase clock signal MPCK is locked in the initial interval, the lock detector 170 can detect the locked state of the phase-locked loop circuit 110 and generate a lock enable signal LOCK_EN. For example, the lock detector 170 can generate the lock enable signal LOCK_EN when the control voltage VC supplied to the voltage-controlled oscillator 160 has a substantially constant voltage level during a predetermined time period.

[0076] The dead zone calibration circuit 200 can determine the final rate corresponding to the data rates DR1, DR2, DR3 of the input data DAT among the multiple rates of the multi-rate phase detector 120 in response to the lock enable signal LOCK_EN. For example, the dead zone calibration circuit 200 can determine the final rate as the full rate FULL RATE when the data rate of the input data DAT is the first data rate DR1, determine the final rate as the half rate HALF RATE when the data rate of the input data DAT is the second data rate DR2 which is twice the first data rate DR1, and determine the final rate as the quarter rate QUARTER RATE when the data rate of the input data DAT is the third data rate DR3 which is twice the second data rate DR2.

[0077] In one embodiment, a phase range of approximately 0 degrees to approximately 360 degrees of the multi-phase clock signal MPCK corresponding to one cycle PED of the multi-phase clock signal MPCK is divided into a first phase range of approximately 0 degrees to approximately 90 degrees, a second phase range of approximately 90 degrees to approximately 180 degrees, a third phase range of approximately 180 degrees to approximately 270 degrees, and a fourth phase range of approximately 270 degrees to approximately 360 degrees. The multi-phase clock signal MPCK can be locked by the multi-rate phase detector 120 operating at the initial rate (e.g., full rate FULL RATE) in the initial interval within the first phase range of approximately 0 degrees to approximately 90 degrees. The dead zone calibration circuit 200 can detect a first edge of the input data DAT within the second phase range of approximately 90 degrees to approximately 180 degrees and a second edge of the input data DAT within the third phase range of approximately 180 degrees to approximately 270 degrees. Also, the dead zone calibration circuit 200 can determine the final rate as the full rate FULL RATE in response to the lock enable signal LOCK_EN when neither the first edge nor the second edge is detected, determine the final rate as the half rate HALF RATE in response to the lock enable signal LOCK_EN when the first edge is not detected and the second edge is detected, and determine the final rate as the quarter rate QUARTER RATE in response to the lock enable signal LOCK_EN when both the first edge and the second edge are detected.

[0078] The digital block 180 can control the multi-rate phase detector 120 to operate at the final rate determined by the dead zone calibration circuit 200. For example, the digital block 180 can provide a digital code DCODE of "1000" to the multi-rate phase detector 120 when the final rate is determined to be the full rate FULL RATE, provide a digital code DCODE that alternates between "1000" and "0010" within one cycle PED when the final rate is determined to be the half rate HALF RATE, and provide a digital code DCODE that alternates between "1000", "0100", "0010", and "0001" within one cycle PED when the final rate is determined to be the quarter rate QUARTER RATE. The digital block 180 can generate a calibration enable signal CAL_EN. In one embodiment, the calibration enable signal CAL_EN can continue to have a high level after the final rate of the multi-rate phase detector 120 is determined, but is not limited thereto. In another embodiment, after the final rate is determined, the calibration enable signal CAL_EN can have the high level periodically or aperiodically.

[0079] The dead zone calibration circuit 200 may perform a Dead Zone Calibration operation in response to a calibration enable signal CAL_EN. In one embodiment, the dead zone calibration circuit 200 may, in response to the calibration enable signal CAL_EN, determine whether the multi-phase clock signal MPCK is locked within the dead zone, and change the phase of the multi-phase clock signal MPCK if the multi-phase clock signal MPCK is locked within the dead zone.

[0080] In one embodiment, the dead zone calibration circuit 200 may also detect a third edge of the input data DAT within the fourth phase range of approximately 270 degrees to approximately 360 degrees. When the final rate is determined to be the FULL RATE, the dead zone calibration circuit 200 may, in response to the calibration enable signal CAL_EN, determine that the multi-phase clock signal MPCK is locked within the dead zone when detecting the first edge, the second edge, or the third edge, and determine that the multi-phase clock signal MPCK is not locked within the dead zone when not detecting the first edge, the second edge, and the third edge. Further, when the final rate is determined to be the HALF RATE, the dead zone calibration circuit 200 may, in response to the calibration enable signal CAL_EN, determine that the multi-phase clock signal MPCK is locked within the dead zone when detecting the first edge or the third edge, and determine that the multi-phase clock signal MPCK is not locked within the dead zone when not detecting the first edge and the third edge. Further, when the final rate is determined to be the QUARTER RATE, the dead zone calibration circuit 200 may, in response to the calibration enable signal CAL_EN, determine that the multi-phase clock signal MPCK is not locked within the dead zone. The dead zone calibration circuit 200 may provide an additional charge pump current IACP to the loop filter 150 included in the phase-locked loop circuit 110 to change the phase of the multi-phase clock signal MPCK when determining that the multi-phase clock signal MPCK is locked within the dead zone.

[0081] In one embodiment, to determine the final rate and perform the dead zone calibration operation, as Figure 8 shown, the dead zone calibration circuit 200 may include an edge detection block 210, a rate determination block 230, a dead zone detection block 250, and a dead zone charge pump 280.

[0082] The edge detection block 210 may detect the first edge of the input data DAT within the second phase range of approximately 90 degrees to approximately 180 degrees, the second edge of the input data DAT within the third phase range of approximately 180 degrees to approximately 270 degrees, and the third edge of the input data DAT within the fourth phase range of approximately 270 degrees to approximately 360 degrees.

[0083] For example, as Figure 8 shown, the edge detection block 210 includes: a first flip-flop 211 that samples the input data DAT in response to a third clock signal CK90 having a phase of approximately 90 degrees; a second flip-flop 212 that samples the input data DAT in response to a fifth clock signal CK180 having a phase of approximately 180 degrees; a third flip-flop 213 that samples the input data DAT in response to a seventh clock signal CK270 having a phase of approximately 270 degrees; a fourth flip-flop 214 that samples the input data DAT in response to a first clock signal CK0 having a phase of approximately 0 degrees (i.e., approximately 360 degrees); a first exclusive-OR gate 221 that performs an exclusive-OR operation on the output signals of the first flip-flop 211 and the second flip-flop 212 to detect the first edge; a second exclusive-OR gate 222 that performs an exclusive-OR operation on the output signal of the second flip-flop 212 and the output signal of the third flip-flop 213 to detect the second edge; and a third exclusive-OR gate 223 that performs an exclusive-OR operation on the output signal of the third flip-flop 213 and the output signal of the fourth flip-flop 214 to detect the third edge. In one embodiment, the edge detection block 210 may further include fifth flip-flops 215 to tenth flip-flops 220 for aligning the output signals of the first flip-flop 211 to the fourth flip-flop 214. For example, the fifth flip-flop 215 may be located between the first flip-flop 211 and the first exclusive-OR gate 221 and samples the output signal of the first flip-flop 211 in response to a fourth clock signal CK135 having a phase of approximately 135 degrees. The sixth flip-flop 216 may be located between the second flip-flop 212 and the first exclusive-OR gate 221 and samples the output signal of the second flip-flop 212 in response to a sixth clock signal CK225 having a phase of approximately 225 degrees. The seventh flip-flop 217 may be located between the second flip-flop 212 and the second exclusive-OR gate 222 and samples the output signal of the second flip-flop 212 in response to a sixth clock signal CK225 having a phase of approximately 225 degrees. The eighth flip-flop 218 may be located between the third flip-flop 213 and the second exclusive-OR gate 222 and samples the output signal of the third flip-flop 213 in response to a sixth clock signal CK225 having a phase of approximately 225 degrees. The ninth flip-flop 219 may be located between the third flip-flop 213 and the third exclusive-OR gate 223 and samples the output signal of the third flip-flop 213 in response to an eighth clock signal CK315 having a phase of approximately 315 degrees. The tenth flip-flop 220 may be located between the fourth flip-flop 214 and the third exclusive-OR gate 223 and samples the output signal of the fourth flip-flop 214 in response to an eighth clock signal CK315 having a phase of approximately 315 degrees.

[0084] The rate determination block 230 may determine the final rate based on the lock enable signal LOCK_EN, the output signal of the first exclusive-OR gate 221 (i.e., the first edge), and the output signal of the second exclusive-OR gate 222 (i.e., the second edge).

[0085] For example, as Figure 8 shown, the rate determination block 230 may include: a first multiplexer 231 that selectively outputs the output signal of the first exclusive-OR gate 221 or the low power supply voltage VSS in response to the lock enable signal LOCK_EN; a second multiplexer 232 that selectively outputs the output signal of the second exclusive-OR gate 222 or the low power supply voltage VSS in response to the lock enable signal LOCK_EN; an eleventh flip-flop 241 that samples the high power supply voltage VDD in response to the output signal of the first multiplexer 231 to generate a first rate detection signal RDS1; and a twelfth flip-flop 242 that samples the high power supply voltage VDD in response to the output signal of the second multiplexer 232 to generate a second rate detection signal RDS2.

[0086] As Figure 9As shown, the first rate detection signal RDS1 with a low level and the second rate detection signal RDS2 with the low level may indicate that the first edge and the second edge are not detected, that is, it indicates that the input data DAT is received at the first data rate DR1. Accordingly, when both the first rate detection signal RDS1 and the second rate detection signal RDS2 have the low level, the digital block 180 may control the multi-rate phase detector 120 to operate at the full rate FULL RATE corresponding to the first data rate DR1 as the final rate. Also, the first rate detection signal RDS1 with the low level and the second rate detection signal RDS2 with a high level may indicate that the first edge is not detected while the second edge is detected, that is, it indicates that the input data DAT is received at the second data rate DR2 which is twice the first data rate DR1. Accordingly, when the first rate detection signal RDS1 has the low level and the second rate detection signal RDS2 has the high level, the digital block 180 may control the multi-rate phase detector 120 to operate at the half rate HALF RATE corresponding to the second data rate DR2 as the final rate. Also, the first rate detection signal RDS1 with the high level and the second rate detection signal RDS2 with the high level may indicate that the first edge and the second edge are detected, that is, it indicates that the input data DAT is received at the third data rate DR3 which is twice the second data rate DR2. Accordingly, when both the first rate detection signal RDS1 and the second rate detection signal RDS2 have the high level, the digital block 180 may control the multi-rate phase detector 120 to operate at the quarter rate QUARTER RATE corresponding to the third data rate DR3 as the final rate.

[0087] The dead zone detection block 250 may determine whether the multi-phase clock signal MPCK is locked in the dead zone based on the calibration enable signal CAL_EN, the final rate, the first edge, the second edge, and the third edge.

[0088] For example, as Figure 8As shown, the dead zone detection block 250 may include: a third multiplexer 251 that selectively outputs the output signal of the first exclusive-OR gate 221 or the low power supply voltage VSS as a first calibration signal CAL1 in response to a calibration enable signal CAL_EN; a fourth multiplexer 252 that selectively outputs the output signal of the second exclusive-OR gate 222 or the low power supply voltage VSS as a second calibration signal CAL2 in response to the calibration enable signal CAL_EN; a fifth multiplexer 253 that selectively outputs the output signal of the third exclusive-OR gate 223 or the low power supply voltage VSS as a third calibration signal CAL3 in response to the calibration enable signal CAL_EN; a first OR gate 261 that performs an OR operation on the first calibration signal CAL1, the second calibration signal CAL2, and the third calibration signal CAL3 and outputs a full-rate calibration signal FULL_CAL; a second OR gate 262 that performs an OR operation on the first calibration signal CAL1 and the third calibration signal CAL3 and outputs a half-rate calibration signal HALF_CAL; and a sixth multiplexer 270 that selectively outputs the full-rate calibration signal FULL_CAL, the half-rate calibration signal HALF_CAL, or the low power supply voltage VSS as a dead zone detection signal DZDS in response to a final rate signal FRATES corresponding to the final rate.

[0089] The first calibration signal CAL1 having a high level may indicate that the input data DAT has the first edge in the second phase range of about 90 degrees to about 180 degrees, the second calibration signal CAL2 having the high level indicates that the input data DAT has the second edge in the third phase range of about 180 degrees to about 270 degrees, and the third calibration signal CAL3 having the high level indicates that the input data DAT has the third edge in the fourth phase range of about 270 degrees to about 360 degrees. Also, the first OR gate 261 may output the high-level full-rate calibration signal FULL_CAL when any one or more of the first calibration signal CAL1, the second calibration signal CAL2, and the third calibration signal CAL3 have the high level, and the second OR gate 262 outputs the high-level half-rate calibration signal HALF_CAL when one or more of the first calibration signal CAL1 and the third calibration signal CAL3 have the high level. Also, the sixth multiplexer 270 may output the full-rate calibration signal FULL_CAL as the dead zone detection signal DZDS in response to the final rate signal FRATES corresponding to the full rate FULL RATE, output the half-rate calibration signal HALF_CAL as the dead zone detection signal DZDS in response to the final rate signal FRATES corresponding to the half rate HALF RATE, and output the low power supply voltage VSS as the dead zone detection signal DZDS in response to the final rate signal FRATES corresponding to the quarter rate QUARTER RATE.

[0090] Accordingly, as Figure 10 shown, when the final rate signal FRATES corresponds to the full rate FULLRATE, the dead zone detection block 250 can output a low-level dead zone detection signal DZDS when all of the first calibration signal CAL1, the second calibration signal CAL2, and the third calibration signal CAL3 are at a low level, and output a high-level dead zone detection signal DZDS when one or more of the first calibration signal CAL1, the second calibration signal CAL2, and the third calibration signal CAL3 are at a high level. Also, when the final rate signal FRATES corresponds to the half rate HALF RATE, the dead zone detection block 250 can output a low-level dead zone detection signal DZDS when both the first calibration signal CAL1 and the third calibration signal CAL3 are at a low level, and output a high-level dead zone detection signal DZDS when one or more of the first calibration signal CAL1 and the third calibration signal CAL3 are at a high level. Also, when the final rate signal FRATES corresponds to the quarter rate QUARTER RATE, the dead zone detection block 250 can output a low-level dead zone detection signal DZDS regardless of the first calibration signal CAL1, the second calibration signal CAL2, and the third calibration signal CAL3.

[0091] The dead zone charge pump 280 can supply an additional charge pump current IACP to the loop filter 150 included in the phase-locked loop circuit 110 when the multi-phase clock signal MPCK is determined to be locked within the dead zone. The dead zone charge pump 280 can not supply the additional charge pump current IACP to the loop filter 150 when the dead zone detection signal DZDS is at the low level, and supply the additional charge pump current IACP to the loop filter 150 when the dead zone detection signal DZDS is at the high level. In one embodiment, the additional charge pump current IACP can be a negative current, and the phase-locked loop circuit 110 increases the phase of the multi-phase clock signal MPCK based on the additional charge pump current IACP provided by the dead zone charge pump 280.

[0092] Accordingly, as Figure 11 shown by reference numeral 610 in the drawing of Figure 11As shown by reference numeral 630 in the figure, when the multi-rate phase detector 120 is driven at a half rate (HALF RATE), even if the multi-phase clock signal MPCK is locked in a second dead zone DZ2 of approximately 90 degrees to approximately 270 degrees, the phase of the multi-phase clock signal MPCK can be increased by an additional charge pump current IACP, and the multi-phase clock signal MPCK can also be locked at a normal lock point NLP. Additionally, as Figure 11 shown by reference numeral 650 in the figure, when the multi-rate phase detector 120 is driven at a quarter rate (QUARTER RATE), there is no dead zone, and the multi-phase clock signal MPCK can be locked at a normal lock point NLP.

[0093] As described above, in the clock data recovery circuit 100 according to an embodiment of the present invention, the multi-rate phase detector 120 operates at a full rate (FULL RATE) in an initial period. The dead zone calibration circuit 200 determines the final rate corresponding to data rates DR1, DR2, and DR3 in response to a lock enable signal LOCK_EN, and the multi-rate phase detector 120 operates at the final rate. The dead zone calibration circuit 200 can perform the dead zone calibration operation of changing the phase of the multi-phase clock signal MPCK when it determines that the multi-phase clock signal MPCK is locked within the dead zone in response to a calibration enable signal CAL_EN. Accordingly, it is possible to prevent the multi-phase clock signal MPCK from being locked within the dead zone, and it is possible to prevent errors in the recovered data RDAT generated by sampling the input data DAT in response to the multi-phase clock signal MPCK. Also, since the clock data recovery circuit 100 utilizes the multi-rate phase detector 120, the clock data recovery circuit 100 can have a small size and low power consumption.

[0094] Figure 12 is a flowchart showing a driving method of a clock data recovery circuit according to an embodiment of the present invention.

[0095] Referring to Figure 1 and Figure 12 , in the clock data recovery circuit 100 included in a data driver of a display device, a multi-rate phase detector 120 capable of operating at multiple rates operates at an initial rate which is a predetermined one of the multiple rates in an initial period, and at the same time, a phase-locked loop circuit 110 can generate a multi-phase clock signal MPCK based on input data DAT (S710). In one embodiment, the multiple rates of the multi-rate phase detector 120 include a full rate, a half rate, and a quarter rate, and the initial rate can be the full rate.

[0096] The lock detector 170 can detect the locked state of the phase-locked loop circuit 110 and generate a lock enable signal LOCK_EN (S720) when the locked state is detected. The dead zone calibration circuit 200 can determine the final rate corresponding to the data rate of the input data DAT among the multiple rates in response to the lock enable signal LOCK_EN (S730).

[0097] The digital block 180 can control the multi-rate phase detector 120 to operate at the final rate (S740). Also, the digital block 180 can generate a calibration enable signal CAL_EN. The dead zone calibration circuit 200 can determine whether the multi-phase clock signal MPCK is locked within the dead zone in response to the calibration enable signal CAL_EN (S750). The dead zone calibration circuit 200 can change the phase of the multi-phase clock signal MPCK when the multi-phase clock signal MPCK is locked within the dead zone (S760). Accordingly, it is possible to prevent the multi-phase clock signal MPCK from being locked within the dead zone and to prevent errors in the recovered data RDAT generated by sampling the input data DAT in response to the multi-phase clock signal MPCK. Also, since the clock data recovery circuit 100 uses the multi-rate phase detector 120, the clock data recovery circuit 100 can have a small size and low power consumption.

[0098] Figure 13 is a block diagram showing a display device according to an embodiment of the present invention.

[0099] Referring to Figure 13 , the display device 800 may include: a display panel 810 including a plurality of pixels PX; a gate driver 820 providing a gate signal GS to the plurality of pixels PX; a data driver 830 providing a data signal DS to the plurality of pixels PX; and a controller 850 controlling the gate driver 820 and the data driver 830.

[0100] The display panel 810 may include a plurality of data lines, a plurality of gate lines, and a plurality of pixels PX connected to the plurality of data lines and the plurality of gate lines. In one embodiment, each pixel PX may include a switching transistor and a liquid crystal capacitor connected to the switching transistor, and the display panel 810 may be a liquid crystal display (LCD) panel. In another embodiment, each pixel PX may include at least two transistors, at least one capacitor, and an organic light emitting diode (OLED), and the display panel 810 may be an OLED display panel. However, the display panel 810 is not limited to the LCD panel and the OLED display panel and may be any display panel.

[0101] The gate driver 820 may generate a gate signal GS based on a gate control signal GCTRL received from the controller 850, and provide the gate signal GS to a plurality of pixels PX through the plurality of gate lines. In one embodiment, the gate control signal GCTRL may include a gate start signal and a gate clock signal, but is not limited thereto. In one embodiment, the gate driver 820 may be implemented as an amorphous silicon gate (ASG) driver integrated in the peripheral portion of the display panel 810. In another embodiment, the gate driver 820 may be implemented as one or more gate integrated circuits (ICs). Further, according to an embodiment, the gate driver 820 may be directly mounted on the display panel 810, or connected to the display panel 810 in a chip on film (COF) form through a flexible film.

[0102] The data driver 830 may include a clock data recovery circuit 840 that receives input data DAT from the controller 850. The clock data recovery circuit 840 may generate a multi-phase clock signal based on the input data DAT, and sample the input data DAT based on the multi-phase clock signal to generate recovered data RDAT. In one embodiment, the clock data recovery circuit 840 may be Figure 1 the clock data recovery circuit 100. The data driver 830 may generate a data signal DS based on the recovered data RDAT, and provide the data signal DS corresponding to the recovered data RDAT to a plurality of pixels PX through the plurality of data lines. In one embodiment, the data driver 830 may be implemented using one or more data driver ICs. According to an embodiment, the data driver IC may be directly mounted on the display panel 810, or connected to the display panel 810 in a COF form. In another embodiment, the data driver 830 may be integrated in the peripheral portion of the display panel 810.

[0103] A controller (e.g., a timing controller (TCON)) 850 can receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU) or a graphics card). In an embodiment, the input image data IDAT can be RGB image data including red image data, green image data, and blue image data. The controller 850 can convert the input image data IDAT into input data DAT in a form suitable for the data driver 830. And, in an embodiment, the control signal CTRL can include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a main clock signal, etc., but is not limited thereto. The controller 850 can generate the input data DAT and a gate control signal GCTRL based on the input image data IDAT and the control signal CTRL. The controller 850 can provide the gate control signal GCTRL to the gate driver 820 to control the operation of the gate driver 820, and provide the input data DAT to the data driver 830 to control the operation of the data driver 830.

[0104] In the display device 800 according to an embodiment of the present invention, the multi-rate phase detector of the clock data recovery circuit 840 can operate at a full rate in an initial interval, the dead zone calibration circuit of the clock data recovery circuit 840 determines a final rate corresponding to the data rate of the input data DAT in response to a lock enable signal, the multi-rate phase detector operates at the final rate, and the dead zone calibration circuit performs a dead zone calibration operation of changing the phase of the multi-phase clock signal when it is determined that the multi-phase clock signal is locked in the dead zone in response to a calibration enable signal. Accordingly, it is possible to prevent the multi-phase clock signal from being locked in the dead zone, and it is possible to prevent an error in the recovered data RDAT generated by sampling the input data DAT in response to the multi-phase clock signal. And, since the clock data recovery circuit 840 uses the multi-rate phase detector, the clock data recovery circuit 840 can have a small size and low power consumption.

[0105] Figure 14 is a block diagram showing an electronic device including a display device according to an embodiment of the present invention.

[0106] Referring to Figure 14 , the electronic device 1100 can include a processor 1110, a memory device 1120, a storage device 1130, an input / output device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 can also include a plurality of ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc. or communicating with other systems.

[0107] The processor 1110 may perform specific calculations or tasks. According to an embodiment, the processor 1110 may be a microprocessor, a central processing unit (CPU), etc. The processor 1110 may be connected to other components via an address bus, a control bus, a data bus, etc. According to an embodiment, the processor 1110 may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0108] The memory device 1120 may store data required for the operation of the electronic device 1100. For example, the memory device 1120 may include non-volatile memory devices such as Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash Memory, Phase Change Random Access Memory (PRAM), Resistance Random Access Memory (RRAM), Nano Floating Gate Memory (NFGM), Polymer Random Access Memory (PoRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), etc. and / or volatile memory devices such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Mobile DRAM, etc.

[0109] The storage device 1130 may include a solid state drive (SSD), a hard disk drive (HDD), a compact disc read only memory (CD-ROM), etc. The input / output device 1140 may include input structures such as a keyboard, a keypad, a touchpad, a touch screen, a mouse, etc. and output structures such as a speaker, a printer, etc. The power supply 1150 may supply power required for the operation of the electronic device 1100. The display device 1160 may be connected to other components through the bus or other communication links.

[0110] In the display device 1160, the multi-rate phase detector of the clock data recovery circuit included in the data driver may operate at a full rate in an initial period, the dead zone calibration circuit of the clock data recovery circuit determines a final rate corresponding to the data rate of the input data in response to a lock enable signal, the multi-rate phase detector operates at the final rate, and the dead zone calibration circuit performs a dead zone calibration operation of changing the phase of the multi-phase clock signal when it is determined that the multi-phase clock signal is locked in the dead zone in response to a calibration enable signal. Accordingly, it is possible to prevent the multi-phase clock signal from being locked in the dead zone and to prevent errors in the recovered data generated by sampling the input data in response to the multi-phase clock signal. Also, since the clock data recovery circuit uses the multi-rate phase detector, the clock data recovery circuit may have a small size and low power consumption.

[0111] According to an embodiment, the electronic device 1100 may be any electronic device including the display device 1160 such as a digital television, a 3D television, a personal computer (PC), a home electronic device, a laptop computer, a tablet computer, a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.

[0112] Industrial Applicability

[0113] The present invention can be applied to any display device in which a data driver performs clock training and an electronic device including the display device. For example, the present invention can be applied to any electronic device including a display device, such as a television (TV), a digital TV, a 3D TV, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal computer (PC), a home electronic device, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.

[0114] As described above, although the present invention has been described with reference to the embodiments of the present invention, those skilled in the art should be able to understand that various modifications and changes can be made to the present invention without departing from the spirit and concept of the present invention described in the claims.

Claims

1. A clock data recovery circuit included in a data driver of a display device, characterized in that Comprising: A phase-locked loop circuit that generates a multi-phase clock signal based on input data and includes a multi-rate phase detector capable of operating at multiple rates and operating at an initial rate that is a predetermined one of the multiple rates during an initial interval; A lock detector that detects the locked state of the phase-locked loop circuit and generates a lock enable signal; A dead zone calibration circuit that determines a final rate corresponding to the data rate of the input data among the multiple rates in response to the lock enable signal; And A digital block that controls the multi-rate phase detector to operate at the final rate and generates a calibration enable signal, wherein the dead zone calibration circuit determines whether the multi-phase clock signal is locked within a dead zone in response to the calibration enable signal, and changes the phase of the multi-phase clock signal when the multi-phase clock signal is locked within the dead zone, The initial rate is the full rate at which the multi-rate phase detector performs phase detection in each period of the multi-phase clock signal.

2. The clock data recovery circuit according to claim 1, wherein The multiple rates include the full rate, a half rate at which the multi-rate phase detector performs the phase detection in each half period of the multi-phase clock signal, and a quarter rate at which the multi-rate phase detector performs the phase detection in each 1 / 4 period of the multi-phase clock signal.

3. The clock data recovery circuit according to claim 2, wherein The data rate of the input data is one of a first data rate, a second data rate that is twice the first data rate, and a third data rate that is twice the second data rate, When the data rate of the input data is the first data rate, the dead zone calibration circuit determines the final rate as the full rate in response to the lock enable signal, When the data rate of the input data is the second data rate, the dead zone calibration circuit determines the final rate as the half rate in response to the lock enable signal, When the data rate of the input data is the third data rate, the dead zone calibration circuit determines the final rate as the quarter rate in response to the lock enable signal.

4. The clock data recovery circuit according to claim 2, wherein The phase range of the multi-phase clock signal corresponding to one period of the multi-phase clock signal is divided into a first phase range, a second phase range, a third phase range, and a fourth phase range, and the multi-phase clock signal is locked within the first phase range by the multi-rate phase detector operating at the initial rate, The dead zone calibration circuit detects a first edge of the input data within the second phase range and a second edge of the input data within the third phase range, In the case where neither the first edge nor the second edge is detected, the dead zone calibration circuit determines the final rate as the full rate in response to the lock enable signal. In the case where the first edge is not detected and the second edge is detected, the dead zone calibration circuit determines the final rate as the half rate in response to the lock enable signal. In the case where the first edge and the second edge are detected, the dead zone calibration circuit determines the final rate as the quarter rate in response to the lock enable signal.

5. The clock data recovery circuit according to claim 4, wherein the dead zone calibration circuit further detects a third edge of the input data within the fourth phase range. In the case where the final rate is determined as the full rate, the dead zone calibration circuit determines that the multi-phase clock signal is locked within the dead zone when at least one of the first edge, the second edge, and the third edge is detected in response to the calibration enable signal. In the case where the final rate is determined as the half rate, the dead zone calibration circuit determines that the multi-phase clock signal is locked within the dead zone when at least one of the first edge and the third edge is detected in response to the calibration enable signal. In the case where the final rate is determined as the quarter rate, the dead zone calibration circuit determines that the multi-phase clock signal is not locked within the dead zone in response to the calibration enable signal.

6. The clock data recovery circuit according to claim 1, wherein in the case where the multi-phase clock signal is determined to be locked within the dead zone, the dead zone calibration circuit provides an additional charge pump current to a loop filter included in the phase locked loop circuit to change the phase of the multi-phase clock signal.

7. The clock data recovery circuit according to claim 1, wherein a phase range of the multi-phase clock signal corresponding to one period of the multi-phase clock signal is divided into a first phase range, a second phase range, a third phase range, and a fourth phase range. The dead zone calibration circuit includes: an edge detection block that detects a first edge of the input data within the second phase range, a second edge of the input data within the third phase range, and a third edge of the input data within the fourth phase range; a rate determination block that determines the final rate based on the lock enable signal, the first edge, and the second edge; a dead zone detection block that determines whether the multi-phase clock signal is locked within the dead zone based on the calibration enable signal, the final rate, the first edge, the second edge, and the third edge; and a dead zone charge pump that provides an additional charge pump current to a loop filter included in the phase locked loop circuit in the case where the multi-phase clock signal is determined to be locked within the dead zone.

8. The clock data recovery circuit according to claim 7, wherein The multi-phase clock signal includes a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal, and an eighth clock signal having different phases from each other. The edge detection block includes: A first flip-flop that samples the input data in response to the third clock signal; A second flip-flop that samples the input data in response to the fifth clock signal; A third flip-flop that samples the input data in response to the seventh clock signal; A fourth flip-flop that samples the input data in response to the first clock signal; A first exclusive-OR gate that performs an exclusive-OR operation on the output signals of the first flip-flop and the second flip-flop to detect the first edge; A second exclusive-OR gate that performs an exclusive-OR operation on the output signal of the second flip-flop and the output signal of the third flip-flop to detect the second edge; and A third exclusive-OR gate that performs an exclusive-OR operation on the output signal of the third flip-flop and the output signal of the fourth flip-flop to detect the third edge.

9. The clock data recovery circuit according to claim 8, wherein The edge detection block further includes: A fifth flip-flop located between the first flip-flop and the first exclusive-OR gate, and sampling the output signal of the first flip-flop in response to the fourth clock signal; A sixth flip-flop located between the second flip-flop and the first exclusive-OR gate, and sampling the output signal of the second flip-flop in response to the sixth clock signal; A seventh flip-flop located between the second flip-flop and the second exclusive-OR gate, and sampling the output signal of the second flip-flop in response to the sixth clock signal; An eighth flip-flop located between the third flip-flop and the second exclusive-OR gate, and sampling the output signal of the third flip-flop in response to the sixth clock signal; A ninth flip-flop located between the third flip-flop and the third exclusive-OR gate, and sampling the output signal of the third flip-flop in response to the eighth clock signal; and A tenth flip-flop located between the fourth flip-flop and the third exclusive-OR gate, and sampling the output signal of the fourth flip-flop in response to the eighth clock signal.

10. The clock data recovery circuit according to claim 8, wherein The rate determination block includes: A first multiplexer that selectively outputs the output signal of the first exclusive-OR gate or a low power supply voltage in response to the lock enable signal; A second multiplexer that selectively outputs the output signal of the second exclusive-OR gate or the low power supply voltage in response to the lock enable signal; An eleventh flip-flop that samples the high power supply voltage in response to the output signal of the first multiplexer to generate a first rate detection signal; and A twelfth flip-flop that samples the high power supply voltage in response to the output signal of the second multiplexer to generate a second rate detection signal.

11. The clock data recovery circuit according to claim 10, wherein when both the first rate detection signal and the second rate detection signal have a low level, the digital block controls the multi-rate phase detector to operate at the full rate as the final rate; when the first rate detection signal has the low level and the second rate detection signal has a high level, the digital block controls the multi-rate phase detector to operate at the half rate as the final rate; when both the first rate detection signal and the second rate detection signal have the high level, the digital block controls the multi-rate phase detector to operate at the quarter rate as the final rate.

12. The clock data recovery circuit according to claim 8, wherein the dead zone detection block includes: a third multiplexer that selectively outputs the output signal of the first exclusive-OR gate or the low supply voltage as a first calibration signal in response to the calibration enable signal; a fourth multiplexer that selectively outputs the output signal of the second exclusive-OR gate or the low supply voltage as a second calibration signal in response to the calibration enable signal; a fifth multiplexer that selectively outputs the output signal of the third exclusive-OR gate or the low supply voltage as a third calibration signal in response to the calibration enable signal; a first OR gate that performs an OR operation on the first calibration signal, the second calibration signal, and the third calibration signal and outputs a full rate calibration signal; a second OR gate that performs an OR operation on the first calibration signal and the third calibration signal and outputs a half rate calibration signal; and a sixth multiplexer that selectively outputs the full rate calibration signal, the half rate calibration signal, or the low supply voltage as a dead zone detection signal in response to a final rate signal corresponding to the final rate.

13. The clock data recovery circuit according to claim 12, wherein the dead zone charge pump does not supply the additional charge pump current to the loop filter when the dead zone detection signal has a low level, and supplies the additional charge pump current to the loop filter when the dead zone detection signal has a high level.

14. The clock data recovery circuit according to claim 7, wherein the additional charge pump current is a negative current, and the phase-locked loop circuit increases the phase of the multi-phase clock signal based on the additional charge pump current provided by the dead zone charge pump.

15. The clock data recovery circuit according to claim 1, wherein the multi-rate phase detector detects the phase difference between the input data and the multi-phase clock signal, and the phase-locked loop circuit further includes: a charge pump that generates a charge pump current in response to the phase difference detected by the multi-rate phase detector; a loop filter that filters the charge pump current to generate a control voltage; and a voltage-controlled oscillator that generates the multi-phase clock signal based on the control voltage.

16. The clock data recovery circuit according to claim 15, wherein The multi-phase clock signal includes a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a fifth clock signal, a sixth clock signal, a seventh clock signal, and an eighth clock signal having different phases from each other. The multi-rate phase detector includes: A first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop, a sixth flip-flop, a seventh flip-flop, and an eighth flip-flop, which sample the input data in response to the first clock signal to the eighth clock signal respectively; A first exclusive-OR gate, including a first input terminal, a second input terminal, and a first output terminal for outputting an up-signal; A second exclusive-OR gate, including a third input terminal, a fourth input terminal, and a second output terminal for outputting a down-signal; A first switch block, which selectively provides the output signal of the first flip-flop, the output signal of the third flip-flop, the output signal of the fifth flip-flop, or the output signal of the seventh flip-flop to the first input terminal in response to a digital code received from the digital block; A second switch block, which selectively provides the output signal of the second flip-flop, the output signal of the fourth flip-flop, the output signal of the sixth flip-flop, or the output signal of the eighth flip-flop to the second input terminal and the third input terminal in response to the digital code; and A third switch block, which provides the output signal of the third flip-flop, the output signal of the fifth flip-flop, the output signal of the seventh flip-flop, or the output signal of the first flip-flop to the fourth input terminal in response to the digital code.

17. The clock data recovery circuit according to claim 16, wherein when the final rate is determined to be the full rate, the multi-rate phase detector outputs the output signal of the sixth flip-flop as the recovered data, when the final rate is determined to be the half rate, the multi-rate phase detector outputs the output signal of the fourth flip-flop and the output signal of the eighth flip-flop as the recovered data, when the final rate is determined to be the quarter rate, the multi-rate phase detector outputs the output signal of the first flip-flop, the output signal of the third flip-flop, the output signal of the fifth flip-flop, and the output signal of the seventh flip-flop as the recovered data.

18. A display device, characterized in that, including: A display panel including a plurality of pixels; A data driver including a clock data recovery circuit that generates a multi-phase clock signal and recovered data based on input data, and provides a data signal corresponding to the recovered data to the plurality of pixels; and A controller that provides the input data to the data driver, wherein the clock data recovery circuit includes: A phase-locked loop circuit that generates the multi-phase clock signal based on the input data, and includes a multi-rate phase detector that can operate at multiple rates and operates at an initial rate, which is a predetermined one of the multiple rates, in an initial interval. A lock detector that detects the locked state of the phase-locked loop circuit to generate a lock enable signal; A dead zone calibration circuit that determines a final rate corresponding to the data rate of the input data among the multiple rates in response to the lock enable signal; and A digital block that controls the multi-rate phase detector to operate at the final rate and generates a calibration enable signal, wherein the dead zone calibration circuit determines whether the multi-phase clock signal is locked within the dead zone in response to the calibration enable signal, and changes the phase of the multi-phase clock signal when the multi-phase clock signal is locked within the dead zone, The initial rate is the full rate at which the multi-rate phase detector performs phase detection in each cycle of the multi-phase clock signal.

19. A driving method for a clock data recovery circuit, which is a driving method for a clock data recovery circuit included in a data driver of a display device, characterized in that, Including the following steps: Operating a multi-rate phase detector capable of operating at multiple rates at an initial rate that is a predetermined one of the multiple rates in an initial interval to generate a multi-phase clock signal based on input data; Detecting the locked state of a phase-locked loop circuit including the multi-rate phase detector; Determining a final rate corresponding to the data rate of the input data among the multiple rates; Controlling the multi-rate phase detector to operate at the final rate; Determining whether the multi-phase clock signal is locked within the dead zone; And Changing the phase of the multi-phase clock signal when the multi-phase clock signal is locked within the dead zone, The initial rate is the full rate at which the multi-rate phase detector performs phase detection in each cycle of the multi-phase clock signal.

20. The driving method of the clock data recovery circuit according to claim 19, characterized in that The multiple rates of the multi-rate phase detector include the full rate, half rate, and quarter rate.

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