Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing an initial substrate, the initial substrate including a plurality of first invalid regions and a first effective region surrounding the plurality of first invalid regions; forming an initial stress layer in the first effective region; etching the initial substrate and the initial stress layer in the first effective region and the first invalid region to form a substrate, a plurality of first fin structures located on the substrate in the first effective region, and a plurality of first isolation fin structures located on the substrate in the first invalid region. Thus, the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the field of semiconductor technology, as the feature size of integrated circuits continues to decrease and as there is a demand for higher signal transmission speeds in integrated circuits, transistors need to have higher drive currents while gradually decreasing in size.

[0003] In order to make semiconductor devices have higher driving current while gradually reducing their size, the structure of fin field effect transistor is usually adopted. Since the fin field effect transistor is a three-dimensional structure located on the substrate, its characteristic size is smaller and it can better meet the requirements of high integration. In addition, the gate of the fin field effect transistor is opposite to the upper surface of the fin, and the gate is opposite to the two opposite side wall surfaces of the fin. When working, the upper surface of the fin in contact with the gate and the two opposite side wall surfaces can form a channel region, which improves the mobility of carriers.

[0004] However, the performance of semiconductor devices still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, thereby increasing the driving current of a channel of a semiconductor device to improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing an initial substrate, the initial substrate including a plurality of first invalid areas, and a first effective area surrounding the plurality of first invalid areas; forming an initial stress layer in the first effective area, the material of the initial stress layer being different from the material of the initial substrate; etching the initial substrate and the initial stress layer of the first effective area and the first invalid area to form a substrate, a plurality of first fin structures located on the substrate of the first effective area, and a plurality of first isolation fin structures located on the substrate of the first invalid area, the plurality of first fin structures being separated from each other, each of the first fin structures including a stress layer, the first isolation fin structure being connected to the first fin structure in the extension direction of the first fin structure, and the material of the stress layer being different from the material of the first isolation fin structure.

[0007] Optionally, the first fin structure further includes a first fin layer, and the stress layer is located on a surface of the first fin layer.

[0008] Optionally, the material of the stress layer includes silicon germanium, germanium, gallium arsenide or a multi-element semiconductor material composed of III-V group elements.

[0009] Optionally, the method for forming the initial stress layer includes: forming a first opening in the initial substrate of the first effective area; forming a stress material layer in the first opening and on the surface of the initial substrate; and flattening the stress material layer until the initial substrate surface of the first invalid area is exposed.

[0010] Optionally, the method for forming the first opening includes: forming a first mask structure on the surface of the initial substrate, the first mask structure exposing the initial substrate surface of the first effective area; and etching the initial substrate using the first mask structure as a mask until the first opening is formed.

[0011] Optionally, the method for forming the substrate, the first fin structure and the first isolation fin structure includes: forming a plurality of mutually discrete second mask structures on the surface of the initial stress layer in the first effective region and the surface of the initial substrate in the first invalid region, and at least one second mask structure spans the first invalid region; using the plurality of second mask structures as masks, etching the initial strain layer and the initial substrate in the first invalid region to form the substrate, the first fin structure and the first isolation fin structure.

[0012] Optionally, the initial substrate also includes a second effective area, and the plurality of second mask structures are also located on the surface of the initial substrate in the second effective area; the method for forming the semiconductor structure also includes: while etching the initial strained layer and the initial substrate of the first invalid area using the plurality of second mask structures as masks, etching the initial substrate of the second effective area using the second mask structure as a mask to form the substrate in the second effective area, as well as a plurality of discrete initial second fin structures located on the substrate.

[0013] Optionally, the initial substrate also includes a plurality of second invalid regions, the second effective regions surround the plurality of second invalid regions, and at least one of the initial second fin structures spans the second invalid regions; the method for forming the semiconductor structure also includes: after forming the plurality of initial second fin structures, removing the initial second fin structures of the second invalid regions to form a plurality of second fin structures.

[0014] Optionally, the method for removing the initial second fin structure in the second invalid region includes: forming a third mask layer on the surface of the first fin structure, the surface of the initial second fin structure, the surface of the first isolation fin structure and the surface of the substrate; forming a fourth mask structure on the surface of the third mask layer, the fourth mask structure exposing the surface of the third mask layer in the second invalid region; using the fourth mask structure as a mask, etching the third mask layer and the initial second fin structure until the initial second fin structure in the second invalid region is removed.

[0015] Optionally, it also includes: after forming the first fin structure and the first isolation fin structure, removing the first isolation fin structure; the method for removing the first isolation fin structure includes: the fourth mask structure also exposes the surface of the third mask layer of the first invalid area; using the fourth mask structure as a mask, etching the third mask layer and the initial second fin structure while etching the first isolation fin structure until the first isolation fin structure is removed.

[0016] Optionally, the method for forming the second mask structure includes: forming a second mask material layer on the surface of the initial stress layer and the surface of the initial substrate; forming a plurality of mutually discrete first core mold structures on the surface of the second mask material layer; forming a first side wall on the side wall surface of each of the first core mold structures; and etching the second mask material layer using the first side wall as a mask until the surface of the initial stress layer and the surface of the initial substrate are exposed.

[0017] Optionally, the method for forming the plurality of first core mold structures includes: forming a first core mold material layer on the surface of the second mask material layer; forming a first core mold photoresist structure on the surface of the first core mold material layer, the first core mold photoresist structure exposing a portion of the surface of the first core mold material layer; using the first core mold photoresist structure as a mask, etching the first core mold material layer until the surface of the second mask material layer is exposed.

[0018] Optionally, the method for forming several of the first core mold structures includes: forming a first core mold material layer on the surface of the second mask material layer; forming several separate second core mold structures on the surface of the first core mold material layer; forming a second side wall on the side wall surface of each of the second core mold structures; and etching the first core mold material layer using the second side wall as a mask until the surface of the second mask material layer is exposed.

[0019] Optionally, the method for forming the first side wall includes: forming a first side wall material layer on the surface of the second mask material layer and the surfaces of several of the first core mold structures; and etching back the first side wall material layer until the surface of the second mask material layer and the top surface of the first core mold structure are exposed.

[0020] Optionally, the method further includes: after forming the first fin structure and the first isolation fin structure, removing the first isolation fin structure.

[0021] Optionally, the material of the stress layer contains germanium atoms, and the stress layer has a first atomic percentage concentration, which is the atomic percentage concentration of germanium atoms in the material of the stress layer; the method for forming the semiconductor structure also includes: removing the first isolation fin structure, and before removing the first isolation fin structure, forming a first source-drain doping layer in the first fin structure, the material of the first source-drain doping layer contains germanium atoms, and the first source-drain doping layer has a second atomic percentage concentration, which is the atomic percentage concentration of germanium atoms in the material of the first source-drain doping layer, and the second atomic percentage concentration is more than twice the first atomic percentage concentration.

[0022] Optionally, the method for removing the first isolation fin structure includes: forming a first dielectric structure on the first fin structure, the first isolation fin structure and the substrate surface.

[0023] Optionally, the first dielectric structure includes a first dielectric layer located on the substrate surface, the sidewall surface of the first fin structure and the sidewall surface of the first isolation fin structure, and a second dielectric layer located on the surface of the first dielectric layer, wherein the surface of the second dielectric layer is higher than the top surface of the first fin structure.

[0024] Optionally, it also includes: before removing the first isolation fin structure, forming a gate opening spanning the first fin structure and the first isolation fin structure in the first dielectric structure, the gate opening exposing the first fin structure and the first isolation fin structure surface; forming a gate structure in the gate opening, and the first source-drain doping layer is located in the first fin structure on both sides of the gate structure.

[0025] Optionally, the method for removing the first isolation fin structure also includes: forming a fifth mask structure on the surface of the gate structure and the first dielectric structure, the fifth mask structure exposing the surface of the gate structure in the first invalid area; using the fifth mask structure as a mask, etching the gate structure and the first isolation fin structure until the first isolation fin structure is removed.

[0026] Optionally, the method for removing the first isolation fin structure also includes: forming a sixth mask structure on the surface of the first dielectric structure, the sixth mask structure exposing the surface of the first dielectric structure in the first invalid area; and etching the first dielectric structure and the first isolation fin structure using the sixth mask structure as a mask until the first isolation fin structure is removed.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the initial stress layer formed in the first effective area is used to form a stress layer of the first fin structure, and the first isolation fin structure is used to separate adjacent first fin structures in the extension direction of the first fin structure. Since the first effective area surrounds a plurality of first invalid areas, and the initial stress layer is formed only in the first effective area, when etching the initial substrate and the initial stress layer of the first effective area and the first invalid area, a plurality of first fin structures including stress layers and separated from each other, and a first isolation fin structure connected to the first fin structure can be directly formed, so that when the first isolation fin structure is subsequently removed to disconnect the adjacent first fin structure, the etching of the first fin structure for disconnecting the adjacent first fin structure can be reduced, that is, the cutting of the stress layer in the first fin structure is avoided. By avoiding the cutting of the stress layer in the first fin structure, the damage to the internal structure balance of the first isolation structure, especially the stress layer, can be reduced, thereby reducing the stress released in the channel of the first fin structure, increasing the driving current in the channel, and improving the performance of the semiconductor device. On the other hand, since the material of the initial stress layer is different from the material of the substrate, that is, the material of the stress layer is different from the material of the first isolation fin structure, it is possible to adjust the selective etching ratio of the material of the initial stress layer and the material of the substrate by selecting the material of the initial stress layer and the material of the substrate when removing the first isolation fin structure, so as to reduce the damage of the etching process to the first fin structure, thereby improving the performance of the semiconductor device.

[0029] Furthermore, since the first fin structure also includes a first fin layer, and the stress layer is located on the surface of the first fin layer, the distance between the stress layer and the substrate is increased through the first fin layer, thereby reducing the mutual diffusion between the material of the stress layer and the material of the substrate, thereby improving the reliability of the semiconductor device.

[0030] Furthermore, since the material of the initial second fin structure and the first isolation fin structure is the same, both are the material of the substrate, and the initial second fin structure and the first isolation fin structure in the second invalid area are removed at the same time, therefore, on the one hand, the steps of forming the semiconductor structure can be reduced, reducing the time and cost of the semiconductor structure process, and on the other hand, the etching of removing the initial second fin structure and the first isolation fin structure can have the same etching rate for the initial second fin structure and the first isolation fin structure, reducing the residual problem of the initial second fin structure or the first isolation fin structure after the etching, thereby being able to reduce the time and cost of the semiconductor structure process while improving the reliability and performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1 to 3It is a structural schematic diagram of each step of the formation process of a semiconductor structure;

[0032] Figures 4 to 28 It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the performance of semiconductor structures still needs to be improved.

[0034] It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

[0035] Figures 1 to 3 It is a structural schematic diagram of the various steps in the formation process of a semiconductor structure.

[0036] Please refer to Figure 1 and Figure 2 , Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor structure. Figure 2 yes Figure 1 A schematic diagram of a top-down structure along direction Q; providing an initial substrate (not shown), wherein the initial substrate includes region C; forming a stress material layer (not shown) on the surface of the initial substrate; forming a plurality of mutually discrete first mask structures 31 on the surface of the stress material layer; etching the stress material layer and the initial substrate with the first mask structure 31 to form a substrate 10, and a plurality of mutually discrete initial fin structures 50 on the substrate 10.

[0037] The initial fin structure 50 includes: an initial first fin layer 11 located on the substrate 10 and an initial stress layer 21 located on the surface of the initial first fin layer 11 .

[0038] Please Figure 2 Based on reference Figure 3 , the initial fin structure 50 in the region C is removed to form a plurality of separate fin structures (not shown); after the fin structures are formed, the first mask structure 31 is removed.

[0039] The fin structure includes: a first fin layer (not shown) located on the substrate 10 and a stress layer 22 located on the surface of the first fin layer.

[0040] The method for removing the initial fin structure 50 in region C includes: forming a second mask structure (not shown) on the surfaces of several initial fin structures 50, the surface of the first mask structure 31 and the surface of the substrate 10; forming a third mask structure (not shown) on the surface of the second mask structure, the third mask structure exposing the surface of the second mask structure in region C; using the third mask structure as a mask, etching the second mask structure, the first mask structure 31 and the initial fin structure 50 until the initial fin structure 50 in region C is removed.

[0041] In the above method, on the one hand, by forming the stress layer 22, the stress inside the fin structure is increased, thereby improving the driving current of the semiconductor device. On the other hand, by etching the initial fin structure 50 and removing the initial fin structure 50 in the region C, the initial fin structure 50 is cut off along the extension direction of the initial fin structure 50 to form a fin structure, so as to improve the integration of the semiconductor structure.

[0042] However, when removing the initial fin structure 50 in region C, the process of etching the initial fin structure 50 cuts off the formed initial stress layer 21, which causes the internal structural balance of the initial stress layer 21 material to be destroyed, causing the stress in the initial stress layer 21 to be released, thereby reducing the driving current of the fin structure, resulting in poor performance of the semiconductor structure that needs to be improved.

[0043] To solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, by providing an initial substrate including a plurality of first invalid regions and a first effective region surrounding the plurality of first invalid regions, and forming an initial stress layer different from the initial substrate material in the first effective region, thereby improving the driving current of the channel and thus improving the performance of the semiconductor structure.

[0044] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] Figures 4 to 28 It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0046] Please refer to Figure 4 and Figure 5 , Figure 4 is a schematic diagram of a top view of a semiconductor structure in an embodiment of the present invention, Figure 5 yes Figure 4 The cross-sectional structure schematic diagram along the X-X1 direction in FIG. 1 provides an initial substrate 100, wherein the initial substrate 100 includes a plurality of first invalid regions A and a first effective region I surrounding the plurality of first invalid regions A.

[0047] The material of the initial substrate 100 is different from the material of the stress layer formed subsequently.

[0048] The material of the initial substrate 100 is semiconductor material.

[0049] In this embodiment, the material of the initial substrate 100 is silicon.

[0050] In other embodiments, the material of the initial substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0051] In this embodiment, the initial substrate 100 further includes a second active region II.

[0052] In other embodiments, the initial substrate does not include a second active region.

[0053] In this embodiment, the initial substrate 100 further includes a plurality of second ineffective regions B, and the second effective region II surrounds the plurality of second ineffective regions B.

[0054] In other embodiments, the initial substrate does not include the plurality of second ineffective regions.

[0055] In this embodiment, the conductivity types of the devices subsequently formed in the first active region I and the second active region II are opposite.

[0056] In this embodiment, a PMOS device is subsequently formed in the first active region I, and an NMOS device is formed in the second active region II.

[0057] In other embodiments, an NMOS device is subsequently formed in the first active region I, and a PMOS device is subsequently formed in the second active region II.

[0058] Subsequently, an initial stress layer is formed in the first effective area I. For the specific process of forming the initial stress layer, please refer to Figures 6 to 9 .

[0059] Please refer to Figure 6 , Figure 6 is with Figure 5 A schematic cross-sectional structural diagram along the same direction shows that a first opening 110 is formed in the initial substrate 100 of the first active region I.

[0060] The first opening 110 is used to provide a space for subsequently forming an initial stress layer.

[0061] In this embodiment, the method for forming the first opening 110 includes: forming a first mask structure 111 on the surface of the initial substrate 100, the first mask structure 111 exposing the surface of the initial substrate 100 of the first effective area I; etching the initial substrate 100 using the first mask structure 111 as a mask until the first opening 110 is formed.

[0062] The process of etching the initial substrate 100 includes a dry etching process or a wet etching process.

[0063] The material of the first mask structure 111 includes: a first mask layer (not shown) located on the surface of the initial substrate 100, a first mask anti-reflection layer (not shown) located on the surface of the first mask layer, and a first mask photoresist layer (not shown) located on the surface of the first mask anti-reflection layer.

[0064] In this embodiment, after the first opening 110 is formed, the first mask structure 111 is removed.

[0065] Please refer to Figure 7 , Figure 7 is with Figure 6 In the schematic cross-sectional structure diagram along the same direction, a stress material layer 112 is formed in the first opening 110 and on the surface of the initial substrate 100 .

[0066] The stress material layer 112 provides material for subsequently forming an initial stress layer.

[0067] The material of the stress material layer 112 includes silicon germanium, germanium, gallium arsenide or a multi-component semiconductor material composed of III-V elements. Correspondingly, the material of the initial stress layer includes silicon germanium, germanium, gallium arsenide or a multi-component semiconductor material composed of III-V elements.

[0068] In this embodiment, the material of the stress material layer 112 is silicon germanium. Accordingly, the material of the stress layer is silicon germanium.

[0069] In this embodiment, the material of the stress layer contains germanium atoms, and the stress layer has a first atomic percentage concentration, which is the atomic percentage concentration of germanium atoms in the material of the stress layer.

[0070] In this embodiment, the process of forming the stress material layer 112 includes an epitaxial growth process or a deposition process. The deposition process may be a chemical vapor deposition process or an atomic layer deposition process.

[0071] Please refer to Figure 8 and Fig. 9 , Figure 8 is with Figure 4 Schematic diagram of the top view structure in the same direction, Fig. 9 yes Figure 8 The cross-sectional structure schematic diagram along the X-X1 direction in the figure, the stress material layer 112 is flattened until the surface of the initial substrate 100 of the first invalid area A is exposed to form an initial stress layer 113 in the first effective area I.

[0072] The initial stress layer 113 provides material for subsequently forming a stress layer of the first fin structure.

[0073] Since the first effective area I surrounds several first invalid areas A, and the initial stress layer 113 is formed only in the first effective area I, when the initial substrate 100 and the initial stress layer 113 of the first effective area I and the first invalid area A are subsequently etched, several first fin structures including stress layers and separated from each other, and a first isolation fin structure connected to the first fin structure can be directly formed, and the first isolation fin structure is used to separate adjacent first fin structures in the extension direction of the first fin structure.

[0074] Since the adjacent first fin structure can be disconnected by removing the first isolation fin structure later, etching of the first fin structure for disconnecting the adjacent first fin structure can be reduced, that is, cutting of the stress layer in the first fin structure is avoided.

[0075] By avoiding cutting of the stress layer in the first fin structure, the damage to the first isolation structure, especially the internal structural balance of the stress layer, can be reduced, thereby reducing the stress released in the channel of the first fin structure and increasing the driving current in the channel, thereby improving the performance of the semiconductor device.

[0076] In this embodiment, the material of the initial stress layer 113 is different from the material of the initial substrate 100 .

[0077] Since the material of the initial stress layer 113 is different from the material of the initial substrate 100, and the initial substrate 100 provides material for the subsequent formation of the substrate and the first isolation fin structure, accordingly, the material of the stress layer is different from the material of the first isolation fin structure. Therefore, by selecting the material of the initial stress layer and the material of the substrate, the selective etching ratio of the material of the initial stress layer 113 and the material of the initial substrate 100 in the etching process during the removal of the first isolation fin structure can be adjusted to reduce the damage of the etching process to the first fin structure, thereby improving the performance of the semiconductor device.

[0078] In this embodiment, the process of planarizing the stress material layer 112 includes a chemical mechanical planarization process, a dry etching process or a wet etching process.

[0079] Subsequently, the initial substrate 100 and the initial stress layer 113 of the first effective area I and the first ineffective area A are etched to form a substrate, a plurality of first fin structures located on the substrate of the first effective area I, and a plurality of first isolation fin structures located on the substrate of the first ineffective area A. The plurality of first fin structures are separated from each other, each of the first fin structures includes a stress layer, and the first isolation fin structure is connected to the first fin structure in the extension direction of the first fin structure, and the material of the stress layer is different from the material of the first isolation fin structure. For detailed process, please refer to Figures 10 to 17 .

[0080] Please refer to Fig.10 and Fig.11 , Fig.10 is Figure 8 Schematic diagram of the top view of the structure on the foundation. Fig.11 yes Fig.10 The schematic diagram of the cross-sectional structure along the X-X1 direction in the figure shows that a second mask material layer 120 is formed on the surface of the initial stress layer 113 and the surface of the initial substrate 100; a first core mold material layer 130 is formed on the surface of the second mask material layer 120; a plurality of mutually independent second core mold structures (not shown) are formed on the surface of the first core mold material layer 130; and a second side wall 141 is formed on the side wall surface of each of the second core mold structures.

[0081] The second mask material layer 120 is used to provide material for subsequently forming a second mask structure.

[0082] The first core mold material layer 130 is used to provide material for subsequently forming a first core mold structure.

[0083] In this embodiment, the process of forming the second mask material layer 120 and the first core mold material layer 130 includes: a chemical vapor deposition process or an atomic layer deposition process.

[0084] In this embodiment, the method for forming the second core mold structure includes: forming a second core mold material layer (not shown) on the surface of the first core mold material layer 130; forming a second core mold photoresist structure (not shown) on the surface of the second core mold material layer, the second core mold photoresist structure exposing a portion of the surface of the second core mold material layer; using the second core mold photoresist structure as a mask, etching the second core mold material layer until the surface of the first core mold material layer 130 is exposed.

[0085] In this embodiment, the second core mold photoresist structure includes: a second photoresist mask layer (not shown) located on the surface of the second core mold material layer; a second anti-reflection layer (not shown) located on the surface of the second photoresist mask layer; and a second photoresist layer (not shown) located on the surface of the second anti-reflection layer.

[0086] The second photoresist mask layer is helpful to improve the stability of the second photoresist layer in pattern transmission. The second anti-reflection layer is helpful to improve the anti-reflection effect when forming the second photoresist layer, thereby improving the pattern accuracy of the second photoresist layer. In summary, the pattern accuracy of the second photoresist structure can be improved.

[0087] In this embodiment, the material of the second photoresist mask layer includes spin-coated carbon, and the second anti-reflection layer includes: a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0088] The material of the second photoresist layer includes photoresist.

[0089] In other embodiments, one or both of the second photoresist mask layer and the second anti-reflective layer are not included.

[0090] The process of forming the second core mold material layer includes a chemical vapor deposition process or an atomic layer deposition process.

[0091] In this embodiment, after the second core mold structure is formed, the second core mold photoresist structure is removed, and the process of removing the second core mold photoresist structure includes an ashing process.

[0092] In other embodiments, the process of forming the second core mold structure includes a self-aligned multi-patterning process.

[0093] In this embodiment, the method for forming the second side wall 141 includes: depositing a second side wall material layer (not shown) on the exposed surfaces of the second core mold structure and the first core mold material layer 130; and etching back the second side wall material layer until the top surface of the second core mold structure and the surface of the first core mold material layer 130 are exposed.

[0094] The process of etching back the second spacer material layer includes: an anisotropic dry etching process.

[0095] In this embodiment, after the second sidewall 141 is formed, the second core mold structure is removed.

[0096] In this embodiment, before forming the second mask material layer 120, an oxide layer (not shown) is formed on the surface of the initial stress layer 113 and the surface of the initial substrate 100. Since the oxide layer is formed, on the one hand, the oxide layer can be used as an adhesion layer, so that the adhesion between the second mask material layer 120 and the initial substrate 100, and the adhesion between the initial stress layer 113 and the second mask material layer 120 can be increased through the oxide layer; on the other hand, the interface state of the surface of the initial substrate 100 and the surface of the initial stress layer 113 can also be improved through the oxide layer. Therefore, it is beneficial to improve the performance of the semiconductor structure.

[0097] Please refer to Fig.12 and Fig.13 , Fig.12 is Fig.10 Schematic diagram of the top view of the structure on the foundation. Fig.13 yes Fig.12 In the schematic diagram of the cross-sectional structure along the X-X1 direction, the first core mold material layer 130 is etched with the second side wall 141 as a mask until the surface of the second mask material layer 120 is exposed to form a plurality of first core mold structures 131 separated from each other; after the first core mold structure 131 is formed, a first side wall 132 is formed on the side wall surface of each of the first core mold structures 131.

[0098] In other embodiments, the second core mold structure and the second sidewall are not formed. The method for forming a plurality of first core mold structures also includes: after forming the first core mold material layer, forming a first core mold photoresist structure (not shown) on the surface of the first core mold material layer, wherein the first core mold photoresist structure exposes a portion of the surface of the first core mold material layer; and etching the first core mold material layer using the first core mold photoresist structure as a mask until the surface of the second mask material layer is exposed.

[0099] The first core mold photoresist structure includes: a first photoresist mask layer (not shown) located on the surface of the first core mold material layer; a first anti-reflection layer (not shown) located on the surface of the first photoresist mask layer; and a first photoresist layer (not shown) located on the surface of the first anti-reflection layer.

[0100] The first photoresist mask layer is beneficial to improving the stability of the first photoresist layer in pattern transfer.

[0101] The first anti-reflection layer is helpful to improve the anti-reflection effect when forming the first photoresist layer, thereby improving the pattern accuracy of the first photoresist layer. In summary, the pattern accuracy of the first photoresist structure can be improved.

[0102] The material of the first photoresist mask layer includes spin-on carbon, and the first anti-reflection layer includes: a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0103] The material of the first photoresist layer includes photoresist.

[0104] In other embodiments, one or both of the first photoresist mask layer and the first anti-reflection layer are not included.

[0105] In this embodiment, the process of etching the first core mold material layer 130 includes a dry etching process or a wet etching process.

[0106] In this embodiment, the method for forming the first side wall 132 includes: forming a first side wall material layer (not shown) on the surface of the second mask material layer 120 and the surfaces of several of the first core mold structures 131; and etching back the first side wall material layer until the surface of the second mask material layer 120 and the top surface of the first core mold structure 131 are exposed.

[0107] In this embodiment, the process of forming the first spacer material layer includes a chemical vapor deposition process or an atomic layer deposition process.

[0108] In this embodiment, after the first sidewalls 132 are formed, a number of the first core mold structures 131 are removed.

[0109] Please refer to Fig.14 and Fig.15 , Fig.14 is Fig.12 Schematic diagram of the top view of the structure on the foundation. Fig.15 yes Fig.14 The cross-sectional structure schematic diagram along the X-X1 direction in the figure shows that the second mask material layer 120 is etched with the first side wall 132 as a mask until the surface of the initial stress layer 113 and the surface of the initial substrate 100 are exposed, so as to form a plurality of mutually discrete second mask structures 121 on the surface of the initial stress layer 113 of the first effective area I and the surface of the initial substrate 100 of the first invalid area A, and at least one second mask structure 121 spans across the first invalid area A.

[0110] The second mask structure 121 located on the first active region I and the first inactive region A is used to subsequently form a first fin structure in the first active region I and a first isolation fin structure in the first inactive region A. Since at least one second mask structure 121 spans across the first inactive region A, it is possible to simultaneously form the first fin structure and the first isolation fin structure in the process of etching the initial stress layer 113 and the initial substrate 100 in the first inactive region A using the second mask structure 121 as a mask.

[0111] In this embodiment, the process of etching the second mask material layer 120 includes a dry etching process or a wet etching process.

[0112] In this embodiment, the plurality of second mask structures 121 are also located on the surface of the initial substrate 100 in the second active region II, and at least one of the second mask structures 121 also spans across the surface of the initial substrate 100 in the second inactive region B. Thus, an initial second fin structure can be formed in the second active region II while the first fin structure and the first isolation fin structure are subsequently formed, and the initial second fin structure spans across the second inactive region B.

[0113] In other embodiments, since there is no second active region, the initial second fin structure is not formed in the second active region.

[0114] In other embodiments, since there is no second ineffective region, the initially formed second fin structure does not cross the second ineffective region.

[0115] In this embodiment, after the second mask structure 121 is formed, the first sidewall spacer 132 is removed.

[0116] Please refer to Fig.16 and Fig.17 , Fig.16 is Fig.14 Schematic diagram of the top view of the structure on the foundation. Fig.17 yes Fig.16 The schematic diagram of the cross-sectional structure along the X-X1 direction shows that the initial strained layer 113 and the initial substrate 100 of the first invalid area A are etched using the plurality of second mask structures 121 as masks to form a substrate 101, a plurality of first fin structures 150 and a plurality of first isolation fin structures 160.

[0117] The first fin structure 150 is located on the substrate 101 of the first effective area I, and the several first isolation fin structures 160 are located on the substrate 101 of the first invalid area A. The several first fin structures 150 are separated from each other, and each of the first fin structures 150 includes a stress layer 151. In the extension direction of the first fin structure 150, the first isolation fin structure 160 is connected to the first fin structure 150, and the material of the stress layer 151 is different from the material of the first isolation fin structure 160.

[0118] Since the initial substrate 100 provides material for forming the first isolation fin structure 160 , and the material of the initial substrate 100 is different from that of the stress layer 151 , the material of the stress layer 151 can be different from that of the first isolation fin structure 160 .

[0119] The material of the stress layer 151 includes silicon germanium, germanium, gallium arsenide or a multi-element semiconductor material composed of III-V group elements.

[0120] In this embodiment, the material of the stress layer 151 is silicon germanium.

[0121] In this embodiment, the first fin structure 150 further includes a first fin layer 152 , and the stress layer 151 is located on the surface of the first fin layer 152 .

[0122] Since the first fin structure 150 also includes a first fin layer 152, and the stress layer 151 is located on the surface of the first fin layer 152, the first fin layer 152 increases the distance between the stress layer 151 and the substrate 101, thereby reducing the mutual diffusion between the material of the stress layer 151 and the material of the substrate 101, thereby improving the reliability of the semiconductor device.

[0123] In other embodiments, the first fin structure 150 does not include a first fin layer.

[0124] In this embodiment, while the initial strained layer 113 and the initial substrate 100 of the first invalid area I are etched using the several second mask structures 121 as masks, the initial substrate 100 of the second effective area I and the second invalid area B are etched using the second mask structure 121 as a mask to form the substrate 101 in the second effective area II, and several separate initial second fin structures 170 located on the substrate 101, at least one of the initial second fin structures 170 spanning the second invalid area B.

[0125] In this embodiment, the process of etching the initial strained layer 113 and the initial substrate 100 includes a dry etching process or a wet etching process.

[0126] In this embodiment, after the first fin structure 150 , the first isolation fin structure 160 , and the initial second fin structure 170 are formed, a number of the second mask structures 121 are removed.

[0127] In this embodiment, after forming the plurality of initial second fin structures 170, the initial second fin structures 170 in the second invalid region B are removed to form a plurality of second fin structures 171. In other embodiments, since there is no second invalid region, the initial second fin structures in the second invalid region are not removed. For the specific process of removing the initial second fin structures 170 in the second invalid region B to form a plurality of second fin structures 171, please refer to Figures 18 to 21 .

[0128] Please refer to Fig.18 and Fig.19 , Fig.18 is Fig.16 Schematic diagram of the top view of the structure on the foundation. Fig.19 yes Fig.18 In the schematic diagram of the cross-sectional structure along the X-X1 direction, a third mask layer 180 is formed on the surface of the first fin structure 150, the surface of the initial second fin structure 170, the surface of the first isolation fin structure 160 and the surface of the substrate 101; a fourth mask structure 182 is formed on the surface of the third mask layer 180, and the fourth mask structure 182 exposes the surface of the third mask layer 180 of the second invalid area B.

[0129] In this embodiment, the material of the fourth mask structure 182 includes photoresist.

[0130] In this embodiment, before forming the fourth mask structure 182 , a third anti-reflection layer 181 is formed on the surface of the third mask layer 180 .

[0131] Therefore, during the exposure process of forming the fourth mask structure 182 , the third anti-reflection layer 181 is beneficial for improving the anti-reflection effect of the fourth mask structure 182 during the exposure process, thereby improving the pattern accuracy of the fourth mask structure 182 .

[0132] The third anti-reflection layer 181 includes: a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0133] It should be noted that, since in this embodiment, a third anti-reflection layer 181 is formed on the surface of the third mask layer 180, the fourth mask structure 182 exposing the surface of the third mask layer 180 of the second invalid area B means that the fourth mask structure 182 exposes the surface of the third anti-reflection layer 181 of the second invalid area B.

[0134] The third mask layer 180 is used, on the one hand, to transfer the pattern of the fourth mask structure 182, and on the other hand, to protect the substrate 101, the first fin structure 150, the first isolation fin structure 160 and the initial second fin structure 170 of the first effective area I, the first invalid area A and the second effective area II in the subsequent etching process of transferring the pattern of the fourth mask structure 182, thereby reducing the damage of the etching process to the substrate 101, the first fin structure 150, the first isolation fin structure 160 and the initial second fin structure 170 of the first effective area I, the first invalid area A and the second effective area II, thereby improving the performance of the semiconductor structure.

[0135] In this embodiment, the material of the third mask layer 180 includes spin-on carbon. The spin-on carbon has good filling properties and can improve the flatness of the surface of the third mask layer 180, thereby facilitating the improvement of the pattern accuracy of the fourth mask structure 182 and improving the performance of the semiconductor structure.

[0136] Please refer to Fig. 20 and Fig.21 , Fig. 20 is Fig.18 Schematic diagram of the top view of the structure on the foundation. Fig.21 yes Fig. 20 In the schematic diagram of the cross-sectional structure along the X-X1 direction, the third mask layer 180 and the initial second fin structure 170 are etched using the fourth mask structure 182 as a mask until the initial second fin structure 170 in the second invalid area B is removed to form a plurality of discrete second fin structures 171 in the second effective area II.

[0137] Since the initial second fin structure 170 in the second invalid area B is removed before the first isolation fin structure 160 is subsequently removed, that is, the initial second fin structure 170 in the second invalid area B is removed alone, the etching process for removing the initial second fin structure 170 is more targeted, and the initial second fin structure 170 in the second invalid area B can be removed more accurately to reduce the residual problem of the initial second fin structure 170 in the second invalid area B, thereby improving the reliability and performance of the semiconductor device.

[0138] The process of etching the third mask layer 180 and the initial second fin structure 170 includes a dry etching process or a wet etching process.

[0139] In this embodiment, since the initial substrate 100 provides material for the initial second fin structure 170 and the second fin structure 171 is the initial second fin structure 170 with the second invalid region B removed, the material of the second fin structure 171 is the same as that of the initial substrate 100 .

[0140] In other embodiments, the fourth mask structure further exposes the surface of the third mask layer of the first invalid region. Therefore, the method for removing the first isolation fin structure includes: using the fourth mask structure as a mask, etching the third mask layer and the initial second fin structure while etching the first isolation fin structure until the first isolation fin structure is removed.

[0141] Since the material of the initial second fin structure and the first isolation fin structure are the same, both are the material of the substrate, and the initial second fin structure and the first isolation fin structure in the second invalid area are removed at the same time, therefore, on the one hand, the steps of forming the semiconductor structure can be reduced, reducing the time and cost of the semiconductor structure process, and on the other hand, the etching of removing the initial second fin structure and the first isolation fin structure can have the same etching rate for the initial second fin structure and the first isolation fin structure, reducing the residual problem of the initial second fin structure or the first isolation fin structure after the etching, thereby reducing the time and cost of the semiconductor structure process while improving the reliability and performance of the semiconductor device.

[0142] In this embodiment, after the second fin structure 171 is formed, the third mask layer 180 , the third anti-reflection layer 181 and the fourth mask structure 182 are removed.

[0143] Please refer to Figure 22 to Figure 24 , Fig. 22 is Fig. 20 Schematic diagram of the top view of the structure on the foundation. Fig.23 yes Fig. 22 Schematic diagram of the cross-sectional structure along the X-X1 direction, Fig.24 yes Fig. 22 In the schematic diagram of the cross-sectional structure along the Y-Y1 direction, a first dielectric layer 210 is formed on the surface of the substrate 101, the side wall surface of the first fin structure 150 and the side wall surface of the first isolation fin structure 160; a second dielectric layer 220 is formed on the surface of the first dielectric layer 210, and the surface of the second dielectric layer 220 is higher than the top surface of the first fin structure 150; a gate opening 221 is formed in the second dielectric layer 220, spanning the first fin structure 150 and the first isolation fin structure 160, and the gate opening 221 exposes the surfaces of the first fin structure 150 and the first isolation fin structure 160.

[0144] The first dielectric layer 210 and the second dielectric layer 220 form a first dielectric structure.

[0145] In this embodiment, the first dielectric layer 210 is also located on the sidewall surface of the second fin structure 171 .

[0146] In this embodiment, the method for forming the first dielectric layer 210 includes: depositing a first dielectric material layer (not shown) on the surface of the first fin structure 150, the first isolation fin structure 160, the second fin structure 171 and the substrate 101; and etching back the first dielectric material layer until a portion of the sidewall surfaces of the first fin structure 150, the first isolation fin structure 160 and the second fin structure 171 are exposed.

[0147] In this embodiment, the second dielectric layer 220 also covers the sidewall surface of the second fin structure 171 , and the gate opening 221 also exposes the surface of the second fin structure 171 .

[0148] In this embodiment, the process of forming the second dielectric layer 220 includes a deposition process or a spin coating process.

[0149] In this embodiment, before the first isolation fin structure 160 is subsequently removed, a first source-drain doped layer 250 is formed in the first fin structure 150 .

[0150] Specifically, in this embodiment, before forming the gate opening 221 , a first source-drain doped layer 250 is formed in the first fin structure 150 on both sides of the gate opening 221 .

[0151] In this embodiment, the material of the first source / drain doping layer 250 contains germanium atoms, and the first source / drain doping layer 250 has a second atomic percentage concentration, which is the atomic percentage concentration of germanium atoms in the material of the first source / drain doping layer 250, and the second atomic percentage concentration is more than twice the first atomic percentage concentration.

[0152] Since the first isolation fin structure 160 is removed after the first source-drain doping layer 250 is formed, and the second atomic percentage concentration is more than twice the first atomic percentage concentration, the stress in the stress layer 151 can be further fixed by the first source-drain doping layer 250 having the second atomic percentage concentration, i.e., a high concentration. Therefore, in the subsequent process of removing the first isolation fin structure 160, the stress released in the channel of the first fin structure 150 can be better reduced, which is beneficial to increase the driving current in the channel, so as to further improve the performance of the semiconductor device.

[0153] In this embodiment, before forming the gate opening 221 , a second source-drain doped layer 270 is formed in the second fin structure 171 on both sides of the gate opening 221 .

[0154] The method for forming the first source-drain doped layer 250 includes: etching the second dielectric layer 220 on both sides of the gate opening 221 of the first effective area I to form a second opening (not shown) in the second dielectric layer 220, wherein the second opening exposes the top surface of the first fin structure 150 on both sides of the gate opening 221; continuing to etch the exposed first fin structure 150 to form a first source-drain opening (not shown) in the first fin structure 150; and forming the first source-drain doped layer 250 in the first source-drain opening.

[0155] The method for forming the second source-drain doped layer 270 includes: etching the second dielectric layer 220 on both sides of the gate opening 221 of the second effective region II to form a third opening (not shown) in the second dielectric layer 220, wherein the third opening exposes the top surface of the second fin structure 171 on both sides of the gate opening 221; continuing to etch the exposed second fin structure 171 to form a second source-drain opening (not shown) in the second fin structure 171; and forming the second source-drain doped layer 270 in the second source-drain opening.

[0156] Please refer to Fig.25 , Fig.25 is Fig. 22 A schematic top view of the structure based on FIG. 2 , a gate structure 230 is formed in the gate opening 221 .

[0157] In this embodiment, the method for forming the gate structure 230 includes: depositing a gate structure material layer (not shown) in the gate opening 221 and on the surface of the second dielectric layer 220 ; and etching back the gate structure material layer until the surface of the second dielectric layer 220 is exposed.

[0158] In this embodiment, the gate structure 230 includes: a gate dielectric layer (not shown), a work function layer located on the surface of the gate dielectric layer, and a gate electrode layer located on the surface of the work function layer.

[0159] Since the first source-drain doped layer 250 is formed in the first fin structure 150 on both sides of the gate opening 221 , the first source-drain doped layer 250 is located in the first fin structure 150 on both sides of the gate structure 230 .

[0160] In this embodiment, the first isolation fin structure 160 is subsequently removed. For a specific process, please refer to Figure 26 to Figure 28 .

[0161] Please refer to Fig.26 and Fig. 27, Fig.26 is Fig.25 Schematic diagram of the top view of the structure on the foundation. Fig. 27 yes Fig.26 In the cross-sectional structural diagram along the X-X1 direction, a fifth mask structure 240 is formed on the surface of the first dielectric structure, and the fifth mask structure 240 exposes the surface of the gate structure 230 of the first invalid area A.

[0162] In this embodiment, the fifth mask structure 240 includes a fifth mask layer 241 located on the surface of the first dielectric layer, a fifth anti-reflection layer 242 located on the surface of the fifth mask layer 241 , and a fifth photoresist layer 243 located on the surface of the fifth anti-reflection layer 242 .

[0163] The material of the fifth photoresist layer 243 includes photoresist.

[0164] The fifth mask layer 241 is helpful to improve the stability of the fifth photoresist layer 243 in pattern transmission. The fifth anti-reflection layer 242 is helpful to improve the anti-reflection effect when forming the fifth photoresist layer 243, thereby improving the pattern accuracy of the fifth photoresist layer 243.

[0165] The fifth anti-reflection layer 242 includes: a thin silicon anti-reflection layer (Si-ARC), an organic bottom anti-reflection layer (organic BARC), a dielectric anti-reflection layer (DARC), or a combination of an organic bottom anti-reflection layer and a dielectric anti-reflection layer.

[0166] Please refer to Fig.28 , Fig.28 is with Fig. 27 In the cross-sectional structural diagram along the same direction, the gate structure 230 and the first isolation fin structure 160 are etched using the fifth mask structure 240 as a mask until the first isolation fin structure 160 is removed.

[0167] The process of etching the first isolation fin structure 160 includes a dry etching process or a wet etching process.

[0168] In this embodiment, after removing the first isolation structure 160, a fourth opening (not shown) is formed in the first dielectric structure; after forming the fourth opening, a second dielectric structure (not shown) is formed in the fourth opening, on the surface of the gate structure 230, and on the surface of the first dielectric structure.

[0169] In this embodiment, after forming the fourth opening and before forming the second dielectric structure, the fifth mask structure 240 is removed.

[0170] In other embodiments, before forming the first source-drain doping layer, a sixth mask structure is formed on the surface of the first dielectric structure, the sixth mask structure exposing the surface of the first dielectric structure in the first invalid area; using the sixth mask structure as a mask, the first dielectric structure and the first isolation fin structure are etched until the first isolation fin structure is removed.

[0171] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing an initial substrate, the initial substrate comprising a plurality of first invalid regions and a first valid region surrounding the plurality of first invalid regions; An initial stress layer is formed in the first effective region, wherein the material of the initial stress layer is different from the material of the initial substrate, wherein the method for forming the initial stress layer comprises: forming a first opening in the initial substrate of the first effective region; forming a stress material layer in the first opening and on the surface of the initial substrate; and flattening the stress material layer until the surface of the initial substrate of the first ineffective region is exposed; The initial substrate and the initial stress layer of the first effective area and the first invalid area are etched to form a substrate, a plurality of first fin structures located on the substrate of the first effective area, and a plurality of first isolation fin structures located on the substrate of the first invalid area, wherein the plurality of first fin structures are separated from each other, each of the first fin structures includes a stress layer, and in the extension direction of the first fin structure, the first isolation fin structure is connected to the first fin structure, and the material of the stress layer is different from the material of the first isolation fin structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first fin structure further includes a first fin layer, and the stress layer is located on a surface of the first fin layer.

3. The method for forming a semiconductor structure according to claim 1, wherein: The material of the stress layer includes silicon germanium, germanium, gallium arsenide or a multi-element semiconductor material composed of III-V group elements.

4. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first opening includes: forming a first mask structure on the surface of the initial substrate, the first mask structure exposing the initial substrate surface of the first effective area; etching the initial substrate using the first mask structure as a mask until the first opening is formed.

5. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the substrate, the first fin structure and the first isolation fin structure includes: forming a plurality of mutually discrete second mask structures on the surface of the initial stress layer in the first effective area and the surface of the initial substrate in the first invalid area, and at least one second mask structure spans the first invalid area; using the plurality of second mask structures as masks, etching the initial stress layer and the initial substrate in the first invalid area to form the substrate, the first fin structure and the first isolation fin structure.

6. The method for forming a semiconductor structure according to claim 5, wherein: The initial substrate further includes a second effective area, and the plurality of second mask structures are also located on the surface of the initial substrate in the second effective area; The method for forming the semiconductor structure also includes: while etching the initial stress layer and the initial substrate of the first invalid area using the plurality of second mask structures as masks, etching the initial substrate of the second effective area using the second mask structure as a mask to form the substrate in the second effective area, and a plurality of mutually discrete initial second fin structures located on the substrate.

7. The method for forming a semiconductor structure according to claim 6, wherein: The initial substrate also includes a plurality of second invalid regions, the second effective regions surround the plurality of second invalid regions, and at least one of the initial second fin structures spans the second invalid regions; the method for forming the semiconductor structure also includes: after forming the plurality of initial second fin structures, removing the initial second fin structure of the second invalid region to form a plurality of second fin structures.

8. The method for forming a semiconductor structure according to claim 7, wherein: The method for removing the initial second fin structure in the second invalid area includes: forming a third mask layer on the surface of the first fin structure, the surface of the initial second fin structure, the surface of the first isolation fin structure and the surface of the substrate; forming a fourth mask structure on the surface of the third mask layer, the fourth mask structure exposing the surface of the third mask layer in the second invalid area; using the fourth mask structure as a mask, etching the third mask layer and the initial second fin structure until the initial second fin structure in the second invalid area is removed.

9. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: After forming the first fin structure and the first isolation fin structure, removing the first isolation fin structure; The method for removing the first isolation fin structure includes: the fourth mask structure further exposes the surface of the third mask layer of the first ineffective area; Using the fourth mask structure as a mask, while etching the third mask layer and the initial second fin structure, the first isolation fin structure is etched until the first isolation fin structure is removed.

10. The method for forming a semiconductor structure according to claim 5, wherein: The method for forming the second mask structure includes: forming a second mask material layer on the surface of the initial stress layer and the surface of the initial substrate; forming a plurality of mutually discrete first core mold structures on the surface of the second mask material layer; forming a first side wall on the side wall surface of each of the first core mold structures; and etching the second mask material layer using the first side wall as a mask until the surface of the initial stress layer and the surface of the initial substrate are exposed.

11. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the plurality of first core mold structures includes: forming a first core mold material layer on the surface of the second mask material layer; forming a first core mold photoresist structure on the surface of the first core mold material layer, wherein the first core mold photoresist structure exposes a portion of the surface of the first core mold material layer; and etching the first core mold material layer using the first core mold photoresist structure as a mask until the surface of the second mask material layer is exposed.

12. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming several of the first core mold structures includes: forming a first core mold material layer on the surface of the second mask material layer; forming several separate second core mold structures on the surface of the first core mold material layer; forming a second side wall on the side wall surface of each of the second core mold structures; and etching the first core mold material layer using the second side wall as a mask until the surface of the second mask material layer is exposed.

13. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the first sidewall includes: forming a first sidewall material layer on the surface of the second mask material layer and the surfaces of several of the first core mold structures; etching back the first sidewall material layer until the surface of the second mask material layer and the top surface of the first core mold structure are exposed.

14. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the first fin structure and the first isolated fin structure, removing the first isolated fin structure.

15. The method for forming a semiconductor structure according to claim 14, wherein: The material of the stress layer contains germanium atoms, and the stress layer has a first atomic percentage concentration, where the first atomic percentage concentration is the atomic percentage concentration of germanium atoms in the material of the stress layer; The method for forming the semiconductor structure also includes: removing the first isolation fin structure, and before removing the first isolation fin structure, forming a first source-drain doping layer in the first fin structure, the material of the first source-drain doping layer contains germanium atoms, the first source-drain doping layer has a second atomic percentage concentration, the second atomic percentage concentration is the atomic percentage concentration of germanium atoms in the material of the first source-drain doping layer, and the second atomic percentage concentration is more than twice the first atomic percentage concentration.

16. The method for forming a semiconductor structure according to claim 15, wherein: The method for removing the first isolation fin structure includes: forming a first dielectric structure on the first fin structure, the first isolation fin structure and the substrate surface.

17. The method for forming a semiconductor structure according to claim 16, wherein: The first dielectric structure includes a first dielectric layer located on the substrate surface, the sidewall surface of the first fin structure and the sidewall surface of the first isolation fin structure, and a second dielectric layer located on the surface of the first dielectric layer, wherein the surface of the second dielectric layer is higher than the top surface of the first fin structure.

18. The method for forming a semiconductor structure according to claim 17, wherein: Also includes: Before removing the first isolation fin structure, forming a gate opening across the first fin structure and the first isolation fin structure in the first dielectric structure, wherein the gate opening exposes the surfaces of the first fin structure and the first isolation fin structure; A gate structure is formed in the gate opening, and the first source-drain doped layer is located in the first fin structure on both sides of the gate structure.

19. The method for forming a semiconductor structure according to claim 18, wherein: The method for removing the first isolation fin structure also includes: forming a fifth mask structure on the surface of the gate structure and the first dielectric structure, the fifth mask structure exposing the surface of the gate structure in the first invalid area; using the fifth mask structure as a mask, etching the gate structure and the first isolation fin structure until the first isolation fin structure is removed.

20. The method for forming a semiconductor structure according to claim 16, wherein: The method for removing the first isolation fin structure also includes: forming a sixth mask structure on the surface of the first dielectric structure, the sixth mask structure exposing the surface of the first dielectric structure in the first invalid area; using the sixth mask structure as a mask, etching the first dielectric structure and the first isolation fin structure until the first isolation fin structure is removed.

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