Method for manufacturing a semiconductor chip and mask-integrated surface protection tape for the manufacturing method

Abstract

The present invention relates to a method for manufacturing a semiconductor chip and a mask-integrated surface protection tape for use in the manufacturing method. A method for manufacturing a semiconductor chip includes the following steps (a) to (d). (a) A step of grinding the back surface of a semiconductor wafer in a state where a mask-integrated surface protection tape is attached to the pattern surface side of the semiconductor wafer, attaching a wafer fixing tape to the ground back surface, and fixing it using an annular frame; (b) A step of exposing the mask material layer on the surface by peeling off the surface protection tape and then opening the dicing streets of the semiconductor wafer; (c) A plasma cutting step of singulating the semiconductor wafer into chips by plasma irradiation; and (d) An ashing step of removing the above mask material layer by plasma irradiation.

Description

[0001] This application is a divisional application. The Chinese national application number of its original application is 201680008788.8, the filing date is November 7, 2016, and the invention title is "Method for manufacturing a semiconductor chip and mask integrated surface protection tape for the manufacturing method". Technical Field

[0002] The present invention relates to a method for manufacturing a semiconductor chip and a mask integrated surface protection tape for the manufacturing method. Background Art

[0003] Recently, the development of semiconductor chips towards thinner films and smaller chips has been remarkable. In particular, for IC cards with semiconductor IC chips such as memory cards or smart cards, thinning is required, and for devices for driving LEDs and LCDs, smaller chips are required. It is considered that in the future, with the increase in these demands, the demand for thinner films and smaller chips of semiconductor chips will further increase.

[0004] These semiconductor chips can be obtained by thinning a semiconductor wafer to a specified thickness in a back grinding process or an etching process, etc., and then dividing it into individual chips through a dicing process. In this dicing process, a blade dicing method that cuts through a dicing blade is used. In the blade dicing method, the cutting resistance caused by the blade during cutting is directly applied to the semiconductor wafer. Therefore, sometimes due to this cutting resistance, minute defects (chipping) may occur in the semiconductor chip. The occurrence of chipping not only impairs the appearance of the semiconductor chip, but in some cases, chip breakage during picking may occur due to insufficient bending strength, and even the circuit pattern on the chip may be damaged. In addition, in this physical cutting process using a blade, it is impossible to make the width of the kerf (also called a scribeline or a street), which is the interval between chips, narrower than the width of the blade having a thickness. As a result, the number of chips (yield) that can be obtained from one wafer becomes smaller. In addition, there is also a problem that the processing time of the wafer is long.

[0005] In addition to the blade dicing method, various methods are also used in the dicing process. For example, it includes the following DBG (pre-dicing) method. In view of the difficulty of dicing after thinning the wafer, a groove is first formed in the wafer only to a specified thickness, and then grinding is performed while thinning and singulating into chips. According to this method, although the kerf width is the same as that in the blade dicing process, it has the advantage that the bending strength of the chips is improved, thereby suppressing chip breakage.

[0006] In addition, there is a laser cutting method that uses a laser for cutting. According to the laser cutting method, there are also advantages such as a narrow cut width and a dry process. However, there is a problem that the wafer surface is contaminated by the sublimates generated during laser cutting, and sometimes a pretreatment of protecting the wafer surface with a specified liquid protective material is required. In addition, although it is a dry process, a complete dry process has not been achieved. Moreover, compared with the blade cutting method, the laser cutting method can increase the processing speed. However, there is no change when processing one by one on the production line, and it takes time accordingly in the manufacture of extremely small chips.

[0007] In addition, there are methods using a wet process such as a water jet method that cuts with water pressure. In this method, problems may occur in materials that require high suppression of surface contamination, such as MEMS devices or CMOS sensors. In addition, there are limitations in narrowing the cut width, and the yield of the obtained chips is also low.

[0008] In addition, a stealth dicing method is also known, in which a modified layer is formed by a laser in the thickness direction of the wafer, and then expanded and divided into individual chips. This method has the advantages of a zero cut width and dry processing. However, there is a tendency for the bending strength of the chips to decrease due to the thermal history during the formation of the modified layer. In addition, silicon chips may sometimes be generated during expansion and division. Furthermore, collisions with adjacent chips may cause insufficient bending strength.

[0009] In addition, as a method of combining stealth dicing and pre-cutting, there is a method of singulating chips that can handle a narrow scribe width. In this method, a modified layer is formed to a specified thickness before thinning, and then grinding is performed from the back side to simultaneously thin the film and singulate the chips into individual ones. This technology can improve the disadvantages of the above processes. In the back grinding process of the wafer, the modified layer of silicon is split by stress to singulate the chips. Therefore, it has the advantages of a zero cut width, a high chip yield, and an improved bending strength. However, since singulation is performed during back grinding, there may sometimes be a phenomenon in which the chip end face collides with adjacent chips, resulting in chip corner defects.

[0010] In addition, a cutting technology based on a plasma cutting method has also been proposed (for example, refer to Patent Document 1). The plasma cutting method is a method of dividing a semiconductor wafer by selectively etching the portions not covered by a mask with a plasma. If this cutting method is used, the chips can be selectively divided, and even if the cutting line is bent, it can be divided without problems. In addition, since the etching rate is very high, it has been regarded as one of the most suitable processes for chip division in recent years.

[0011] Prior Art Documents

[0012] Patent Document

[0013] Patent Document 1: Japanese Patent Laid-Open No. 2007-19385 Summary of the Invention

[0014] Problems to be Solved by the Invention

[0015] In the plasma cutting method, a fluorine-based gas having a very high reactivity with a wafer, such as sulfur hexafluoride (SF6) or carbon tetrafluoride (CF4), is used as a gas for generating plasma. Therefore, the etching rate is high, and it is necessary to protect the unetched surface with a mask.

[0016] In order to form this mask, as described in Patent Document 1, the following technique is generally adopted: after applying a resist to the back surface of the wafer, a portion corresponding to the cutting lane is removed by a photolithography process to form a mask. Therefore, in order to perform plasma cutting, equipment for a photolithography process in addition to the plasma cutting equipment is required, resulting in a problem of an increase in chip cost. In addition, a resist film remains after plasma etching, and thus a large amount of solvent is used to remove the resist. Furthermore, if the resist cannot be sufficiently removed, the resist may form residual glue and cause defective chips. In addition, since a masking process using a resist is performed, there is also a problem of an increase in the overall processing time.

[0017] An object of the present invention is to provide a method for manufacturing a semiconductor chip, which is a method for manufacturing a semiconductor chip using a plasma cutting method, and which does not require a photolithography process, and can more reliably divide (individualize) a wafer into chips by plasma irradiation, and can highly suppress the generation of defective chips.

[0018] In addition, a problem of the present invention is to provide a mask-integrated surface protection tape, which is a mask-integrated surface protection tape that can form a mask without using a photolithography process in the manufacture of a semiconductor chip using a plasma cutting method, and the mask formed on the circuit surface using this mask-integrated surface protection tape exhibits good shielding properties during plasma cutting and can be more reliably removed by ashing. That is, a problem of the present invention is to provide a mask-integrated surface protection tape that can simplify and shorten the manufacturing process of a semiconductor chip implemented by plasma cutting and can highly suppress the generation of defective chips.

[0019] Means for Solving the Problems

[0020] The above problems of the present invention can be achieved by the following means. [1]

[0022] A method for manufacturing a semiconductor chip, which includes the following steps (a) to (d).

[0023] (a) A process of grinding the back surface of a semiconductor wafer in a state where a mask-integrated surface protection tape having a base film, an adhesive layer provided on the base film, and a mask material layer provided on the adhesive layer is adhered to the pattern surface side of the semiconductor wafer, adhering a wafer fixing tape to the ground back surface of the semiconductor wafer, and supporting and fixing it with an annular frame;

[0024] (b) A process of integrally peeling the base film and the adhesive layer from the mask-integrated surface protection tape to expose the mask material layer on the surface, and then cutting a portion corresponding to the scribe line of the semiconductor wafer in the mask material layer with a laser to open the scribe line of the semiconductor wafer;

[0025] (c) A plasma cutting process of singulating the semiconductor wafer into semiconductor chips by irradiating the scribe line with plasma; and

[0026] (d) An ashing process of removing the mask material layer by plasma irradiation. [2]

[0028] The method for manufacturing a semiconductor chip according to [1], wherein at least the adhesive layer in the mask-integrated surface protection tape is a radiation-curable type, and before integrally peeling the base film and the adhesive layer from the mask-integrated surface protection tape to expose the mask material layer on the surface in the process (b), it includes a process of irradiating radiation to cure the adhesive layer. [3]

[0030] The method for manufacturing a semiconductor chip according to [1] or [2], wherein in the process (c), the plasma irradiation is plasma irradiation of a fluorine compound. [4]

[0032] The method for manufacturing a semiconductor chip according to any one of [1] to [3], wherein in the process (d), the plasma irradiation is oxygen plasma irradiation. [5]

[0034] The method for manufacturing a semiconductor chip according to any one of [1] to [4], wherein after the process (d), it includes a process (e) of picking up the semiconductor chip from the wafer fixing tape. [6]

[0036] The method for manufacturing a semiconductor chip according to [5], wherein after the process (e), it includes a process (f) of transferring the picked-up semiconductor chip to a die bonding process. [7]

[0038] A mask-integrated surface protection tape, which is a mask-integrated surface protection tape used in a method for manufacturing a semiconductor chip including the following steps (a) to (d). The mask-integrated surface protection tape is a mask-integrated surface protection tape in which an adhesive layer and a mask material layer are sequentially formed on a base film. The etching rate of the mask material layer using SF6 plasma is lower than the etching rate using O2 plasma.

[0039] (a) A step of grinding the back surface of the semiconductor wafer in a state where the mask-integrated surface protection tape is attached to the pattern surface side of the semiconductor wafer, attaching a wafer fixing tape to the ground back surface of the semiconductor wafer, and supporting and fixing it using an annular frame;

[0040] (b) A step of integrally peeling the base film and the adhesive layer from the mask-integrated surface protection tape to expose the mask material layer on the surface, and then cutting the portion of the mask material layer corresponding to the dicing streets of the semiconductor wafer using a laser to open the dicing streets of the semiconductor wafer;

[0041] (c) A plasma cutting step of dividing the semiconductor wafer into individual semiconductor chips by irradiating with plasma through the dicing streets; and

[0042] (d) An ashing step of removing the mask material layer by irradiating with plasma. [8]

[0044] The mask-integrated surface protection tape according to [7], wherein, for the mask material layer, the etching rate (E O2 ) using the above O2 plasma relative to the etching rate (E F ) using the above SF6 plasma, the ratio (E O2 / E F ) is 2.0 or more. [9]

[0046] The mask-integrated surface protection tape according to [7] or [8], wherein the light transmittance of the mask material layer at a wavelength of 10 μm is 80% or less, and the visible light transmittance at a wavelength of 350 nm to 700 nm is 50% or more.

[10]

[0048] The mask-integrated surface protection tape according to any one of [7] to [9], wherein the mask material layer contains an acrylate compound having one or two photopolymerizable carbon-carbon double bonds in the molecule, and the content of the acrylate compound is 15% by mass or more.

[0049] Effects of the invention

[0050] The method for manufacturing a semiconductor chip according to the present invention can perform plasma cutting using a simpler process without a lithography process. In addition, the method for manufacturing a semiconductor chip according to the present invention can more reliably divide a wafer into chips by plasma irradiation, and can highly suppress the generation of defective chips.

[0051] The mask-integrated surface protection tape of the present invention is a surface protection tape that can form a mask without using a lithography process in the manufacture of semiconductor chips using a plasma cutting method. The mask-integrated surface protection tape of the present invention can simplify the mask formation process on the circuit surface. In addition, the mask formed on the circuit surface exhibits good shielding properties during plasma cutting and can be more reliably removed by ashing. Therefore, the mask-integrated surface protection tape of the present invention can simplify and shorten the semiconductor chip manufacturing process, and can also highly suppress the generation of defective chips.

[0052] The above and other features and advantages of the present invention will be further clarified by the following description with appropriate reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 It is a schematic cross-sectional view illustrating the steps up to attaching a surface protection tape to a semiconductor wafer in the first embodiment of the present invention. Figure 1 (a) shows a semiconductor wafer, Figure 1 (b) shows the case of attaching a mask-integrated surface protection tape, Figure 1 (c) shows a semiconductor wafer to which a mask-integrated surface protection tape is attached.

[0054] Figure 2 It is a schematic cross-sectional view illustrating the steps up to thinning and fixing a semiconductor wafer in the first embodiment of the present invention. Figure 2 (a) shows the thinning process of a semiconductor wafer, Figure 2 (b) shows the case of attaching a wafer fixing tape, Figure 2 (c) shows the state of fixing a semiconductor wafer to an annular frame.

[0055] Figure 3 It is a schematic cross-sectional view illustrating the steps up to forming a mask in the first embodiment of the present invention. Figure 3 (a) shows the case of peeling off the surface protection tape from the mask-integrated surface protection tape leaving a mask material layer, Figure 3 (b) shows the state in which the mask material layer of the mask-integrated surface protection tape is exposed, Figure 3 (c) shows the step of excising the mask material layer corresponding to a dicing street using a laser.

[0056] Figure 4It is a schematic cross-sectional view showing the processes of plasma cutting and plasma ashing in the first embodiment of the present invention, and it is divided into Figure 4 (a) shows the case of performing plasma cutting, and it is divided into Figure 4 (b) shows the state of being singulated into chips, and it is divided into Figure 4 (c) shows the case of performing plasma ashing.

[0057] Figure 5 It is a schematic cross-sectional view showing the processes up to picking up chips in the first embodiment of the present invention, and it is divided into Figure 5 (a) shows the state after removing the mask material layer, and it is divided into Figure 5 (b) shows the case of picking up chips.

[0058] Figure 6 It is a schematic cross-sectional view showing the states before and after performing ultraviolet irradiation treatment in the second embodiment of the present invention, and it is divided into Figure 6 (a) shows the state where the front and back surfaces of a semiconductor wafer are respectively covered and fixed with a mask-integrated surface protection tape and a wafer fixing tape, and it is divided into Figure 6 (b) shows the case of irradiating ultraviolet rays, and it is divided into Figure 6 (c) shows the case of peeling off the surface protection tape from the mask-integrated surface protection tape while leaving the mask material layer. Detailed Embodiments

[0059] [Method for Manufacturing Semiconductor Chip of the Present Invention]

[0060] The method for manufacturing a semiconductor chip of the present invention (hereinafter simply referred to as "the manufacturing method of the present invention") is a method for obtaining semiconductor chips by performing plasma cutting on a semiconductor wafer. As will be described below, the manufacturing method of the present invention does not require a lithography process and can greatly suppress the manufacturing cost of semiconductor chips or semiconductor products.

[0061] The manufacturing method of the present invention at least includes the following steps (a) to (d).

[0062] (a) A step of grinding the back surface of the semiconductor wafer in a state where a mask-integrated surface protection tape having a base film, an adhesive layer provided on the base film, and a mask material layer provided on the adhesive layer is attached to the pattern surface side of the semiconductor wafer, attaching a wafer fixing tape to the ground back surface of the semiconductor wafer, and supporting and fixing it with a ring frame;

[0063] (b) A step of integrally peeling the base film and the adhesive layer from the above-mentioned mask-integrated surface protection tape (i.e., peeling the surface protection tape from the mask-integrated surface protection tape) to expose the mask material layer on the surface, and then cutting the portion corresponding to the dicing street of the semiconductor wafer in the mask material layer by using a laser to open the dicing street of the semiconductor wafer;

[0064] (c) A plasma cutting step of singulating the semiconductor wafer into semiconductor chips by irradiating the plasma to divide the semiconductor wafer through the above-mentioned dicing street; and

[0065] (d) An ashing step of removing the above-mentioned mask material layer by irradiating the plasma.

[0066] The manufacturing method of the present invention preferably includes the following step (e) after step (d). In addition, when the manufacturing method of the present invention includes the following step (e), it preferably further includes the following step (f) after this step (e).

[0067] (e) A step of picking up the semiconductor chip from the wafer fixing tape

[0068] (f) A step of transferring the picked-up semiconductor chip to the die bonding process

[0069] The mask-integrated surface protection tape used in the present invention has a base film, an adhesive layer provided on the base film, and a mask material layer provided on the adhesive layer. In this specification, the laminate composed of the base film and the adhesive layer provided on the base film is sometimes referred to as the "surface protection tape". That is, the mask-integrated surface protection tape used in the present invention is a tape having a laminated structure in which a mask material layer is further provided on the adhesive layer of the surface protection tape. In the mask-integrated surface protection tape used in the present invention, the base film, the adhesive layer, and the mask material layer may be a single-layer structure or a multi-layer structure of two or more layers. The adhesive layer and the mask material layer are preferably a single-layer structure.

[0070] The mask-integrated surface protection tape used in the present invention preferably has at least the adhesive layer being radiation-curable (i.e., having the property of being cured by radiation irradiation), and more preferably only the adhesive layer being radiation-curable. In addition, the mask material layer is preferably pressure-sensitive.

[0071] When the adhesive layer is radiation-curable, it is preferably to include a step of irradiating radiation to cure the adhesive layer before integrally peeling the base film and the adhesive layer from the above-mentioned mask-integrated surface protection tape to expose the mask material layer on the surface in the above step (b). By curing the adhesive layer, the interlayer peelability between the mask material layer and the adhesive layer is improved, and it is easy to peel the surface protection tape from the mask-integrated surface protection tape.

[0072] Next, a preferred embodiment of the manufacturing method of the present invention will be described with reference to the accompanying drawings. However, except for the matters specified in the present invention, the present invention is not limited to the following embodiments. In addition, the forms shown in the respective drawings are schematic diagrams for easily understanding the present invention. Regarding the dimensions, thicknesses, or relative size relationships of the respective components, the sizes are sometimes changed for the sake of explanation and do not directly show the actual relationships. In addition, except for the matters specified in the present invention, the outer shapes and forms shown in these drawings are not limited thereto.

[0073] Preferred embodiments of the manufacturing method of the semiconductor chip of the present invention can be classified into the following first and second embodiments.

[0074] It should be noted that regarding the devices and materials used in the following embodiments, as long as there is no special statement, the usual devices and materials used for semiconductor wafer processing can be used, and their usage conditions can also be appropriately set and optimized within the range of the usual usage methods according to the purpose. In addition, repeated descriptions of the common materials, structures, methods, effects, etc. in each embodiment are omitted.

[0075] <First Embodiment Figures 1 to 5 >

[0076] Refer to Figures 1 to 5 , and the first embodiment of the manufacturing method of the present invention will be described.

[0077] The semiconductor wafer 1 has a pattern surface 2 (refer to Figure 1 (a)) on which a circuit or the like of a semiconductor element is formed on its surface S. A mask-integrated surface protection tape 3 is bonded to the pattern surface 2. The mask-integrated surface protection tape 3 further has a mask material layer 3b provided on the adhesive layer 3ab of the surface protection tape 3a provided with the adhesive layer 3ab on the base material film 3aa (refer to Figure 1 (b)), thereby obtaining a semiconductor wafer 1 in which the pattern surface 2 is covered with the mask-integrated surface protection tape 3 (refer to Figure 1 (c)).

[0078] Next, the back surface B of the semiconductor wafer 1 is ground using a wafer grinding device M1 to reduce the thickness of the semiconductor wafer 1 (refer to Figure 2 (a)). A wafer fixing tape 4 is bonded to the ground back surface B (refer to Figure 2 (b)), and it is supported and fixed to a ring frame F (refer to Figure 2 (c)).

[0079] The surface protection tape 3a of the mask-integrated surface protection tape 3 is peeled off from the semiconductor wafer 1, and its mask material layer 3b remains on the semiconductor wafer 1 (refer to Figure 3 (a)), and the mask material layer 3b is peeled out (refer to Figure 3(b)). Further, CO2 laser L is irradiated from the surface S side to a plurality of scribing lanes (not shown) appropriately formed in a lattice pattern or the like on the pattern surface 2, and the portion of the mask material layer 3b corresponding to the scribing lanes is removed to open the scribing lanes of the semiconductor wafer (see Figure 3 (c)).

[0080] Next, the semiconductor wafer 1 exposed in the scribing lane portion is etched by processing with the plasma P1 of SF6 gas from the surface S side (see Figure 4 (a)), and it is divided into individual chips 7 (see Figure 4 (b)). Next, ashing is performed by the plasma P2 of O2 gas (see Figure 4 (c)), and the mask material layer 3b remaining on the surface S is removed (see Figure 5 (a)). And finally, the singulated chip 7 is pushed out by the pin M2 and picked up by adsorption with an elastic collet M3 (see Figure 5 (b)).

[0081] Here, the etching process of Si of the semiconductor wafer using SF6 gas is also called the BOSCH process, which reacts the exposed Si with the F atoms generated by plasmaizing SF6 and removes it as silicon tetrafluoride (SiF4), and is also called reactive ion etching (RIE). On the other hand, the removal using O2 plasma is also a method used as a plasma cleaner in the semiconductor manufacturing process, which is also called ashing, and it is one of the methods for removing organic substances. It is performed to clean the organic residue remaining on the surface of the semiconductor device.

[0082] Next, before describing the second embodiment, the materials used in the manufacturing method of the present invention will be described. These materials can also be preferably used in the following second embodiment.

[0083] The semiconductor wafer 1 is a silicon wafer or the like having a pattern surface 2 formed with a circuit or the like of semiconductor elements on one side. The pattern surface 2 is the surface formed with a circuit or the like of semiconductor elements, and has scribing lanes when viewed from above.

[0084] The mask-integrated surface protection tape 3 is configured such that an adhesive layer 3ab is provided on a base material film 3aa, and further a mask material layer is provided on the adhesive layer 3ab, and has the function of protecting the semiconductor element formed on the pattern surface 2. That is, in the subsequent wafer thinning process, the semiconductor wafer 1 is supported by the pattern surface 2 and the back surface of the wafer is ground, so it is necessary to withstand the load during the grinding. Therefore, different from a simple resist film or the like, the mask-integrated surface protection tape 3 has a thickness that only covers the elements formed on the pattern surface, has a low pressing resistance, and closely adheres to the elements as much as possible in such a way that dust or grinding water during grinding does not penetrate, and has a high adhesion.

[0085] In the mask-integrated surface protection tape 3, the base material film 3aa is made of plastic, rubber, or the like. Examples of its material include homopolymers or copolymers of α-olefins such as polyethylene, polypropylene, ethylene-propylene copolymer, poly-1-butene, poly-4-methyl-1-pentene, ethylene-vinyl acetate copolymer, ethylene-acrylic acid copolymer, ionomer, or mixtures thereof, polyethylene terephthalate, polyethylene naphthalate, polyphenylene sulfide, polyetherimide, polyimide, polycarbonate, polymethyl methacrylate, polyurethane, styrene-ethylene-butene or pentene-based copolymer, etc., single components or components mixed with two or more of these, and resin compositions in which resins, filler materials, additives, etc. other than these are mixed therein. They can be appropriately selected according to the required characteristics. A laminate of low-density polyethylene and ethylene-vinyl acetate copolymer, or a laminate of polypropylene and polyethylene terephthalate, polyethylene terephthalate, and polyethylene naphthalate are one of the preferred materials.

[0086] These base material films 3aa can be manufactured using a general extrusion method. In the case of obtaining the base material film 3aa by laminating various resins, they are manufactured using a co-extrusion method, a lamination method, or the like. At this time, a bonding layer can also be provided between the resins as is usually done in the manufacturing method of a normal laminated film. Regarding the thickness of such a base material film 3aa, from the viewpoints of characteristics such as strength and elongation, and radiation permeability, it is preferably 20 μm to 200 μm.

[0087] The adhesive layer 3ab, together with the mask material, serves to absorb the unevenness of the elements formed on the pattern surface to improve the adhesion to the pattern surface, thereby protecting the pattern surface. In order for the mask-integrated surface protection tape to withstand the load of the wafer thinning process (back grinding process), the adhesive layer 3ab preferably has a high adhesion to the mask material layer 3b or the base film 3aa during the wafer thinning process. On the other hand, after the wafer thinning process, in order to be integrated with the base film 3aa and peel off from the mask material layer, it is preferably to have a low adhesion to the mask material layer (preferably high peelability). In order to achieve this property at a higher level, it is preferable to use a radiation-curable adhesive in the adhesive layer 3ab. By making the adhesive layer 3ab a radiation-curable adhesive layer, the adhesive layer is three-dimensionally crosslinked by irradiation with radiation, and the adhesive force is reduced. Therefore, by irradiating radiation after the wafer thinning process, the strong adhesion to the mask material layer is released, and it can be easily peeled off from the mask material layer (this specific embodiment will be described later). In the case where the adhesive layer 3ab is a radiation-curable adhesive layer, the manufacturing method of the present invention is preferably the following second embodiment. It should be noted that the adhesive layer 3ab in the present invention is not limited to a radiation-curable adhesive, and a non-radiation-curable adhesive (pressure-sensitive adhesive) can also be used within the range of having the desired properties. In this case, the manufacturing method of the present invention is preferably the above first embodiment.

[0088] In this specification, the term "radiation" is used to include both light such as ultraviolet rays and ionizing radiation such as electron rays. The radiation used in the present invention is preferably ultraviolet rays.

[0089] When the adhesive layer 3ab is composed of a radiation-curable adhesive, an adhesive containing an acrylic adhesive and a radiation-polymerizable compound can be preferably used.

[0090] The acrylic adhesive is a (meth)acrylic copolymer or a mixture of a (meth)acrylic copolymer and a curing agent. Examples of the (meth)acrylic copolymer include a copolymer having (meth)acrylate as a constituent component, or a mixture of two or more copolymers having (meth)acrylate as a constituent component. The weight-average molecular weight of these copolymers is usually about 300,000 to 1,000,000. In all monomer components of the (meth)acrylic copolymer, the proportion of the (meth)acrylate component is preferably 70 mol% or more, more preferably 80 mol% or more, and further preferably 90 mol% or more. In addition, when the proportion of the (meth)acrylate component in the monomer components of the (meth)acrylic copolymer is not 100 mol%, the remaining monomer components are preferably monomer components present in a form polymerized with a (meth)acryloyl group as a polymerizable group (constituent components from (meth)acrylic acid, etc.). In addition, in all monomer components of the (meth)acrylic copolymer, the proportion of the (meth)acrylate component having a functional group (such as a hydroxyl group) that reacts with the following curing agent is preferably 1 mol% or more, more preferably 2 mol% or more, further preferably 5 mol% or more, and more preferably 10 mol% or more. In addition, the proportion of this (meth)acrylate component is preferably 35 mol% or less, more preferably 25 mol% or less. In addition, in all monomer components of the (meth)acrylic copolymer, the proportion of the constituent component (monomer component) having a functional group (such as a hydroxyl group) that reacts with the following curing agent is preferably 5 mol% or more, more preferably 10 mol% or more. The upper limit value of this proportion is preferably 35 mol% or less, more preferably 25 mol% or less.

[0091] The above (meth)acrylate component is preferably an alkyl (meth)acrylate (also referred to as alkyl (meth)acrylate). The number of carbon atoms of the alkyl group constituting the alkyl (meth)acrylate is preferably 1 to 20, more preferably 1 to 15, and further preferably 1 to 12.

[0092] The curing agent is used to react with the functional groups of the (meth)acrylic copolymer to adjust the adhesive force and cohesive force. Examples thereof include epoxy compounds having two or more epoxy groups in the molecule, such as 1,3-bis(N,N-diglycidylaminomethyl)cyclohexane, 1,3-bis(N,N-diglycidylaminomethyl)toluene, 1,3-bis(N,N-diglycidylaminomethyl)benzene, and N,N,N,N'-tetraglycidyl-m-xylenediamine; isocyanate compounds having two or more isocyanate groups in the molecule, such as 2,4-toluene diisocyanate, 2,6-toluene diisocyanate, 1,3-benzenedimethylene diisocyanate, 1,4-benzenedimethylene diisocyanate, and diphenylmethane-4,4'-diisocyanate; aziridine compounds having two or more aziridine groups in the molecule, such as tetramethylol-tris-β-aziridinyl propionate, trimethylol-tris-β-aziridinyl propionate, trimethylolpropane-tris-β-aziridinyl propionate, and trimethylolpropane-tris-β-(2-methylaziridinyl)propionate. The addition amount of the curing agent can be adjusted according to the desired adhesive force, and 0.1 to 5.0 parts by mass is appropriate relative to 100 parts by mass of the (meth)acrylic copolymer. In the adhesive layer of the mask-integrated surface protection tape used in the present invention, the curing agent is in a state of reacting with the (meth)acrylic copolymer.

[0093] As the above radiation-polymerizable compound, a low-molecular-weight compound having at least two or more photopolymerizable carbon-carbon double bonds in the molecule, which can be three-dimensionally crosslinked by irradiation with radiation, is widely used. Specifically, acrylate compounds such as trimethylolpropane triacrylate, pentaerythritol tetraacrylate, pentaerythritol triacrylate, dipentaerythritol monohydroxy pentaacrylate, dipentaerythritol hexaacrylate, 1,4-butanediol diacrylate, 1,6-hexanediol diacrylate, polyethylene glycol diacrylate, and low-polyester acrylate can be widely used.

[0094] In addition to the above acrylate compounds, urethane acrylate oligomers can also be used. The urethane acrylate oligomer is obtained by reacting an acrylate or methacrylate having a hydroxyl group (for example, 2-hydroxyethyl acrylate, 2-hydroxyethyl methacrylate, 2-hydroxypropyl acrylate, 2-hydroxypropyl methacrylate, polyethylene glycol acrylate, polyethylene glycol methacrylate, etc.) with a terminal isocyanate urethane prepolymer, and the terminal isocyanate urethane prepolymer is obtained by reacting a polyol compound such as a polyester type or a polyether type with a polyisocyanate compound (for example, 2,4-toluene diisocyanate, 2,6-toluene diisocyanate, 1,3-benzenedimethylene diisocyanate, 1,4-benzenedimethylene diisocyanate, diphenylmethane 4,4-diisocyanate, etc.).

[0095] As the mixing ratio of the acrylic adhesive and the radiation-polymerizable compound in the radiation-curable adhesive, it is preferable to mix the radiation-polymerizable compound in the range of 50 parts by mass to 200 parts by mass, preferably 50 parts by mass to 150 parts by mass, relative to 100 parts by mass of the acrylic adhesive. When within this mixing ratio range, the adhesive force of the adhesive layer can be significantly reduced after irradiation with radiation.

[0096] In addition, as the radiation-curable adhesive used in the adhesive layer 3ab, it is also preferable to use a radiation-polymerizable (meth)acrylic copolymer in which the above-mentioned (meth)acrylic copolymer itself is radiation-polymerizable. In this case, the radiation-curable adhesive may also contain a curing agent.

[0097] The radiation-polymerizable (meth)acrylic copolymer is a copolymer having a reactive group in the molecule of the copolymer that can undergo a polymerization reaction by irradiation with radiation, particularly ultraviolet irradiation. As such a reactive group, a group having an ethylenically unsaturated group, that is, a carbon-carbon double bond, is preferable. Examples of such a group include vinyl, allyl, styryl, (meth)acryloyloxy, (meth)acryloylamino, and the like.

[0098] The introduction of the above-mentioned reactive group into the copolymer can be carried out, for example, by reacting a copolymer having a hydroxyl group and a compound having a group reactive with the hydroxyl group (such as an isocyanate group) and having the above-mentioned reactive group [representatively 2-(meth)acryloyloxyethyl isocyanate].

[0099] In addition, in all the monomer components constituting the above-mentioned radiation-polymerizable (meth)acrylic copolymer, the proportion of the monomer component having the above-mentioned reactive group is preferably 2 mol% to 40 mol%, more preferably 5 mol% to 30 mol%, and still more preferably 10 mol% to 30 mol%.

[0100] In addition, when the adhesive layer 3ab is polymerized and cured by radiation, a photoinitiator such as isopropylbenzyl ether, isobutylbenzyl ether, benzophenone, Michler's ketone, chlorothioxanthone, benzyl methyl ketal, α-hydroxycyclohexyl phenyl ketone, 2-hydroxy-2-methylpropiophenone, etc. can be used. By adding at least one of these to the adhesive layer, the polymerization reaction can be carried out efficiently.

[0101] The above-mentioned adhesive layer 3ab may further contain a photosensitizer, a tackifier known in the art, a softener, an antioxidant, and the like.

[0102] As the above-mentioned adhesive layer 3ab, it is also preferable to adopt the form described in paragraphs 0036 to 0055 of Japanese Unexamined Patent Application Publication No. 2014-192204.

[0103] Regarding the thickness of the adhesive layer 3ab, from the aspect of further improving the protection ability of elements formed on the pattern surface 2, further improving the adhesion to the pattern surface, and further improving the removability based on ashing treatment, it is preferably 5 μm to 100 μm, more preferably 10 μm to 100 μm, and still more preferably 2 μm to 50 μm. It should be noted that although it also depends on the type of device, the unevenness of the pattern surface is approximately several μm to about 15 μm, so the thickness of the adhesive layer 3ab is more preferably 5 μm to 30 μm.

[0104] For the mask material layer 3b, it is preferable to use a so-called pressure-sensitive adhesive that is non-radiation curable. As this pressure-sensitive adhesive, a mixture of the above-mentioned (meth)acrylic copolymer and a curing agent can be preferably used.

[0105] In addition, the mask material layer preferably has the following etching rate characteristics. In this case, it is also preferable to use a radiation curable adhesive as the mask material layer 3b.

[0106] Regarding the thickness of the mask material layer 3b, from the aspects of followability to the pattern surface and removability using plasma, it is preferably 1 μm to 50 μm, more preferably 5 μm to 20 μm.

[0107] The wafer fixing tape 4 holds the semiconductor wafer 1 and needs to have plasma resistance that can withstand even when exposed to the plasma cutting process. In addition, it needs to have good pick-up properties in the pick-up process, and may also need to have expandability, etc. depending on the situation. Such a wafer fixing tape 4 can use the same tape as the above-mentioned surface protection tape 3a. In addition, a known dicing tape used in existing plasma cutting methods, which is generally called a dicing tape, can be used. In addition, in order to facilitate the transfer from the pick-up to the die bonding process, a dicing-die bonding tape in which a die bonding adhesive is laminated between the adhesive layer and the base film can also be used.

[0108] In the laser irradiation for cutting the mask material layer 3b, a laser irradiation device that irradiates ultraviolet or infrared laser can be used. This laser irradiation device is provided with a laser irradiation unit that can move freely along the dicing lane of the semiconductor wafer 1 and can irradiate laser with an output power appropriately controlled to remove the mask material layer 3b. Among them, a CO2 laser can obtain a large output power of several W to several tens of W and can be preferably used in the present invention.

[0109] For plasma cutting and plasma ashing, a plasma etching apparatus can be used. The plasma etching apparatus is a device capable of dry-etching a semiconductor wafer 1. A sealed processing space is formed in a vacuum chamber. The semiconductor wafer 1 is placed on a high-frequency side electrode, and a gas for generating plasma is supplied from the side of a gas supply electrode disposed opposite to the high-frequency side electrode. When a high-frequency voltage is applied to the high-frequency side electrode, plasma is generated between the gas supply electrode and the high-frequency side electrode, and thus these plasmas are utilized. A refrigerant is circulated in the heat-generating high-frequency electrode to prevent the semiconductor wafer 1 from being heated due to the heat of the plasma.

[0110] According to the above-described method for manufacturing a semiconductor chip (method for processing a semiconductor wafer), by making the surface protection tape on the surface of the protection pattern have a mask function in plasma cutting, there is no need for a photolithography process or the like for setting a resist used in an existing plasma cutting process. In particular, since the surface protection tape is used, there is no need for highly accurate position alignment techniques such as printing or transfer in the formation of the mask, and it can be simply attached to the surface of the semiconductor wafer, and a mask can be simply formed by a laser device.

[0111] In addition, since the mask material layer 3b can be removed by using O2 plasma, the mask portion can be removed by the same device as the device for performing plasma cutting. Further, since plasma cutting is performed from the side of the pattern surface 2 (surface S side), it is not necessary to invert the chip up and down before the pick-up operation. For these reasons, the equipment can be simplified and the process cost can be significantly reduced.

[0112] <Second Embodiment Figure 6 >

[0113] In the second embodiment, the difference from the first embodiment is that, before the step of peeling the surface protection tape 3a in the first embodiment, there is a step of irradiating the mask-integrated surface protection tape 3 with radiation such as ultraviolet rays to cure the adhesive layer. Other steps are the same as those in the first embodiment.

[0114] That is, the mask-integrated surface protection tape 3 is attached to the surface S side of the semiconductor wafer 1, and the wafer fixing tape 4 is attached to the ground back surface B side of the semiconductor wafer 1 and supported and fixed to the annular frame F (see Figure 2 (c), Figure 6 (a)), and then ultraviolet rays UV are irradiated from the surface S side to the mask-integrated surface protection tape 3 (see Figure 6 (b)). After the adhesive layer 3ab of the mask-integrated surface protection tape 3 is cured, the surface protection tape 3a is removed (see Figure 6 (c)) to expose the adhesive layer 3b. Then, it is transferred to the step of cutting the mask material layer 3b corresponding to the dicing street by using the laser L.

[0115] The mask-integrated surface protection tape used in the second embodiment is a mask-integrated surface protection tape in which the material that can be cured by radiation such as ultraviolet rays is used for the adhesive layer 3ab in the mask-integrated surface protection tape 3 shown in the first embodiment.

[0116] By curing the adhesive layer 3ab using ultraviolet rays or the like, the peeling of the surface protection tape 3a from the mask material layer 3b becomes easy.

[0117] Next, an embodiment of the mask-integrated surface protection tape preferably used in the manufacturing method of the present invention (hereinafter also referred to as "the mask-integrated surface protection tape of the present invention") will be described in detail. However, the mask-integrated surface protection tape used in the manufacturing method of the present invention is not limited to the following embodiment, and the mask-integrated surface protection tape in the manner described above can be widely used.

[0118] <Mask-integrated surface protection tape of the present invention>

[0119] The mask-integrated surface protection tape 3 of the present invention is a tape in which a mask material layer 3b is further formed on the adhesive layer 3ab of the surface protection tape 3a having an adhesive layer 3ab formed on a base material film 3aa. The etching rate (E F ) of the mask material layer 3b using SF6 plasma is lower than the etching rate (E O2 ) using O2 plasma.

[0120] In the mask-integrated surface protection tape of the present invention, the base material film, the adhesive layer, and the mask material layer may be of a single-layer structure or a multi-layer structure of two or more layers. The adhesive layer and the mask material layer are preferably of a single-layer structure. In the mask-integrated surface protection tape of the present invention, the constitution of the base material film and the adhesive layer can be applied in the manner described in the manufacturing method of the present invention above. The constitution of the mask material layer of the mask-integrated surface protection tape of the present invention will be described below.

[0121] (Mask material layer 3b)

[0122] In the mask-integrated surface protection tape of the present invention, the mask material layer 3b is not likely to damage semiconductor elements or the like when being attached to the pattern surface 2, and is not likely to cause breakage of semiconductor elements or the like or the residue of the adhesive on the surface when being removed. Further, in the present invention, for the mask material layer 3b, the etching rate (E F ) using SF6 plasma is lower than the etching rate (E O2 ) using O2 plasma. Therefore, the mask formed on the circuit surface has plasma resistance to function as a mask during plasma cutting, and the formed mask can be more reliably removed by ashing.

[0123] In the mask-integrated surface protection tape of the present invention, as described in the examples, the etching rate (E F ) of the mask material layer using SF6 plasma is the etching rate of the mask material layer under the condition of etching a Si wafer with SF6 gas plasma at an etching rate of 15 μm / minute.

[0124] In addition, in the mask-integrated surface protection tape of the present invention, the etching rate (E O2 ) of the mask material layer using O2 plasma is the etching rate of the mask material layer under the condition of etching the mask material layer a with O2 gas plasma at an etching rate of 1 μm / minute as described in the examples.

[0125] Furthermore, in the mask-integrated surface protection tape of the present invention, the ratio E O2 of the etching rate (E F ) using O2 plasma to the etching rate (E O2 ) using SF6 plasma, i.e., E F / E 10μm is preferably 2.0 or more, more preferably 4.0 or more, and further preferably 6.0 or more. There is no particular limitation on the upper limit value, but it is actually 8.0 or less.

[0126]

[0127] It should be noted that in the case where the mask material layer is a radiation-polymerizable mask material, the above etching rate refers to the etching rate of the radiation-polymerized mask material layer.

[0128] In addition, in the mask-integrated surface protection tape of the present invention, the light transmittance (hereinafter also referred to as the light transmittance 350-700μm ) of the mask material layer 3b at a wavelength of 10 μm is preferably 80% or less, and the visible light transmittance (hereinafter also referred to as the visible light transmittance 10μm ) at a wavelength of 350 nm to 700 nm is preferably 50% or more.

[0129] The light transmittance 350-700μm is more preferably 79% or less, and further preferably 75% or less. There is no particular limitation on the lower limit value, but it is actually 30% or more.

[0130]

[0131] By making the light transmittance 10μm within the above preferred range, it is possible to efficiently cut the portion corresponding to the dicing street of the semiconductor wafer in the mask material layer using a CO2 laser.​In addition, by making the visible light transmittance 350-700μm fall within the above-preferred range, the pattern surface 2 of the semiconductor wafer can be appropriately recognized, and misrecognition during the opening of the scribe lane can be prevented.

[0132] The above light transmittance is measured by the method described in the following examples.

[0133] In addition, the mask-integrated surface protection tape 3 of the present invention has the function of protecting the pattern surface 2. That is, in the subsequent wafer thinning process, the semiconductor wafer 1 is supported by the pattern surface 2 and the back surface of the wafer is ground, so it needs to withstand the load during the grinding. Therefore, different from a simple resist film or the like, the mask-integrated surface protection tape 3 of the present invention has a thickness that only covers the elements formed on the pattern surface, has a low pressing resistance, and can closely adhere to the elements in such a way that dust or grinding water during grinding does not penetrate, and has a high adhesion.

[0134] In the mask-integrated surface protection tape of the present invention, the above various properties are required for the mask material layer 3b, so a non-curable mask material having such properties can be used for the mask material layer 3b. In addition, a radiation-polymerizable mask material such as the following ultraviolet-curable type or ionizing radiation-curable type such as electron beam can be used. The ultraviolet-curable mask material preferably forms a three-dimensional network for the mask material layer by radiation, more preferably by ultraviolet irradiation, and does not easily generate residues of the mask material layer by ashing.

[0135] As such a mask material, an acrylic-based adhesive or a mask material containing the acrylic-based adhesive and a radiation-polymerizable compound can be preferably used.

[0136] The above acrylic-based adhesive is a (meth)acrylic-based copolymer or a mixture of a (meth)acrylic-based copolymer and a curing agent, and the acrylic-based adhesive described in the above adhesive layer can be preferably used.

[0137] It should be noted that from the aspect of adhesion, in all monomer components of the (meth)acrylic-based copolymer, the proportion of the (meth)acrylate component having a functional group (such as a hydroxyl group) that reacts with the curing agent is preferably 0.1 mol% or more, more preferably 0.5 mol% or more. The upper limit value is preferably 20 mol% or less, more preferably 15 mol% or less. The mass average molecular weight of the (meth)acrylic-based copolymer is preferably about 100,000 to 1,000,000.

[0138] In the mask-integrated surface protection tape of the present invention, as the mask material layer 3b, a radiation-curable adhesive cured by radiation or a pressure-sensitive adhesive not cured by radiation can be preferably used.

[0139] As the above-mentioned radiation-curable adhesive, an adhesive containing the above-mentioned acrylic adhesive and an acrylate compound having one or two photopolymerizable carbon-carbon double bonds in the molecule is preferred. In the above-mentioned radiation-curable adhesive, the content of the acrylate compound having one or two photopolymerizable carbon-carbon double bonds in the molecule is preferably 15% by mass or more, more preferably 15% by mass to 70% by mass, and still more preferably 15% by mass to 65% by mass. In addition, the acrylate compound having one or two photopolymerizable carbon-carbon double bonds in the molecule is preferably an acrylate compound having one photopolymerizable carbon-carbon double bond in the molecule.

[0140] Specifically, the above-mentioned acrylate compound having one or two photopolymerizable carbon-carbon double bonds in the molecule can be widely applied to 2-hydroxy-3-phenoxypropyl acrylate, 1,4-butanediol diacrylate, 1,6-hexanediol diacrylate, polyethylene glycol diacrylate, etc.

[0141] In addition, a urethane acrylate oligomer having one or two photopolymerizable carbon-carbon double bonds in the molecule can be preferably used, and a urethane acrylate oligomer obtained by the method described in the above-mentioned adhesive layer can be preferably used.

[0142] As the mixing ratio of the acrylic adhesive and the acrylate compound having one or two photopolymerizable carbon-carbon double bonds in the above-mentioned radiation-curable adhesive, relative to 100 parts by mass of the acrylic adhesive, it is preferably mixed with 10 parts by mass to 250 parts by mass, preferably 15 parts by mass to 200 parts by mass of the acrylate compound having one or two photopolymerizable carbon-carbon double bonds in the molecule. If it is below the above upper limit value, the mask material layer will not be excessively deformed during back grinding, and the breakage of the wafer can be more effectively prevented.

[0143] In addition, in the mask-integrated surface protection tape of the present invention, the mask material layer can preferably apply the radiation-polymerizable (meth)acrylate copolymer, photoinitiator and other components (photosensitizer, conventionally known tackifier, softener, antioxidant, etc.) in the above-mentioned adhesive layer.

[0144] In the mask-integrated surface protection tape of the present invention, regarding the thickness of the mask material layer 3b, from the aspects of further improving the protection ability of the elements formed on the pattern surface 2, further improving the adhesion to the pattern surface to prevent the intrusion of SF6 gas, and further improving the removability of ashing treatment, it is preferably 5 μm to 100 μm, more preferably 5 μm to 30 μm. It should be noted that although it also depends on the type of device, the unevenness of the pattern surface is approximately several μm to 15 μm, so the thickness of the mask material layer 3b is more preferably 5 μm to 30 μm.

[0145] The above-described embodiments are examples of the present invention, and the present invention is not limited to such embodiments. Additions, deletions, changes, etc. of known processes in each process can be made within the scope not violating the gist of the present invention.

[0146] Example

[0147] Hereinafter, the present invention will be described in more detail based on examples, but the present invention is not limited thereto.

[0148] [Reference Example 1] Production of Mask-Integrated Surface Protection Tape - 1

[0149] [Preparation of Surface Protection Tape 3a]

[0150] 2-Isocyanatoethyl methacrylate (MOI, manufactured by Showa Denko K.K.) having an ethylenically unsaturated bond (photo-reactive group) and an isocyanate group in the molecule was reacted with an acrylic polymer (random polymer) composed of constituent components of 80 mol% of 2-ethylhexyl acrylate, 1 mol% of methyl acrylate, and 19 mol% of 2-hydroxyethyl acrylate to obtain an acrylic polymer A1 having an ethylenically unsaturated bond in the molecule (Mw: 800,000, acid value: 12 mgKOH / g, hydroxyl value: 43 mgKOH / g, double bond equivalent: 0.9 eq).

[0151] 2.0 parts by mass of an isocyanate curing agent (trade name: L-45, manufactured by Tosoh Corporation) and 5.0 parts by mass of a photopolymerization initiator (Esacure KIP 100F, manufactured by Lamberti) were blended with respect to 100 parts by mass of the above acrylic polymer A1 to obtain an adhesive composition A.

[0152] LDPE (low density polyethylene) resin (Nipolon Hard 205, manufactured by Tosoh Corporation) and EVA (ethylene-vinyl acetate copolymer) resin (Ultrathene 540, manufactured by Tosoh Corporation) were used to form a film by an extrusion method to a thickness of 110 μm to prepare a two-layer substrate film 3aa.

[0153] The above adhesive composition A was coated on a release film, and the dried adhesive layer was laminated on the EVA layer of the above substrate film 3aa and transferred to form a radiation-curable adhesive layer 3ab with a thickness of 20 μm, thereby obtaining a surface protection tape 3a.

[0154] [Preparation of Mask-Integrated Surface Protection Tape 3]

[0155] Relative to 100 parts by mass of acrylic polymer A2 (random polymer, Mw: 1 million, acid value: 23 mgKOH / g, hydroxyl value: 0 mgKOH / g) composed of constituent components of butyl acrylate: 95 mol% and methyl acrylate: 5 mol% each monomer, 2.0 parts by mass of an epoxy curing agent (Tetrad-C, manufactured by Mitsubishi Gas Chemical) was blended to obtain mask material composition A. Using this mask material composition A, a film was formed on the adhesive layer 3ab side of the above surface protection tape 3a so that the thickness after drying reached 10 μm to form a mask material layer 3b as a pressure-sensitive adhesive layer, and a mask-integrated surface protection tape 3 was obtained.

[0156] [Example 1] Fabrication of Semiconductor Chip - 1

[0157] Using a tape laminating device (trade name: DR-3000II, manufactured by Nitto Seiki Co., Ltd.), the obtained mask-integrated surface protection tape 3 was laminated onto a silicon wafer (8 inches in diameter). Using a back grinding device (trade name: DGP8760, manufactured by DISCO Corporation), the wafer laminated with the mask-integrated surface protection tape 3 was ground to a thickness of 50 μm, and the wafer was visually and microscopically inspected for cracks at this time.

[0158] A UV-curable wafer fixing tape 4 (trade name: UC-353EP-110, manufactured by Furukawa Electric Co., Ltd.) was laminated on the back side of the ground wafer and supported and fixed using a ring frame. Then, ultraviolet rays were irradiated from the mask-integrated surface protection tape 3 side, and then the surface protection tape 3a was peeled off while retaining the mask material layer 3b. CO2 laser was irradiated along the dicing street portion of the silicon wafer from the peeled mask material layer 3b to remove the mask material layer 3b in this portion to open the dicing street portion.

[0159] Then, using SF6 gas as the plasma generation gas, plasma cutting was performed by irradiating plasma from the surface side of the peeled mask material layer 3b at an etching rate of 0.5 μm / minute, thereby cutting the wafer into individual chips. Then, using O2 gas as the plasma generation gas, ashing was performed at an etching rate of 1.0 μm / minute to remove the mask material layer 3b to obtain semiconductor chips.

[0160] [Reference Example 2] Fabrication of Mask-Integrated Surface Protection Tape - 2

[0161] In Reference Example 1, instead of the acrylic polymer A2 used in the mask material composition A, an acrylic polymer B (random polymer, Mw: 350,000, acid value: 23 mgKOH / g, hydroxyl value: 3.6 mgKOH / g) composed of constituent components from each of butyl acrylate: 47 mol%, 2-ethylhexyl acrylate: 47 mol%, methyl acrylate: 5 mol%, and 2-hydroxyethyl acrylate: 1 mol% was used to prepare a mask material composition B. Using this mask material composition B, a mask material layer 3b as a pressure-sensitive adhesive layer was formed, and a mask-integrated surface protection tape was obtained in the same manner as in Reference Example 1 except for this.

[0162] [Example 2] Fabrication of Semiconductor Chip - 2

[0163] In Example 1, as the mask-integrated surface protection tape 3, instead of the mask-integrated surface protection tape fabricated in Reference Example 1, the mask-integrated surface protection tape fabricated in Reference Example 2 was used, and a semiconductor chip was obtained in the same manner as in Example 1 except for this.

[0164] [Reference Example 3] Fabrication of Mask-Integrated Surface Protection Tape - 3

[0165] In Reference Example 1, as the base film 3aa, instead of the base film composed of a two-layer structure of LDPE and EVA, a PET (polyethylene terephthalate) film with a thickness of 50 μm was used, and a mask-integrated surface protection tape was obtained in the same manner as in Reference Example 1 except for this.

[0166] [Example 3] Fabrication of Semiconductor Chip - 3

[0167] In Example 1, as the mask-integrated surface protection tape 3, instead of the mask-integrated surface protection tape fabricated in Reference Example 1, the mask-integrated surface protection tape fabricated in Reference Example 3 was used, and a semiconductor chip was obtained in the same manner as in Example 1 except for this.

[0168] [Reference Example 4] Fabrication of Mask-Integrated Surface Protection Tape - 4

[0169] In Reference Example 1, as the base film 3aa, instead of the base film composed of a two-layer structure of LDPE and EVA, a single-layer film (thickness 100 μm) of EVA resin (Ultrathene 510, manufactured by Tosoh Corporation) was used, and a mask-integrated surface protection tape was obtained in the same manner as in Reference Example 1 except for this.

[0170] [Example 4] Fabrication of Semiconductor Chip - 4

[0171] In Example 1, as the mask-integrated surface protection tape 3, the mask-integrated surface protection tape fabricated in Reference Example 4 was used instead of the mask-integrated surface protection tape fabricated in Reference Example 1, and a semiconductor chip was obtained in the same manner as in Example 1 except for this.

[0172] [Comparative Example 1] Fabrication of Semiconductor Chip - 5

[0173] Using a spin coater, a positive photosensitive material was spin-coated on a silicon wafer (8 inches in diameter) to a thickness of 10 μm to form a resist layer. After exposing the portion of the resist layer that was to become the dicing lines, development was carried out using tetramethylammonium hydroxide to obtain a masked wafer with dicing line openings. The surface protection tape 3a (without a mask material layer) prepared in Reference Example 1 was attached to the mask of the masked wafer.

[0174] Using a back grinding device (trade name: DGP8760, manufactured by DISCO Corporation), the wafer with the surface protection tape attached was ground to a thickness of 50 μm, and the wafer was visually and microscopically inspected for cracks at this time.

[0175] A UV-curable wafer fixing tape 4 (trade name: UC-353EP-110, manufactured by Furukawa Electric Co., Ltd.) was attached to the back side of the ground wafer and supported and fixed using an annular frame. Then, ultraviolet rays were irradiated from the surface protection tape side to remove the surface protection tape while leaving the mask material.

[0176] Then, using SF6 gas as the plasma generation gas, plasma was irradiated from the exposed mask surface side at an etching rate of 0.5 μm / minute for plasma dicing, thereby cutting the wafer into individual chips. Next, using O2 gas as the plasma generation gas, ashing was carried out at an etching rate of 1.0 μm / minute to remove the mask.

[0177] In each of the above Examples and Comparative Examples, grindability, opening property, and plasma adaptability were evaluated according to the following evaluation criteria.

[0178] - Grindability -

[0179] ◎: No cracks were generated in the wafer due to back grinding at all.

[0180] ○: A few cracks were generated in the wafer due to back grinding, but at a level that is not a problem for practical use.

[0181] ×: Cracks were generated in the wafer due to back grinding at a level that poses a problem for practical use.

[0182] - Opening Property -

[0183] ○: The mask on the dicing lines was completely removed by laser irradiation.

[0184] ×: Even with laser irradiation, a mask remains on the cutting line.

[0185] - Plasma adaptability -

[0186] ○: The wafer is completely divided by plasma irradiation using SF6 gas.

[0187] ×: Even with plasma irradiation using SF6 gas, the wafer is not completely divided.

[0188]

Table 1

[0189] Table 1

[0190] Example 1 Example 2 Example 3 Example 4 Comparative Example 1 Substrate film LDPE + EVA (two layers) LDPE + EVA (two layers) PET (one layer) EVA (one layer) LDPE + EVA (two layers) Adhesive layer Adhesive composition A Adhesive composition A Adhesive composition A Adhesive composition A Adhesive composition A Mask material layer Mask material composition A Mask material composition B Mask material composition A Mask material composition A Photo-resist Grindability ◎ 〇 ◎ 〇 〇 Openability 〇 〇 〇 〇 〇 Plasma adaptability 〇 〇 〇 〇 ×

[0191] In Examples 1 to 4, good results were obtained in terms of grindability, opening property, and plasma adaptability. On the other hand, in Comparative Example 1, there were no problems with grindability and opening property, but residual adhesive was generated at the opening part on the cutting line when peeling the surface protective tape from the mask, and silicon was not sufficiently etched when etching with SF6 gas.

[0192] It should be noted that the evaluation "○" of the opening property in Comparative Example 1 means that the mask on the cutting line was completely removed by development.

[0193] [Manufacture of Mask-Integrated Surface Protective Tape]

[0194] (Specimen 1)

[0195] To 100 parts by mass of the acrylic polymer, 2-isocyanatoethyl methacrylate (trade name: MOI, manufactured by Showa Denko K.K.) having a photopolymerizable carbon-carbon double bond and an isocyanate group in the molecule was reacted. The above acrylic polymer had structural units of 2-ethylhexyl acrylate: 80 mol%, methyl acrylate: 1 mol%, and 2-hydroxyethyl acrylate: 19 mol% as structural units in each molar ratio, and an acrylic polymer a having a photopolymerizable carbon-carbon double bond in the molecule was obtained (Mw: 750,000, acid value: 6 mgKOH / g, hydroxyl value: 30 mgKOH / g).

[0196] To 100 parts by mass of the above acrylic polymer a, 2.0 parts by mass of an isocyanate curing agent (trade name: L-45, manufactured by Tosoh Corporation) and 5.0 parts by mass of a photopolymerization initiator (trade name: Esacure KIP 100F, manufactured by Lamberti) were blended to obtain an adhesive composition a.

[0197] Further, a base film a (3aa) composed of a low-density polyethylene (LDPE) resin (trade name: Nipolon Hard 205, manufactured by Tosoh Corporation) and an ethylene-vinyl acetate copolymer (EVA) resin (trade name: Ultrathene 540, manufactured by Tosoh Corporation) was formed into a film by an extrusion method with a thickness of 110 μm.

[0198] The above adhesive composition a was applied to the EVA resin layer of the above base film a at a dried thickness of 20 μm and dried to form an adhesive layer (3ab), obtaining an adhesive tape a.

[0199] Relative to 100 parts by mass of an acrylic polymer b (Mw: 350,000, acid value: 21 mgKOH / g, hydroxyl value: 1 mgKOH / g) having structural units of butyl acrylate: 47 mol%, 2-ethylhexyl acrylate: 47 mol%, methyl acrylate: 5 mol%, and 2-hydroxyethyl acrylate: 1 mol% in each molar ratio, 2.0 parts by mass of an epoxy curing agent (trade name: Tetrad-C, manufactured by Mitsubishi Gas Chemical) was blended to obtain a mask material composition a.

[0200] The above mask material composition a was applied to the adhesive layer (3ab) of the above adhesive tape a at a dried thickness of 10 μm and dried to laminate a mask material layer a (3b), obtaining a mask-integrated surface protection tape a (3).

[0201] (Specimen 2)

[0202] Relative to 100 parts by mass of an acrylic polymer c (Mw: 250,000, acid value: 47 mgKOH / g, hydroxyl value: 8 mgKOH / g) having structural units of methyl acrylate: 75 mol%, 2-ethylhexyl acrylate: 10 mol%, methacrylic acid: 7 mol%, and 2-hydroxyethyl acrylate: 8 mol% in each molar ratio, 25 parts by mass of an acrylate monomer having one photopolymerizable carbon-carbon double bond in the molecule (trade name: M-5700, manufactured by Toagosei Co., Ltd.), 1.0 part by mass of an epoxy curing agent (trade name: Tetrad-C, manufactured by Mitsubishi Gas Chemical Company), and 5.0 parts by mass of a photopolymerization initiator (trade name: Esacure KIP 100F, manufactured by Lamberti) were blended to obtain a mask material composition b.

[0203] Instead of the mask material composition a, the mask material composition b was used, and a mask-integrated surface protection tape b (3) was obtained in the same manner as in Specimen 1 except for this.

[0204] (Specimen 3)

[0205] In Specimen 2, the blending amount of the acrylate monomer having one photopolymerizable carbon-carbon double bond in the molecule (trade name: M-5700, manufactured by Toagosei Co., Ltd.) relative to 100 parts by mass of the acrylic polymer c was replaced with 150 parts by mass. Otherwise, the mask material composition c and the mask-integrated surface protection tape c(3) using the mask material composition c were obtained in the same manner as in Specimen 2.

[0206] (Specimen c1)

[0207] In Specimen 2, instead of the acrylate monomer having one photopolymerizable carbon-carbon double bond in the molecule (trade name: M-5700, manufactured by Toagosei Co., Ltd.), 100 parts by mass of an acrylate oligomer having five photopolymerizable carbon-carbon double bonds in the molecule (trade name: BEAMSET 575, manufactured by Arakawa Chemical Industries, Ltd.) and 10 parts by mass of an acrylate oligomer having three photopolymerizable carbon-carbon double bonds in the molecule (trade name: CN944, manufactured by Sartomer Company) were used relative to 100 parts by mass of the acrylic polymer c. Otherwise, the mask material composition e and the mask-integrated surface protection tape e using the mask material composition e were obtained in the same manner as in Specimen 2.

[0208] <Evaluation>

[0209] Using the mask-integrated surface protection tapes a to c and e obtained above, the following semiconductor wafer processing steps were performed to evaluate each mask-integrated surface protection tape.

[0210] (Peelability)

[0211] First, on the patterned surface side of an 8-inch silicon wafer (Si wafer), the mask-integrated surface protection tape (3) was attached in a manner substantially the same as the wafer diameter, and it was ground with a back grinder [DFD8540 (manufactured by DISCO Corporation)] until the wafer thickness reached 50 μm.

[0212] Next, ultraviolet rays were irradiated from the mask-integrated surface protection tape side at 500 mJ / cm 2 After that, a UV-curable dicing tape (trade name: UC-353EP-110, manufactured by Furukawa Electric Co., Ltd.) was attached to the back side of the ground wafer and supported and fixed with a ring frame. The surface protection tape (adhesive layer 3ab and base tape 3aa) was peeled off while retaining the mask material layer (3b).

[0213] The case where only the surface protection tape could be peeled off and the mask material layer remained on the wafer was evaluated as "A", and other cases were evaluated as "C".

[0214] Here, the specimen c1 was evaluated as "C", and a part of the mask material layer peeled off from the wafer when the surface protective tape was peeled off.

[0215] For the wafer having the mask material layer obtained in the above peelability test, the mask material layer (3b) was removed from the exposed mask material layer along the scribe line portion of the silicon wafer using a CO2 laser, and the scribe line portion was opened to 50 μm.

[0216] Next, using SF6 gas as the plasma generation gas, plasma was irradiated from the surface side of the exposed mask material layer to perform plasma cutting, and the wafer was cut and divided into individual chips. The etching was performed under the condition that the etching rate of the Si wafer was 15 μm / min, and the SF6 etching rate [μm / min] of each mask material layer under this condition was measured.

[0217] Next, ashing was performed using O2 gas as the plasma generation gas. Regarding the plasma etching of O2, it was performed under the condition that the etching rate of the mask material layer a was 1 μm / min, and the O2 etching rate [μm / min] of each other mask material layer under this condition was measured.

[0218] After removing the mask material layer (3b) by the above ashing, ultraviolet rays were irradiated from the dicing tape side to reduce the adhesion of the dicing tape, and the chips were picked up in the pick-up process.

[0219] (Transmittance evaluation)

[0220] The mask-integrated surface protective tape obtained above was adhered to the PET film subjected to easy adhesion treatment and irradiated with UV, and only the surface protective tape was peeled off. The transmittance of the laminate composed of the PET film and the mask material layer obtained was measured using a spectrophotometer (trade name: UV-1800, manufactured by Shimadzu Corporation). The transmittance of the mask material layer was calculated by subtracting the transmittance of the PET film alone from the obtained transmittance.

[0221] It should be noted that regarding the etching rate of the mask material layer e in the specimen c1, a wafer having a mask material layer produced by the following method was used as the wafer having the mask material layer, and the etching rate was measured under the same conditions as the above measurement of the etching rate.

[0222] -Fabrication of wafer with mask material layer-

[0223] The mask material composition e was separately coated on the patterned surface side of the Si wafer and dried to form a mask material layer, and a Si wafer having a mask material layer was fabricated.

[0224] The compositions and evaluations of the mask-integrated surface protective tapes a to c and e are summarized in the following table.

[0225]

Table 2

[0226]

[0227] In Samples 1 to 3 of the mask-integrated surface protection tape of the present invention, the peelability was good in all cases. In addition, when the mask-integrated surface protection tape of the present invention was used, the shielding property during plasma cutting was good and the ashing property was also good.

[0228] The present invention has been described in connection with its embodiments. However, the applicant believes that, unless otherwise specified, the present invention is not limited to any of the details described, and should be broadly construed without departing from the spirit and scope of the invention as set forth in the appended claims.

[0229] This application claims priority based on Japanese Patent Application Nos. 2015-219736 and 2015-219738 filed in Japan on November 9, 2015, the disclosures of which are incorporated herein by reference and made a part of the content of this specification.

[0230] Symbol Explanation

[0231] 1 Semiconductor wafer

[0232] 2 Pattern surface

[0233] 3 Mask-integrated surface protection tape

[0234] 3a Surface protection tape

[0235] 3aa Base film

[0236] 3ab Adhesive layer

[0237] 3b Mask material layer

[0238] 4 Wafer fixing tape

[0239] 7 Chip

[0240] S Surface

[0241] B Back side

[0242] M1 Wafer grinding device

[0243] M2 Pin

[0244] M3 Elastic chuck

[0245] F Annular frame

[0246] L Laser (CO2 laser)

[0247] P1 Plasma of SF6 gas

[0248] Plasma of P2 and O2 gases

Claims

1. A method for manufacturing a semiconductor chip, comprising the following steps (a) to (d): (a) A step of grinding the back surface of the semiconductor wafer while a mask-integrated surface protection tape having a base film, an adhesive layer provided on the base film, and a mask material layer provided on the adhesive layer is attached to the pattern surface side of the semiconductor wafer, attaching a wafer fixing tape to the ground back surface of the semiconductor wafer, and supporting and fixing it with an annular frame; (b) A step of integrally peeling the base film and the adhesive layer from the mask-integrated surface protection tape to expose the mask material layer on the surface, and then cutting a portion of the mask material layer corresponding to the dicing streets of the semiconductor wafer with a laser to open the dicing streets of the semiconductor wafer; (c) A plasma cutting step of dividing the semiconductor wafer along the dicing streets by plasma irradiation to singulate it into semiconductor chips; and (d) An ashing step of removing the mask material layer by plasma irradiation, wherein the mask material layer has a light transmittance of 80% or less at a wavelength of 10 μm and a visible light transmittance of 50% or more at wavelengths of 350 nm to 700 nm, in the step (c), the plasma irradiation is plasma irradiation of a fluorine compound, in the step (d), the plasma irradiation is oxygen plasma irradiation, For the mask material layer, the etching rate E using O2 plasma O2 relative to the etching rate E using SF6 plasma F The ratio E O2 / E F is 2.0 or more. the mask material layer is radiation-polymerizable, the mask material layer contains an acrylate compound having one or two photopolymerizable carbon-carbon double bonds in the molecule, and the content of the acrylate compound is 15% by mass to 70% by mass.

2. The manufacturing method of the semiconductor chip according to claim 1, wherein, At least the adhesive layer in the mask-integrated surface protection tape is radiation-curable. In the step (b), before integrally peeling the base film and the adhesive layer from the mask-integrated surface protection tape to expose the mask material layer on the surface, a step of irradiating radiation to cure the adhesive layer is included.

3. The manufacturing method of the semiconductor chip according to claim 1 or 2, wherein, After the step (d), a step (e) of picking up the semiconductor chip from the wafer fixing tape is included.

4. The manufacturing method of the semiconductor chip according to claim 3, wherein, After the step (e), a step (f) of transferring the picked-up semiconductor chip to a die bonding process is included.

5. The manufacturing method of the semiconductor chip according to claim 1 or 2, wherein, The mask material layer is ultraviolet-curable.

6. A mask-integrated surface protection tape, which is a mask-integrated surface protection tape used in a method for manufacturing a semiconductor chip including the following steps (a) to (d). The mask-integrated surface protection tape is a mask-integrated surface protection tape having an adhesive layer and a mask material layer formed in sequence on a base film. The etching rate of the mask material layer using SF6 plasma is lower than the etching rate using O2 plasma. (a) A step of grinding the back surface of the semiconductor wafer while the mask-integrated surface protection tape is attached to the pattern surface side of the semiconductor wafer, attaching a wafer fixing tape to the ground back surface of the semiconductor wafer, and supporting and fixing it with an annular frame; (b) A step of integrally peeling the base film and the adhesive layer from the mask-integrated surface protection tape to expose the mask material layer on the surface, and then cutting the portion of the mask material layer corresponding to the dicing streets of the semiconductor wafer with a laser to open the dicing streets of the semiconductor wafer; (c) A plasma cutting step of dividing the semiconductor wafer by plasma irradiation through the dicing streets to singulate it into semiconductor chips; and (d) An ashing step of removing the mask material layer by plasma irradiation, wherein the light transmittance of the mask material layer at a wavelength of 10 μm is 80% or less, and the visible light transmittance at a wavelength of 350 nm to 700 nm is 50% or more, in the step (c), the plasma irradiation is plasma irradiation of a fluorine compound, in the step (d), the plasma irradiation is oxygen plasma irradiation, For the mask material layer, the etching rate E of the O2 plasma O2 relative to the etching rate E of the SF6 plasma F The ratio E O2 / E F is 2.0 or more. the mask material layer is a radiation polymerization type, the mask material layer contains an acrylate compound having one or two photopolymerizable carbon-carbon double bonds in the molecule, and the content of the acrylate compound is 15% by mass to 70% by mass.

7. The mask-integrated surface protection tape according to claim 6, wherein, the mask material layer is an ultraviolet curable type.

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