Semiconductor structure and method for forming the same

Abstract

A semiconductor structure includes: a semiconductor substrate; a metallization component located above the semiconductor substrate; a first dielectric component; a second dielectric component; and a through-hole contact. The metallization component includes a first bottom angle and a second bottom angle opposite to the first bottom angle. The first dielectric component is adjacent to the first bottom angle, and the second dielectric component is adjacent to the second bottom angle. The metallization component is between the first dielectric component and the second dielectric component. In some embodiments, the angle of the first bottom angle defined by the sidewall of the first dielectric component and the bottom surface of the metallization component is less than 90°. The through-hole contact is configured to connect the metallization component to the semiconductor substrate. Embodiments of the present application also relate to a method for forming a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced continuous improvements in subsequent generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs.

[0003] Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the size of the smallest component (or line) that can be manufactured using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0004] However, as feature sizes continue to decrease, manufacturing processes continue to become more difficult to perform. As a result, it has become a challenge to form reliable semiconductor devices with increasingly smaller dimensions. Summary of the invention

[0005] Some embodiments of the present application provide a semiconductor structure, including: a semiconductor substrate; a metallization component located above the semiconductor substrate, wherein the metallization component includes at least a first bottom angle and a second bottom angle opposite to the first bottom angle; a first dielectric component adjacent to the first bottom angle of the metallization component, wherein the angle of the first bottom angle defined by the sidewall of the first dielectric component and the bottom surface of the metallization component is less than 90°; a second dielectric component adjacent to the second bottom angle of the metallization component, such that the metallization component is interposed between the first dielectric component and the second dielectric component; and a through-hole contact configured to connect the metallization component to the semiconductor substrate.

[0006] Some other embodiments of the present application provide a semiconductor structure, comprising: a semiconductor substrate; a first metallization component located above the semiconductor substrate, wherein the metallization component includes a first bottom angle and a second bottom angle opposite to the first bottom angle; a second metallization component located above the semiconductor substrate, wherein the metallization component includes a third bottom angle and a fourth bottom angle opposite to the third bottom angle; a first dielectric component located between the first metallization component and the second metallization component; and a second dielectric component adjacent to the first metallization component at a side opposite to the first dielectric component, wherein the first metallization component, the second metallization component, the first dielectric component and the second dielectric component are arranged along the same direction, the first bottom angle of the first metallization component is adjacent to the first dielectric component and is defined by an acute angle, and the third bottom angle C3 / C3′ of the second metallization component is adjacent to the first dielectric component and is defined by an acute angle.

[0007] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: receiving a semiconductor substrate, wherein a first dielectric layer is formed above the semiconductor substrate; forming a groove in the first dielectric layer; filling the groove to form a conductive layer in the first dielectric layer; segmenting the conductive layer to form a first conductive component and a second conductive component separated from each other by a groove; and filling the groove with a second dielectric layer so that one or two of the conductive components are terminated by a portion of the first dielectric layer and a portion of the second dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 is a flow chart of a method 10 for forming a semiconductor structure according to various aspects of the present invention.

[0010] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19Ais a schematic top plan view of a semiconductor structure at various stages of method 10 according to aspects of one or more embodiments of the present invention.

[0011] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B and Fig.19B According to one or more embodiments of the present invention, Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A Schematic cross-sectional view of the semiconductor structure taken along line II-II'.

[0012] Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig.18C and Fig.19C According to one or more embodiments of the present invention, Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A, Fig.11A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A Schematic cross-sectional view taken along line II'.

[0013] Fig.12 According to one or more embodiments of the present invention, Fig.11A Schematic cross-sectional view of the semiconductor structure taken along line II'.

[0014] Fig. 20 According to one or more embodiments of the present invention, Fig.19A Schematic cross-sectional view of the semiconductor structure taken along line II-II'. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] In addition, when "about", "approximately", etc. are used to describe a value or a range of values, the term is intended to cover values ​​within a reasonable range including the described value, such as + / -10% of the described value or other values ​​as understood by those skilled in the art. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm. Moreover, for ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper", "above", etc. may be used herein to describe the relationship between one element or component as shown in the figure and another (or other) elements or components. In addition to the orientation shown in the figure, spatially relative terms are intended to include different orientations of the device in use or operation. The device can be oriented in other ways (rotated 100 degrees or in other orientations), and the spatially relative descriptors used therein can be interpreted accordingly.

[0017] As used herein, terms such as "first", "second", and "third" describe individual elements, components, regions, layers, and / or parts, but these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Unless the context clearly indicates, terms such as "first", "second", and "third" used in this article do not imply a sequence or order.

[0018] The IC manufacturing process flow can generally be divided into three categories: front-end-of-line (FEOL), middle-end-of-line (MEOL), and back-end-of-line (BEOL). FEOL generally includes processes related to the manufacture of IC devices (such as transistors). For example, the FEOL process may include forming an isolation structure for isolating IC devices, gate structures, and source and drain structures (also known as source / drain structures) that form transistors. MEOL generally includes processes related to the manufacture of connection structures (also known as contacts or plugs) connected to conductive components (or conductive regions) of IC devices. For example, the MEOL process may include forming a connection structure connected to the gate structure and a connection structure connected to the source / drain structure. BEOL generally includes processes related to the manufacture of a multi-layer interconnect (MLI) structure that electrically connects the IC device to the connection structure manufactured by the FEOL and MEOL. Therefore, the operation of the IC device can be achieved. As described above, the scaling down process increases the complexity of processing and manufacturing ICs.

[0019] In some embodiments, the BEOL MLI includes a plurality of metal layers (or metal lines) referred to in ascending order as a zeroth metal layer M0, a first metal layer M1, and an Nth metal layer Mn, and a plurality of connecting vias referred to as a first via V1, a second via V2, and an (N-1)th via Vn-1, where n is a positive integer. The connecting vias are configured to electrically couple two adjacent metal layers together. For example, the (N-1)th metal layer Mn-1 may be electrically connected to the Nth metal layer Mn through the (N-1)th via Vn-1. In addition, the metal layer Mn and the connecting via Vn-1 may be formed in an inter-metal dielectric (IMD) layer IMDn to provide mechanical support and electrical isolation therebetween. In some embodiments, forming the metal layer and the connecting via includes forming an opening in the IMD layer, filling the opening with a conductive material, and performing a planarization process on the conductive material, such as a chemical mechanical polishing (CMP) operation. In some comparative methods, it was found that the above-mentioned filling of the opening with a conductive material becomes more challenging when the metal layer becomes shorter due to scaling down. The challenges associated with opening fill or gap fill may result in voids in the metal layer, which may adversely affect device performance.

[0020] The present invention provides a semiconductor structure and a method for forming the same. In this embodiment, a metal line is formed in an intermetallic dielectric layer and a metal cutting operation is performed to remove a portion of the metal line, thereby segmenting the metal line into a plurality of metallization components. Subsequently, the openings formed by the segmentation are filled with a dielectric material to provide isolation between the metallization components. Therefore, the gap filling problem can be alleviated and the device performance can be ensured.

[0021] Figure 1 1 is a flow chart representing a method 10 for forming a semiconductor structure 200 according to aspects of the present invention. In some embodiments, method 10 includes a plurality of operations (11, 12, 13, 14, and 15) and is further described below according to one or more embodiments. It should be noted that the operations of method 10 may be omitted, rearranged, or otherwise modified within the scope of various aspects. It should also be noted that additional operations may be provided before, during, and after method 10, and only some other operations are briefly described herein. In the present embodiment, method 10 is used to partially or fully form a BEOL interconnect (e.g., MLI) structure above a semiconductor structure.

[0022] In some embodiments, the method 10 may be used to form a zero-metal layer M0 of a semiconductor structure. For example, Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A is a schematic top plan view of a semiconductor structure at various stages of method 10 according to aspects of one or more embodiments of the present invention. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B and Fig.19B According to one or more embodiments of the present invention, Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A Schematic cross-sectional view of the semiconductor structure taken along line II-II'. Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig.12 , Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig.18C and Fig.19C According to one or more embodiments of the present invention, Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A Schematic cross-sectional view taken along line II'.

[0023] refer to FIG. 2A to FIG. 2CIn operation 11, method 10 receives (or is provided with) a semiconductor structure 200 (hereinafter referred to as structure 200) including a semiconductor substrate 202. In some embodiments, the semiconductor substrate 202 including one or more FEOL devices may be part of an IC chip, a system on a chip (SoC), or part of a system on a chip. In some embodiments, semiconductor substrate 202 may be a substrate that houses FEOL devices such as a microprocessor, a memory, and / or other IC devices. In some embodiments, semiconductor substrate 202 may include various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable elements, or combinations thereof. The transistor may be a planar transistor or a multi-gate transistor, such as a fin FET (FinFET). For clarity, FIG. 2A to FIG. 2C It has been simplified to better illustrate the inventive concept of the present invention.

[0024] In some embodiments, the semiconductor substrate 202 includes silicon. Alternatively or additionally, the semiconductor substrate 202 includes another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. In some implementations, the semiconductor substrate 202 includes one or more III-V materials, one or more II-IV materials, or a combination thereof. In some implementations, the semiconductor substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be manufactured by isolation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0025] In the present embodiment, the semiconductor substrate 202 includes one or more three-dimensional fin-type active regions (or fins) 204, over which components including gate structures and epitaxial source / drain features are subsequently formed to provide one or more FEOL devices. Figure 2B, the fins 204 are longitudinally oriented along a direction D2 and are spaced apart from each other along a direction D1 substantially perpendicular to the direction D2. In some embodiments, the fins 204 include a single semiconductor layer configured to provide a fin-type device, such as a fin field effect transistor (FinFET). In some embodiments, the fins 204 include a semiconductor layer stack interleaved with a portion of a gate structure to provide a full-all-around (GAA) device, such as a GAA FET.

[0026] The semiconductor substrate 202 may include various doped regions (not shown) configured according to the design requirements of the FEOL device, such as a p-type doped region, an n-type doped region, or a combination thereof. The p-type doped region (e.g., a p-type well) includes a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. The n-type doped region (e.g., an n-type well) includes an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. In some implementations, the semiconductor substrate 202 includes a doped region formed by a combination of a p-type dopant and an n-type dopant. Various doped regions may be formed directly above and / or in the semiconductor substrate 202, for example, to provide a p-type well structure, an n-type well structure, a double well structure, a raised structure, or a combination thereof. An ion implantation process, a diffusion process, and / or another suitable doping process may be performed to form the various doped regions.

[0027] The structure 200 also includes an isolation component 206 formed above and / or in the semiconductor substrate 202 to electrically isolate various regions of the structure 200, such as various device regions. For example, the isolation component 206 can define and electrically isolate active device regions and / or passive device regions from each other. The isolation component 206 can include silicon oxide, silicon nitride, silicon oxynitride, another suitable isolation material, or a combination thereof. The isolation component 206 can include different structures, such as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, and / or a local oxidation of silicon (LOCOS) structure.

[0028] Various gate structures may be disposed over the semiconductor substrate 202, such as gate structure 208. In some embodiments, the gate structures 208 extend longitudinally along direction D1 and are spaced apart from each other along direction D2, i.e., the gate structures 208 are oriented substantially perpendicular to the fins 204. Figure 2BAs shown, the gate structure 208 is between the source region and the drain region, wherein a channel region is defined between the source region and the drain region. In some embodiments, the gate structure 208 is formed above the fin structure. In some embodiments, the gate structure 208 includes a metal gate structure. In some embodiments, the metal gate structure includes a gate dielectric layer and a gate electrode disposed above the gate dielectric layer. The gate dielectric layer includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof. A high-k dielectric material generally refers to a dielectric material having a high dielectric constant, such as a dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, other suitable materials, or a combination thereof. For example, the gate dielectric layer may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, HfO2-Al2O3, TiO2, Ta2O5, La2O3, Y2O3, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the gate structure 208 may include other material layers, such as an interfacial layer (IL), including, for example, silicon oxide, a barrier layer, a capping layer, other suitable layers, or combinations thereof.

[0029] The gate electrode includes a conductive material, such as one or more metals. Therefore, the gate structure 208 may be referred to as a high-k metal gate stack. In some implementations, the gate electrode includes multiple layers, such as one or more work function metal layers and a gap fill metal layer. The work function metal layer includes a conductive material adjusted to have a desired work function (such as an n-type work function or a p-type work function). Exemplary work function materials include TiN, TaN, Ru, Mo, Al, ZrSi2, MoSi2, TaSi2, NiSi2, WN, Ti, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other suitable work function materials, or combinations thereof. The gap fill metal layer may include a suitable conductive material, such as Al, W, Cu, Co, Ru, other suitable conductive materials, or combinations thereof.

[0030] The gate structure 208 may also include a spacer 209 disposed adjacent to the gate structure 208 (e.g., along its sidewalls). The spacer 209 may be formed by any suitable process and include a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). In some embodiments, the spacer 209 includes a multilayer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, multiple sets of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, are formed adjacent to the gate structure 208. Implantation, diffusion, and / or annealing processes may be performed to form lightly doped source and drain (LDD) components and / or heavily doped source and drain (HDD) components in the semiconductor substrate 202 before and / or after forming the spacers.

[0031] In the present embodiment, the source / drain (S / D) region of each fin 204 includes an epitaxial S / D structure 210. For example, a semiconductor material may be epitaxially grown on the semiconductor substrate 202 to form the epitaxial S / D structure 210 over the source region and the drain region of the semiconductor substrate 202. Thus, the gate structure 208, the epitaxial S / D structure 210, and the channel region defined between the epitaxial source / drain structure form a FEOL device, such as a transistor. In some embodiments, the epitaxial S / D structure 210 surrounds the source / drain region of the fin structure. In some embodiments, the epitaxial S / D structure 210 replaces a portion of the fin structure. The epitaxial S / D structure 210 is doped with an n-type dopant and / or a p-type dopant. In some embodiments, the transistor is configured as an n-type device (e.g., a device having an n-channel), and the epitaxial S / D structure 210 includes a silicon-containing epitaxial layer or a silicon-carbon-containing epitaxial layer doped with phosphorus, other n-type dopants, or a combination thereof (e.g., forming a Si:P epitaxial layer or a Si:C:P epitaxial layer). In some embodiments in which the transistor is configured as a p-type device (e.g., a device having a p-channel), the epitaxial S / D structure 210 includes a silicon- and germanium-containing epitaxial layer doped with boron, other p-type dopants, or a combination thereof (e.g., forming a Si:Ge:B epitaxial layer). In some embodiments, the epitaxial S / D structure 210 includes materials and / or dopants that achieve desired tensile stress and / or compressive stress in the channel region. In some embodiments, a metal silicide layer 210s may be formed on a top surface of the epitaxial S / D structure 210.

[0032] like FIG. 2A to FIG. 2CAs shown, the structure 200 may also include a plurality of S / D contacts 211 on the epitaxial S / D structure 210 and in dielectric layers 212 and 213. In the present embodiment, the dielectric layer 212 is a contact etch stop layer (CESL) and includes a suitable dielectric material, such as silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), other dielectric materials, or combinations thereof. In the present embodiment, the dielectric layer 213 is an interlayer dielectric (ILD) layer and includes a suitable dielectric material, such as silicon oxide (SiO), tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, other dielectric materials, or combinations thereof. Exemplary low-k dielectric materials may include fluorine-doped silicate glass (FSG), carbon-doped silicon oxide, Black (Applied Materials, Santa Clara, CA, USA), xerogels, aerogels, amorphous fluorinated carbon, parylene, BCB, SILK (Dow Chemical, Midland, MI), polyimide, other low-k dielectric materials, and combinations thereof. FIG. 2A to FIG. 2C As shown, a dielectric layer 212 is disposed over the epitaxial S / D structure 210 , and a dielectric layer 213 is disposed over the dielectric layer 212 .

[0033] In addition, the structure 200 includes a dielectric layer 214 disposed over the S / D contacts 211 and the dielectric layers 212 and 213. In the present embodiment, the dielectric layer 214 is an etch stop layer having a single layer structure or a multi-layer structure. For example, in the depicted embodiment, the dielectric layer 214 includes a first etch stop layer 214-1 and a second etch stop layer 214-2 located over the first etch stop layer 214-1. In some embodiments, both the first etch stop layer 214-1 and the second etch stop layer 214-2 may include silicon nitride (SiN), silicon carbide (SiC), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum oxynitride (AlON), zirconium oxide (ZrO), zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), hafnium oxide (HfO), zinc oxide (ZnO), titanium oxide (TiO), tantalum oxide (TaO), tantalum carbonitride (TaCN), yttrium oxide (YO), silicon nitride (SiN), silicon oxide (SiO), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), other suitable materials or combinations thereof. In some embodiments, the first etch stop layer 214-1 and the second etch stop layer 214-2 include different materials. In some embodiments, the thickness of each of the first etch stop layer 214-1 and the second etch stop layer 214-2 is about 2 nanometers to about 20 nanometers, but the present invention is not limited thereto.

[0034] In some embodiments, a plurality of connecting vias 216 are formed in the dielectric layer 214 above the source / drain regions or the gate structure 208, such as FIG. 2A to FIG. 2C As shown. In some embodiments, the connecting vias 216 each include a bulk conductive layer having Co, W, Ru, Al, Mo, Ti, Cu, other suitable conductive materials, or combinations thereof. In some embodiments, the connecting vias 216 each include a barrier layer (not separately shown) with the bulk conductive layer disposed thereon, and the barrier layer may include titanium nitride (TiN), titanium silicide (TiSi), titanium nitride silicide (TiSiN), cobalt silicide (CoSi), Ni, nickel silicide (NiSi), Cu, tantalum nitride (TaN), other suitable materials, or combinations thereof. In some embodiments, the connecting vias 216 include a to-gate via (VG), which generally refers to a contact coupled to the gate structure 208, such that the gate structure 208 can be connected to a BEOL interconnect (not shown) through the connecting vias 216. In some embodiments, the connecting vias 216 include a to-drain via (VD), which generally refers to a contact coupled to the source / drain region, such that the epitaxial S / D structure 210 can be connected to the BEOL interconnect through the connecting vias 216. Thus, FEOL devices may be electrically connected to BEOL interconnects through connecting vias 216, which may also be referred to as MEOL interconnect structures.

[0035] refer to FIG. 3A to FIG. 3C In operation 11, method 10 forms a dielectric layer 220 over structure 200. Dielectric layer 220 may be referred to as an IMD layer or alternatively as an ILD layer. Dielectric layer 220 may include a dielectric material including, for example, silicon oxide, TEOS, PSG, BPSG, a low-k dielectric material (examples provided above), another suitable dielectric material, or a combination thereof. In some embodiments, dielectric layer 220 and dielectric layer 214 include different materials. In some embodiments, dielectric layer 220 and second etch stop layer 214-2 include different materials. The thickness of dielectric layer 220 may be about 0.5 nanometers to about 30 nanometers, but the present invention is not limited thereto. In the present embodiment, the thickness of dielectric layer 220 is greater than the thickness of first etch stop layer 214-1 and second etch stop layer 214-2.

[0036] In operation 12, method 10 forms trench 225 in dielectric layer 220. FIG. 4A to FIG. 4CIn some embodiments, forming the trench 225 includes first forming a patterned mask element 221 above the dielectric layer 220. In some embodiments, the patterned mask element 221 includes a top layer (e.g., a photoresist layer), an intermediate layer, and a bottom layer (e.g., an anti-reflective coating) including a resist material. The mask element can be patterned by a series of photolithography and etching processes, during which the top layer is patterned by exposure to radiation through a photomask, the exposed top layer is developed to form a patterned resist, and the patterned resist is used as a mask to form the patterned mask element 221 to subsequently etch the underlying intermediate layer and bottom layer (e.g., by a dry etching process, a wet etching process, a reactive ion etching (RIE) process, or a combination thereof). In the present embodiment, the patterned mask element 221 includes a plurality of openings 223, which are configured to define the size and position of the trench 225 formed in the dielectric layer 220. Therefore, portions of the dielectric layer 220 are exposed through the openings 223.

[0037] refer to FIG. 5A to FIG. 5C , portions of the dielectric layer 220 exposed by the openings 223 of the patterned mask element 221 are removed by one or more suitable etching processes (such as a dry etching process, a wet etching process, an RIE process, or a combination thereof), thereby forming one or more trenches 225 in the dielectric layer 220. After the trenches 225 are formed, the patterned mask element 221 is removed by a suitable method (such as plasma ashing and / or resist stripping). In the present embodiment, the trenches 225 are configured to expose the top surface of each connecting via 216 and the dielectric layer 214 (i.e., the second etch stop layer 214-2) and further define the sidewalls of the dielectric layer 220. Due to factors such as uneven etchant loading when forming the trenches 225, the opening of the bottom portion of the trench 225 (e.g., the length of the trench 225 defined along the direction D2) is smaller than the opening of the top portion of the trench 225, that is, the trench 225 is configured with an inverted trapezoidal profile, such as Figure 5C In other words, Figure 5C The angle 226 of the groove 225 is shown to be greater than about 90°, ie, the angle 226 is an obtuse angle.

[0038] In some embodiments, still refer to FIG. 5A to FIG. 5C, the length L of the groove 225 defined along the direction D2 is greater than the width W of the groove 225 defined along the direction D1, but the present invention does not limit the length L or the width W to any particular size. It is worth noting that in the present embodiment, the width W corresponds to the width of the metallization component subsequently formed in the groove 225 along the direction D1, and the length L is greater than the length of such metallization component along the direction D2. In other words, the metal line subsequently formed in the groove 225 is further subjected to a cutting (or etching) process to define the desired size (i.e., length) and position of multiple metallization components. In contrast, existing implementations typically form metallization components by directly patterning the dielectric layer 220 to form an opening having the desired final size (i.e., length and width) for the metallization component and then filling the opening with a conductive material to form a metallization. In some instances, filling such small openings may introduce unwanted voids, which may adversely affect the performance of the device. Embodiments provided herein avoid these disadvantages by first forming a metal line in a trench configured to have a length greater than the final length of each metallization feature, thereby reducing the formation of voids, and then segmenting (and isolating) the metal line into multiple portions corresponding to the final length of the metallization feature.

[0039] In operation 13, method 10 fills trench 225 to form metal line (or metal layer) 234 in dielectric layer 220. FIG. 6A to FIG. 6C In the present embodiment, the trench 225 is filled with a conductive material 230, including, for example, Co, W, Ru, Al, Mo, Ti, Cu, other suitable conductive materials, or combinations thereof. In some embodiments, the conductive material 230 is the same component as the bulk conductive layer of the connecting via 216. The conductive material 230 can be formed by any suitable deposition process, including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, other suitable processes, or combinations thereof. In the present embodiment, according to the profile of the trench 225 discussed in detail above, the metal line 234 is configured in an inverted trapezoidal shape.

[0040] In some embodiments, a barrier layer 232 is formed in the trench 225 before depositing the conductive material 230. In some embodiments, the barrier layer 232 includes Ti, TiN, Ta, TaN, W, WN, other suitable materials, or combinations thereof. The barrier layer 232 may be formed by any suitable method, such as CVD, ALD, PVD, other methods, or combinations thereof. The thickness of the barrier layer 232 may be about 0.5 nanometers to about 10 nanometers, but the present invention is not limited thereto. The barrier layer 234 may be a single-layer structure, or alternatively may be a multi-layer structure. For example, the barrier layer 232 may include a sub-barrier layer 232-1 and a sub-barrier layer 232-2 (both shown in Fig.12In such an embodiment, the sub-blocking layer 232-1 and the sub-blocking layer 232-2 include different materials. The thickness of the sub-blocking layer 232-1 may be about 0.5 nanometers to about 10 nanometers, and the thickness of the sub-blocking layer 232-2 may be about 0.5 nanometers to about 10 nanometers, but the present invention is not limited thereto.

[0041] refer to 7A to 7C , method 10 removes any excess material from the top surface of dielectric layer 220 in a CMP operation. Thus, portions of conductive material 230 and portions of barrier layer 232 are removed to obtain metal line 234 in dielectric layer 220. Fig. 7A and Figure 7C As shown, the metal line 234 extends along the direction D2. In some embodiments, the width of the metal line 234, that is, the width W defined previously, is greater than the width of the connecting via 216, such as Figure 7B As shown, to ensure that the metal line 234 contacts the connecting via 216 and is thus electrically connected to the FEOL device formed above the semiconductor substrate 202. In the present embodiment, the metal line 234 includes a plurality of bottom angles, and each of the bottom angles is defined by the previously defined included angle 226. Therefore, in the present embodiment, the included angle 226 of the bottom angle of the metal line 234 is greater than 90°, i.e., an obtuse angle.

[0042] In operation 14, the method 10 segments (or separates) the metal line 234 to form at least one metallization component 240a and a metallization component 240b, which are disposed adjacent to each other and oriented longitudinally along the direction D2. In the present embodiment, the metallization component 240a and the metallization component 240b are formed by the metal line 234 and the dielectric layer 220 (such as 9A to 9C As shown in the figure, the grooves 241 defined by the embodiment of the present invention are separated from each other. FIG. 8A to FIG. 8C In the present embodiment, a patterned mask element 235 is formed over the semiconductor substrate 202 and includes a plurality of openings 237 to define the size and location of the recesses 241 to be formed. In some embodiments, the patterned mask element 235 is similar to the patterned mask element 221 in terms of structure and processing methods. In the present embodiment, a portion of the metal line 234 is exposed through the openings 237. In the depicted embodiment, the length of a portion of the metal line 234 disposed under the patterned mask element 235 corresponds to the length of the subsequently formed metallization feature 240a or 240b, wherein the width of each of the metallization features 240a and 240b has been previously defined as the width W.

[0043] refer to 9A to 9C, method 10 performs an etching operation, such as a dry etching process, a wet etching process, an RIE process, or a combination thereof, to remove portions of metal line 234 exposed by patterned mask element 235, thereby producing one or more grooves 241. In the present embodiment, grooves 241 are formed to segment (or separate) metal line 234 into at least metallization components 240a and 240b. In the present embodiment, grooves 241 expose portions of dielectric layer 214. In some embodiments, because metallization components 240a and 240b are formed by etching metal line 234, the geometric profiles of metallization components 240a and 240b may be different from each other, details of which are discussed below. After segmenting metal line 234, patterned mask element 235 is removed from structure 200 by a suitable method, such as plasma ashing and / or resist stripping.

[0044] In operation 15, method 10 fills recess 241 with dielectric material 242. FIG. 10A to FIG. 10C In the present embodiment, dielectric material 242 is formed to fill recess 241 and may cover metallization features 240a and 240b and the top surface of dielectric layer 220. Dielectric material 242 may be referred to as an IMD layer. Dielectric material 242 may include, for example, silicon oxide, TEOS, PSG, BPSG, a low-k dielectric material (examples provided above), another suitable dielectric material, or a combination thereof. In some embodiments, dielectric material 242 and dielectric layer 220 include different materials. In some embodiments, dielectric material 242 and dielectric layer 220 include the same material.

[0045] refer to FIG. 11A to FIG. 11C In the present embodiment, method 10 removes excess dielectric material 242 by a planarization process such as a CMP process, thereby forming a dielectric component 244 between metallization components 240a and 240b. In other words, metallization component 240a and metallization component 240b are separated from each other by dielectric component 244. For the purpose of discussion and not limitation, metallization components 240a and 240a' (as well as metallization components 240b and 240b') are substantially identical in size and geometry and are separated along direction D1. As depicted herein, when viewed along direction D2, metallization component 240a is terminated by a portion of dielectric layer 220 and dielectric component 244, and metallization component 240b is terminated by dielectric component 244. As depicted herein, when viewed along direction D2, metallization component 240a is terminated by a portion of dielectric layer 220 and dielectric component 244, and metallization component 240b is terminated by dielectric component 244. Fig. 11CAs shown, the top surfaces of the metallization components 240a and 240b, the top surface of the dielectric layer 220, and the top surface of the dielectric component 244 are substantially aligned with each other, i.e., substantially coplanar. Therefore, in this embodiment, metallization components belonging to different metal lines 234, such as metallization components 240a and 240a' or metallization components 240b and 240b', are separated from each other by the dielectric layer 220 along the direction D1. In contrast, metallization components belonging to the same metal line 234, such as metallization components 240a and 240b, are separated from each other by the dielectric component 244. In the depicted embodiment, the metallization component 240a and the metallization component 240b are defined by lengths L1 and L2 along the direction D2, respectively, which are less than the length L of the trench 225 previously defined.

[0046] References Fig. 11C The same but depicted in more detail Fig.12 , structure 200 includes at least a zeroth metal layer M0 formed by method 10 , wherein metal layer M0 includes metallization component 240 a and metallization component 240 b , which have different geometric profiles and are separated by dielectric layer 220 and / or dielectric component 244 .

[0047] In this embodiment, reference FIG. 11A to FIG. 11C and Fig.12 The metallization component 240a includes a pair of long sides defined by a portion of the dielectric layer (this portion may also be referred to as the dielectric component 220 hereinafter) along the direction D2, a short side defined by the dielectric component 244, and another short side defined by a portion of the dielectric layer 220 along the direction D1. The metallization component 240a has a first bottom angle C1 adjacent to the dielectric component 244 and a second bottom angle C2 adjacent to the dielectric layer 220, wherein the first bottom angle C1 is defined by an angle θ1, and the second bottom angle C2 is defined by an angle θ2 (corresponding to the above reference Figure 6C The angle 226) in question is defined.

[0048] In the present embodiment, the included angle θ1 of the first bottom angle C1 is less than about 90° (i.e., an acute angle), while the included angle θ2 of the second bottom angle C2 is greater than about 90° (i.e., an obtuse angle). In addition, in the present embodiment, because the barrier layer 232 is formed before the dielectric component 244 is formed, the barrier layer 232 is disposed along and in direct contact with the entire sidewall of the metallization component 240a defined by the dielectric layer 220 rather than along the opposite sidewall of the metallization component 240a defined by the dielectric component 244. In the present embodiment, a portion of the barrier layer 232 is disposed between the metallization component 240a and the underlying dielectric layer 214. Further, in the present embodiment, the metallization component 240a is in direct contact with at least one connecting via 216, thereby allowing a FEOL device disposed above the semiconductor substrate 202 to be electrically connected to the metallization component 240a.

[0049] In this embodiment, still refer to FIG. 11A to FIG. 11C and Fig.12 The metallization component 240b includes a portion of the dielectric layer 220 (ie, the dielectric component 220) along the direction D2 (eg, Fig.11A 240b is a semiconductor substrate 202 having a pair of long sides defined by the dielectric component 244 along the direction D1. In other words, the metallization component 240b is terminated by the dielectric component 244. The metallization component 240b has a third bottom angle C3 and a fourth bottom angle C4 opposite to the third bottom angle C3 along the direction D2. The third bottom angle C3 is defined by an angle θ3, and the fourth bottom angle C4 is defined by an angle θ4. In the present embodiment, the angle θ3 of the third bottom angle C3 and the angle θ4 of the fourth bottom angle C4 are both less than 90°, that is, both are acute angles, although they are different in magnitude. Therefore, the metallization component 240b is defined by a trapezoidal shape, so that its width along the direction D2 increases toward the semiconductor substrate 202. In addition, in the present embodiment, because the barrier layer 232 is formed before the dielectric component 244 is formed, the barrier layer 232 is not completely disposed along any side wall of the dielectric component 244 of the end cap metallization component 240b. Of course, the barrier layer 232 is disposed between the metallization feature 240b and the dielectric layer 214, as discussed above with respect to the metallization feature 240a. Further, in the present embodiment, the metallization feature 240b is in direct contact with at least the connecting via 216 (not shown), thereby electrically connecting the FEOL device formed above the semiconductor substrate 202 to the metallization feature 240b.

[0050] In the present embodiment, and for the reasons discussed above with respect to angle 226, the angle θ2 of the second bottom angle C2 of the metallization feature 240a formed adjacent to the dielectric layer 220 and prior to forming the metallization features 240a and 240b is greater than about 90°. In contrast, the angle θ1 of the first bottom angle C1 of the metallization feature 240a, the angle θ3 of the third bottom angle C3 of the metallization feature 240b, and the angle θ4 of the fourth bottom angle C4 of the metallization feature 240b, adjacent to the dielectric feature 244 and formed as the metallization features 240a and 240b are formed, are less than about 90°. Thus, the present embodiment provides that the dielectric feature 244 is defined by an inverted trapezoidal shape. In other words, the width defined by the dielectric feature 244 along the direction D2 decreases toward the semiconductor substrate 202. In some embodiments, the width of the bottom portion of the dielectric feature 244 is about 1 nanometer to about 13 nanometers, while the width of the top portion of the dielectric feature 244 is about 2 nanometers to about 15 nanometers; of course, the present invention is not limited thereto.

[0051] In some embodiments, method 10 may be used to form an Nth metal layer Mn above structure 200, where N is a positive integer. For example, Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A is a schematic top plan view of a semiconductor structure at various stages of method 10 according to aspects of one or more embodiments of the present invention. Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B and 20 Along the Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A Schematic cross-sectional view taken along line II-II'. Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig.18C and Fig.19C Along the Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A It should be noted that in this embodiment, method 10 is performed to form the above-mentioned Figures 2A to 12 The zeroth metal layer M0 discussed may form any subsequent metal layer, for example, a first metal layer M1 located above the zeroth metal layer M0, a second metal layer M2 located above the first metal layer M1, etc. Figures 2A to 12 and FIG. 13A to FIG. 20 The same elements of the structure 200 are denoted by the same reference numerals, and repeated description of these elements is omitted for the sake of brevity.

[0052] refer to FIG. 13A to FIG. 13CIn operation 11, method 10 receives (or is provided with) structure 200 including semiconductor substrate 202. Semiconductor substrate 202 may include various FEOL devices configured with, for example, epitaxial source / drain structures and gate structures, MEOL interconnect structures (such as, for example, connecting vias electrically coupled to VD or VG), and at least metal layer Mn-1 formed thereon and including at least metallization features 240a and 240b as discussed in detail above. In some embodiments, structure 200 also includes connecting vias 252 disposed in dielectric layer 250, which is formed above and electrically coupled to metallization features 240a and 240b. Dielectric layer 250 may include a single layer structure or a multi-layer structure. Dielectric layer 250 may be referred to as an IMD layer and may include substantially the same composition as dielectric layer 220 as described above. In some embodiments, when the connection via 252 is coupled to a metallization feature (such as metallization feature 240a or 240b) in the metal layer Mn-1, the connection via 252 is referred to as the (N-1)th via or Vn-1. For example, the connection via 252 coupled to the metallization feature 240a (or 240b; not shown) may be referred to as the zeroth via V0. In some embodiments, the connection via 252 is similar in structure to the connection via 216 and is formed by a similar process. In the depicted embodiment, the connection vias 252 are each electrically coupled to one of the metallization features 240a and 240a', so that the connection vias 252 are spaced apart from each other along the direction D1 and separated by the dielectric layer 220; of course, the present invention is not limited to this arrangement. For example, additional connection vias 252 may be formed to electrically couple with the metallization features 240b and / or 240b'.

[0053] Still reference FIG. 13A to FIG. 13C , method 10 forms dielectric layer 260 over structure 200. In the present embodiment, dielectric layer 260 is similar in composition and structure to dielectric layer 250. In some embodiments, dielectric layer 250 and dielectric layer 260 are referred to as IMDn layers, which accommodate the formation of the Nth metal layer Mn and the (N-1)th via Vn-1. For example, dielectric layer 250 and dielectric layer 260 may be referred to as first IMD1 layers, which accommodate the formation of the first metal layer M1 and the zeroth via V0 (i.e., connecting via 252).

[0054] In operation 12, method 10 forms trench 265 in dielectric layer 260. FIG. 14A to FIG. 14C In some embodiments, forming trench 265 includes first forming patterned mask element 261 over dielectric layer 260, wherein patterned mask element 261 includes at least opening 263 configured to define the size and location of trench 265 to be formed in dielectric layer 260. In some embodiments, patterned mask element 261 is similar to patterned mask element 221 in terms of structure and processing methods.

[0055] refer to FIG. 15A to FIG. 15C , the portion of the dielectric layer 260 exposed by the patterned mask element 261 is removed by a suitable etching process (such as a dry etching process, a wet etching process, an RIE process, or a combination thereof) to form a trench 265 in the dielectric layer 260. After the trench 265 is formed, the patterned mask element 261 is removed by a suitable method (such as plasma ashing and / or resist stripping). In the depicted embodiment, the trench 265 extends longitudinally along the direction D1, as shown in FIG. Fig.15A and Fig. 15B As shown, but the present invention is not limited thereto. For example, according to specific design requirements, the groove 265 can also be formed to extend longitudinally along the direction D2, that is, to extend substantially parallel to the metallization components 240a and 240b. In the depicted embodiment, the connecting via 252 and the portion of the dielectric layer 250 are exposed through the groove 265, and the sidewalls of the groove are defined by the dielectric layer 260. Similar to the above discussion about the groove 225, the opening of the bottom portion of the groove 265 (e.g., the length of the groove 225 defined along the direction D2) is smaller than the opening of the top portion of the groove 265, that is, the groove 265 is configured with an inverted trapezoidal profile, as shown in FIG. Fig. 15B In other words, Fig. 15B The angle 266 is shown to be greater than about 90°, ie, the angle 266 is an obtuse angle.

[0056] In operation 13, refer to FIG. 16A to FIG. 16C , method 10 fills trench 265 with a conductive material to form metal line 270 in dielectric layer 260. In some embodiments, the conductive material of metal line 270 includes Co, W, Ru, Al, Mo, Ti, Cu, other suitable conductive materials or combinations thereof, and can be formed by any suitable method such as CVD, PVD, ALD, electroplating, other suitable methods or combinations thereof. In some embodiments, the conductive material used to form metal line 270 is the same composition as the conductive material 230 discussed in detail above with respect to metal line 234. Subsequently, any excess conductive material is removed by a planarization process such as a CMP operation, thereby producing metal line 270. In the present embodiment, according to the same profile of trench 265 as described above, the resulting metal line 270 is configured in an inverted trapezoidal shape.

[0057] In some embodiments, barrier layer 272 is formed before filling trench 265. In some embodiments, barrier layer 272 is a single layer structure. In some embodiments, barrier layer 272 is a multi-layer structure. Barrier layer 272 may include a material similar to that of barrier layer 232 and may be formed by a process similar to that discussed with respect to barrier layer 232. In some embodiments, barrier layer 272 includes Ti, TiN, Ta, TaN, W, WN, other suitable materials, or combinations thereof.

[0058] like Fig.16A and Fig. 16B As shown, the metal line 270 extends longitudinally along the direction D1. In some embodiments, the width D of the metal line 270 defined along the direction D2 is greater than the width D' of the connecting via 252 defined along the same direction. Fig. 16C As shown. In the present embodiment, the metal line 270 is configured to contact (i.e., electrically couple) with the connecting via 252. In addition, in the present embodiment, the metal line 270 is electrically connected to the FEOL device located above the semiconductor substrate 202 through the connecting via 252, the metallization component 240a (or the metallization component 240b), and the connecting via 216. In the present embodiment, the metal line 270 includes a plurality of bottom angles, each of which is defined by an angle greater than about 90°, i.e., the angle is an obtuse angle.

[0059] In operation 14, method 10 segments (or separates) metal line 270 to form metallization feature 280a and metallization feature 280b. FIG. 17A to FIG. 17C In the present embodiment, a patterned mask element 271 is formed over the structure 200. The patterned mask element 271 includes at least one opening 273 for defining the size and location of the groove 281 to be formed in the metal line 270. As such, a portion of the metal line 270 is exposed through the opening 273. In some embodiments, the patterned mask element 271 is similar to the patterned mask element 221 in terms of structure and processing methods.

[0060] refer to 18A to 18C Method 10 performs an etching operation to remove portions of metal line 270 exposed through opening 273 of patterned mask element 271, thereby forming grooves 281 separating metal line 270 into metallization components 280a and 280b along direction D2. In this embodiment, a portion of dielectric layer 250 is exposed through grooves 281.

[0061] In operation 15, method 10 fills recess 281 with dielectric member 282. FIG. 19A to FIG. 19C In the present embodiment, dielectric component 282 fills recess 281 and provides isolation between metallization components 280a and 280b. In the present embodiment, dielectric component 282 comprises silicon oxide, TEOS, PSG, BPSG, low-k dielectric materials (examples provided above), other suitable materials, or combinations thereof. In some embodiments, dielectric component 282 comprises a material similar to the material of dielectric component 244 discussed in detail above. In some embodiments, dielectric component 282 and dielectric layer 260 comprise different materials. In some embodiments, dielectric component 282 and dielectric layer 260 comprise the same material. Fig.19CAs shown, the top surfaces of metallization features 280a and 280b, the top surface of dielectric layer 260, and the top surface of dielectric feature 282 are aligned with each other (ie, substantially coplanar). Fig.19A and Fig.19B As shown, along direction D1 , metallization components 280 a and 280 b are separated from each other by dielectric component 282 .

[0062] References Fig.19C The same but depicted in more detail Fig. 20 , structure 200 includes an Nth metal layer Mn formed by method 10. For example, a first metal layer M1 may be formed over a zeroth metal layer M0 by method 10. Of course, additional metal layers may be formed over the first metal layer M1 using method 10 provided herein.

[0063] In this embodiment, reference FIG. 19A to FIG. 19C and Fig. 20 , each of the metallization components 280a and 280b includes a pair of long sides defined by a portion of the dielectric layer 260 (the portion may alternatively be referred to as the dielectric component 260 hereinafter), one short side defined by the dielectric component 282, and another short side defined by the dielectric layer 260. In some embodiments, if one end of the metallization component 280a defines one end of the metal line 270, the end of the metallization component 280a is defined by the dielectric layer 260, while the other end of the metallization component 280a is defined by the dielectric component 282. Similarly, if one end of the metallization component 280b defines one end of the metal line 270, the end is defined by the dielectric layer 260, while the other end of the metallization component 280b is defined by the dielectric component 282.

[0064] In this embodiment, the metallization component 280a has a first bottom angle C1 adjacent to the dielectric component 282 and a second bottom angle C2 adjacent to the dielectric layer 260' (i.e., opposite to the first bottom angle C1 along the direction D1), wherein the first bottom angle C1' is defined by the angle θ1', and the second bottom angle C2' is defined by its corresponding Fig. 15B. In the present embodiment, the angle θ1' of the first bottom angle C1' is less than about 90° (i.e., an acute angle), while the angle θ2' of the second bottom angle C2' is greater than about 90° (i.e., an obtuse angle). In addition, similar to the above discussion about the barrier layer 232, because the barrier layer 272 is formed before the dielectric feature 282 is formed, the barrier layer 272 is disposed along the entire sidewall of the metallization feature 280a defined by the dielectric layer 260 rather than along the opposite sidewall of the metallization feature 280a defined by the dielectric feature 282 (i.e., in direct contact with it). In the present embodiment, a portion of the barrier layer 272 is disposed between the metallization feature 280a and the dielectric layer 250. Further, in the present embodiment, the metallization feature 280a is in direct contact with at least one connecting via 252, thereby allowing the FEOL device disposed above the semiconductor substrate 202 to be electrically connected to the metallization feature 280a.

[0065] In the depicted embodiment, reference is still made to FIG. 19A to FIG. 19C and Fig. 20 , the metallization component 280b has a geometry substantially similar to that of the metallization component 280a. For example, the metallization component 280b further includes a pair of long sides defined by a portion of the dielectric layer 260 (i.e., the dielectric component 260) along the direction D1, a short side defined by the dielectric component 282, and a short side opposite to one side defined by the dielectric layer 260. In addition, in the present embodiment, the metallization component 240b has a third bottom angle C3' adjacent to the dielectric component 282 and a fourth bottom angle C4' adjacent to the dielectric layer 260, wherein the third bottom angle C3' is defined by an angle θ3', and the fourth bottom angle C4' is defined by an angle θ4'. In the present embodiment, the angle θ3' of the third bottom angle C3' is less than about 90° (i.e., an acute angle), and the angle θ4 of the fourth bottom angle C4' is greater than about 90° (i.e., an obtuse angle). Furthermore, a portion of the barrier layer 272 is disposed between the metallization feature 280 b and the dielectric layer 250 and between the metallization feature 280 b and the dielectric layer 260, but is not disposed along the sidewalls defined by the dielectric feature 282. In addition, in the present embodiment, the metallization feature 280 b is in direct contact with one of the connecting vias 252, thereby allowing a FEOL device disposed above the semiconductor substrate 202 to be electrically connected to the metallization feature 280 b.

[0066] In the present embodiment and for the reasons discussed above with respect to angle 226, the angle θ2′ of the second bottom angle C2′ of metallization feature 280a and the angle θ4′ of the fourth bottom angle C4′ of metallization feature 280b are greater than about 90°, which are adjacent to dielectric feature 260 and formed prior to forming metallization features 280a and 280b. In contrast, the angle θ1′ of the first bottom angle C1′ of metallization feature 280a and the angle θ3′ of the third bottom angle C3′ of metallization feature 280b, which are adjacent to dielectric feature 282 and formed with the formation of metallization features 280a and 280b, are less than about 90°. Thus, the present embodiment provides that dielectric feature 282 is defined by an inverted trapezoidal shape. In other words, the width of dielectric feature 282 defined along direction D1 decreases toward semiconductor substrate 202.

[0067] According to the present embodiment, a metal line is formed in a trench provided in an IMD (or ILD) layer, the trench having a relatively larger size (i.e., a larger length) than a metallization component to be formed in the metal line, wherein the metallization component is configured as part of a BEOL interconnect structure. Therefore, any gap filling issues associated with forming metal lines at a reduced length scale can be mitigated by filling the larger size trenches. Subsequently, a metal cutting operation (including, for example, patterning and etching processes) is performed to segment the metal line through one or more grooves, thereby producing metallization components. In addition, in the present embodiment, the metallization components are electrically isolated from each other by filling the grooves with a dielectric material. In some embodiments, the dielectric material used to fill the grooves is different in composition from the IMD (or ILD) layer, thereby providing greater design freedom during device manufacturing.

[0068] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a semiconductor substrate; a metallization component located above the semiconductor substrate, a first dielectric component, a second dielectric component, and a through-hole contact. The metallization component includes a first bottom angle and a second bottom angle opposite to the first bottom angle. The first dielectric component is adjacent to the first bottom angle, and the second dielectric component is adjacent to the second bottom angle. The metallization component is between the first dielectric component and the second dielectric component. In some embodiments, the angle of the first bottom angle defined by the sidewall of the first dielectric component and the bottom surface of the metallization component is less than 90°. The through-hole contact is configured to connect the metallization component to the semiconductor substrate.

[0069] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a semiconductor substrate; a first metallization component located above the semiconductor substrate; a second metallization component located above the semiconductor substrate; a first dielectric component located between the first metallization component and the second metallization component; and a second dielectric component adjacent to the first metallization component at a side opposite to the first dielectric component. The first metallization component includes a first bottom angle and a second bottom angle opposite to the first bottom angle, and the second metallization component includes a third bottom angle and a fourth bottom angle opposite to the third bottom angle. In some embodiments, the first metallization component, the second metallization component, the first dielectric component and the second dielectric component are arranged along the same direction. In some embodiments, the first bottom angle of the first metallization component is adjacent to the first dielectric component and is defined by an acute angle. The third bottom angle of the second metallization component is adjacent to the first dielectric component and is defined by an acute angle.

[0070] In some embodiments, a method for forming a semiconductor structure is provided. The method includes the following operations. A semiconductor substrate is received. In some embodiments, a first dielectric layer is formed over the semiconductor substrate. A groove is formed in the first dielectric layer. The groove is filled to form a conductive layer in the first dielectric layer. The conductive layer is segmented to form a first conductive component and a second conductive component separated from each other by a groove. The groove is filled with a second dielectric layer so that one or both of the conductive components are terminated by a portion of the first dielectric layer and a portion of the second dielectric layer.

[0071] Some embodiments of the present application provide a semiconductor structure, including: a semiconductor substrate; a metallization component located above the semiconductor substrate, wherein the metallization component includes at least a first bottom angle and a second bottom angle opposite to the first bottom angle; a first dielectric component adjacent to the first bottom angle of the metallization component, wherein the angle of the first bottom angle defined by the sidewall of the first dielectric component and the bottom surface of the metallization component is less than 90°; a second dielectric component adjacent to the second bottom angle of the metallization component, such that the metallization component is interposed between the first dielectric component and the second dielectric component; and a through-hole contact configured to connect the metallization component to the semiconductor substrate.

[0072] In some embodiments, the angle defined by the sidewall of the second dielectric component and the bottom surface of the metallization component of the second bottom angle is greater than 90°. In some embodiments, the angle defined by the sidewall of the second dielectric component and the bottom surface of the metallization component of the second bottom angle is less than 90°. In some embodiments, the first dielectric component and the second dielectric component have the same composition. In some embodiments, the first dielectric component and the second dielectric component have different compositions. In some embodiments, the semiconductor structure further includes at least one gate structure disposed above the semiconductor substrate, wherein the gate structure and the metallization component extend longitudinally in different directions.

[0073] Some other embodiments of the present application provide a semiconductor structure, comprising: a semiconductor substrate; a first metallization component located above the semiconductor substrate, wherein the metallization component includes a first bottom angle and a second bottom angle opposite to the first bottom angle; a second metallization component located above the semiconductor substrate, wherein the metallization component includes a third bottom angle and a fourth bottom angle opposite to the third bottom angle; a first dielectric component located between the first metallization component and the second metallization component; and a second dielectric component adjacent to the first metallization component at a side opposite to the first dielectric component, wherein the first metallization component, the second metallization component, the first dielectric component and the second dielectric component are arranged along the same direction, the first bottom angle of the first metallization component is adjacent to the first dielectric component and is defined by an acute angle, and the third bottom angle C3 / C3′ of the second metallization component is adjacent to the first dielectric component and is defined by an acute angle.

[0074] In some embodiments, the second base angle is defined by an obtuse angle. In some embodiments, the semiconductor structure further comprises a third dielectric component adjacent to the second metallization component at a side opposite to the first dielectric component, such that the fourth base angle is adjacent to the third dielectric component, wherein the fourth base angle is defined by an obtuse angle. In some embodiments, the semiconductor structure further comprises a third dielectric component adjacent to the second metallization component at a side opposite to the first dielectric component, such that the fourth base angle is adjacent to the third dielectric component, wherein the fourth base angle is defined by an acute angle. In some embodiments, the first dielectric component and the second dielectric component comprise the same dielectric material. In some embodiments, the first dielectric component and the second dielectric component comprise different dielectric materials. In some embodiments, the semiconductor structure further comprises a third dielectric component adjacent to the second metallization component at a side opposite to the first dielectric component, such that the fourth base angle is adjacent to the third dielectric component, wherein the third dielectric component and the second dielectric component have the same composition, and wherein the fourth base angle is an obtuse angle. In some embodiments, the semiconductor structure further comprises a third dielectric component adjacent to the second metallization component at a side opposite to the first dielectric component, such that the fourth bottom angle is adjacent to the third dielectric component, wherein the third dielectric component has the same composition as the first dielectric component, and wherein the fourth bottom angle is an acute angle. In some embodiments, the semiconductor structure further comprises a via contact configured to electrically couple the first metallization component or the second metallization component to the semiconductor substrate.

[0075] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: receiving a semiconductor substrate, wherein a first dielectric layer is formed above the semiconductor substrate; forming a groove in the first dielectric layer; filling the groove to form a conductive layer in the first dielectric layer; segmenting the conductive layer to form a first conductive component and a second conductive component separated from each other by a groove; and filling the groove with a second dielectric layer so that one or two of the conductive components are terminated by a portion of the first dielectric layer and a portion of the second dielectric layer.

[0076] In some embodiments, the method further comprises: forming a third dielectric layer between the semiconductor substrate and the first dielectric layer; and forming a connecting via in the third dielectric layer, wherein the first conductive component and the second conductive component are formed so that the first conductive component and the second conductive component are electrically coupled to the semiconductor substrate through the connecting via. In some embodiments, the first dielectric layer and the second dielectric layer have the same composition. In some embodiments, the first dielectric layer and the second dielectric layer have different compositions. In some embodiments, the trench is filled so that the conductive layer has a first inverted trapezoidal shape, and wherein the groove is filled so that the second dielectric layer has a second inverted trapezoidal shape.

[0077] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: Semiconductor substrate; a metallization component located above the semiconductor substrate, wherein the metallization component comprises at least a first bottom angle and a second bottom angle opposite to the first bottom angle; a first dielectric component, adjacent to the first bottom corner of the metallized component, wherein an angle of the first bottom corner defined by a side wall of the first dielectric component and a bottom surface of the metallized component is less than 90°; a second dielectric component adjacent to the second bottom corner of the metallization component such that the metallization component is interposed between the first dielectric component and the second dielectric component; and a through-hole contact configured to connect the metallization feature to the semiconductor substrate, The metallization component includes a barrier layer disposed on a bottom surface of the metallization component and extending along a side wall of the second dielectric component, and the side wall of the first dielectric component has no barrier layer.

2. The semiconductor structure according to claim 1, wherein: An included angle of the second bottom angle defined by the side wall of the second dielectric component and the bottom surface of the metallization component is greater than 90°.

3. The semiconductor structure according to claim 1, wherein: An included angle of the second bottom angle defined by the side wall of the second dielectric component and the bottom surface of the metallization component is less than 90°.

4. The semiconductor structure according to claim 1, wherein: The first dielectric member and the second dielectric member have the same composition.

5. The semiconductor structure according to claim 1, wherein: The first dielectric component and the second dielectric component have different compositions.

6. The semiconductor structure according to claim 1, further comprising at least one gate structure disposed above the semiconductor substrate, wherein The gate structure and the metallization component extend longitudinally along different directions.

7. A semiconductor structure comprising: Semiconductor substrate; a first metallization component located above the semiconductor substrate, wherein the metallization component comprises a first bottom angle and a second bottom angle opposite to the first bottom angle; a second metallization component located above the semiconductor substrate, wherein the metallization component comprises a third bottom angle and a fourth bottom angle opposite to the third bottom angle; a first dielectric component located between the first metallization component and the second metallization component; and a second dielectric component adjacent to the first metallization component at a side opposite to the first dielectric component, wherein The first metallization component, the second metallization component, the first dielectric component and the second dielectric component are arranged along the same direction, The first bottom corner of the first metallization component is adjacent to the first dielectric component and is defined by an acute angle, and The third bottom angle C3 / C3' of the second metallization component is adjacent to the first dielectric component and is defined by an acute angle, The first metallization component includes a barrier layer disposed on a bottom surface of the first metallization component and extending along a side wall of the second dielectric component, and the side wall of the first dielectric component has no barrier layer.

8. The semiconductor structure according to claim 7, wherein: The second base angle is defined by an obtuse angle.

9. The semiconductor structure of claim 7, further comprising a third dielectric feature adjacent to the second metallization feature at a side opposite to the first dielectric feature, such that the fourth bottom corner is adjacent to the third dielectric feature, wherein The fourth base angle is defined by an obtuse angle.

10. The semiconductor structure of claim 7, further comprising a third dielectric feature adjacent to the second metallization feature at a side opposite to the first dielectric feature, such that the fourth bottom corner is adjacent to the third dielectric feature, wherein The fourth base angle is defined by an acute angle.

11. The semiconductor structure according to claim 7, wherein: The first dielectric member and the second dielectric member include the same dielectric material.

12. The semiconductor structure according to claim 7, wherein: The first dielectric member and the second dielectric member include different dielectric materials.

13. The semiconductor structure of claim 12, further comprising a third dielectric feature adjacent to the second metallization feature at a side opposite to the first dielectric feature, such that the fourth bottom corner is adjacent to the third dielectric feature, wherein The third dielectric member has the same composition as the second dielectric member, and wherein the fourth base angle is an obtuse angle.

14. The semiconductor structure of claim 12, further comprising a third dielectric feature adjacent to the second metallization feature at a side opposite to the first dielectric feature, such that the fourth bottom corner is adjacent to the third dielectric feature, wherein The third dielectric member has the same composition as the first dielectric member, and wherein the fourth base angle is an acute angle. 15 . The semiconductor structure of claim 7 , further comprising a via contact configured to electrically couple the first metallization feature or the second metallization feature with the semiconductor substrate.

16. A method for forming a semiconductor structure, comprising: receiving a semiconductor substrate, wherein a first dielectric layer is formed over the semiconductor substrate; forming a trench in the first dielectric layer; forming a barrier layer in the trench; filling the trench to form a conductive layer in the first dielectric layer; segmenting the conductive layer to form a first conductive component and a second conductive component separated from each other by a groove; and filling the recess with a second dielectric layer such that one or both of the conductive features are terminated by a portion of the first dielectric layer and a portion of the second dielectric layer, The barrier layer is disposed on the bottom surface of the first conductive component and extends along the side wall of the first dielectric layer, and there is no barrier layer on the side wall of the second dielectric layer.

17. The method according to claim 16, further comprising: forming a third dielectric layer between the semiconductor substrate and the first dielectric layer; as well as A connection via is formed in the third dielectric layer, wherein the first conductive component and the second conductive component are formed such that the first conductive component and the second conductive component are electrically coupled to the semiconductor substrate through the connection via.

18. The method according to claim 16, wherein: The first dielectric layer and the second dielectric layer have the same composition.

19. The method according to claim 16, wherein: The first dielectric layer and the second dielectric layer have different compositions.

20. The method according to claim 16, wherein: The trench is filled so that the conductive layer has a first inverted trapezoidal shape, and wherein the recess is filled so that the second dielectric layer has a second inverted trapezoidal shape.

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