Processes and methods for achieving high immunity to ultrafast high voltage transients across inorganic electrically isolating barriers

Abstract

A microelectronic device (100) includes a high voltage component (104) having an upper plate (132) and a lower plate (130). At a surface of a substrate (102) of the microelectronic device, the upper plate is isolated from the lower plate by a main dielectric (136) between the upper plate and a low voltage element (106). A lower bandgap dielectric layer (140) is disposed between the upper plate and the main dielectric. The lower bandgap dielectric layer includes at least one sublayer (144) of silicon nitride having an index of refraction between 2.11 and 2.23. The lower bandgap dielectric layer extends continuously around the upper plate beyond the upper plate. The lower bandgap dielectric layer has an isolated break (150) around the upper plate that is at least twice the thickness of the lower bandgap dielectric layer from the upper plate.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of microelectronic devices. More specifically, the present invention relates to high voltage components in microelectronic devices. BACKGROUND

[0002] Microelectronic devices with high voltage components that operate at potentials greater than 100 volts with a high voltage node can have a thin lower bandgap dielectric layer between the high voltage node and a main dielectric that is several microns thick that separates the high voltage node from lower voltage components. The lower bandgap dielectric layer, which is typically less than 10% of the thickness of the main dielectric, has a bandgap energy less than the main dielectric and provides reliability for the main dielectric by reducing the peak electric field at the corners of the high voltage node. The lower bandgap dielectric layer can enhance the high voltage performance and reliability of the device and the degree of enhancement can be tailored by changing the refractive index value of the layer. SUMMARY

[0003] The following simplified summary is presented in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is not intended to identify key or critical elements of the invention or to delineate the scope thereof. Rather, the sole purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.

[0004] A microelectronic device includes a high voltage component having an upper plate and a lower plate. The upper plate is isolated from the lower plate by a main dielectric formed near a surface of a substrate of the microelectronic device. A lower bandgap dielectric layer is disposed between the upper plate and the main dielectric. The lower bandgap dielectric layer includes at least one sublayer of silicon nitride. The at least one sublayer of silicon nitride has a refractive index (RI) between 2.11 and 2.24. The lower bandgap dielectric layer extends continuously around the upper plate beyond the upper plate. The lower bandgap dielectric layer has an isolation break around the upper plate that is at least twice the thickness of the lower bandgap dielectric layer from the upper plate. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 is a cross-section of an example microelectronic device including a high voltage component.

[0006] Figures 2A to 2F is a cross-section of the microelectronic device of Figure 1 depicted at successive stages of fabrication.

[0007] Figures 3A to 3C is a cross-section of the microelectronic device of Figure 1 at an isolation break depicting an alternative method of forming the isolation break and a high voltage node.

[0008] Figure 4 is a plot of breakdown voltage Vbd versus refractive index (RI).

[0009] Figure 5 is a plot of failure rate versus peak voltage Vpk at various RIs.

[0010] Figures 6 to 10 is a plot of various parameters versus RI.

[0011] Figure 11 is a cross-section of another example microelectronic device including a high voltage component.

[0012] Figure 12 is a three-dimensional (isometric) view of a multi-chip module MCM having a laminated inductor packaged with an ISO device including Figure 1 and Figure 11 a high voltage component. DETAILED DESCRIPTION

[0013] The application is described with reference to the drawings. The drawings are not drawn to scale and they are only intended to show the application. Several aspects of the application are described below with reference to exemplary applications for ease of explanation. It should be understood that numerous specific details, relationships, and methods are set forth in order to provide a full understanding of the application. However, it will be readily apparent to one skilled in the relevant arts that the application can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the application. The application is not limited by the ordering of acts or events set forth in the figures, as some acts can occur in different orders and / or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the application.

[0014] A microelectronic device includes a high voltage capacitor having an upper plate (typically, a high voltage node) and a lower plate (typically, a low voltage node). The upper plate is isolated from the lower plate by a primary dielectric between the upper plate and a low voltage element formed at a surface of a substrate of the microelectronic device. A lower bandgap dielectric layer is disposed between the upper plate and the primary dielectric. The lower bandgap dielectric layer includes at least one sublayer having a bandgap energy less than a bandgap energy of the primary dielectric. The lower bandgap dielectric layer extends continuously around the upper plate beyond the upper plate. The lower bandgap dielectric layer has an isolation break around the upper plate, the isolation break being at least twice as far from the upper plate as a thickness of the lower bandgap dielectric layer. The isolation break is located between the upper plate and the low voltage element of the microelectronic device.

[0015] As is common for IC manufacturers, efforts are being made to simplify and optimize processes to reduce cost and improve product reliability. As a result of such efforts, it was discovered that the number of metal levels could be reduced from 7 to 5 while preserving high voltage capability for almost all parameters. However, a marginal issue was discovered in which the device failed to meet the International Electrotechnical Commission 8kV Electrostatic Discharge (IEC-ESD) immunity standard (IEC / EN 61000-4-2, class 4). The IEC-ESD isolation barrier test is a system-level ultra-fast transient voltage test that is not typically performed by IC manufacturers at the component level. In an effort to improve IEC-ESD performance, a number of potential factors were investigated, such as the thickness of the lower bandgap dielectric layer, the thickness of the main capacitor dielectric, and thermal annealing of the lower bandgap dielectric layer, but none resulted in a solution.

[0016] However, the present inventors discovered that when the silicon nitride has a lower refractive index (RI), there is an unexpected and dramatic improvement in the IEC-ESD breakdown voltage performance of high voltage capacitors that use a silicon nitride layer in the lower bandgap layer. A lower RI would reduce protection from 1000 times slower transient voltage "SURGE", and thus, it would be counter-intuitive that a lower RI would result in an increase in the ultra-fast transient breakdown voltage of such capacitors. Figure 4 The IEC-ESD breakdown voltage (Vbd) was presented as a function of the RI of representative non-production test structures, where the IEC-ESD Vbd was obtained using transient voltage pulses that rise in 1.2 ns and fall in 1.2 ns, after 12 pulses of positive polarity, plus 12 pulses of negative polarity. The Vbd characteristic shows a clear increase from about 10 kV to about 13 kV when the RI of the silicon nitride layer is reduced from 2.26 to 2.08. Figure 5 The "SURGE" capability was presented as a function of the failure rate of representative capacitive isolation devices for five values of RI, obtained using 25 voltage pulses that rise in 1.2 μβ, fall in 50 μβ, followed by 25 pulses of opposite polarity with similar rise and fall times, as specified by the enhanced isolation standard VDE-0884-11. These plots show that, while the best "SURGE" performance is achieved for higher RI values (> 2.23), the best IEC-ESD capability is achieved when the RI is less than 2.23, for example, about 2.0 to 2.1. Thus, the present inventors have determined that the SiN layer under the top high voltage (HV) capacitor plate provides excellent HV performance, but can not be optimized for both "SURGE" capability and IEC-ESD transient capability.

[0017] As detailed below, the present inventors have determined that the use of silicon nitride in a lower bandgap dielectric layer, with a refractive index ranging from 2.11 to 2.23, such as 2.17 ± 0.04, can balance surge protection and IEC-ESD performance. A CVD process flowing SiH4+ NH3+ Ar in a plasma can be used. The gas flow ratio of SiH4 / NH3is selected to obtain a refractive index of about 2.17. Temperature, RF power, and chamber pressure also affect the RI. Figures 6 to 10 A general trend is shown for the RI dependence on key manufacturing parameters that can be applicable to a variety of different deposition tools, where Figure 6 The relationship of the RI to the silane flow rate is presented; Figure 7 The relationship of the RI to the ammonia flow rate is presented; Figure 8 The relationship of the RI to the spacing between the reactant showerhead and the substrate surface is presented; Figure 9 The relationship of the RI to the deposition pressure is presented; and Figure 10 The relationship of the RI to the deposition power is presented.

[0018] Turning to Figure 1 , a cross-section of an example microelectronic device 100 containing high voltage components is presented. Various aspects of the device 100 are described without implied limitation so as to provide context for the lower bandgap dielectric layer described below. In the present example, the microelectronic device 100 is described as an integrated circuit 100. Other configurations for the microelectronic device 100, such as a discrete component or hybrid circuit, are within the scope of the present example. The microelectronic device 100 is formed on a substrate 102, such as a silicon wafer. The microelectronic device 100 includes a high voltage component 104 (depicted as a high voltage capacitor 104) in Figure 1 and can include a low voltage component 106 (depicted as a metal oxide semiconductor (MOS) transistor 106 with a gate dielectric layer 110 thickness less than 70 nm) that operates at 24 volts or less. The microelectronic device 100 can optionally include a Faraday cage 108 surrounding the high voltage component 104.

[0019] A field oxide 112 can be formed in the substrate 102 to laterally isolate elements of the microelectronic device 100. A pre-metal dielectric (PMD) layer 114 is formed over the substrate 102. Contacts 116 are disposed through the PMD layer 114 to provide electrical connections for the low voltage component 106 and the Faraday cage 108.

[0020] A plurality of metal levels 118 are disposed above the PMD layer 114. The metal levels 118 include metal interconnects 120 connected to the low voltage components 106 and the Faraday cage 108. Between the metal interconnects 120 in each metal level 118 is disposed a metal- in-dielectric (IMD) layer 122 of silicon dioxide-based dielectric material. Disposed between the metal levels 118 are via levels 124. The via levels 124 include metal vias 126 connecting the metal interconnects 120. The metal vias 126 are disposed through an interlayer dielectric (ILD) layer 128 of silicon dioxide-based dielectric material in each via level 124. Other dielectric materials for the IMD layers 122 and the ILD layers 128, such as low-k materials, are within the scope of the present example. The IMD layers 122 and the ILD layers 128 can include cap and etch stop layers of different dielectric materials, such as silicon nitride. The IMD layers 122 can be portions of the ILD layers 128, depending on the process sequence used to form the plurality of metal levels 118.

[0021] A lower plate 130 of the high voltage component 104, depicted as a lower plate 130 of the high voltage capacitor 104, is disposed in one of the metal levels 118, such as the first metal level 118 depicted in Figure 1 A lower plate 130 of the high voltage component 104, depicted as a lower plate 130 of the high voltage capacitor 104, is disposed in one of the metal levels 118, such as the first metal level 118 depicted in Figure 1 A lower plate 130 of the high voltage component 104, depicted as a lower plate 130 of the high voltage capacitor 104, is disposed in one of the metal levels 118, such as the first metal level 118 depicted in

[0022] A lower bandgap dielectric layer 140 is disposed between the bulk dielectric 136 and the upper plate 132, opposite the lower plate 130. The lower bandgap dielectric layer 140 includes at least one sublayer of dielectric having a bandgap energy less than that of a portion of the bulk dielectric 136 adjacent the upper plate 132. In this example, the lower bandgap dielectric layer 140 includes a first sublayer 142 of silicon oxynitride 200 nm to 600 nm thick in contact with the bulk dielectric 136, and a second sublayer 144 of silicon nitride 400 nm to 800 nm thick (e.g., 600 nm) between and in contact with the first sublayer 142 and the upper plate 132. The first sublayer 142 of silicon oxynitride has a lower bandgap energy than the silicon dioxide-based dielectric material of the bulk dielectric 136, and the second sublayer 144 of silicon nitride has a lower bandgap energy than the first sublayer 142. The lower bandgap dielectric layer 140 extends beyond the upper plate 132, continuously around the upper plate 132, with a distance 146 that is at least twice the thickness 148 of the lower bandgap dielectric layer 140. There is an isolation break 150 in the lower bandgap dielectric layer 140 that is in contact with the upper plate 132; the isolation break 150 encircles the upper plate 132. The location of the isolation break 150 is no closer to the upper plate 132 than the distance 146. An optional low voltage portion 152 of the lower bandgap dielectric layer 140 can be disposed outside the isolation break 150, such that the low voltage portion 152 of the lower bandgap dielectric layer 140 is separated from the lower bandgap dielectric layer 140 that is in contact with the upper plate 132 by the isolation break 150. The low voltage portion 152 of the lower bandgap dielectric layer 140 can contact low voltage elements of the microelectronic device 100 that extend to the lower bandgap dielectric layer 140, such as the Faraday cage 108. The isolation break 150 is located between the upper plate 132 and any low voltage elements of the microelectronic device 100, such that the lower bandgap dielectric layer 140 that is in contact with the upper plate 132 does not contact any low voltage elements. The isolation break 150 advantageously prevents leakage current through the interface of the lower bandgap dielectric layer 140 from the upper plate 132 to low voltage elements of the microelectronic device 100. The low voltage portion 152 of the lower bandgap dielectric layer 140, if present, is laterally separated from the lower bandgap dielectric layer 140 that is in contact with the upper plate 132 by an isolation distance 154 that is at least 1 pm, and can be 10 pm to 25 pm, to advantageously provide process margin in photolithography processes used to form the isolation break 150. Forming the lower bandgap dielectric layer 140 with the isolation break 150 is particularly advantageous for examples of high voltage components 104 that operate at 1000 volts or higher, as such components would have low reliability without the lower bandgap dielectric layer 140 with the isolation break 150, thereby precluding useful embodiments of the microelectronic device 100.

[0023] The upper plate 132 is disposed in an upper IMD layer 156 that covers the edge of the lower bandgap dielectric layer 140 at the isolation break 150. The upper IMD layer 156 can include silicon dioxide, similar to the bulk dielectric 136.

[0024] The upper plate 132 can be connected to, or can be part of, the pads 158 of the microelectronic device 100, as depicted in Figure 1 A protective overcoat 160 of polyimide, silicon nitride, silicon oxynitride, and / or silicon dioxide can be disposed over the upper plate 132, or can overlap the edges of the upper plate 132, as depicted in Figure 1 Electrical connections 162 to the upper plate 132 can be made by wirebonds 162. The low voltage portion 152 of the lower bandgap dielectric layer 140 can advantageously shield the low voltage components 106 from electrical fields from the electrical connections 162 to the upper plate 132.

[0025] During operation of the microelectronic device 100, when a high voltage potential difference is applied between the upper plate 132 and the lower plate 130, the lower bandgap dielectric layer 140 advantageously provides reliability for the main dielectric 136 by reducing the electrical field near the corners of the upper plate 132. The isolation break 150 advantageously provides reliability by preventing leakage current from the upper plate 132 to the low voltage elements of the microelectronic device 100 through the lower bandgap dielectric layer 140.

[0026] Figures 2A to 2F is a cross-section of a microelectronic device of Figure 1 depicted in successive stages of fabrication. Referring to Figure 2A , a microelectronic device 100 is formed on a substrate 102, which can be a silicon wafer or other semiconductor substrate, or can be a dielectric substrate such as sapphire or alumina ceramic. In versions of the present example in which the substrate 102 is a semiconductor substrate, a field oxide 112 can be formed to laterally isolate elements of the microelectronic device 100 in the substrate 102. The field oxide 112 can be formed by a shallow trench isolation (STI) process, a local oxidation of silicon (LOCOS) process, or other method.

[0027] Low voltage components 106 are formed in and on the substrate 102. The low voltage components 106 can be near the high voltage components 104, and can be separated from the high voltage components 104 by a Faraday cage 108.

[0028] A PMD layer 114 is formed over the substrate 102. The PMD layer 114 can include a dielectric layer stack including a 10 nm to 100 nm thick silicon nitride or silicon dioxide PMD liner formed by a plasma-enhanced chemical vapor deposition (PECVD) process, a 100 nm to 1000 nm thick layer of silicon dioxide, phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG) formed by a PECVD process, typically planarized by a chemical mechanical polishing (CMP) process, and an optional PMD cap layer (typically 10 nm to 100 nm of a hard material such as silicon nitride, silicon carbide nitride, or silicon carbide formed by another PECVD process). Contact holes are formed through the PMD layer 114 to expose the substrate 102, for example in the low voltage components 106 and the Faraday cage 108, and possibly in the high voltage components 104. Contacts 116 are formed in the contact holes to provide electrical connections. The contacts 116 can be formed by forming liners of titanium and titanium nitride using a sputtering process and a CVD process, respectively, forming a layer of tungsten on the liners using a CVD plasma process to fill the contact holes, and removing the tungsten and the liners from the top surface of the PMD layer 114 using an etchback and / or CMP process.

[0029] The metal levels 118 and IMD layers 122, and the via levels 124 and ILD layers 128, can be formed by any of several methods. In one version of the example, any of the metal levels 118 can be formed by forming an aluminum-based interconnect metal layer over the underlying PMD layer 114 or ILD layer 128. The aluminum-based interconnect metal layer can include an adhesion layer of titanium, titanium tungsten, or titanium nitride, an aluminum layer containing a few percent of silicon, titanium, and / or copper, having a thickness of 200 nm to a few microns, and possibly including an anti-reflective layer of titanium or titanium nitride over the aluminum layer. An interconnect etch mask including photoresist is formed over the interconnect metal layer, covering areas of the metal interconnects 120, and an etching process such as a plasma etch using chlorine radicals is used to remove the interconnect metal layer in areas exposed by the interconnect etch mask, leaving the metal interconnects 120. Corresponding IMD layers 122 are subsequently formed between the metal interconnects 120. The IMD layers 122 can be formed by depositing a layer of silicon dioxide-based dielectric material using a PECVD process of tetraethyl orthosilicate (also known as tetraethoxysilane (TEOS)), and subsequently planarizing the dielectric material by a resist etchback process or a CMP process, such that the IMD layers 122 cover the metal interconnects 120, as shown in FIG. 1C. The IMD layers 122 can include a silicon dioxide-based dielectric material formed by spin coating the microelectronic device 100 with a solution containing methylsilsesquioxane (MSQ) and subsequently baking the solution to remove volatile materials. Figure 1

[0030] ​In another version of the present case, any of the metal levels 118 can be formed by a single damascene process, in which the IMD layer 122 is first formed, and interconnect trenches are formed through the IMD layer 122 in areas for the metal interconnects 120. The IMD layer 122 can be a stack of dielectric layers formed by sequential PECVD processes, including an etch stop layer, a main layer, and a cap layer. A liner of tantalum nitride is formed over the IMD layer 122 by a CVD plasma process, extending as a conformal liner into the interconnect trenches. A seed layer of sputtered copper is formed on the liner, and electroplated copper is formed on the seed layer to fill the interconnect trenches. A copper CMP process removes the copper and the liner from the top surface of the IMD layer 122, leaving the metal interconnects 120 in the interconnect trenches.

[0031] In another version, the metal interconnects 120 can be formed by a lift-off process, in which a lift-off pattern of organic material such as photoresist is formed over the corresponding lower ILD layer 128, which has openings for the metal interconnects 120. A metal layer for the metal interconnects 120 is deposited over the lift-off pattern and onto the ILD layer 128 in the openings. Subsequently, the lift-off pattern is removed using a solvent spray, taking the metal layer on the lift-off pattern with it, leaving the metal interconnects 120.

[0032] In one version of the present case, any of the via levels 124, including the corresponding vias 126 and ILD layers 128, can be formed by similar processes described for the contacts 116. In another version, the via levels 124, including the corresponding vias 126 and ILD layers 128, can be formed by a single damascene process, as described for the metal levels 118 including the metal interconnects 120 and the IMD layers 122.

[0033] In another version of the present case, any of the metal levels 118 and the corresponding lower via levels 124 can be formed simultaneously by a dual damascene process. In a dual damascene process, an ILD layer 128 is formed and a corresponding IMD layer 122 is formed over the ILD layer 128. Interconnect trenches are formed through the IMD layer 122 and vias are formed through the ILD layer 128 by a sequence of patterning and etching steps, which can be, for example, trench-first, via-first, or partial via-first. A liner, a seed layer, and electroplated copper fill metal are formed over the IMD layer 122, simultaneously filling the vias and the interconnect trenches. A subsequent copper CMP process removes the copper and the liner from the top surface of the IMD layer 122, leaving the metal interconnects 120 in the interconnect trenches and the vias 126 in the vias.

[0034] In another version of the present example, any of the metal levels 118 can be formed by a masked electroplating process. An adhesion layer of titanium and a seed layer of copper are formed on the top surface of the associated ILD layer 128. The adhesion layer makes electrical contact with the underlying instance of the via 126 or the contact 116. A photoresist plating mask is formed over the seed layer to expose the area for the metal interconnect 120. A plating operation plates copper on the seed layer to the desired thickness in the area exposed by the plating mask. The plating mask is removed, for example, by ashing or dissolving in a solvent. The seed layer and the adhesion layer outside the plated copper are removed, for example, by a reactive ion etching (RIE) process, leaving the plated copper with the underlying seed layer and adhesion layer to provide the metal interconnect 120.

[0035] The lower plate 130 of the high voltage component 104 is formed in one of the lower metal levels 118, possibly the lowest metal level 118. The lower plate 130 can be formed at the same time as the metal interconnects 120 in the metal levels 118. Alternatively, the lower plate 130 can be formed separately from the metal interconnects 120. The ILD layers 128 and the IMD layers 122 above the lower plate 130 provide the main dielectric 136 of the high voltage component 104.

[0036] Reference is made to Figure 2B A lower bandgap dielectric layer 140 is formed over the ILD layers 128 and the IMD layers 122 that contain the main dielectric 136 of the high voltage component 104. The lower bandgap dielectric layer 140 includes at least one layer of silicon nitride. In the present example, the lower bandgap dielectric layer 140 is formed by a PECVD reaction using bis(tert-butylamino)silane (BTBAS) and TEOS or N2O and NH3 to form a first sublayer 142 of 200 nm to 600 nm thick silicon oxynitride (sometimes referred to as nitrided silicon oxide, or SiON). The atomic fractions of nitrogen and oxygen in the first sublayer 142 can be selected by adjusting the relative gas flow of the nitrogen-containing and oxygen-containing feed gases. The lower bandgap dielectric layer 140 is continued by a CVD process of SiH4 + NH3 + Ar flowing in a plasma at about 375 degrees Celsius to form a second sublayer 144 of 400 nm to 800 nm thick silicon nitride. In other versions of the present example, the lower bandgap dielectric layer 140 can consist of only one sublayer of silicon nitride. There are several key parameters that affect the RI, such as gas ratio, RF power, and pressure. Figures 6 to 10 The interaction between the RI and the various parameters is shown. The RI of silicon nitride is in the range of 2.11 to 2.24 and can be formed using the parameters shown in Table 1.

[0037] Table 1

[0038]

[0039]

[0040] In further versions, the lower bandgap dielectric layer 140 can have more than two sub-layers. Dielectric materials that can be used for the sub-layers of the lower bandgap dielectric layer 140 can include the dielectric materials of Table 2.

[0041] Table 2

[0042] Dielectric material Band gap range (eV) Silicon oxide nitride ～7.5 Silicon nitride 4.7 to ~ 6 Silicon oxide carbide nitride Higher than silicon carbide nitride Silicon carbide nitride 3.8 to 4.7 Tantalum pentoxide 3.8 to 5.3 Diamond-like carbon 5.5 Titanium dioxide 3.3 Aluminium nitride 6.2 Aluminium oxide 6.5 to 7.0 Silicon monoxide Lower than SiO2 Zinc oxide 3.4

[0043] The bandgaps of the variable stoichiometry materials of Table 2, such as silicon oxynitride, silicon oxycarbonitride, and silicon carbonnitride, can be different, depending on the relative atomic fractions of oxygen, nitrogen, and / or carbon. Versions of the silicon-containing dielectric materials that are rich in silicon can provide inferior performance as sub-layers of the lower bandgap dielectric layer 140 due to lower than desired electrical resistance.

[0044] Referring to Figure 2C , the via 126 through the lower bandgap dielectric layer 140 is formed after the lower bandgap dielectric layer 140 is formed. The via 126 through the lower bandgap dielectric layer 140 can be formed by any of the methods described with reference to Figure 2A .

[0045] Referring to Figure 2D , the metal interconnects 120 and the upper plate 132 are formed above the lower bandgap dielectric layer 140. The metal interconnects 120 above the lower bandgap dielectric layer 140 can be formed using any of the methods described with reference to Figure 2A . The upper plate 132 can be formed simultaneously with the metal interconnects 120 above the lower bandgap dielectric layer 140, or can be formed separately.

[0046] Referring to Figure 2E , the isolation break 150 is formed through the lower bandgap dielectric layer 140. The isolation break 150 can be formed by forming an isolation etch mask above the lower bandgap dielectric layer 140, the metal interconnects 120 above the lower bandgap dielectric layer, and the upper plate 132, and etching through the lower bandgap dielectric layer 140 into the lower ILD layer 128, leaving the lower bandgap dielectric layer 140 below the upper plate 132 and a low voltage portion 152 of the lower bandgap dielectric layer 140. Other methods of forming the isolation break 150 are discussed below.

[0047] Referring to Figure 2F , the IMD layer 156 is formed above the lower bandgap dielectric layer 140, abutting the isolation break 150. The IMD layer 156 above the lower bandgap dielectric layer 140 can be formed by any of the methods described with reference to Figure 2AAny of the described methods forms. Forming the IMD layer 156 to abut the isolation break 150 advantageously prevents leakage current from passing through the interface of the lower bandgap dielectric layer 140 from the upper plate 132 to low voltage components of the microelectronic device 100. Formation of the microelectronic device 100 continues with formation of the protective overcoat 160 to subsequently provide Figure 1 structure.

[0048] Figures 3A to 3C is Figure 1 a cross-section of the microelectronic device at the isolation break, depicting an alternative method of forming the isolation break and high voltage node. Referring to Figure 3A , the microelectronic device 100 is fabricated as described with reference to Figures 2A to 2C . The lower bandgap dielectric layer 140 is formed over the ILD layer 128 at the top of the host dielectric 136. In this example, the lower bandgap dielectric layer 140 includes a first sub-layer 142 formed on the ILD layer 128 and a second sub-layer 144 formed on the first sub-layer 142. After forming the second sub-layer 144, an oxidation process, such as a N2O plasma process, forms an oxygen-rich top region 164 at the top of the second sub-layer 144. The oxygen-rich top region 164 can be less than 30 nm thick. A lower region 166 of the second sub-layer 144 is substantially unaltered by the oxidation process.

[0049] An interconnect metal layer 168 is formed on the lower bandgap dielectric layer 140. The interconnect metal layer 168 includes an adhesion layer 170 of titanium, titanium tungsten, or titanium nitride 2 nm to 15 nm thick formed by a sputtering process or a reactive sputtering process. The interconnect metal layer 168 further includes an aluminum layer 172 formed on the adhesion layer 170. The aluminum layer 172 can include up to 2% silicon, titanium, and / or copper. The aluminum layer 172 can be 200 nm to several microns thick, formed by a sputtering process. The interconnect metal layer 168 also includes an anti-reflective layer 174 of titanium nitride 10 nm to 20 nm thick formed by a reactive sputtering process on the aluminum layer 172. Other configurations for the interconnect metal layer 168 are within the scope of this example.

[0050] An interconnect mask 176 is formed over the interconnect metal layer 168 to cover regions of the upper plate 132 and metal interconnects 120 over the lower bandgap dielectric layer 140. The interconnect mask 176 can include photoresist formed by a photolithography process, and can also include an anti-reflective layer and / or a hard mask layer. Figure 1 depicts a portion of the interconnect mask 176 over the subsequently formed upper plate 132. Figure 3A

[0051] Referring to Figure 3B , an interconnect etch process removes the interconnect metal layer 168 in the regions exposed by the interconnect mask 176, leaving the lower bandgap dielectric layer 140 over the upper plate 132 and metal interconnects 120.​Figure 1 the upper plate 132 and the metal interconnect 120. In this example, the interconnect etch process further removes a portion, but not all, of the second sub-layer 144 of the lower bandgap dielectric layer 140 in the region exposed by the interconnect mask 176. The interconnect mask 176 is then removed, for example by an ashing process. After the interconnect etch process is complete and the interconnect mask 176 is removed, at least 10 nm of the second sub-layer 144 remains in the region exposed by the interconnect mask 176.

[0052] Referring to Figure 3C , an isolation etch mask 178 is formed over the upper plate 132 and the lower bandgap dielectric layer 140 to expose a region for the isolation break 150. The isolation etch mask 178 can include photoresist formed by a photolithography process. The region for the isolation break 150 is laterally separated from the upper plate 132 by a distance 146, as described with reference to Figure 1 . A width 154 of the region for the isolation break 150 is described with reference to Figure 1 . The width 154 can be 10 pm to 25 pm to advantageously facilitate the photolithography process for forming the isolation etch mask 178 with a desired level of process margin. An isolation etch process removes the first sub-layer 142, the second sub-layer 144, and a portion of the ILD layer 128 in the region exposed by the isolation etch mask 178. The isolation etch mask 178 is then removed, for example by an ashing process.

[0053] Figure 11 is another example microelectronic device 1100 that shares some characteristics with the microelectronic device 100 of Figure 1 . In Figure 11 , the microelectronic device 1100 shares some characteristics with the microelectronic device 100 of Figure 1Structural features similar to those of the structure of Figure 11 retain the same feature labels, with the understanding that various material substitutions can be made within the scope of the foregoing discussion. The substrate 102 is omitted to conserve space. The device 1100 includes five metal levels M1-M5 and four via levels. For clarity, the feature indices of the metal elements and vias are omitted. As described previously, the metal features and vias are located within IMD layers 122 and ILD layers 128. For clarity, these dielectric layers are represented by the combined indices 122 / 128. The high voltage capacitor 104 includes a lower plate 130 formed in the M2 level and an upper plate 132 formed in the M5 level. The high voltage capacitor 104 is surrounded by a Faraday cage 1110 that includes a continuous chain from M5 to Ml through the associated via levels, and is grounded to the underlying substrate at the referenceless contacts. Circuitry 1120 outside the Faraday cage 1110 can support other attributes of the device, such as an analog-to-digital converter, digital transmission across the high voltage capacitor 104, or data reception. The scribe seal structure 1130 includes stacked M1-M5 features and associated vias. An upper IMD layer 156, e.g., 1.5 μm of SiO2, covers the M5 level, as described previously. A first protective overcoat 160', e.g., 2.8 μm of SiON, covers the upper IMD layer 156, and a second protective overcoat 160", e.g., 10 μm of polyimide, covers the first protective overcoat 160'. In this example, wirebonds 162 are made directly to the upper plate 132.

[0054] A lower bandgap dielectric layer 140 is located between the M5 features, including the upper plate 132, and the dielectric layer 122 / 128 on which the M5 level is formed. In this example, the lower bandgap dielectric layer 140 includes a first sublayer 142 of SiON and a second sublayer 144 of silicon nitride, both of which can be formed as described previously. As described previously, the lower bandgap dielectric layer 140 extends continuously around the upper plate 132, over the upper plate 132 a distance 146, and ends at an isolated break 152 around the upper plate 132. A low voltage portion 152 of the lower bandgap dielectric layer 140 is separated from the portion of the lower bandgap dielectric layer 140 extending from the upper plate 132 by a distance 154. The low voltage portion 152 extends to and beyond the scribe seal 1130.

[0055] Figure 12Another example is shown including a multi-chip module (MCM) 1200 including one or more high voltage capacitors according to examples described herein. A package substrate 1210 supports, for example, multiple device dies, and a laminated transformer 1240 that can provide isolated power delivery between device dies 1220, 1230. Each of the first device die 1220 and the second device die 1230 can include one or more instances of a high voltage capacitor 1250 constructed according to principles described herein. The device dies 1220, 1230 can also include one or more instances of a high voltage capacitor (not shown) constructed according to principles described herein. In particular, the high voltage capacitor 1250 includes the previously described lower bandgap dielectric layer 140. The device 1200 is expected to benefit from improved high voltage performance associated with the silicon nitride sublayer 144 having a lower bandgap energy and a refractive index in the range of 2.11 to 2.24 (e.g., 2.14 ± 0.04). The high voltage capacitor 1250 improves the overall IEC-ESD performance of the system compared to using a Si02 capacitor that does not include the lower bandgap dielectric layer 140. An improvement of 2300V can be obtained with this combination of laminated transformer and device dies 1220, 1230. Other types of MCMs with different device arrangements and / or functionality are within the scope of the present disclosure.

[0056] While various embodiments of the application have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the application. Therefore, the breadth and scope of the present application should not be limited by any of the above described embodiments. Rather, the scope of the application should be defined in accordance with the following claims and their equivalents.

Claims

1. A microelectronic device comprising: The lower plate of the high-voltage capacitor of the microelectronic device; The upper plate of the high-voltage capacitor; A main dielectric material with a thickness of at least 2 micrometers is disposed between the lower plate and the upper plate; as well as A lower bandgap dielectric layer is disposed between the main dielectric and the upper plate, wherein: The lower bandgap dielectric layer includes at least a first sublayer of silicon nitride with a refractive index in the range of 2.11-2.23; The lower bandgap dielectric layer extends continuously around the upper plate and beyond the upper plate for a certain distance, the distance being at least twice the thickness of the lower bandgap dielectric layer; The lower bandgap dielectric layer has an isolation break, causing the lower bandgap dielectric layer to be discontinuous at the isolation break; and The isolation break surrounds the upper plate.

2. The microelectronic device according to claim 1, wherein the lower bandgap dielectric layer further comprises a second sublayer disposed between the first sublayer and the lower plate, the bandgap energy of the second sublayer being less than the bandgap energy of the main dielectric.

3. The microelectronic device of claim 2, wherein the portion of the main dielectric adjacent to the lower bandgap dielectric layer comprises a silicon dioxide-based dielectric material, and the second sublayer comprises silicon oxide nitride.

4. The microelectronic device according to claim 1, wherein the main dielectric comprises a plurality of internal metal dielectric layers, i.e., IMD layers and interlayer dielectric layers, i.e., ILD layers, wherein the IMD layers comprise silicon dioxide-based dielectric materials, and the ILD layers comprise silicon dioxide-based dielectric materials.

5. The microelectronic device according to claim 1, further comprising a low-voltage component disposed outside the isolation break.

6. The microelectronic device of claim 5, wherein the low-voltage component is a metal-oxide-semiconductor transistor, i.e., a MOS transistor, having a gate dielectric layer less than 70 nm thick.

7. The microelectronic device according to claim 1, wherein the lower bandgap dielectric layer includes a portion disposed outside the isolation break.

8. The microelectronic device of claim 7, wherein the portion of the lower bandgap dielectric layer disposed outside the isolation break contacts a low-voltage element of the microelectronic device.

9. The microelectronic device of claim 1, wherein the edge of the lower bandgap dielectric layer at the isolation break is covered with a dielectric material.

10. The microelectronic device of claim 1, wherein the silicon nitride of the first sublayer has a thickness of about 600 nm.

11. A method of forming a microelectronic device, comprising: The lower plate forms the high-voltage component of the microelectronic device; A main dielectric layer at least 2 micrometers thick is formed adjacent to the lower plate; A lower bandgap dielectric layer is formed adjacent to the main dielectric layer and opposite to the lower plate, the lower bandgap dielectric layer comprising a silicon nitride layer with a refractive index in the range of 2.11-2.23; An upper plate is formed adjacent to the lower bandgap dielectric layer of the high-voltage component; as well as An isolation break is formed in the lower bandgap dielectric layer such that the lower bandgap dielectric layer is discontinuous at the isolation break and the isolation break surrounds the upper plate.

12. The method of claim 11, wherein the step of forming the lower bandgap dielectric layer further comprises forming a silicon oxynitride layer between the silicon nitride and the main dielectric.

13. The method of claim 12, wherein the portion of the primary dielectric adjacent to the lower bandgap dielectric layer comprises a silicon dioxide-based dielectric material.

14. The method of claim 11, wherein the main dielectric comprises a plurality of IMD layers and ILD layers, the IMD layers comprising a silicon dioxide-based dielectric material, and the ILD layers comprising a silicon dioxide-based dielectric material.

15. The method of claim 11, further comprising forming a low-pressure component disposed outside the isolation break.

16. The method of claim 15, wherein the low-voltage component is a MOS transistor having a gate dielectric layer less than 70 nm thick.

17. The method of claim 11, wherein the step of forming the isolation break includes removing the lower bandgap dielectric layer in the region for the isolation break, leaving a portion of the lower bandgap dielectric layer disposed outside the isolation break.

18. The method of claim 17, wherein the portion of the lower bandgap dielectric layer disposed outside the isolation break contacts a low-voltage element of the microelectronic device.

19. The method of claim 11, further comprising forming a dielectric material on the edge of the isolation break in the lower bandgap dielectric layer.

20. A multi-chip module device, comprising: Each has a first semiconductor die and a second semiconductor die, each having a high-voltage capacitor, wherein the high-voltage capacitor has: Lower board; upper plate; The main dielectric material disposed between the lower plate and the upper plate; and A silicon nitride layer is disposed between the main dielectric and the upper plate, wherein: The refractive index of the silicon nitride layer is in the range of 2.11-2.23; The silicon nitride layer extends continuously around the upper plate and beyond the upper plate for a certain distance, the distance being at least twice the thickness of the silicon nitride layer; The silicon nitride layer has an isolation break, causing the silicon nitride layer to be discontinuous at the isolation break; and The isolation break surrounds the upper plate; and A laminated inductor is connected in parallel with an isolation barrier provided by the high-voltage capacitors of the first semiconductor die and the second semiconductor die.

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