Flash Array

Abstract

The present disclosure provides a flash memory array. The flash memory array according to the present disclosure includes: a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction; a plurality of word line groups extending in the row direction; and a plurality of bit line groups extending in the column direction, wherein a flash memory cell pair is arranged at the intersection of the word line group and the bit line group, and the flash memory cell pair includes a first flash memory cell and a second flash memory cell adjacent in the row direction and sharing the same bit line group. The flash memory array according to the present disclosure can increase the arrangement density of the bit lines and reduce the parasitic resistance of the bit lines without increasing the size of the array. In addition, compared with the flash memory array of the prior art, the flash memory array according to the present disclosure also has better process compatibility and miniaturization characteristics.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a flash memory array. Background Art

[0002] Flash memory, also known as flash memory, is a non-volatile memory, which means that the stored data will not be lost even when the power is disconnected. It is particularly suitable for fields such as mobile communications and computer storage components. In addition, some flash memories also have high-density storage capabilities, which are suitable for applications such as large-capacity mobile storage media.

[0003] Traditional flash memory uses a floating gate cell structure. The floating gate non-volatile memory originated from the MIMIS (Metal-Insulator-Metal-Insulator-Semiconductor) structure proposed by D. Kahng and S. Sze in 1967. This structure adds a metal floating gate and an ultra-thin tunneling oxide layer to the traditional MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), thereby using the metal floating gate to store charge. Based on this, Masuoka et al. first proposed the concept of flash memory in 1984, that is, to achieve high-speed erasing capability by erasing and writing bit by bit by sector, and eliminate the selection tube required in EEPROM (Erasable Programmable Read-only memory), thereby having a smaller storage unit size. After the emergence of flash memory, it has developed rapidly with its high writing speed, high integration and superior performance. In 1988, Intel proposed the ETOX structure flash memory cell (ETOX: Electron Tunneling Oxide device), which has become the development foundation of most floating gate flash memory cell structures to date.

[0004] However, floating gate flash memory has the following disadvantages: the process is relatively complex; the existence of the floating gate structure in the flash memory cell increases the vertical height of the gate structure, which is not conducive to proportionally reducing the process size and unit area; at the same time, due to the conductivity of the floating gate, the stored charge can move freely in the floating gate, which is not conducive to improving the reliability of the memory. In order to solve the problems of complex process and poor reliability of floating gate flash memory, researchers proposed a charge trapping memory (CTM: Charge-Trapping-Memory) that uses silicon nitride medium to store charge, also known as SONOS (Silicon-Oxide-Nitride-Oxide-Silicon: Silicon-Oxide-Nitride-Oxide-Silicon) flash memory. Based on this, B.Eitan et al. proposed a two-bit storage cell structure NROM (Nitride-Read-Only-Memory: Silicon Nitride Read-Only Memory) in 2000. This cell structure uses the non-conductive properties of the insulating silicon nitride storage medium to realize two storage bits at the source and drain ends of a storage transistor respectively. However, this cell structure has the disadvantages that the two storage bits interfere with each other and the device size cannot be reduced.

[0005] However, existing floating gate ETOX flash memories and SONOS NROM flash memories have problems such as inability to reduce process size, large cell area, high write power consumption and large array area overhead, and cannot achieve high-density integration above Gb capacity.

[0006] In addition, the existing flash memory array needs to set bit lines, word lines and source lines to realize the selection and operation of flash memory cells. However, the source lines of the existing flash memory array are formed in the active area, and the block resistance of the active area is much higher than that of metal. Therefore, in order to reduce the series resistance of the source line, it is necessary to short-circuit the active area source lines together through a common source line of metal every several rows or columns in the row direction or column direction, resulting in an increase in the area overhead of the flash memory array.

[0007] With the rapid development of applications such as mobile smart terminals, wearable devices, and smart sensor networks, higher requirements are placed on the power consumption, storage capacity, and cost of flash memory. Therefore, a flash memory technology with the advantages of low power consumption, small unit area, shrinkable process size, high array integration density, and large capacity is needed. Summary of the invention

[0008] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute prior art.

[0009] In order to solve the above problems existing in the prior art, the present disclosure proposes a flash memory array.

[0010] According to one aspect of the present disclosure, a flash memory array is provided, comprising: a plurality of flash memory cells arranged in a row direction and in a column direction perpendicular to the row direction; a plurality of word line groups extending in the row direction; and a plurality of bit line groups extending in the column direction, wherein flash memory cell pairs are arranged at intersections of the word line groups and the bit line groups, the flash memory cell pairs comprising a first flash memory cell and a second flash memory cell adjacent in the row direction and sharing the same bit line group.

[0011] The flash memory array according to the present disclosure can improve the arrangement density of the bit lines and reduce the parasitic resistance of the bit lines without increasing the size of the array. In addition, compared with the flash memory array of the prior art, the flash memory array according to the present disclosure also has better process compatibility and miniaturization characteristics.

[0012] However, the effects of the present disclosure are not limited to the above-mentioned effects, and various extensions may be made without departing from the spirit and scope of the present disclosure. It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the concept of the invention.

[0014] Figure 1 is a cross-sectional view showing a flash memory cell according to an embodiment of the present disclosure.

[0015] Figure 2 An equivalent circuit diagram of a flash memory cell according to an embodiment of the present disclosure is shown.

[0016] Figure 3 A circuit diagram of a flash memory cell pair according to a first embodiment of the present disclosure is shown.

[0017] Figure 4 A circuit diagram of a flash memory array according to a first embodiment of the present disclosure is shown.

[0018] Figure 5 A schematic diagram showing a layout example of a bit line group according to the first embodiment of the present disclosure.

[0019] Figure 6 A schematic diagram showing another layout example of the bit line group according to the first embodiment of the present disclosure.

[0020] Figure 7 A circuit diagram of a flash memory cell pair according to a second embodiment of the present disclosure is shown.

[0021] Figure 8 A circuit diagram of a flash memory array according to a second embodiment of the present disclosure is shown.

[0022] Fig. 9 A schematic diagram showing a layout example of a bit line group according to a second embodiment of the present disclosure.

[0023] Fig.10 A schematic diagram showing the layout of control lines of a flash memory array according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of each exemplary embodiment or implementation of the present invention. As used herein, "implementation" and "implementation" are interchangeable words, which are non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that each exemplary embodiment can be practiced without these specific details or with one or more equivalent arrangements. In other examples, known structures and devices are shown in block diagram form to avoid unnecessary confusion of each exemplary embodiment. In addition, each exemplary embodiment may be different, but does not have to be exclusive. For example, without departing from the present invention, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in other exemplary embodiments.

[0025] Unless otherwise specified, the illustrated exemplary embodiments should be understood as providing exemplary features of varying details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments, etc. (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged without departing from the concept of the present invention.

[0026] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, the presence or absence of cross hatching or shading cannot convey or indicate any preference or requirement for a particular material, material properties, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, shapes, etc. of the elements, unless otherwise stated. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, a specific processing sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. Likewise, the same reference numerals represent the same elements.

[0027] When an element such as a layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or coupled to, another element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, there may be no intervening element or layer. For this reason, the term "connection" may refer to a physical, electrical and / or fluid connection with or without an intervening element. In addition, the D1 axis, the D2 axis, and the D3 axis are not limited to the three axes of a rectangular coordinate system, such as the x, y, and z axes, and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0029] Spatially relative terms, such as "below," "beneath," "below," "above," "upper," and "on the side" (e.g., as in "sidewall"), etc., may be used herein for descriptive purposes to describe the relationship between one element as shown in the figures and other elements. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture other than the orientation shown in the drawings. For example, if the device in the drawings is flipped, an element described as being "below" or "beneath" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both above and below orientations. Additionally, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus the spatially relative descriptors used herein are interpreted accordingly.

[0030] The terms used herein are for the purpose of describing specific embodiments, but are not intended to be restrictive. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "include" and / or "comprise" indicate that there are stated features, integers, steps, operations, elements, parts and / or their groups, but do not exclude the presence or increase of one or more other features, integers, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than degree terms, and are therefore utilized to account for the inherent deviations in the values ​​recognized by those of ordinary skill in the art, calculated and / or provided.

[0031] As is customary in the art, some exemplary embodiments are described and shown in the accompanying drawings in terms of functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be written and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also considered that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and a processor that performs other operations (e.g., one or more microprocessors and related circuits written). In addition, without departing from the scope of the inventive concept, each block, unit and / or module of some exemplary embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0032] Embodiments are described herein with reference to cross-sectional views and / or exploded views, which are schematic diagrams of idealized embodiments and / or intermediate structures. In this way, variations in the illustrated shapes, for example due to manufacturing techniques and / or tolerances, are to be expected. Therefore, the embodiments disclosed herein need not necessarily be interpreted as being limited to the specific illustrated shapes of the regions, but rather include shape deviations caused by, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore this is not necessarily intended to be limiting.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0034] Figure 1 A cross-sectional view of a flash memory cell MC 100 according to an embodiment of the present disclosure is shown.

[0035] like Figure 1 As shown, a flash memory cell MC 100 according to an embodiment of the present disclosure may include a substrate 101 including a deep well region DNW 103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103 .

[0036] Despite Figure 1 As an example, the first doping type is defined as P type and the second doping type is defined as N type, but those skilled in the art should recognize that the present disclosure is not limited to this, and the first doping type may also be N type, in which case the second doping type may be P type.

[0037] According to an embodiment of the present disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

[0038] In addition, the flash memory cell MC100 includes a first storage transistor MS110, a gate transistor MG120, and a second storage transistor MD130 connected in series in sequence. The first storage transistor MS110 may be disposed on the well region PW102 and store first data DATA1. The second storage transistor MD130 may be disposed on the well region PW102 and store second data DATA2. The gate transistor MG120 is disposed between the first storage transistor MS110 and the second storage transistor MD130 along the horizontal direction DR1 on the well region PW102, and is used to isolate the first storage transistor MS110 and the second storage transistor MD130 and perform a gate operation on the first storage transistor MS110 and the second storage transistor MD130.

[0039] According to an embodiment of the present disclosure, the flash memory cell MC100 includes two storage transistors MS110 and MD130, so the flash memory cell MC100 can implement a two-bit storage function, that is, store the first data DATA1 and the second data DATA2 simultaneously.

[0040] In addition, if Figure 1As shown, the source region of the first storage transistor MS 110 is connected to the first electrode S of the flash memory cell MC 100, which can also be referred to as the source S of the flash memory cell MC 100, and the drain region of the second storage transistor MD 130 is connected to the second electrode D of the flash memory cell MC 100, which can also be referred to as the drain D of the flash memory cell MC 100.

[0041] Those skilled in the art should recognize that the source and drain of a flash memory cell are defined herein for ease of description; however, the definition of the source and drain of a flash memory cell is relative, and the terms "source" and "drain" may be used interchangeably under different operating conditions.

[0042] In addition, if Figure 1 As shown, the first storage transistor MS 110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask stopper 117 sequentially arranged along a vertical direction DR2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 sequentially stacked along the vertical direction. In addition, the second storage transistor MD 130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask stopper 137 sequentially arranged along the vertical direction DR2. The gate dielectric stack 132 has a first oxide layer 133, a storage dielectric layer 134, and a second oxide layer 135 sequentially stacked along the vertical direction.

[0043] According to an embodiment of the present disclosure, the flash memory cell MC100 includes two storage transistors MS110 and MD130, and thus can implement a two-bit storage function.

[0044] According to the embodiments of the present disclosure, Figure 1 As shown, the flash memory cell MC100 for two-bit storage may be composed of three closely arranged transistors, namely, a gate transistor MG120 located in the middle of the flash memory cell MC100, a first storage transistor MS110 located at a first end of the flash memory cell MC100, and a second storage transistor MD130 located at a second end of the flash memory cell MC100.

[0045] like Figure 1 As shown, the flash memory cell MC 100 may be formed on a well region PW 102 in a semiconductor substrate 101. In addition, in order to isolate the well region PW 102 from the substrate 101 so as to apply a voltage to the well region PW 102 under certain working conditions, such as Figure 1 As shown in FIG. 1 , the well region PW 102 may be formed in the deep well region DNW 103 .

[0046] like Figure 1As shown, a source region 140 formed by N-type doping is provided at the first end of the flash memory cell MC 100, and a drain region 150 formed by N-type doping is also provided at the second end of the flash memory cell MC 100. The source region 140 is connected to a metal source electrode 142 located at an upper layer, i.e., a first electrode S, through a contact hole 141, and the drain region 150 is connected to a metal drain electrode 152 located at an upper layer, i.e., a second electrode D, through a contact hole 151.

[0047] According to an embodiment of the present disclosure, the first electrode S and the second electrode D may include metal or highly doped polysilicon. When the first electrode S and the second electrode D are formed of metal, they may include at least one of the following materials: aluminum, titanium, titanium nitride, copper, tungsten, cobalt, and manganese.

[0048] As mentioned above, if Figure 1 As shown, the gate structure of the first storage transistor MS 110 may include, from bottom to top, a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask barrier 117 for sidewall self-alignment. According to an embodiment of the present disclosure, the gate electrode 116 may include, for example, polysilicon, a metal gate, a metal silicide material, or a combination of the above materials. According to an embodiment of the present disclosure, the hard mask barrier 117 may include, for example, silicon oxide, silicon nitride, silicon glass material, or a combination of the above materials.

[0049] In addition, if Figure 1 As shown, the gate dielectric stack 112 has a first oxide layer (tunneling oxide layer) 113, a storage dielectric layer (charge storage layer) 114, and a second oxide layer (blocking oxide layer) 115 stacked in sequence along the vertical direction. According to an embodiment of the present disclosure, the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide or aluminum oxide.

[0050] According to an embodiment of the present disclosure, the storage medium layer 114 may include one or more layers of storage medium. In addition, according to an embodiment of the present disclosure, the storage medium forming the storage medium layer 114 may include: a monovalent or polyvalent oxide, such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide; a monovalent or polyvalent nitride, such as silicon nitride; a monovalent or polyvalent oxynitride, such as silicon oxynitride; polycrystalline silicon or nanocrystalline material; or a combination of the above materials.

[0051] According to an embodiment of the present disclosure, when the storage medium layer 114 is formed of, for example, a silicon nitride material, the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 may form a gate dielectric stack 112 as an ONO (oxide-nitride-oxide) composite storage medium. In this case, the first storage transistor MS 110 may be a SONOS type storage transistor.

[0052] In addition, according to an embodiment of the present disclosure, the first storage transistor MS 110 may be other trapped charge capture type storage transistors having a similar operating mechanism to the SONOS type storage transistor. This type of storage transistor uses a high-K material rich in charge traps such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, etc. to replace the silicon nitride material in the SONOS memory as the storage medium layer 114.

[0053] In addition, according to an embodiment of the present disclosure, the first storage transistor MS 110 may also be a floating gate storage transistor. This type of storage transistor uses polysilicon material to replace the silicon nitride material in the SONOS memory to form a floating gate for storing charges as the storage medium layer 114 .

[0054] In addition, according to an embodiment of the present disclosure, the first storage transistor MS 110 may also be a nano-crystal memory transistor. This type of storage transistor uses a nano-crystal material with quantum dots to replace the silicon nitride material in the SONOS memory as the storage medium layer 114 .

[0055] According to an embodiment of the present disclosure, the length of the gate electrode 116 of the first storage transistor MS 110 can be defined by the length of the hard mask stopper 117 disposed on the gate electrode 116 through a self-alignment process. Those skilled in the art should note that the "length" mentioned herein means the size of the stated object in the horizontal direction DR1.

[0056] According to an embodiment of the present disclosure, the second storage transistor MD130 has the same structure as the first storage transistor MS110 except that it is disposed on the opposite side of the selection transistor MG120 and can be manufactured by the same process as the first storage transistor MS110, so for the sake of brevity, a detailed description of the structure of the second storage transistor MD130 will be omitted here.

[0057] The gate structure of the gate transistor MG 120 may include a channel region 121, a gate dielectric layer 122, and a gate electrode 123 from bottom to top. According to an embodiment of the present disclosure, the gate electrode 123 of the gate transistor MG 120 is connected to the word line, and the length of the gate electrode 123 is defined by the process size of the photolithography process. According to an embodiment of the present disclosure, the gate dielectric layer 122 may include materials such as silicon oxide, silicon oxynitride, and hafnium oxide. In addition, according to an embodiment of the present disclosure, the gate electrode 123 may include, for example, polysilicon, a metal gate, a metal silicide material, or a combination of the above materials.

[0058] According to an embodiment of the present disclosure, the channel regions 111, 131 and 121 of the first storage transistor MS110, the second storage transistor MD130 and the selection transistor MG120 may all have a first doping type, and the doping concentration of the channel regions 111 and 131 of the first storage transistor MS110 and the second storage transistor MD130 may be lower than the doping concentration of the channel region 121 of the selection transistor MG120.

[0059] Furthermore, according to an embodiment of the present disclosure, the channel regions 111 and 131 of the first and second storage transistors MS110 and MD130 may have a second doping type or be undoped intrinsic channel regions, and the channel region 121 of the gate transistor MG120 may have a first doping type different from the second doping type.

[0060] For example, Figure 1 As shown, when the first doping type is P-type and the second doping type is N-type, the doping concentrations of the P-type channels 111 and 131 of the first storage transistor MS 110 and the second storage transistor MD 130 are lower than the doping concentration of the P-type channel 121 of the gate transistor MG 120. In addition, according to an embodiment of the present disclosure, the channel regions 111 and 131 may also be undoped intrinsic channels or N-type doped channel regions.

[0061] According to an embodiment of the present disclosure, the flash memory cell MC100 also includes: a first isolation portion 124, which is arranged between the first storage transistor MS110 and the selection transistor MG120 along the horizontal direction DR1, and is used to isolate the gate electrode 116 of the first storage transistor MS110 and the gate electrode 123 of the selection transistor MG120; and a second isolation portion 125, which is arranged between the selection transistor MG120 and the second storage transistor MD130 along the horizontal direction DR1, and is used to isolate the gate electrode 123 of the selection transistor MG120 and the gate electrode 136 of the second storage transistor MD130.

[0062] Specifically, Figure 1 As shown, a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls are provided on both sides of the gate electrode 123 of the gate transistor MG 120, which are respectively used to electrically isolate the gate electrode 116 of the first storage transistor MS110 and the gate electrode 136 of the second storage transistor MD 130 with a specific isolation gap length. According to an embodiment of the present disclosure, the first isolation portion 124 and the second isolation portion 125 may include the same material as the gate dielectric layer 122.

[0063] The flash memory cell according to the embodiment of the present disclosure can implement two storage transistors in one flash memory cell, so the equivalent area of ​​each storage bit can be greatly reduced, thereby achieving lower cost and higher integration density.

[0064] In addition, the storage transistor in the flash memory cell according to the embodiment of the present disclosure can adopt a simple SONOS type device structure, which has the advantages of simple process, low gate electrode operation voltage, and good data retention reliability.

[0065] In addition, in the flash memory cell according to the embodiment of the present disclosure, the mutual influence of the two storage bits is isolated by the selection transistor, and the distribution width and lateral diffusion of the stored charge are suppressed, so that a higher storage charge density can be obtained in the silicon nitride storage layer, avoiding the problems of wide charge distribution, large mutual interference, and inability to reduce gate length that exist in the existing NROM storage cell that also uses two-bit storage, thereby significantly improving the storage window and data reliability.

[0066] In particular, the equivalent channel length of the flash memory cell according to the embodiment of the present disclosure is the sum of the lengths of the gate electrodes of the first storage transistor, the selection transistor, and the second storage transistor. As described above, the gate electrode length of the selection transistor is defined by the process feature size of the photolithography process, and is generally approximately equal to or slightly greater than the critical feature size (Critical Feature Size) of the photolithography process, which is generally represented as F (or CF). In addition, the gate electrode lengths of the first storage transistor and the second storage transistor are respectively defined by the lengths of the self-aligned sidewall hard mask blocking portion, so that their sizes can be smaller than F. Therefore, according to the embodiment of the present disclosure, a smaller channel length of the flash memory cell can be obtained under the same process feature size, thereby achieving the purpose of reducing the area and manufacturing cost of the flash memory cell.

[0067] In addition, in a flash memory array composed of flash memory cells according to the embodiments of the present disclosure, for flash memory cells that are not selected for operation, the gate electrodes of the selection transistor and the first and second storage transistors are grounded, so that the entire series channel of the flash memory cell is completely turned off, and the equivalent channel length is enlarged, so that the source-drain punch-through of the flash memory cell under high operating voltage can be avoided at a smaller process feature size, thereby overcoming the problem that the gate electrode length of the existing flash memory cell cannot be reduced as the process feature size is reduced. Therefore, the flash memory cell according to the embodiments of the present disclosure has better process miniaturization capability, and can obtain a smaller unit area and manufacturing cost by reducing the process feature size.

[0068] In addition, in the flash memory cell according to the embodiment of the present disclosure, by reducing the doping concentration of the P-type channel region of the first storage transistor and the second storage transistor or designing them as N-type doped channel regions, the threshold voltage of the storage transistor and the gate electrode operating voltage during erase and read operations can be reduced, thereby improving the reliability of the storage transistor. At the same time, by increasing the doping concentration of the P-type channel region of the selection transistor, the punch-through voltage of the flash memory cell can be increased, and the leakage current between the source region and the drain region of the non-selected flash memory cell can be reduced.

[0069] Figure 2 An equivalent circuit diagram of a flash memory cell MC100 according to an embodiment of the present disclosure is shown.

[0070] Specifically, Figure 2 As shown in FIG. 1 , the flash memory cell MC100 includes a first storage transistor MS110, a gate transistor MG120, and a second storage transistor MD130 sequentially connected in series. The gate transistor MG120 can isolate the first storage transistor MS110 and the second storage transistor MD130 and perform a gate operation on the first storage transistor MS110 and the second storage transistor MD130.

[0071] Figure 3 FIG. 1 is a circuit diagram of a flash memory cell pair 200 according to a first embodiment of the present disclosure. Figure 4 A circuit diagram of a flash memory array according to a first embodiment of the present disclosure is shown.

[0072] According to an embodiment of the present disclosure, a flash memory array may include: a plurality of flash memory cells arranged in a row direction and in a column direction perpendicular to the row direction; a plurality of word line groups extending in the row direction; and a plurality of bit line groups extending in the column direction, wherein a flash memory cell pair is arranged at the intersection of the word line group and the bit line group, and the flash memory cell pair includes a first flash memory cell and a second flash memory cell adjacent in the row direction and sharing the same bit line group.

[0073] like Figure 3 and Figure 4 As shown, according to an embodiment of the present disclosure, the flash memory array may include multiple Figure 2 The flash memory cells shown in the figure can be arranged in an m×2n array along the row direction and the column direction perpendicular to the row direction, where m and n are natural numbers greater than 1. Therefore, the plurality of flash memory cells form a flash memory array of m rows×2n columns.

[0074] like Figure 3As shown, according to an embodiment of the present disclosure, two adjacent flash memory cells in the row direction may constitute a flash memory cell pair 200, which includes a first flash memory cell 210 and a second flash memory cell 220. For example, the first flash memory cell 210 may be a flash memory cell located at the 0th row and the 0th column in the flash memory array, and the second flash memory cell 220 may be a flash memory cell located at the 0th row and the 1st column in the flash memory array. Therefore, according to an embodiment of the present disclosure, the flash memory array may include flash memory cell pairs arranged in m rows×n columns.

[0075] The first flash memory cell 210 includes a first storage transistor 211, a gate transistor 212, and a second storage transistor 213 connected in series in the column direction. The second flash memory cell 220 includes a first storage transistor 221, a gate transistor 222, and a second storage transistor 223 connected in series in the column direction.

[0076] According to an embodiment of the present disclosure, in the first flash memory cell 210 , the source region of the first storage transistor 211 is connected to the first electrode S1 of the first flash memory cell 210 , and the drain region of the second storage transistor 213 is connected to the second electrode D1 of the first flash memory cell 210 .

[0077] In addition, according to an embodiment of the present disclosure, in the second flash memory unit 220 , the source region of the first storage transistor 221 is connected to the first electrode S2 of the second flash memory unit 220 , and the drain region of the second storage transistor 223 is connected to the second electrode D2 of the second flash memory unit 220 .

[0078] In addition, according to an embodiment of the present disclosure, the flash memory cell pair 200, i.e., a pair of the first flash memory cell 210 and the second flash memory cell 220, shares a bit line group extending in a column direction, the bit line group including a first bit line BSL0, a middle bit line BLM0, and a second bit line BLD0. According to the first embodiment of the present disclosure, the first bit line BSL0 may be connected to the first electrode S1 of the first flash memory cell 210, the second bit line BLD0 may be connected to the second electrode D2 of the second flash memory cell 220, and the middle bit line BLM0 may connect the second electrode D1 of the first flash memory cell 210 and the first electrode S2 of the second flash memory cell 220.

[0079] As described above, according to an embodiment of the present disclosure, the first flash memory cell 210 and the second flash memory cell 220 adjacent in the row direction are connected to the same first bit line BSL0, middle bit line BLM0 and second bit line BLD0. That is, according to an embodiment of the present disclosure, in a flash memory array, a pair of flash memory cells share the same bit line group. For example, the flash memory cells in the 0th column and the flash memory cells in the 1st column share a bit line group including the first bit line BLS0, the middle bit line BLM0 and the second bit line BLD0, the flash memory cells in the 2nd column and the flash memory cells in the 3rd column share a bit line group including the first bit line BLS1, the middle bit line BLM1 and the second bit line BLD1, until the flash memory cells in the 2n-2nd column and the flash memory cells in the 2n-1st column share a bit line group including the first bit line BLS <n-1>, Middle bit line BLM <n-1>and the second bit line BLD <n-1>of bit line groups.

[0080] In addition, according to an embodiment of the present disclosure, the flash memory array also includes a plurality of word line groups extending along the row direction, each word line group includes a first control line, a word line, and a second control line, wherein the first control line is connected to the gate electrode of the first storage transistor of the flash memory cell pair, the word line is connected to the gate electrode of the selection transistor of the flash memory cell pair, and the second control line is connected to the gate electrode of the second storage transistor of the flash memory cell pair.

[0081] According to an embodiment of the present disclosure, in a flash memory array, flash memory cells (pairs) in the same row share the same word line group, ie, a first control line, a word line, and a second control line.

[0082] like Figure 3 and Figure 4 As shown, taking the flash memory cell pair 200 as an example, the flash memory cell pair 200, namely the first flash memory cell 210 and the second flash memory cell 220, is located in row 0 and shares the same word line group, namely the first control line MS0, the word line WL0 and the second control line MD0, with other flash memory cells (pairs) in row 0. The first control line MS0 is connected to the gate electrodes of the first storage transistors 211 and 221 of the first flash memory cell 210 and the second flash memory cell 220, the word line WL0 is connected to the gate electrodes of the selection transistors 212 and 222 of the first flash memory cell 210 and the second flash memory cell 220, and the second control line MD0 is connected to the gate electrodes of the second storage transistors 213 and 223 of the first flash memory cell 210 and the second flash memory cell 220.

[0083] Similarly, the gate electrodes of the first storage transistors in the flash memory cells (pairs) of the 1st row are commonly connected to the first control line MS1, the gate electrodes of the selection transistors in the flash memory cells of the 1st row are commonly connected to the word line WL1, and the gate electrodes of the second storage transistors in the flash memory cells of the 1st row are commonly connected to the second control line MD1. Similarly, the gate electrodes of the first storage transistors in the flash memory cells of the m-2th row are commonly connected to the first control line MS1. <m-2>The gate electrodes of the gate transistors in the flash memory cells of the m-2th row are connected to the word line WL <m-2>, and the gate electrodes of the second storage transistors in the flash memory cells of the m-2th row are commonly connected to the second control line MD <m-2>Similarly, the gate electrodes of the first storage transistors in the flash memory cells in the m-1th row are commonly connected to the first control line MS <m-1>The gate electrodes of the gate transistors in the flash memory cells in the m-1th row are connected to the word line WL <m-1>, and the gate electrodes of the second storage transistors in the flash memory cells of the m-1th row are commonly connected to the second control line MD <m-1>.

[0084] Those skilled in the art should recognize that the flash memory cells according to the embodiments of the present disclosure have a symmetrical structure, and therefore, based on the connection relationship among the first control line, the word line, the second control line, the first bit line, the intermediate bit line, and the second bit line as described above, the flash memory cells adjacent in the column direction are arranged oppositely, that is, the first storage transistor of the flash memory cell in the current row is adjacent to the first storage transistor of the flash memory cell in the previous row in the column direction, and the second storage transistor of the flash memory cell in the current row is adjacent to the second storage transistor of the flash memory cell in the next row in the column direction; or, the second storage transistor of the flash memory cell in the current row is adjacent to the second storage transistor of the flash memory cell in the previous row in the column direction, and the first storage transistor of the flash memory cell in the current row is adjacent to the first storage transistor of the flash memory cell in the next row in the column direction.

[0085] Figure 5 A schematic diagram showing a layout example of a bit line group according to the first embodiment of the present disclosure.

[0086] According to an embodiment of the present disclosure, the first control line, the word line, and the second control line may be formed of at least one of polysilicon, silicide, and a metal gate. In addition, according to an embodiment of the present disclosure, the middle bit line may be formed of a first metal layer, and the first bit line and the second bit line may be formed of a second metal layer different from the first metal layer. In other words, the metal layer used to form the middle bit line is different from the metal layer used to form the first bit line and the second bit line. In addition, the first bit line and the second bit line may be formed of the same metal layer.

[0087] According to an embodiment of the present disclosure, the first metal layer and the second metal layer may include at least one of the following materials: aluminum, titanium, titanium nitride, copper, tungsten, cobalt, and manganese.

[0088] According to an embodiment of the present disclosure, the middle bit line may include a first portion extending in a column direction and a second portion extending in a row direction, and the first bit line and the second bit line extend in the column direction.

[0089] like Figure 5 As shown in (a) of FIG. 1 , taking the flash memory cell pair 200 as an example, the first electrodes S1 and S2 and the second electrodes D1 and D2 of the first flash memory cell 210 and the second flash memory cell 220 may be formed by a first metal layer M1 disposed on a first control line MS0, a word line WL0, and a second control line MD0, such as polysilicon. Figure 5 As shown in FIG. 1 , the first control line MS0 , the word line WL0 , and the second control line MD0 extend parallel to each other in a row direction.

[0090] In addition, if Figure 5 As shown in (a), the middle bit line BLM0 is formed by the first metal layer M1 in a continuous zigzag manner in the column direction, and includes a first portion P1 extending in the column direction and a second portion P2 extending in the row direction. According to an embodiment of the present disclosure, the second portion P2 of the middle bit line BLM0 may overlap the word line WL0 thereunder.

[0091] In addition, if Figure 5 As shown in (b) of FIG. 1 , the first bit line BLS0 and the second bit line BLD0 may be formed by the second metal layer M2 in the column direction and overlap the first portion P1 of the middle bit line BLM0 .

[0092] According to an embodiment of the present disclosure, the electrical connection between the first bit line BLS0 and the first electrode S1 of the first flash memory unit 210 can be achieved through a through hole V1 between the first metal layer M1 and the second metal layer M2, and the electrical connection between the second bit line BLD0 and the second electrode D2 of the second flash memory unit 220 can be achieved through a through hole V1 between the first metal layer M1 and the second metal layer M2.

[0093] According to the embodiment of the present disclosure, since the first part P1 of the middle bit line can overlap with the first bit line and the second bit line, and the second part P2 of the middle bit line can overlap with the polysilicon word line in the row direction, the additional area for setting the middle bit line can be eliminated, thereby obtaining a more compact flash memory array. In addition, since the first bit line and the second bit line are both formed of metal, the need to set a common source line in the prior art is eliminated, thereby further reducing the area of ​​the flash memory array.

[0094] Figure 5 The embodiment shown uses two metal layers to realize the setting of the first bit line, the middle bit line and the second bit line. However, the present disclosure is not limited thereto. According to the embodiment of the present disclosure, more metal layers can be used to realize the setting of the first bit line, the middle bit line and the second bit line according to the application scenario of the flash memory array.

[0095] Figure 6 A schematic diagram showing another layout example of the bit line group according to the first embodiment of the present disclosure.

[0096] Specifically, Figure 6 As shown in (a) of FIG. 1 , the first electrode and the second electrode of the flash memory cell may be formed by a first metal layer M1 disposed above a first control line, a word line, and a second control line, such as polysilicon. Figure 5 ,like Figure 6 As shown in (c), the middle bit line can be formed by the third metal layer M3 in a continuous zigzag manner in the column direction. That is, the middle bit line includes a first portion P1 extending in the column direction and a second portion P2 extending in the row direction.

[0097] In addition, if Figure 6 As shown in (d) in FIG. 1 , the first bit line and the second bit line are formed by the fourth metal layer M4 in the column direction and overlap with the first portion P1 of the middle bit line in the column direction. Figure 6 As shown in (b) of FIG. 1 , the electrical connection between the middle bit line and the first electrode and the second electrode can be realized through the second metal layer M2 between the first metal layer M1 and the third metal layer M3 and the through holes V1 and V2 between the metal layers M1 to M3. Figure 6 As shown in (b) and (c) of FIG. 1 , the electrical connection between the first bit line and the first electrode can be achieved through the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4 and the through holes V1 to V3 between the metal layers M1 to M4. Figure 6 As shown in (b) and (c), the electrical connection between the second bit line and the second electrode can also be achieved through the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4 and the through holes V1 to V3 between the metal layers M1 to M4.

[0098] Compared with Figure 5 The two-layer metal bitline layout shown in Figure 6 The four-layer metal bitline layout shown may allow for greater flexibility in the layout of the first bitline, the middle bitline, and the second bitline.

[0099] In addition, those skilled in the art will recognize that the bit line arrangement of the flash memory array according to the present disclosure requires at least two metal layers, so although Figure 6 The embodiment of using four metal layers to implement the bit line setting of the flash memory array according to the present disclosure is shown, but the present disclosure is not limited thereto. Those skilled in the art can use three metal layers or five or more metal layers to implement the bit line setting of the flash memory array according to the present disclosure according to the teachings of the present disclosure.

[0100] Figure 7 FIG. 1 is a circuit diagram of a flash memory cell pair 300 according to a second embodiment of the present disclosure. Figure 8 A circuit diagram of a flash memory array according to a second embodiment of the present disclosure is shown.

[0101] like Figure 7 As shown, according to an embodiment of the present disclosure, two adjacent flash memory cells in the row direction may constitute a flash memory cell pair 300, which includes a first flash memory cell 310 and a second flash memory cell 320. For example, the first flash memory cell 310 may be a flash memory cell located at the 0th row and the 0th column in the flash memory array, and the second flash memory cell 320 may be a flash memory cell located at the 0th row and the 1st column in the flash memory array. Therefore, according to an embodiment of the present disclosure, the flash memory array may include flash memory cell pairs arranged in m rows×n columns.

[0102] The first flash memory cell 310 includes a first storage transistor 311, a gate transistor 312, and a second storage transistor 313 connected in series in the column direction. The second flash memory cell 320 includes a first storage transistor 321, a gate transistor 322, and a second storage transistor 323 connected in series in the column direction.

[0103] According to an embodiment of the present disclosure, in the first flash memory cell 310 , the source region of the first storage transistor 311 is connected to the first electrode S1 of the first flash memory cell 310 , and the drain region of the second storage transistor 313 is connected to the second electrode D1 of the first flash memory cell 310 .

[0104] In addition, according to an embodiment of the present disclosure, in the second flash memory unit 320 , the source region of the first storage transistor 321 is connected to the first electrode S2 of the second flash memory unit 320 , and the drain region of the second storage transistor 323 is connected to the second electrode D2 of the second flash memory unit 320 .

[0105] Figure 7 and Figure 8 The flash memory cell pair and the flash memory array of the second embodiment of the present disclosure are shown in FIG. Figure 3 and Figure 4 The flash memory cell pair and the flash memory array of the first embodiment of the present disclosure are substantially the same, except for the connection manner of the bit line groups of the flash memory cell pair.

[0106] Specifically, Figure 7 and Figure 8 As shown, according to the second embodiment of the present disclosure, the first bit line BSL0 can be connected to the second electrode D1 of the first flash memory unit 310, the second bit line BLD0 can be connected to the second electrode D2 of the second flash memory unit 320, and the middle bit line BLM0 can connect the first electrode S1 of the first flash memory unit 310 and the first electrode S2 of the second flash memory unit 320.

[0107] Fig. 9 A schematic diagram showing a layout example of a bit line group according to a second embodiment of the present disclosure.

[0108] Specifically, Fig. 9 As shown in (a) of FIG. 1 , the first electrode and the second electrode of the flash memory cell may be formed by a first metal layer M1 disposed above a first control line, a word line, and a second control line, such as polysilicon. Fig. 9 As shown in (c), the middle bit line can be formed by the third metal layer M3 in a continuous zigzag manner in the column direction. That is, the middle bit line includes a first portion P1 extending in the column direction and a second portion P2 extending in the row direction.

[0109] In addition, if Fig. 9 As shown in (d) in FIG. 1 , the first bit line and the second bit line are formed by the fourth metal layer M4 in the column direction and overlap with the first portion P1 of the middle bit line in the column direction. Fig. 9 As shown in (b) of FIG. 1 , the electrical connection between the middle bit line and the first electrode can be achieved through the second metal layer M2 between the first metal layer M1 and the third metal layer M3 and the through holes V1 and V2 between the metal layers M1 to M3. Fig. 9 As shown in (b) and (c) of FIG. 1 , the electrical connection between the first bit line and the second electrode can be realized through the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4 and the through holes V1 to V3 between the metal layers M1 to M4. Fig. 9 As shown in (b) and (c), the electrical connection between the second bit line and the second electrode can also be achieved through the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4 and the through holes V1 to V3 between the metal layers M1 to M4.

[0110] The flash memory array according to the above embodiments of the present disclosure can improve the arrangement density of the bit lines and reduce the parasitic resistance of the bit lines without increasing the size of the array. In addition, compared with the flash memory array of the prior art, the flash memory array according to the present disclosure also has better process compatibility and miniaturization characteristics.

[0111] Furthermore, according to an embodiment of the present disclosure, first control lines or second control lines adjacent to each other in a column direction may be connected together through a metal layer. Fig.10 A schematic diagram showing the layout of control lines of a flash memory array according to an embodiment of the present disclosure.

[0112] like Fig.10 As shown, for example, in Figure 4 Based on the flash memory array shown, the adjacent first control lines can be connected together in the column direction using the first metal control line MCS<0:m / 2-1> formed by the metal layer. In addition, the adjacent second control lines in the column direction can be connected together using the second metal control line MCD<1:m / 2> formed by the metal layer.

[0113] According to an embodiment of the present disclosure, a metal layer used to form the first metal control line MCS<0:m / 2-1> and the second metal control line MCD<1:m / 2> may be different from a metal layer used to form a bit line (including a first bit line, an intermediate bit line, and a second bit line). According to an embodiment of the present disclosure, a metal layer used to form the first metal control line MCS<0:m / 2-1> and the second metal control line MCD<1:m / 2> may be disposed above a metal layer used to form a bit line (including a first bit line, an intermediate bit line, and a second bit line).

[0114] According to an embodiment of the present disclosure, two flash memory cells adjacent in the column direction can share a control line (a first control line or a second control line) through a metal control line (a first metal control line or a second metal control line). By connecting the first control line and the second control line together using the first metal control line and the second metal control line, the parasitic resistance of the first control line and the second control line, such as polysilicon, can be effectively reduced, thereby effectively improving the operating speed of the flash memory array. In addition, by connecting the first control line and the second control line together using the first metal control line and the second metal control line, the wiring density and process complexity of the metal control line can be reduced. In addition, such a flash memory array that shares control lines can also reduce the number of peripheral circuits of the flash memory array for driving the control lines, thereby reducing the area overhead of the peripheral circuits and the manufacturing cost of the memory chip.

[0115] Those skilled in the art will appreciate that although the above Figure 1 The flash memory cell MC 100 shown in the figure describes the flash memory array of the present disclosure, but the flash memory array of the present disclosure is not limited to Figure 1 The flash memory cell MC 100 is shown. Based on the teachings of the present disclosure, those skilled in the art may conceive of applying the flash memory array of the present disclosure to other types of flash memory cells, such as a flash memory cell including only one storage transistor or a flash memory cell using one storage transistor to store two bits of data, and all these variations should be included in the scope of the present disclosure.

[0116] Although the present disclosure has been described with reference to the embodiments thereof, it will be appreciated by those skilled in the art that various modifications and changes may be made to the present disclosure without departing from the spirit and scope of the present disclosure as disclosed in the appended claims.

Claims

1. A flash memory array, comprising: A plurality of flash memory cells are arranged along a row direction and a column direction perpendicular to the row direction; A plurality of word line groups extending along the row direction, each word line group comprising a first control line, a word line, and a second control line extending along the row direction; as well as A plurality of bit line groups extending along the column direction, each bit line group comprising a first bit line, a middle bit line, and a second bit line; Wherein, a flash memory cell pair is arranged at the intersection of the word line group and the bit line group, and the flash memory cell pair includes a first flash memory cell and a second flash memory cell which are adjacent in the row direction and share the same bit line group; The middle bit line is formed from a first metal layer, and The first bit line and the second bit line are formed of a second metal layer different from the first metal layer; The middle bit line includes a first portion extending in the column direction and a second portion extending in the row direction, and The first bit line and the second bit line extend in the column direction; A first portion of the middle bit line overlaps the first bit line and the second bit line, and a second portion overlaps the word line thereunder.

2. The flash memory array according to claim 1, in, Each of the first flash memory cell and the second flash memory cell includes a first storage transistor, a gate transistor, and a second storage transistor sequentially connected in series in the column direction, and In each of the first flash memory unit and the second flash memory unit, the source region of the first storage transistor is connected to the first electrode of the flash memory unit, and the drain region of the second storage transistor is connected to the second electrode of the flash memory unit.

3. The flash memory array according to claim 2, in, The first bit line is connected to a first electrode of a first flash memory cell of the flash memory cell pair, the second bit line is connected to a second electrode of a second flash memory cell of the flash memory cell pair, and the middle bit line connects the second electrode of the first flash memory cell and the first electrode of the second flash memory cell.

4. The flash memory array according to claim 2, in, The first bit line is connected to the second electrode of the first flash memory cell of the flash memory cell pair, the second bit line is connected to the second electrode of the second flash memory cell of the flash memory cell pair, and the middle bit line connects the first electrode of the first flash memory cell and the first electrode of the second flash memory cell.

5. The flash memory array according to claim 3 or 4, wherein: in, The first control line is connected to a gate electrode of the first storage transistor, the word line is connected to a gate electrode of the gate transistor, and the second control line is connected to a gate electrode of the second storage transistor.

6. The flash memory array according to claim 5, wherein: Two first control lines adjacent to each other in the column direction are connected together through a first common control line, and Wherein, two second control lines adjacent to each other in the column direction are connected together through a second common control line.

7. The flash memory array according to claim 5, wherein: The first control line, the word line and the second control line are formed of at least one of polysilicon, silicide and metal gate.

8. The flash memory array according to claim 6, wherein: The first common control line and the second common control line are formed of a metal layer.

9. A flash memory array, comprising: A plurality of flash memory cells are arranged along a row direction and a column direction perpendicular to the row direction; A plurality of word line groups extending along the row direction; as well as A plurality of bit line groups extending along the column direction, A flash memory cell pair is arranged at the intersection of the word line group and the bit line group, and the flash memory cell pair includes a first flash memory cell and a second flash memory cell that are adjacent in the row direction and share the same bit line group. Each bit line group includes a first bit line, a middle bit line, and a second bit line sequentially arranged in the row direction. Each of the first flash memory unit and the second flash memory unit comprises a first storage transistor, a gate transistor and a second storage transistor connected in series in the column direction, respectively. wherein, in the first flash memory cell, a source region of the first storage transistor is connected to the first bit line, and a drain region of the second storage transistor is connected to the middle bit line, and Wherein, in the second flash memory cell, the source region of the first storage transistor is connected to the middle bit line, and the drain region of the second storage transistor is connected to the second bit line; in, Each word line group includes a first control line, a word line, and a second control line arranged sequentially in the column direction; The first control line is connected to the gate electrodes of the first storage transistors in the first flash memory cell and the second flash memory cell, the word line is connected to the gate electrodes of the selection transistors in the first flash memory cell and the second flash memory cell, and the second control line is connected to the gate electrodes of the second storage transistors in the first flash memory cell and the second flash memory cell.

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