Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the structure comprising: a substrate, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising an effective area and a connection area; a first groove located in the connection area of ​​the substrate, in the direction from the first surface to the second surface of the substrate, the first groove comprises a first area, a second area and a third area, the first area has a first projection on the substrate surface, the second area has a second projection on the substrate surface, the third area has a third projection on the substrate surface, the area of ​​the second projection is greater than the area of ​​the first projection, the area of ​​the second projection is greater than the area of ​​the third projection, and the first projection is within the range of the second projection, and the third projection is within the range of the second projection; a first connection layer contact that can be electrically connected is located in the first groove. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] As semiconductor technology nodes continue to shrink, the size of logic semiconductor standard cells also shrinks. It is necessary to increase the density of logic semiconductor circuits to make the size of standard cells extremely small.

[0003] Currently, miniaturization is used to increase the density of logic semiconductor circuits. However, the density of logic semiconductor circuits increased by miniaturization is limited. Therefore, a method of reducing the height of transistor units is proposed to increase the density of logic semiconductor circuits, that is, reducing the number of standard unit fins and embedding power rails (Buried Power Rail, referred to as BPR). The embedded power rail is usually used in conjunction with the back-side power deliver network (back-side PDN) to increase the voltage drop.

[0004] However, the performance of the existing embedded power lines and backside power transmission networks needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate including a first surface and a second surface relative to each other, the substrate including an effective area and a connection area; a first groove located in the connection area of ​​the substrate, the first groove extending from the first surface of the substrate to the second surface, in the direction from the first surface to the second surface of the substrate, the first groove includes a first area, a second area and a third area, the first area has a first projection on the substrate surface, the second area has a second projection on the substrate surface, the third area has a third projection on the substrate surface, the area of ​​the second projection is larger than the area of ​​the first projection, the area of ​​the second projection is larger than the area of ​​the third projection, and the first projection is within the range of the second projection, and the third projection is within the range of the second projection; a first connection layer that can be electrically connected and is located in the first groove.

[0007] Optionally, in a first direction parallel to the surface of the substrate, a cross-sectional shape of the first groove is spherical or polygonal, and the number of sides of the polygon is greater than or equal to 5.

[0008] Optionally, the effective area on the first surface of the substrate further has a plurality of fin structures, and the plurality of fin structures are arranged in parallel along a first direction parallel to the surface of the substrate; and the connection area is located between adjacent fin structures.

[0009] Optionally, it also includes: a protective layer located on the first surface of the substrate, the protective layer covering the top surface and side wall surface of the fin structure; a second groove located in the protective layer, the second groove is connected to the first groove, and a portion of the first connection layer is located in the second groove; and an isolation layer located in the second groove on the first connection layer.

[0010] Optionally, it further includes: a second connection layer located in the substrate connection region, the second connection layer extends from the second surface of the substrate to the first surface of the substrate, and the second connection layer contacts the first connection layer.

[0011] Optionally, the bottom of the first connection layer has a first size, the top of the second connection layer in contact with the first connection layer has a second size, and the first size is greater than the second size.

[0012] Optionally, the first size is greater than the second size by 10% to 50%.

[0013] Optionally, it also includes: a plurality of conductive structures located on the second surface of the substrate, wherein the conductive structures are electrically connected to the second connection layer.

[0014] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first surface and a second surface relative to each other, the substrate comprising an effective area and a connection area; forming a first groove in the substrate connection area, the first groove extending from the first surface of the substrate to the second surface, in the direction from the first surface to the second surface of the substrate, the first groove comprises a first area, a second area and a third area, the first area has a first projection on the substrate surface, the second area has a second projection on the substrate surface, the third area has a third projection on the substrate surface, the area of ​​the second projection is greater than the area of ​​the first projection, the area of ​​the second projection is greater than the area of ​​the third projection, and the first projection is within the range of the second projection, and the third projection is within the range of the second projection; forming a first connection layer that can be electrically connected in the first groove.

[0015] Optionally, in a first direction parallel to the surface of the substrate, a cross-sectional shape of the first groove is spherical or polygonal, and the number of sides of the polygon is greater than or equal to 5.

[0016] Optionally, the effective area on the first surface of the substrate further has a plurality of fin structures, and the plurality of fin structures are arranged in parallel along a first direction parallel to the surface of the substrate; and the connection area is located between adjacent fin structures.

[0017] Optionally, the method for forming a first groove includes: forming a protective layer on a first surface of a substrate, the protective layer covering a top surface and a side wall surface of the fin structure; forming a first mask layer on the protective layer, the first mask layer exposing a surface of the protective layer on the connection area; etching the protective layer using the first mask layer as a mask until a surface of the substrate is exposed, thereby forming a second groove in the protective layer; and etching the substrate exposed by the second groove to form the first groove.

[0018] Optionally, the method of etching the substrate exposed by the second groove includes: etching the substrate using a first etching process to form an initial first groove, wherein the sidewall of the initial first groove is perpendicular to the bottom surface of the initial first groove; etching the substrate exposed by the initial first groove using a second etching process to form a first groove, wherein the sidewall of the first groove is recessed into the effective area.

[0019] Optionally, the first etching process includes an anisotropic dry etching process.

[0020] Optionally, the second etching process includes a combination of one or more of a wet etching process and an isotropic dry etching process.

[0021] Optionally, part of the first connection layer is also located in the second groove.

[0022] Optionally, after forming the first connection layer, the method further includes: forming an isolation layer in the second groove.

[0023] Optionally, after forming the first connection layer, the method further includes: forming a second connection layer in the substrate connection region, wherein the second connection layer extends from the second surface of the substrate to the first surface of the substrate, and the second connection layer contacts the first connection layer.

[0024] Optionally, the bottom of the first connection layer has a first size, the top of the second connection layer in contact with the first connection layer has a second size, and the first size is greater than the second size.

[0025] Optionally, the first size is greater than the second size by 10% to 50%.

[0026] Optionally, the method for forming the second connecting layer includes: forming a second mask layer on the second surface of the substrate, the second mask layer exposing the surface of the connecting area; using the second mask layer as a mask, etching the substrate until the surface of the first connecting layer is exposed, forming a third groove in the substrate; and forming the second connecting layer in the third groove.

[0027] Optionally, after forming the second connection layer, the method further includes: forming a plurality of conductive structures on the second surface of the substrate, wherein the conductive structures are electrically connected to the second connection layer.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] The semiconductor structure of the technical solution of the present invention has a first groove in the connection area of ​​the first surface of the substrate. In the direction from the first surface to the second surface of the substrate, the first groove includes a first area, a second area and a third area. The first area has a first projection on the substrate surface, the second area has a second projection on the substrate surface, and the third area has a third projection on the substrate surface. The area of ​​the second projection is greater than the area of ​​the first projection, and the area of ​​the second projection is greater than the area of ​​the third projection. The first projection is within the range of the second projection, and the third projection is within the range of the second projection. The first connection layer is located in the first groove, so that the bottom area of ​​the first connection layer is increased. On the one hand, when the second connection layer is formed in the substrate connection area, the bottom of the second connection layer is easy to contact with the bottom of the first connection layer, reducing the poor contact between the second connection layer and the first connection layer, so that the first connection layer can be electrically connected to the conductive structure formed subsequently through the second connection layer; on the other hand, it can reduce the contact resistance of the first connection layer and the second connection layer. In summary, the performance of the semiconductor structure is improved.

[0030] The method for forming a semiconductor structure of the technical solution of the present invention forms a first groove in the connection area of ​​the first surface of the substrate, and the first groove includes a first area, a second area and a third area along the direction from the first surface to the second surface of the substrate, the first area has a first projection on the substrate surface, the second area has a second projection on the substrate surface, and the third area has a third projection on the substrate surface, the area of ​​the second projection is greater than the area of ​​the first projection, the area of ​​the second projection is greater than the area of ​​the third projection, and the first projection is within the range of the second projection, and the third projection is within the range of the second projection, and then a first connection layer is formed in the first groove, so that the bottom area of ​​the first connection layer is increased. On the one hand, when the second connection layer is formed in the substrate connection area, the bottom of the second connection layer is easy to contact with the bottom of the first connection layer, reducing the poor contact between the second connection layer and the first connection layer, so that the first connection layer can be electrically connected to the conductive structure formed subsequently through the second connection layer; on the other hand, the contact resistance between the first connection layer and the second connection layer can be reduced. In summary, the performance of the semiconductor structure is improved.

[0031] Furthermore, in a first direction parallel to the surface of the substrate, the cross-sectional shape of the first groove is spherical or polygonal, and the number of sides of the polygon is greater than or equal to 5, so that the bottom area of ​​the first groove is increased, thereby making it easy for the second connecting layer to contact the bottom of the first connecting layer.

[0032] Furthermore, the bottom of the first connecting layer has a first size, and the top of the second connecting layer in contact with the first connecting layer has a second size, and the first size is larger than the second size, so that when the second connecting layer is formed, the second connecting layer is easy to contact with the bottom of the first connecting layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor structure in one embodiment;

[0034] Figures 2 to 7 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] As described in the background art, the performance of the existing embedded power lines and backside power transmission networks in combination needs to be improved.

[0036] Figure 1 It is a schematic cross-sectional structure diagram of a semiconductor structure in one embodiment.

[0037] Please refer to Figure 1 , comprising: a substrate 100, wherein the substrate 100 comprises a first surface and a second surface opposite to each other, wherein the substrate comprises an effective area (not marked) and a connection area (not marked); a fin structure 101 located on the effective area of ​​the first surface of the substrate 100; a dielectric layer 102 located on the first surface of the substrate 100, wherein the dielectric layer 102 covers the top surface and the sidewall surface of the fin structure 101; a first connection layer 103 located in the connection area of ​​the first surface of the substrate 100, wherein the first connection layer 103 is also located in the dielectric layer 102; a second connection layer 104 located in the connection area of ​​the second surface of the substrate 100, wherein the second connection layer 104 is in contact with the bottom of the first connection layer 103; and a conductive layer 105 located on the second surface of the substrate 100, wherein the conductive layer 105 is electrically connected to the second connection layer 104.

[0038] In the semiconductor structure, as the size of the semiconductor structure becomes smaller and smaller, the size of the first connection layer 103 also becomes smaller and smaller. Therefore, when a second connection layer 104 in contact with the first connection layer 103 is formed in the second surface connection area of ​​the substrate 100, due to the influence of the accuracy of the photolithography process and the accuracy of the etching process, the formed second connection layer 104 has the risk of poor contact with the bottom of the first connection layer 103, so that the first connection layer 103 cannot be electrically connected to the conductive layer 105 through the second connection layer 104, thereby affecting the performance of the semiconductor structure.

[0039] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the semiconductor structure, by forming a first groove in the connection area of ​​the first surface of the substrate, along the direction from the first surface to the second surface of the substrate, the first groove includes a first area, a second area and a third area, the first area has a first projection on the substrate surface, the second area has a second projection on the substrate surface, the third area has a third projection on the substrate surface, the area of ​​the second projection is greater than the area of ​​the first projection, the area of ​​the second projection is greater than the area of ​​the third projection, and the first projection is within the range of the second projection, and the third projection is within the range of the second projection, and then a first connection layer is formed in the first groove, so that the bottom area of ​​the first connection layer is increased. On the one hand, when the second connection layer is formed in the substrate connection area, the bottom of the second connection layer is easy to contact with the bottom of the first connection layer, reducing the poor contact between the second connection layer and the first connection layer, so that the first connection layer can be electrically connected to the conductive structure formed subsequently through the second connection layer; on the other hand, it can reduce the contact resistance between the first connection layer and the second connection layer. In summary, the performance of the semiconductor structure is improved.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 2 to 7 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0042] Please refer to Figure 2 , providing a substrate 200, wherein the substrate 200 includes a first surface and a second surface opposite to each other, and the substrate 200 includes an active area I and a connection area II.

[0043] In this embodiment, the material of the substrate 200 is single crystal silicon; in other embodiments, the substrate may also be a semiconductor material such as polycrystalline silicon, germanium, silicon germanium, gallium arsenide, silicon on insulator or germanium on insulator.

[0044] The first surface active region I of the substrate 200 further has a plurality of fin structures 201 , and the plurality of fin structures 201 are arranged in parallel along a first direction X parallel to the surface of the substrate 200 .

[0045] The connection region II is located between adjacent fin structures 201 .

[0046] In this embodiment, the material of the fin structure 201 is single crystal silicon; in other embodiments, the fin structure may also be made of semiconductor materials such as polycrystalline silicon, germanium, silicon germanium, gallium arsenide, silicon on insulator or germanium on insulator.

[0047] Please continue to refer to Figure 2 , a protection layer 202 is formed on the first surface of the substrate, and the protection layer 202 covers the top surface and the sidewall surface of the fin structure 201.

[0048] The material of the protective layer 202 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the protective layer 202 includes silicon oxide.

[0049] Next, a first groove 205 is formed in the connection region II of the substrate 200, and the first groove 205 extends from the first surface to the second surface of the substrate 200. For the specific formation process of the first groove 205, please refer to Figure 3 to Figure 4 .

[0050] Please refer to Figure 3 , forming a first mask layer 203 on the protective layer 202, wherein the first mask layer 203 exposes the surface of the protective layer 202 on the connection area II; etching the protective layer 202 using the first mask layer 203 as a mask until the surface of the substrate 200 is exposed, and forming a second groove 204 in the protective layer 202.

[0051] The process of etching the protection layer 202 includes a dry etching process and a wet etching process or a combination of one or more of the above.

[0052] In this embodiment, the process of etching the protection layer 202 includes a dry etching process.

[0053] Please refer to Figure 4 , etching the substrate 200 exposed by the second groove 204 to form the first groove 205 in the connection region II.

[0054] The method for etching the substrate 200 exposed by the second groove 204 includes: etching the substrate 200 using a first etching process to form an initial first groove (not shown), wherein the side wall of the initial first groove is perpendicular to the bottom surface of the initial first groove; etching the substrate 200 exposed by the initial first groove using a second etching process to form a first groove 205, wherein the side wall of the first groove 205 is recessed into the effective area I.

[0055] The first etching process can obtain an initial first groove whose sidewall is perpendicular to the bottom surface. In this embodiment, the first etching process includes an anisotropic dry etching process.

[0056] The second etching process can obtain the first groove 205 whose sidewall is recessed into the active area I. The second etching process includes a combination of one or more of a wet etching process and an isotropic dry etching process.

[0057] In this embodiment, the second etching process includes an isotropic dry etching process, and the parameters of the isotropic dry etching process include: the etching gas is a mixed gas of NF3, H2, N2 and O2; the gas pressure is 5mTorr~100mTorr; the power is 100W~1000W; and the gas flow rate is 0sccm~500sccm.

[0058] In a first direction X parallel to the surface of the substrate 200 and perpendicular to the extension direction of the fin structure 201, the cross-sectional shape of the first groove 205 is spherical or polygonal, and the number of sides of the polygon is greater than or equal to 5, thereby increasing the bottom area of ​​the first groove 205, so that the subsequently formed second connection layer can easily contact the bottom of the first connection layer.

[0059] In this embodiment, the size of the first groove 205 in the first direction X is 10nm to 100nm; the size of the first groove 205 in the direction from the first surface to the second surface of the substrate is 10nm to 100nm. For the first groove 205 in the above size range, when the first connection layer is subsequently formed in the first groove 205, the bottom area of ​​the first connection layer is increased, so that the second connection layer formed subsequently is easy to contact with the first connection layer, and the first connection layer has a good conductive effect.

[0060] In this embodiment, the first groove 205 is spherical in shape.

[0061] In the direction from the first surface to the second surface of the substrate 200, the first groove 205 includes a first area (not marked), a second area (not marked) and a third area (not marked), the first area has a first projection on the surface of the substrate 200, the second area 200 has a second projection on the surface of the substrate, and the third area 200 has a third projection on the surface of the substrate, the area of ​​the second projection is greater than the area of ​​the first projection, the area of ​​the second projection is greater than the area of ​​the third projection, and the first projection is within the range of the second projection, and the third projection is within the range of the second projection, so that when a first connection layer is subsequently formed in the first groove 205, the bottom area of ​​the first connection layer is increased, so that the second connection layer formed subsequently can be easily contacted with the first connection layer.

[0062] Please refer to Figure 5 , a first connection layer 206 is formed in the first groove 205 .

[0063] The method for forming the first connection layer 206 includes: forming a connection material layer (not shown) in the second groove 204, in the first groove 205 and on the protective layer 202; flattening the connection material layer until the surface of the protective layer 202 is exposed to form an initial connection layer (not shown); and etching back the initial connection layer to form the first connection layer 206.

[0064] The material of the first connection layer 206 includes metal, and the metal includes: one or more combinations of copper, aluminum, tungsten, cobalt and titanium nitride. The formation process of the connection material layer includes physical vapor deposition process or electroplating process.

[0065] In this embodiment, the material of the first connection layer 206 includes copper; and the process of forming the connection material layer includes a physical vapor deposition process.

[0066] In this embodiment, a portion of the first connection layer 206 is also located in the second groove 204 .

[0067] In the direction from the first surface to the second surface of the substrate 200, the first groove 205 includes a first area, a second area and a third area, the first area has a first projection on the surface of the substrate 200, the second area 200 has a second projection on the surface of the substrate, the third area 200 has a third projection on the surface of the substrate, the area of ​​the second projection is greater than the area of ​​the first projection, the area of ​​the second projection is greater than the area of ​​the third projection, and the first projection is within the range of the second projection, and the third projection is within the range of the second projection, so that the bottom area of ​​the first connection layer 206 located in the first groove 205 is increased. The increase in the bottom area of ​​the first connection layer 206, on the one hand, makes it easy for the bottom of the second connection layer to contact with the bottom of the first connection layer 206 when the second connection layer is subsequently formed in the substrate connection area II, reducing the situation of poor contact between the second connection layer and the first connection layer 206, so that the first connection layer 206 can be electrically connected to the conductive structure formed subsequently through the second connection layer; on the other hand, it can reduce the contact resistance between the first connection layer 206 and the second connection layer.

[0068] Please continue to refer to Figure 5 After forming the first connection layer 206 , an isolation layer 207 is formed in the second groove 204 .

[0069] The material of the isolation layer 207 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the isolation layer 207 includes silicon oxide.

[0070] Please refer to Figure 6 After forming the first connection layer 206 , a second connection layer 208 is formed in the substrate connection region II, wherein the second connection layer 208 extends from the second surface of the substrate 200 to the first surface of the substrate 200 , and the second connection layer 208 contacts the first connection layer 206 .

[0071] The bottom of the first connecting layer 206 has a first size, and the top of the second connecting layer 208 in contact with the first connecting layer 206 has a second size, and the first size is larger than the second size, so that when the second connecting layer 208 is formed, the second connecting layer 208 is easy to contact the bottom of the first connecting layer 206.

[0072] In this embodiment, the first size is greater than the second size by 10% to 50%.

[0073] The method for forming the second connecting layer 208 includes: forming a second mask layer (not shown) on the second surface of the substrate, the second mask layer exposing the surface of the connecting area II; using the second mask layer as a mask, etching the substrate 200 until the surface of the first connecting layer 206 is exposed, forming a third groove (not shown) in the connecting area II; and forming the second connecting layer 208 in the third groove.

[0074] The material of the second connection layer 208 includes metal, and the metal includes: one or more combinations of copper, aluminum, tungsten, cobalt and titanium nitride.

[0075] Since the first size is greater than the second size in the range of 10% to 50%, when the third groove is formed, the bottom of the third groove exposes a larger area of ​​the bottom of the first connection layer 206, so that even if the position of the third groove deviates, the second connection layer 208 formed in the third groove can contact the first connection layer 206, and the contact area between the second connection layer 208 and the first connection layer 206 is also large, thereby reducing the contact resistance between the first connection layer 206 and the second connection layer 208, and also increasing the process window for forming the third groove.

[0076] Please refer to Figure 7 , a plurality of conductive structures 209 are formed on the second surface of the substrate 200 , and the conductive structures 209 are electrically connected to the second connection layer 208 .

[0077] The conductive structure 209 is used to electrically connect the semiconductor structure to an external structure.

[0078] The material of the conductive structure 209 includes metal, and the metal includes: one or more combinations of copper, aluminum, tungsten, cobalt and titanium nitride.

[0079] The second connection layer 208 has good contact with the first connection layer 206 , so that the first connection layer 206 can be electrically connected to the conductive structure 209 through the second connection layer 208 , thereby achieving electrical connection between the semiconductor structure and the external structure.

[0080] Accordingly, the present invention also provides a semiconductor structure, please continue to refer to Figure 7, comprising: a substrate 200, wherein the substrate 200 comprises a first surface and a second surface opposite to each other, and the substrate 200 comprises an effective area I and a connection area II; a first groove 205 located in the connection area II of the substrate 200, wherein the first groove 205 extends from the first surface of the substrate 200 to the second surface, and in the direction from the first surface to the second surface of the substrate 200, the first groove comprises a first area, a second area and a third area, the first area has a first projection on the surface of the substrate 200, the second area has a second projection on the surface of the substrate 200, the third area has a third projection on the surface of the substrate 200, the area of ​​the second projection is greater than the area of ​​the first projection, the area of ​​the second projection is greater than the area of ​​the third projection, and the first projection is within the range of the second projection, and the third projection is within the range of the second projection; a first connection layer 206 which can be electrically connected and is located in the first groove 205.

[0081] In this embodiment, in the first direction X parallel to the surface of the substrate 200 , the shape of the first groove 205 is spherical or polygonal, and the number of sides of the polygon is greater than or equal to 5.

[0082] In this embodiment, the first surface active region I of the substrate 200 further has a plurality of fin structures 201 , and the plurality of fin structures 201 are arranged in parallel along a first direction X parallel to the substrate surface; the connection region II is located between adjacent fin structures 201 .

[0083] In this embodiment, it also includes: a protective layer 202 located on the first surface of the substrate 200, the protective layer 202 covering the top surface and side wall surface of the fin structure 201; a second groove 204 located in the protective layer 202, the second groove 204 is connected to the first groove 205, and part of the first connection layer 206 is located in the second groove 204; an isolation layer 207 located in the second groove 204 on the first connection layer 206.

[0084] In this embodiment, it also includes: a second connection layer 208 located in the connection region II of the substrate 200 , the second connection layer 208 extends from the second surface of the substrate 200 to the first surface of the substrate 200 , and the second connection layer 208 is in contact with the first connection layer 206 .

[0085] In this embodiment, the bottom of the first connection layer 206 has a first size, the top of the second connection layer 208 in contact with the first connection layer 206 has a second size, and the first size is greater than the second size.

[0086] In this embodiment, the first size is greater than the second size by 10% to 50%.

[0087] In this embodiment, the material of the first connection layer 206 includes metal, and the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt and titanium nitride; the material of the second connection layer 208 includes metal, and the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt and titanium nitride.

[0088] In this embodiment, the present invention further includes: a plurality of conductive structures 209 located on the second surface of the substrate 200 , wherein the conductive structures 209 are electrically connected to the second connection layer 208 .

[0089] The semiconductor structure, the first surface connection region II of the substrate 200 has a first groove 205, along the direction from the first surface to the second surface of the substrate, the first groove includes a first region, a second region and a third region, the first region has a first projection on the substrate surface, the second region has a second projection on the substrate surface, the third region has a third projection on the substrate surface, the area of ​​the second projection is greater than the area of ​​the first projection, the area of ​​the second projection is greater than the area of ​​the third projection, and the first projection is within the range of the second projection, the third projection is within the range of the second projection, the first connection layer 206 is located in the first groove 205, so that the bottom area of ​​the first connection layer 206 is increased. On the one hand, when the second connection layer 208 is formed in the connection region II of the substrate 200, the bottom of the second connection layer 208 is easy to contact with the bottom of the first connection layer 206, reducing the situation of poor contact between the second connection layer 208 and the first connection layer 206, so that the first connection layer 206 can be electrically connected to the conductive structure 209 through the second connection layer 208; on the other hand, the contact resistance between the first connection layer 206 and the second connection layer 208 can be reduced. In summary, the performance of the semiconductor structure is improved.

[0090] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising an active area and a connection area; A first groove located in the substrate connection area, the sidewall of the first groove is recessed into the effective area, the first groove extends from the first surface to the second surface of the substrate, and in the direction from the first surface to the second surface of the substrate, the first groove includes a first area, a second area and a third area, the first area has a first projection on the substrate surface, the second area has a second projection on the substrate surface, the third area has a third projection on the substrate surface, the area of ​​the second projection is larger than the area of ​​the first projection, the area of ​​the second projection is larger than the area of ​​the third projection, and the first projection is within the range of the second projection, and the third projection is within the range of the second projection; A first connection layer located in the first groove and capable of being electrically connected; a second connection layer located in the substrate connection region, the second connection layer extending from the second surface of the substrate to the first surface of the substrate, and the second connection layer contacting the first connection layer, the bottom of the first connection layer having a first size, the top of the second connection layer contacting the first connection layer having a second size, and the first size being greater than the second size; a protective layer on the first side of the substrate; a second groove located in the protective layer, the second groove being located on the first groove and being communicated with the first groove; An isolation layer is located in the second groove on the first connection layer.

2. The semiconductor structure according to claim 1, wherein: In a first direction parallel to the surface of the substrate, a cross-sectional shape of the first groove is spherical or polygonal, and the number of sides of the polygon is greater than or equal to 5.

3. The semiconductor structure according to claim 1, wherein: The effective area on the first surface of the substrate is also provided with a plurality of fin structures, and the plurality of fin structures are arranged in parallel along a first direction parallel to the surface of the substrate; the connection area is located between adjacent fin structures.

4. The semiconductor structure according to claim 3, characterized in that The protection layer covers the top surface and sidewall surfaces of the fin structure; a portion of the first connection layer is located in the second groove.

5. The semiconductor structure according to claim 1, wherein: The first size is greater than the second size by 10% to 50%.

6. The semiconductor structure according to claim 1, wherein: Also includes: A plurality of conductive structures are located on the second surface of the substrate, and the conductive structures are electrically connected to the second connection layer.

7. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising an active area and a connection area; forming a protective layer on the first surface of the substrate; A first groove is formed in the substrate connection region, the sidewall of the first groove is recessed into the effective region, the first groove extends from the first surface to the second surface of the substrate, and in the direction from the first surface to the second surface of the substrate, the first groove includes a first area, a second area and a third area, the first area has a first projection on the substrate surface, the second area has a second projection on the substrate surface, the third area has a third projection on the substrate surface, the area of ​​the second projection is larger than the area of ​​the first projection, the area of ​​the second projection is larger than the area of ​​the third projection, and the first projection is within the range of the second projection, and the third projection is within the range of the second projection; forming a first connection layer that can be electrically connected in the first groove; forming a second groove in the protective layer on the first connection layer, wherein the second groove is located on the first groove and communicates with the first groove; forming an isolation layer in the second groove; A second connection layer is formed in the substrate connection area, wherein the second connection layer extends from the second surface of the substrate to the first surface of the substrate, and the second connection layer contacts the first connection layer, the bottom of the first connection layer has a first size, and the top of the second connection layer in contact with the first connection layer has a second size, and the first size is larger than the second size.

8. The method for forming a semiconductor structure according to claim 7, wherein: In a first direction parallel to the surface of the substrate, a cross-sectional shape of the first groove is spherical or polygonal, and the number of sides of the polygon is greater than or equal to 5.

9. The method for forming a semiconductor structure according to claim 7, wherein: The effective area on the first surface of the substrate is also provided with a plurality of fin structures, and the plurality of fin structures are arranged in parallel along a first direction parallel to the surface of the substrate; the connection area is located between adjacent fin structures.

10. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming a first groove includes: forming a protective layer on a first surface of a substrate, the protective layer covering the top surface and side wall surface of the fin structure; forming a first mask layer on the protective layer, the first mask layer exposing the surface of the protective layer on the connection area; etching the protective layer using the first mask layer as a mask until the surface of the substrate is exposed, forming a second groove in the protective layer; etching the substrate exposed by the second groove to form the first groove.

11. The method for forming a semiconductor structure according to claim 10, wherein: The method for etching the substrate exposed by the second groove includes: etching the substrate using a first etching process to form an initial first groove, wherein the sidewall of the initial first groove is perpendicular to the bottom surface of the initial first groove; etching the substrate exposed by the initial first groove using a second etching process to form a first groove, wherein the sidewall of the first groove is recessed into the effective area.

12. The method for forming a semiconductor structure according to claim 11, wherein: The first etching process includes an anisotropic dry etching process.

13. The method for forming a semiconductor structure according to claim 11, wherein: The second etching process includes a combination of one or more of a wet etching process and an isotropic dry etching process.

14. The method for forming a semiconductor structure according to claim 10, wherein: Part of the first connection layer is also located in the second groove.

15. The method for forming a semiconductor structure according to claim 7, wherein: The first size is greater than the second size by 10% to 50%.

16. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the second connecting layer includes: forming a second mask layer on the second surface of the substrate, the second mask layer exposing the surface of the connecting area; using the second mask layer as a mask, etching the substrate until the surface of the first connecting layer is exposed, forming a third groove in the substrate; and forming the second connecting layer in the third groove.

17. The method for forming a semiconductor structure according to claim 7, wherein: After forming the second connection layer, the method further includes: forming a plurality of conductive structures on the second surface of the substrate, wherein the conductive structures are electrically connected to the second connection layer.

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