Method for forming a semiconductor device

Abstract

A method for forming a crystalline protective polysilicon layer is disclosed, wherein the method does not generate defective voids during subsequent processes, thereby providing effective protection for underlying devices. In one embodiment, a method for forming a semiconductor device includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a third polysilicon layer on the epitaxial layer, wherein the protective coating includes a second polysilicon layer, wherein the second polysilicon layer is deposited at a first temperature ranging from 600 degrees Celsius to 700 degrees Celsius, and wherein the second polysilicon layer in the protective coating is configured to protect the first polysilicon layer when the third polysilicon layer is etched.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method for forming a semiconductor device. Background Art

[0002] During the fabrication of semiconductor devices, polycrystalline silicon (poly-Si) layers deposited at deposition temperatures ranging from 540 degrees Celsius to 560 degrees Celsius are amorphous and can recrystallize when processed at temperatures above the deposition temperature. This recrystallization process can result in an increase in grain size and the formation of defective voids in the poly-Si layer, making the semiconductor layer and the devices below the poly-Si layer susceptible to process damage (e.g., plasma, etching, etc.). Therefore, it is desirable to develop a method for forming a poly-Si layer that is inert to higher processing temperatures without generating defective voids, thereby providing effective protection for the semiconductor layer and the devices below. Summary of the invention

[0003] An embodiment of the present disclosure provides a method for forming a semiconductor device, comprising: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a third polysilicon layer on the epitaxial layer, wherein the protective coating includes a second polysilicon layer, wherein the second polysilicon layer is deposited at a first temperature in the range of 600 degrees Celsius to 700 degrees Celsius, and wherein the second polysilicon layer in the protective coating is configured to protect the first polysilicon layer when the third polysilicon layer is etched.

[0004] Another embodiment of the present disclosure provides a method for forming a semiconductor device, comprising: depositing a protective coating on a first polysilicon layer in a first transistor; forming an epitaxial layer on the protective coating for a second transistor; and depositing a third polysilicon layer on the epitaxial layer for the second transistor, wherein the protective coating includes a second polysilicon layer, wherein the second polysilicon layer is deposited at a first temperature in the range of 600 degrees Celsius to 700 degrees Celsius, and wherein the second polysilicon layer in the protective coating is configured to protect the first polysilicon layer of the first transistor when the second transistor is formed.

[0005] Another embodiment of the present disclosure provides a method for forming a semiconductor device, comprising: depositing a first dielectric layer on a first polysilicon layer on a substrate; depositing a second polysilicon layer on the first dielectric layer at a first temperature; patterning the first dielectric layer and the second polysilicon layer; forming an epitaxial layer on the second polysilicon layer and the substrate at a second temperature; depositing a second dielectric layer on the epitaxial layer; depositing a third polysilicon layer on the second dielectric layer; patterning the third polysilicon layer to remove at least a portion of the third polysilicon layer; patterning the epitaxial layer to remove at least a portion of the epitaxial layer on the second polysilicon layer; and etching away the second polysilicon layer, wherein the first temperature is between 600 degrees Celsius and 700 degrees Celsius, wherein the second temperature is between 650 degrees Celsius and 950 degrees Celsius, and wherein the second polysilicon layer is configured to protect the first polysilicon layer when the third polysilicon layer is patterned. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that the various features are not necessarily drawn to scale. In fact, the size and geometry of the various features may be arbitrarily increased or reduced for clarity of description.

[0007] Figure 1 A flow chart illustrating an exemplary method of forming a semiconductor device according to some embodiments of the present disclosure.

[0008] Figure 2A to Figure 2L According to some embodiments of the present disclosure, Figure 1 sectional views of an exemplary semiconductor device with a collimator manufactured by the method at various stages of manufacture.

[0009] Figure 3A Defect mapping of two wafers having two different protective polysilicon layers prepared at different temperatures is shown according to some embodiments of the present disclosure.

[0010] Figure 3B Defect mapping of two wafers having two different protective polysilicon layers prepared at different temperatures is shown according to some embodiments of the present disclosure.

[0011] [Explanation of Symbols]

[0012] 100: Methods

[0013] 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126: Operation

[0014] 200: Semiconductor devices

[0015] 202: Substrate

[0016] 204: First Area

[0017] 206: Second Area

[0018] 212, 214: Conductive characteristics

[0019] 216: First dielectric layer

[0020] 218: First polysilicon layer

[0021] 220: Photoresist layer

[0022] 222: Second dielectric layer

[0023] 224: Second polysilicon layer

[0024] 226: Epitaxial layer

[0025] 228: The third dielectric layer

[0026] 230: Third polysilicon layer

[0027] 240: BJT Device

[0028] 242: CMOS device

[0029] 300, 310: Defect Mapping

[0030] 302, 312: First chip

[0031] 304, 314: Second chip DETAILED DESCRIPTION

[0032] The following disclosure sets forth various exemplary embodiments for implementing the different features of the subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, it should be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected to or coupled to the other element, or one or more intermediate elements may be present.

[0033] During the fabrication of semiconductor devices, polycrystalline silicon (poly-Si) layers deposited at deposition temperatures in the range of 540 degrees Celsius to 560 degrees Celsius are amorphous and can recrystallize when processed at temperatures above the deposition temperature. This recrystallization process can result in larger grain sizes and the formation of defective voids in the poly-Si layer, making the semiconductor layer and devices below the poly-Si layer susceptible to process damage (e.g., plasma, etching, etc.). A method of forming a poly-Si layer that is inert to higher processing temperatures without creating defective voids, thereby providing effective protection for the semiconductor layer and the devices below is disclosed.

[0034] Figure 1 1 is a flow chart showing a method 100 of forming a semiconductor device according to some embodiments of the present disclosure. It should be noted that the method 100 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that in Figure 1 Before the method 100 shown, Figure 1 During the method 100 shown, and in Figure 1 Additional operations may be provided after the method 100 is shown, and some of the other operations may only be briefly described herein. In some embodiments, the operations of the method 100 may be respectively Figure 2A to Figure 2L Cross-sectional views of semiconductor devices at various stages of fabrication are shown in association with each other, which will be discussed in further detail below.

[0035] Reference now Figure 1 , method 100 begins with operation 102, where, in accordance with some embodiments, a substrate is provided. In some embodiments, the substrate includes at least one conductive feature. Method 100 continues with operation 104, where, in accordance with some embodiments, a first dielectric layer is deposited on a first surface of the substrate. In some embodiments, the first dielectric layer is a gate oxide comprising silicon oxide. Method 100 continues with operation 106, where, in accordance with some embodiments, a first polysilicon layer is deposited on a surface of the first dielectric layer under a first deposition condition. In some embodiments, the first deposition condition includes a first deposition temperature in a range of 600 degrees Celsius to 700 degrees Celsius.

[0036] The method 100 continues with operation 108, in which the first polysilicon layer and the first dielectric layer are patterned. In some embodiments, the first polysilicon layer and the first dielectric layer are patterned by a photolithography process followed by an etching process. In some embodiments, the patterned first polysilicon layer and the patterned first dielectric layer are aligned with the conductive features in the first region of the substrate. In some embodiments, the patterned first polysilicon layer and the patterned first dielectric layer are configured as a gate terminal structure of a complementary metal oxide semiconductor (CMOS) transistor in the first region of the substrate. The method 100 continues with operation 110, in which, according to some embodiments, a second dielectric layer is deposited on a surface of the patterned first polysilicon layer and on the first surface of the substrate. In some embodiments, the second dielectric layer comprises silicon oxide. The method 100 continues with operation 112, in which, according to some embodiments, a second polysilicon layer is deposited on a surface of the second dielectric layer under the first deposition condition. In some embodiments, the first deposition conditions include a first deposition temperature in a range between 600 degrees Celsius and 700 degrees Celsius.

[0037] The method 100 continues with operation 114, in which, according to some embodiments, the second dielectric layer and the second polysilicon layer are patterned. In some embodiments, the second dielectric layer and the second polysilicon layer are patterned to expose the first surface of the substrate in the second region. The method 100 continues with operation 116, in which, according to some embodiments, an epitaxial (EPI) layer is grown on the first surface of the substrate in the second region and on the surface of the second polysilicon layer in the first region. In some embodiments, the epitaxial layer on the first surface of the substrate is used to construct at least one bipolar junction transistor (BJT) in the second region. The method 100 continues with operation 118, in which, according to some embodiments, a third dielectric layer and a third polysilicon layer are deposited on the surface of the epitaxial layer. In some embodiments, the third dielectric layer comprises silicon oxide. In some embodiments, the third polysilicon layer is deposited under a second deposition condition, wherein the second deposition condition comprises a second deposition temperature. In some embodiments, the second deposition temperature is within a range of 540 degrees Celsius and 560 degrees Celsius, which can enable lower cost and faster deposition of the amorphous polysilicon layer.

[0038] The method 100 continues with operation 120, in which, according to some embodiments, the third polysilicon layer is patterned. In some embodiments, the third polysilicon layer is patterned by a photolithography process followed by an etching process. In some embodiments, the patterned third polysilicon layer is aligned with the conductive features in the second region as an emitter gate terminal of the BJT in the second region. The method 100 continues with operation 122, in which, according to some embodiments, a BJT is constructed in the second region. In some embodiments, the BJT is constructed by a process step including at least one of the following steps: making an emitter terminal and a spacer, and removing the third dielectric layer using a buffered oxide etch (BOE) process. The method 100 continues with operation 124, in which, according to some embodiments, the EPI layer is patterned. In some embodiments, the EPI layer is patterned by a photolithography process followed by an etching process. In some embodiments, before the EPI layer is patterned, an etching process is used to etch away the third dielectric layer. In some embodiments, the patterned epitaxial layer is aligned with the BJT in the second region of the substrate. Method 100 continues with operation 126 where the patterned second polysilicon layer is further etched away from the first region of the substrate. In some embodiments, the second dielectric layer is also patterned.

[0039] As mentioned above, Figure 2A to Figure 2L Shown in cross-section Figure 1A portion of a semiconductor device 200 at various stages of fabrication of the method 100 is shown. The semiconductor device 200 may be included in an integrated circuit (IC). Figure 2A to Figure 2L Although the various figures show a semiconductor device 200, it should be understood that the integrated circuit may include numerous other devices, such as resistors, capacitors, inductors, fuses, etc., which are not shown in the figure for the sake of clarity. Figure 2A to Figure 2L Shown in.

[0040] Figure 2A According to some embodiments of the present disclosure, a semiconductor device 200 including a substrate 202 is provided in various stages of manufacture. Figure 1 102. In some embodiments, substrate 202 is a silicon (Si) substrate. Alternatively, substrate 202 may include other elemental semiconductor materials such as, for example, germanium (Ge). Substrate 202 may also include compound semiconductors such as silicon carbide (SiC), gallium arsenic (GaAs), indium arsenide (InAs), and indium phosphide (InP). Substrate 202 may include alloy semiconductors such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), and gallium indium phosphide (GaInP). In one embodiment, substrate 202 includes an epitaxial layer. For example, substrate 202 may have an epitaxial layer overlying a bulk semiconductor. In addition, substrate 202 may include a semiconductor-on-insulator (SOI) structure. For example, the substrate 202 may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable techniques such as wafer bonding and polishing.

[0041] In the illustrated embodiment, the substrate 202 includes a first region 204 and a second region 206, wherein the first region 204 and the second region 206 each include a plurality of conductive features 212 / 214. It should be noted that the substrate 202 may include a plurality of first regions 204 and a plurality of second regions 206, wherein each of the plurality of first regions 204 and each of the plurality of second regions 206 include a plurality of conductive features 212 / 214. In some embodiments, the conductive features 214 in the second region are further fabricated in the conductive features 212. In some embodiments, the plurality of conductive features 212 / 214 include various p-type doped regions and / or n-type doped regions implemented by processes such as ion implantation and / or diffusion. Each of the plurality of conductive features 212 / 214 is one of: an n-well, a p-well, a lightly doped region (LDD), a heavily doped source and drain (S / D), and various channel doping profiles configured to form various integrated circuit (IC) devices, such as a CMOS field-effect transistor (CMOS-FET) in the second region 206 and a BJT in the first region 204.

[0042] In some embodiments, the conductive features 212 / 214 are formed by a separate patterning (e.g., photolithography) process, which may include various exposure, development, backing, stripping, etching, and rinsing processes. In some embodiments, the conductive features 212 / 214 are formed by depositing a conductive material on a separate patterned photoresist layer using chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, and / or other suitable techniques, followed by wet etching of the photoresist layer.

[0043] The substrate 202 may also include other functional features formed in and on the substrate, such as resistors or capacitors. The substrate 202 also includes lateral isolation features, such as shallow trench isolation (STI), provided to separate various devices formed in the substrate 202. The various devices in the substrate 202 also include silicides disposed on the source / drain, gate, and other device features to reduce contact resistance and enhance process compatibility when coupling between devices through local interconnects.

[0044] Figure 2B According to some embodiments of the present disclosure, a semiconductor device 200 including a substrate 202 and a first dielectric layer 216 is provided in various stages of manufacture. Figure 1104. In some embodiments, the first dielectric layer 216 includes a material that is at least one of: silicon oxide, a low dielectric constant (low-k) material, other suitable dielectric materials, or a combination thereof. The low dielectric constant material may include fluorinated silica glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x C y ), (Applied Materials of Santa Clara, Calif.), xerogels, aerogels, amorphous fluorinated carbons, parylene, bis-benzocyclobutenes (BCB), SiLK (Dow Chemical, Midland, Mich.), polyimide, and / or other low-k dielectric materials developed in the future. In some embodiments, the first dielectric layer 216 is deposited using plasma enhanced chemical vapor deposition (PECVD) using silane gas as a precursor gas. In some other embodiments, the first dielectric layer 216 is deposited using a physical vapor deposition (PVD) process. In some embodiments, the first dielectric layer 216 is formed by a thermal oxidation process.

[0045] Figure 2C According to some embodiments of the present disclosure, the semiconductor device 200 including the first dielectric layer 216 and the first polysilicon layer 218 is used in various stages of manufacture. Figure 1 106. In some embodiments, plasma enhanced chemical vapor deposition (PECVD) is used to deposit the first polysilicon layer 218. In some embodiments, the first polysilicon layer 218 is deposited under a first deposition condition, wherein the first deposition condition includes a first temperature. In some embodiments, the first temperature is in a range of 600 degrees Celsius to 700 degrees Celsius.

[0046] Figure 2D According to some embodiments of the present disclosure, the semiconductor device 200 in which the photoresist layer 220 is patterned on the first polysilicon layer 218 is used in various stages of manufacturing. Figure 11 is a cross-sectional view of a stage corresponding to operation 108. As described below, the patterned photoresist layer 220 is used to mask the etching of the first polysilicon layer 218 and the first dielectric layer 216 to form a gate oxide and a gate terminal in the second region 206 of the substrate 202. Therefore, in some embodiments, the patterned photoresist layer 220 is formed after a patterning (e.g., photolithography) process to align the gate terminal structure (i.e., the gate oxide and the gate terminal) with the conductive features 212 / 214 in the second region 206 of the substrate 202.

[0047] In some embodiments, the initial photoresist layer 220 before the patterning process may include a negative or positive photoresist layer that can be patterned in response to a lithography light source. In some alternative embodiments, the initial photoresist layer 220 may include an electron beam (e-beam) etchant layer (e.g., polymethyl methacrylate, methyl methacrylate, etc.) that can be patterned in response to an electron beam lithography energy source. In some embodiments, the initial photoresist layer 220 is formed on the first polysilicon layer 218 using a deposition process known in the art such as spin coating, spray coating, dip coating, roller coating, etc. The initial photoresist layer 220 is then patterned in a lithography process, which may involve various exposure, development, baking, stripping, etching, and rinsing processes. As a result, a patterned photoresist layer 220 is formed so that at least a portion of the top surface of the first polysilicon layer 218 is exposed, such as Figure 2D shown.

[0048] Figure 2E According to some embodiments of the present disclosure, the semiconductor device 200 including the patterned first polysilicon layer 218 and the patterned first dielectric layer 216 is used in various stages of manufacture. Figure 1 A cross-sectional view of a stage corresponding to operation 108 is shown. In some embodiments, the patterned photoresist layer 220 is used as a hard mask to form the patterned first polysilicon layer 218 and the patterned first dielectric layer 216. In some embodiments, the first polysilicon layer 218 and the first dielectric layer 216 are etched using at least one of the following etching methods (including dry etching and wet etching).

[0049] In some embodiments, the patterned photoresist layer 220 is then removed. In some embodiments, the patterned photoresist layer 210 can be removed by one or more chemical cleaning processes using acetone, 1-methyl-2-pyrrolidone (NMP), dimethyl sulfoxide (DMSO), or other suitable removal chemicals. In some embodiments, the chemicals used may need to be heated to a temperature above room temperature to effectively dissolve the patterned photoresist layer 220. The choice of remover is determined by the type and chemical structure of the patterned photoresist layer 220, the first polysilicon layer 218, and the first dielectric layer 216 to ensure the chemical compatibility of these layers with the chemical cleaning process. In some embodiments, this cleaning process is followed by a rinse process using isopropyl alcohol or the like, followed by a rinse using deionized water. As a result of this process, a gate terminal structure is formed in the second region 206 of the substrate 202.

[0050] Figure 2F According to some embodiments of the present disclosure, the semiconductor device 200 including the second dielectric layer 222 is used in various manufacturing stages. Figure 1 1. A cross-sectional view of a stage corresponding to operation 110 is shown. In some embodiments, a second dielectric layer 222 is deposited on at least a portion of substrate 202, over first dielectric layer 216 and patterned first polysilicon layer 218. In some embodiments, second dielectric layer 222 comprises silicon oxide. In some embodiments, second dielectric layer 222 is deposited using a thermal oxidation process. In some embodiments, second dielectric layer 222 has a thickness in a range of 40 nanometers to 60 nanometers.

[0051] Figure 2G According to some embodiments of the present disclosure, the semiconductor device 200 including the second dielectric layer 222 and the second polysilicon layer 224 is used in various manufacturing stages. Figure 1112. A cross-sectional view of a stage corresponding to operation 112 is shown. In some embodiments, the second polysilicon layer 224 is deposited under a first deposition condition, wherein the first deposition condition includes a first temperature. In some embodiments, the first temperature is in a range of 600 degrees Celsius to 700 degrees Celsius. In some embodiments, a first grain size in the second polysilicon layer 224 deposited at the first temperature in a range of 1 micron to 1000 microns is greater than a second grain size in the second polysilicon layer 224 when deposited at a second temperature lower than the first temperature and annealed at a typical temperature range of 650 degrees Celsius to 950 degrees Celsius during a subsequent epitaxial process, which will be discussed in detail below. In some embodiments, when fabricated at the second temperature, the second grain size of the second polysilicon layer 224 is in a range of less than 1 micron. In some embodiments, the second polysilicon layer 224 has a thickness in a range of 40 nanometers (nm) to 60 nanometers. In some embodiments, if the thickness of the polysilicon layer 224 is less than 40 nm, the surface of the polysilicon layer may become uneven or rough, thereby producing a poor quality polysilicon layer, while a thickness greater than 60 nm may excessively increase deposition time and cost. In some embodiments, the second dielectric layer 222 and the second polysilicon layer 224 are used to protect the patterned first polysilicon layer 218 in the second region 206 during the fabrication process in the first region 204, as described in detail below. In some embodiments, a second temperature higher than the first temperature is applied to form the second polysilicon layer 224 having a larger grain size, and the second polysilicon layer 224 will not recrystallize in subsequent processes to introduce defects (e.g., voids).

[0052] Figure 2H According to some embodiments of the present disclosure, the semiconductor device 200 including the patterned second dielectric layer 222, the patterned second polysilicon layer 224 and the epitaxial layer 226 is used in various stages of manufacture. Figure 1 A cross-sectional view of a stage corresponding to operations 114 and 116 is shown. In the illustrated embodiment, the second polysilicon layer 224 and the second dielectric layer 222 are patterned by a photolithography process using a patterned photoresist layer (not shown) as a hard mask. In some embodiments, at least a portion of the substrate 202 and at least one conductive feature 212 / 214 in the first region 204 are exposed for fabricating at least one BJT device.

[0053] In some embodiments, the epitaxial (EPI) layer 226 includes silicon. In some embodiments, the epitaxial layer 226 is deposited after removing the patterned photoresist layer used to pattern the second polysilicon layer 224 and the second dielectric layer 222. In some embodiments, the epitaxial layer 226 is deposited on the exposed portion of the substrate 202 in the first region 204 and the surface of the second polysilicon layer 224. In some embodiments, the epitaxial layer 226 is deposited using a silicon epitaxial process at a temperature range of 650° C. to 950° C. In some embodiments, the epitaxial layer 226 is treated at 850 degrees Celsius in a hydrogen (H2) environment to remove native oxide before silicon deposition. In some embodiments, the second polysilicon layer 224 deposited at the first temperature does not recrystallize during the hydrogen treatment process of the epitaxial layer 226, and thus can effectively prevent defective voids that may be formed when the second polysilicon layer 224 recrystallizes. In some embodiments, defects in the epitaxial layer 226 caused by defective voids in the second polysilicon layer 224 can be reduced. In some embodiments, the epitaxial layer 226 is deposited on the surface of the second polysilicon layer 224 having a surface roughness ranging from 6.00 nanometers (nm) to 6.25 nanometers, and the epitaxial layer has a surface roughness ranging from 5.75 nm to 6.00 nm. On the other hand, the epitaxial layer deposited on the surface of the second polysilicon layer 224 deposited at the first temperature has a surface roughness ranging from 7.00 nm to 7.25 nm.

[0054] Fig.2I According to some embodiments of the present disclosure, the semiconductor device 200 including the epitaxial layer 226, the third dielectric layer 228 and the third polysilicon layer 230 is used in various manufacturing stages. Figure 1 118. In some embodiments, the third dielectric layer 228 comprises silicon oxide formed on the surface of the epitaxial layer 226 using a plasma enhanced chemical vapor deposition process (PECVD). In some embodiments, a third polysilicon layer 230 is further deposited on the surface of the third dielectric layer 228 using furnace CVD. In some embodiments, the third polysilicon layer 230 is deposited under a second deposition condition, wherein the second deposition condition includes a second temperature. In some embodiments, the second temperature is in a range of 540 degrees Celsius to 560 degrees Celsius, which is lower than the first temperature used to deposit the first polysilicon layer 218 and the second polysilicon layer 224.

[0055] Figure 2J According to some embodiments of the present disclosure, the semiconductor device 200 including the patterned third polysilicon layer 230 is used in various manufacturing stages. Figure 11. A cross-sectional view of a stage corresponding to operation 120 is shown. In the illustrated embodiment, the third polysilicon layer 230 is patterned by a photolithography process using a patterned photoresist layer (not shown) as a hard mask. In some embodiments, a dry etching process is used to pattern the third polysilicon layer 230. In some embodiments, the patterned third polysilicon layer 230 is aligned with the conductive features 212 / 214 in the first region 206 of the substrate 202. In some embodiments, the etching process for patterning the third polysilicon layer 230 reduces further damage to the epitaxial layer 226 or the second polysilicon layer 224 compared to other approaches due to the reduction of defective voids in the second polysilicon layer 224 and thus the reduction of defects in the epitaxial layer 226.

[0056] Figure 2K According to some embodiments of the present disclosure, a semiconductor device 200 including a BJT device 240 is provided in various stages of manufacture. Figure 1 A cross-sectional view of a stage corresponding to operation 122 is shown. In some embodiments, the BJT device 240 includes the fabrication of an emitter terminal and a spacer. In some embodiments, a buffered oxide etch (BOE) process is used to remove the exposed third dielectric layer 228 .

[0057] Figure 2L According to some embodiments of the present disclosure, the semiconductor device 200 including the patterned EPI layer 226 is used in various stages of manufacture. Figure 1 1 and 126. A cross-sectional view of a stage corresponding to operations 124 and 126 is shown. In the illustrated embodiment, the epitaxial layer 226 is patterned by a photolithography process using a patterned photoresist layer (not shown) as a hard mask. In some embodiments, the epitaxial layer 226 is patterned using a dry etching process. In some embodiments, the patterned epitaxial layer 226 is aligned with the conductive features 212 / 214 in the first region 206 of the substrate 202. In some embodiments, due to the reduction of defective voids in the second polysilicon layer 224 and thus the reduction of defects in the epitaxial layer 226, the etching process used to pattern the epitaxial layer 226 does not cause further damage to the first polysilicon layer 218 as part of the gate terminal structure of the CMOS device 242 in the second region 206 of the substrate 202. In the illustrated embodiment, the second polysilicon layer 224 and the second dielectric layer 222 are further removed and etched to form the CMOS device 242.

[0058] Figure 3AA defect map 300 of two wafers with two protective polysilicon layers according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the defect map is electrically measured by performing functional tests and leakage tests on multiple devices on the two wafers at room temperature (approximately 25 degrees Celsius). In the illustrated embodiment, each defective device is represented as a point in the defect map. In some embodiments, the first wafer 302 includes a protective polysilicon layer deposited at a second temperature in the range of 540 to 560 (e.g., 550) degrees Celsius, and the second wafer 304 includes a protective polysilicon layer deposited at a first temperature in the range of 610 to 630 (e.g., 620) degrees Celsius. In the illustrated embodiment, the second percentage of defective devices in the second wafer is less than the first percentage of defective devices in the first wafer. In some embodiments, the second percentage of defective devices in the second wafer that failed the functional test and / or the leakage test is in the range of about 0% to about 2%.

[0059] Figure 3B A defect map 310 of two wafers having two protective polysilicon layers according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the defect map is electrically measured by performing a leakage test on a plurality of devices on the two wafers at 85 degrees Celsius. In the illustrated embodiment, each defective device is represented as a point in the defect map. In some embodiments, the first wafer 312 includes a protective polysilicon layer deposited at a second temperature of 550 degrees Celsius, and the second wafer 314 includes a protective polysilicon layer deposited at a first temperature of 620 degrees Celsius. In the illustrated embodiment, a second percentage of defective devices in the second wafer is less than the first percentage of defective devices in the first wafer. In some embodiments, the second percentage of defective devices in the second wafer that failed the leakage test is in a range of about 0% to about 0.5%.

[0060] In one embodiment, a method of forming a semiconductor device includes: depositing a protective coating on a first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a third polysilicon layer on the epitaxial layer, wherein the protective coating includes a second polysilicon layer, wherein the second polysilicon layer is deposited at a first temperature ranging from 600 degrees Celsius to 700 degrees Celsius, and wherein the second polysilicon layer in the protective coating is configured to protect the first polysilicon layer when the third polysilicon layer is etched. In some embodiments, it has been found that deposition temperatures above 600 degrees Celsius can prevent recrystallization of the polysilicon layer, while temperatures exceeding 700 degrees Celsius are generally unnecessary to further prevent recrystallization.

[0061] In some embodiments, the second polysilicon layer has a thickness in a range between 40 nanometers and 60 nanometers. In some embodiments, the epitaxial layer is formed at a second temperature in a range between 650 degrees Celsius and 950 degrees Celsius. In some embodiments, the semiconductor device includes at least one bipolar junction transistor and at least one complementary metal oxide semiconductor transistor, wherein the bipolar junction transistor includes the epitaxial layer and the third polysilicon layer, and wherein the complementary metal oxide semiconductor transistor includes the first polysilicon layer.

[0062] In another embodiment, a method of forming a semiconductor device includes: depositing a protective coating on a first polysilicon layer in a first transistor; forming an epitaxial layer on the protective coating for a second transistor; and depositing a third polysilicon layer on the epitaxial layer for the second transistor, wherein the protective coating includes a second polysilicon layer, wherein the second polysilicon layer is deposited at a first temperature between 600 degrees Celsius and 700 degrees Celsius, and wherein the second polysilicon layer in the protective coating is configured to protect the first polysilicon layer of the first transistor when forming the second transistor.

[0063] In some embodiments, each of the first polysilicon layers is deposited at the first temperature. In some embodiments, the protective coating further comprises a first dielectric layer, wherein the first dielectric layer comprises silicon oxide. In some embodiments, the third polysilicon layer is deposited at a second temperature in the range of 540 degrees Celsius and 560 degrees Celsius. In some embodiments, the method further comprises: after depositing the third polysilicon layer, patterning the third polysilicon layer to remove at least a portion of the third polysilicon layer; patterning the epitaxial layer to remove at least a portion of the epitaxial layer on the second polysilicon layer; and etching away the second polysilicon layer.

[0064] However, in another embodiment, a method of forming a semiconductor device includes: depositing a first dielectric layer on a first polysilicon layer on a substrate; depositing a second polysilicon layer on the first dielectric layer at a first temperature; patterning the first dielectric layer and the second polysilicon layer; forming an epitaxial layer on the second polysilicon layer and the substrate at a second temperature; depositing a second dielectric layer on the epitaxial layer; depositing a third polysilicon layer on the second dielectric layer; patterning the third polysilicon layer to remove at least a portion of the third polysilicon layer; patterning the epitaxial layer to remove at least a portion of the epitaxial layer on the second polysilicon layer; and etching away the second polysilicon layer, wherein the first temperature is between 600 degrees Celsius and 700 degrees Celsius, wherein the second temperature is between 650 degrees Celsius and 950 degrees Celsius, and wherein the second polysilicon layer is configured to protect the first polysilicon layer when the third polysilicon layer is patterned.

[0065] In some embodiments, the third polysilicon layer is deposited at a third temperature in a range between 540 degrees Celsius and 560 degrees Celsius. In some embodiments, the first polysilicon layer is deposited at the first temperature. In some embodiments, the second polysilicon layer has a thickness in a range between 40 nanometers and 60 nanometers.

[0066] The foregoing summarizes the features of several embodiments so that those of ordinary skill in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: depositing a protective coating on the first polysilicon layer; forming an epitaxial layer on the protective coating; and depositing a third polysilicon layer on the epitaxial layer, The protective coating includes a second polysilicon layer, wherein the second polysilicon layer is deposited at a first temperature ranging from 600 degrees Celsius to 700 degrees Celsius, and wherein the second polysilicon layer in the protective coating is configured to protect the first polysilicon layer when the third polysilicon layer is etched. The method of claim 1 , wherein the first polysilicon layer is deposited at the first temperature. 3 . The method of claim 1 , wherein the protective coating further comprises a first dielectric layer, wherein the first dielectric layer comprises silicon oxide.

4. The method of claim 1, wherein the third polysilicon layer is deposited at a second temperature ranging from 540 degrees Celsius to 560 degrees Celsius. 5 . The method of claim 1 , wherein the second polysilicon layer has a thickness ranging between 40 nanometers and 60 nanometers.

6. The method of claim 1, wherein the epitaxial layer is formed at a second temperature ranging from 650 degrees Celsius to 950 degrees Celsius.

7. The method according to claim 1, further comprising: After depositing the third polysilicon layer, patterning the third polysilicon layer to remove at least a portion of the third polysilicon layer; patterning the epitaxial layer to remove at least a portion of the epitaxial layer on the second polysilicon layer; and The second polysilicon layer is etched away.

8. The method of claim 1, wherein the semiconductor device comprises at least one bipolar junction transistor and at least one complementary metal oxide semiconductor transistor, wherein the bipolar junction transistor comprises the epitaxial layer and the third polysilicon layer, and wherein the complementary metal oxide semiconductor transistor comprises the first polysilicon layer.

9. A method of forming a semiconductor device, comprising: depositing a protective coating on the first polysilicon layer in the first transistor; forming an epitaxial layer on the protective coating for a second transistor; and depositing a third polysilicon layer over the epitaxial layer for the second transistor, wherein the protective coating comprises a second polysilicon layer, wherein the second polysilicon layer is deposited at a first temperature in a range of 600 degrees Celsius to 700 degrees Celsius, and wherein the second polysilicon layer in the protective coating is configured to protect the first polysilicon layer of the first transistor when the second transistor is formed.

10. The method of claim 9, wherein each of the first polysilicon layers is deposited at the first temperature.

11. The method of claim 9, wherein the protective coating further comprises a first dielectric layer, wherein the first dielectric layer comprises silicon oxide.

12. The method of claim 9, wherein the third polysilicon layer is deposited at a second temperature ranging from 540 degrees Celsius to 560 degrees Celsius.

13. The method of claim 9, wherein the second polysilicon layer has a thickness ranging between 40 nanometers and 60 nanometers.

14. The method of claim 9, wherein the epitaxial layer is formed at a second temperature in a range between 650 degrees Celsius and 950 degrees Celsius.

15. The method according to claim 9, further comprising: After depositing the third polysilicon layer, patterning the third polysilicon layer to remove at least a portion of the third polysilicon layer; patterning the epitaxial layer to remove at least a portion of the epitaxial layer on the second polysilicon layer; and The second polysilicon layer is etched away.

16. The method of claim 9, wherein the first transistor is a complementary metal oxide semiconductor transistor, and wherein the second transistor is a bipolar junction transistor.

17. A method of forming a semiconductor device, comprising: depositing a first dielectric layer on the first polysilicon layer on the substrate; depositing a second polysilicon layer on the first dielectric layer at a first temperature; patterning the first dielectric layer and the second polysilicon layer; forming an epitaxial layer on the second polysilicon layer and the substrate at a second temperature; depositing a second dielectric layer over the epitaxial layer; depositing a third polysilicon layer on the second dielectric layer; patterning the third polysilicon layer to remove at least a portion of the third polysilicon layer; patterning the epitaxial layer to remove at least a portion of the epitaxial layer on the second polysilicon layer; and etching away the second polysilicon layer, The first temperature is within a range of 600 degrees Celsius to 700 degrees Celsius, the second temperature is within a range of 650 degrees Celsius to 950 degrees Celsius, and the second polysilicon layer is configured to protect the first polysilicon layer when the third polysilicon layer is patterned.

18. The method of claim 17, wherein the third polysilicon layer is deposited at a third temperature ranging from 540 degrees Celsius to 560 degrees Celsius.

19. The method of claim 17, wherein the first polysilicon layer is deposited at the first temperature.

20. The method of claim 17, wherein the second polysilicon layer has a thickness in a range between 40 nanometers and 60 nanometers.

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