Semiconductor device and method of forming the same

Abstract

A semiconductor device and method are disclosed herein. In one example, the disclosed semiconductor device includes: an insulating layer; a first electrode having sidewalls and a bottom surface in contact with the insulating layer; a second electrode having sidewalls and a bottom surface in contact with the insulating layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to the sidewalls of the first electrode and to the sidewalls of the second electrode.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor device, and more particularly to a semiconductor device including a high-density metal-insulator-metal capacitor. Background Art

[0002] Capacitors (e.g., metal-insulator-metal (MIM) capacitors) are widely used in integrated circuits (e.g., mixed-signal circuits, analog circuits, radio frequency (RF) circuits, dynamic random access memory (DRAM), embedded DRAM, and logic circuits). The capacitance of a capacitor is proportional to the capacitor area and the dielectric constant (k) of the insulating layer, and inversely proportional to the thickness of the insulating layer. Therefore, to increase the capacitance, it is preferable to increase the area and dielectric constant value and decrease the thickness of the insulating layer.

[0003] A problem associated with the increased area is that traditional MIM capacitors require a large chip area. Traditional MIM capacitors have various horizontal comb structures and occupy a large layout area, resulting in a low area density. Additionally, each traditional MIM capacitor requires a capacitor top metal (CTM) electrode disposed on top of the dielectric layer, which leads to additional costs for manufacturing masks and performing etching processes to form the MIM capacitor. Therefore, existing MIM capacitors and methods of manufacturing the MIM capacitors are not entirely satisfactory. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor device including: an insulating layer and a dielectric layer. The dielectric layer includes a first electrode, a second electrode, and an insulator. The first electrode has sidewalls and a bottom surface in contact with the insulating layer. The second electrode has sidewalls and a bottom surface in contact with the insulating layer. The insulator is formed between the first electrode and the second electrode, wherein the insulator is coupled to the sidewalls of the first electrode and coupled to the sidewalls of the second electrode. At least one metal layer is located on top of the dielectric layer. Wherein, the first electrode is electrically connected to a logic high voltage through the at least one metal layer, and the second electrode is electrically connected to a logic low voltage through the at least one metal layer.

[0005] Embodiments of the present disclosure provide a semiconductor device, including: a substrate, an insulating layer, a dielectric layer, a plurality of first electrodes, and a plurality of second electrodes. The insulating layer is located on the substrate. The dielectric layer is located on the insulating layer. The plurality of first electrodes are formed in the dielectric layer. The plurality of second electrodes are formed in the dielectric layer. Wherein, the first electrodes and the second electrodes are interleaved with each other and form an electrode array extending along a first direction. The top surfaces of the first electrodes and the top surfaces of the second electrodes have the same rectangular shape, and the rectangular shape has: a first dimension extending along the first direction, and a second dimension that is larger than the first dimension and extends along a second direction, where the second direction is perpendicular to the first direction. The dielectric layer includes an insulating structure formed between the first electrodes and the second electrodes.

[0006] Embodiments of the present disclosure provide a method for forming a semiconductor device, including the following steps: forming an insulating layer on a substrate; depositing a dielectric layer on the insulating layer; and forming a plurality of electrodes in the dielectric layer, where the plurality of electrodes include first electrodes and second electrodes, the first electrodes and the second electrodes are interleaved with each other and form an electrode array extending along a first direction, the top surfaces of the plurality of electrodes have the same rectangular shape, the same rectangular shape has: a first dimension extending along the first direction, and a second dimension that is larger than the first dimension and extends along a second direction, where the second direction is perpendicular to the first direction, and the dielectric layer includes an insulating structure located between the first electrodes and the second electrodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Reading the following detailed description in conjunction with the accompanying drawings will best understand various aspects of the present disclosure. It should be noted that the various features are not necessarily drawn to scale. In fact, for clarity of discussion, the sizes and geometric shapes of the various features may be arbitrarily increased or decreased. Throughout the specification and the drawings, like reference numerals denote like features.

[0008] Figure 1 Shows an exemplary layout of a semiconductor device having a vertical capacitor structure according to some embodiments of the present disclosure.

[0009] Figure 2A Shows a cross-sectional view of a semiconductor device having a vertical capacitor structure according to some embodiments of the present disclosure.

[0010] Figure 2B Shows a perspective view of the vertical capacitor structure of a semiconductor device according to some embodiments of the present disclosure.

[0011] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E ,Figure 3F , Figure 3G , Figure 3H , Figure 3I and Figure 3J show cross-sectional views of exemplary semiconductor devices during various fabrication stages in accordance with some embodiments of the present disclosure.

[0012] Figure 4 is a flow chart showing an exemplary method of forming a semiconductor device having a vertical capacitor structure in accordance with some embodiments of the present disclosure.

[0013] [Description of Symbols]

[0014] 100, 200, 300: Semiconductor devices

[0015] 110: Active region

[0016] 120: Insulating layer

[0017] 130: Electrode

[0018] 131, 362: First electrode

[0019] 132, 364: Second electrode

[0020] 210: Substrate

[0021] 220, 320: Insulating layers

[0022] 230, 330: Dielectric layers

[0023] 240, CT: Contacts

[0024] 241: Left sidewall / Sidewall

[0025] 242: Right sidewall / Sidewall

[0026] 243: Bottom surface

[0027] 244: Top surface

[0028] 310: Active region / Substrate

[0029] 322: First oxide layer / Layer

[0030] 324: Nitride layer / Layer

[0031] 326: Second oxide layer / Layer

[0032] 340: Patterned mask / Mask

[0033] 350: Trench

[0034] 355: Stack / Insulator

[0035] 360: Contact / Electrode

[0036] 370: Metal Layer

[0037] 400: Method

[0038] 402, 404, 406, 408, 410, 412, 414, 416, 418, 420: Operations

[0039] A: First Dimension

[0040] B, D: Second Dimension

[0041] C: Distance

[0042] Hi: Logic High Voltage

[0043] Low: Logic Low Voltage

[0044] X, Y: Directions Detailed Implementation Modes

[0045] The following disclosure elaborates various exemplary embodiments for implementing different features of the subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature "on" or "above" a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may reuse reference numerals and / or letters in various instances. Such reuse is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0046] In addition, for ease of description, spatial relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figure with another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figure. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. Unless otherwise explicitly stated, terms such as "attached", "affixed", "connected", and "interconnected" refer to the relationship in which structures are directly or indirectly fastened or attached to each other through an intermediate structure, and both movable or fixed attachment or relationships are included.

[0047] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms (such as those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and should not be interpreted as having an idealized or overly formal meaning unless explicitly defined herein.

[0048] Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. The same reference numerals are used in the drawings and the description as far as possible to refer to the same or similar components.

[0049] The present disclosure provides various embodiments of a novel capacitor structure and methods of forming the novel capacitor structure. In some embodiments, the disclosed capacitor structure includes a plurality of MIM capacitors formed on an insulating layer. Each of the MIM capacitors includes two finger-shaped metal contacts that extend vertically on the insulating layer. The two finger-shaped metal contacts serve as two electrodes separated by a dielectric insulator to form an MIM capacitor. The insulating layer is formed on a substrate and serves as a stop layer for the metal contacts to electrically isolate the two metal contacts. Using this novel structure, the disclosed MIM capacitors can achieve high area density. Additionally, the method of forming the disclosed MIM capacitors does not require an additional mask or etching process to form the capacitor top metal (CTM) electrode. The present disclosure is applicable to any semiconductor device including capacitors.

[0050] Figure 1 An exemplary layout of a semiconductor device 100 having a vertical capacitor structure according to some embodiments of the present disclosure is shown. As Figure 1As shown, a plurality of electrodes 130 are arranged in parallel above the active region 110. In one embodiment, the active region 110 serves as a substrate for the plurality of electrodes 130. Each of the plurality of electrodes 130 may comprise a conductive material, such as a metal (e.g., tungsten, aluminum, copper, etc.). In one embodiment, the plurality of electrodes 130 are formed in a contact layer of the semiconductor device 100 such that each of the plurality of electrodes 130 is a tungsten-containing contact (CT). Every two adjacent electrodes 130 are separated by an insulator comprising a dielectric material (not shown in Figure 1 to form a capacitor.

[0051] The active region 110 may comprise a semiconductor material, such as silicon. To electrically insulate the plurality of electrodes 130 from each other, the plurality of electrodes 130 are not directly formed on the silicon-containing active region 110. The semiconductor device 100 includes an insulating layer 120 formed on the active region 110 and below the plurality of electrodes 130. The insulating layer 120 comprises a dielectric material, such as silicon oxide, silicon nitride, etc. In one embodiment, the insulating layer 120 includes a resist protective oxide (RPO). In one embodiment, the insulating layer 120 includes a plurality of sub-layers. For example, the insulating layer 120 includes at least one nitride layer and at least one oxide layer. The insulating layer 120 serves as a stop layer for the plurality of electrodes 130 to stop on.

[0052] As Figure 1 shown, the plurality of electrodes 130 are divided into two groups of electrodes: a group of first electrodes 131 and a group of second electrodes 132. The group of first electrodes 131 and the group of second electrodes 132 are interleaved with each other. There are no two adjacent electrodes belonging to the same group. As Figure 1 shown, the group of first electrodes 131 are electrically connected to a logic high voltage (Hi); and the group of second electrodes 132 are electrically connected to a logic low voltage (Low). There are no two adjacent electrodes electrically connected to the same voltage. In this way, the group of first electrodes 131 and the group of second electrodes 132 form a plurality of capacitors connected in series. In one embodiment, since each capacitor is formed by two adjacent electrodes made of metal and an insulator located between the two adjacent electrodes, each of the plurality of capacitors is a metal-insulator-metal (MIM) capacitor.

[0053] As Figure 1 shown, the first electrodes 131 and the second electrodes 132 form an electrode array extending along the X direction, while each of the first electrodes 131 and the second electrodes 132 extends along the Y direction, and the Y direction is perpendicular to the X direction. As Figure 1As shown, each of the set of first electrodes 131 and the set of second electrodes 132 has a top surface with a rectangular shape. The rectangular shape has a first dimension A and a second dimension B. In one embodiment, the first dimension A is at least 0.22 micrometers. In one embodiment, the second dimension B is at least 0.19 micrometers. In one embodiment, the first dimension A is greater than the second dimension B, where the first dimension A extends along the Y direction and the second dimension B extends along the X direction, and the X direction is perpendicular to the Y direction. In one embodiment, the first dimension A is more than 50% longer than the second dimension B. In one embodiment, the first dimension A is more than 100% longer than the second dimension B. In one embodiment, the first dimension A is more than 200% longer than the second dimension B. According to various embodiments, the rectangular shape has an area between 0.04 square micrometers and 25 square micrometers.

[0054] Each two adjacent electrodes 130 (i.e., a pair of a first electrode 131 and a second electrode 132) have a distance C therebetween. The distance C can be determined based on design requirements related to the capacitance value of each of the capacitors. In one embodiment, the distance C is at least 0.19 micrometers. According to various embodiments, following Figure 1 The plurality of capacitors following the layout shown in may have a high area density, such as 5 to 225 capacitors per 100 square micrometers.

[0055] Figure 2A A cross-sectional view of a semiconductor device 200 having a vertical capacitor structure according to some embodiments of the present disclosure is shown. As Figure 2A shown, the semiconductor device 200 in this example includes: an active region or substrate 210; an insulating layer 220 located on the substrate 210; and a dielectric layer 230 located on the insulating layer 220.

[0056] The semiconductor device 200 in this example further includes a plurality of contacts 240 formed in the dielectric layer 230. Thus, the dielectric layer 230 can also be referred to as a contact layer. Each of the plurality of contacts 240 is made of a metal material (e.g., tungsten, aluminum, copper, etc.) and stops on the insulating layer 220. In one embodiment, although the substrate 210 includes a semiconductor material (such as silicon), the insulating layer 220 includes a dielectric material (such as a resistance protection oxide). In this way, the plurality of contacts 240 can stop on the insulating layer 220 and be electrically isolated from each other. Except for the plurality of contacts 240, the remaining part of the dielectric layer 230 forms an insulating structure between each two adjacent contacts 240.

[0057] As Figure 2AAs shown in the figure, each of the plurality of contact members 240 has a left side wall 241, a right side wall 242, a bottom surface 243, and a top surface 244. The bottom surface 243 is in contact with the insulating layer 220. An insulator, which is a component of the insulating structure of the dielectric layer 230, is coupled to the opposing side walls of two adjacent contact members, i.e., to the left side wall 241 of the right contact member in the pair of contact members and to the right side wall 242 of the left contact member in the pair of contact members. In this way, each pair of two adjacent contact members and the insulator located between the two adjacent contact members form a capacitor. Therefore, each contact member 240 can be referred to as an electrode of the capacitor. As Figure 2A As shown in the figure, each contact member 240 is a finger-shaped electrode that extends vertically (i.e., extends in a vertical direction perpendicular to the substrate 210).

[0058] Figure 2B A perspective view showing a vertical capacitor structure of a semiconductor device 200 according to some embodiments of the present disclosure is shown. As Figure 2B As shown in the figure, each contact member 240 stops on the insulating layer 220, and the insulating layer 220 includes oxide and / or nitride materials that electrically isolate the contact members 240 from each other. Additionally, each contact member 240 is electrically connected to a logic high voltage or a logic low voltage, for example, through at least one metal layer located above the dielectric layer 230. Each two adjacent contact members 240 are respectively connected to two different voltages, i.e., a logic high voltage and a logic low voltage. That is to say, the contact members connected to the logic high voltage and the contact members connected to the logic low voltage are interlaced with each other. The contact members 240 separated by the insulating structure of the dielectric layer 230 form a plurality of capacitors connected in series. Each of the plurality of capacitors stores electrical energy in an electric field that has a horizontal direction (i.e., a direction parallel to the substrate 210). As Figure 2B As shown in the figure, each contact member 240 is a finger-shaped electrode of a capacitor and extends vertically (i.e., extends in a direction perpendicular to the substrate 210). Therefore, each of the plurality of capacitors is referred to as a vertical capacitor herein.

[0059] Each contact member 240 has side walls 241, 242 and a bottom surface 243 that are in contact with the insulating layer 220. As Figure 2BAs shown, each side wall 241, 242 of each contact 240 has a rectangular shape of the same size. Specifically, each side wall 241, 242 has a first dimension A and a second dimension D, where the second dimension D is equal to the height of the dielectric layer 230. Additionally, there is a distance C between each two adjacent contacts 240. In this way, the capacitance of the capacitor formed by two adjacent contacts 240 is proportional to A*D / C. By adjusting the area A*D of the side walls 241, 242 and / or the distance C between two adjacent contacts 240, a desired capacitance can be achieved based on the design requirements. Additionally, the plurality of capacitors can achieve a high area density based on the vertical capacitor structure and the adjusted dimensions. As Figure 2B shown, the top surface 244 and the bottom surface 243 of each contact 240 also have a rectangular shape.

[0060] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I and Figure 3J show cross-sectional views of exemplary semiconductor devices during various fabrication stages in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor device can be a device including a MIM capacitor. The semiconductor device can be included in a microprocessor, a memory cell, and / or other integrated circuits (ICs). Additionally, for a better understanding of the concepts of the present disclosure, Figures 3A to 3J is simplified. For example, although the figures show MIM capacitors, it should be understood that the integrated circuit in which the MIM capacitors are formed can include multiple other layers (including metal layers, polymer layers, passivation layers, etc.) and can include multiple other devices (including resistors, capacitors, inductors, fuses, etc.). For the purpose of clarity of illustration, Figures 3A to 3J the multiple other layers and the multiple other devices are not shown.

[0061] Figure 3A is a cross-sectional view of a semiconductor device including an active region 310 in accordance with some embodiments of the present disclosure, where the active region 310 is provided in one of the various fabrication stages. Figure 3A The active region 310 in

[0062] Figure 3BA cross-sectional view of a semiconductor device including a first oxide layer 322 according to some embodiments of the present disclosure. The first oxide layer 322 is formed on a substrate 310 during one of various fabrication stages. According to some embodiments, the first oxide layer 322 can be formed by depositing an oxide material (e.g., silicon oxide) on the substrate 310.

[0063] Figure 3C A cross-sectional view of a semiconductor device including a nitride layer 324 according to some embodiments of the present disclosure. The nitride layer 324 is formed on the first oxide layer 322 during one of various fabrication stages. According to some embodiments, the nitride layer 324 can be formed by depositing a nitride material (e.g., silicon nitride) on the first oxide layer 322.

[0064] Figure 3D A cross-sectional view of a semiconductor device including a second oxide layer 326 according to some embodiments of the present disclosure. The second oxide layer 326 is formed on the nitride layer 324 during one of various fabrication stages. According to some embodiments, the second oxide layer 326 can be formed by depositing an oxide material (e.g., silicon oxide) on the nitride layer 324. Layers 322, 324, and 326 all contain dielectric materials and together form an insulating layer 320 to serve as a stop layer for forming contacts thereon. Although the insulating layer 320 has three sub-layers as shown in Figure 3D In other embodiments, the insulating layer 320 can have more than three or fewer than three sub-layers. In some embodiments, each sub-layer of the insulating layer 320 can contain at least one of the following: silicon oxide, silicon nitride, resistive protection oxide (RPO), or other suitable dielectric materials that can stop the formation of contacts thereon.

[0065] Figure 3E A cross-sectional view of a semiconductor device including a dielectric layer 330 according to some embodiments of the present disclosure. The dielectric layer 330 is formed on the second oxide layer 326 during one of various fabrication stages. According to some embodiments, the dielectric layer 330 can be formed by depositing a dielectric material on the second oxide layer 326. In some embodiments, the dielectric material of the dielectric layer 330 can include high-k dielectric materials, and the high-k dielectric materials include: SiOx, SiNx, SiOxNy, ZrO2, Al2O3, HfOx, HfSiOx, ZrTiOx, TiO2, TaOx, etc. or any combination thereof.

[0066] Figure 3FFIG. is a cross-sectional view of a semiconductor device including a patterned mask 340 according to some embodiments of the present disclosure. The patterned mask 340 is formed on the dielectric layer 330 in one of various fabrication stages. According to some embodiments, the patterned mask 340 can be formed by depositing a photoresist material on the dielectric layer 330 and through a patterning process for forming a pattern or profile on the patterned mask 340.

[0067] Figure 3G FIG. is a cross-sectional view of a semiconductor device including a plurality of trenches 350 according to some embodiments of the present disclosure. The plurality of trenches 350 are formed in the dielectric layer 330 in one of various fabrication stages. According to some embodiments, the plurality of trenches 350 can be formed based on a dry etching process / wet etching process and the pattern of the mask 340. For example, the plurality of trenches 350 can be formed by etching the portions of the dielectric layer 330 that are not covered by the pattern of the patterned mask 340 based on a predefined pattern of the patterned mask 340.

[0068] As Figure 3G shown, each of the plurality of trenches 350 stops within the insulating layer 320. In this example, at the bottom of each of the plurality of trenches 350, the second oxide layer 326 is completely removed; the nitride layer 324 is also completely removed; but the first oxide layer 322 is not removed. In another embodiment, at the bottom of each of the plurality of trenches 350, the second oxide layer 326 is completely removed; the nitride layer 324 is partially removed; and the first oxide layer 322 is not removed. In yet another embodiment, at the bottom of each of the plurality of trenches 350, the second oxide layer 326 is completely removed; the nitride layer 324 is also completely removed; and the first oxide layer 322 is partially removed. In any case, each of the plurality of trenches 350 stops within the insulating layer 320 (i.e., stops at the second oxide layer 326, the nitride layer 324, or the first oxide layer 322), without exposing the substrate 310. In some embodiments, a cleaning process and a soft bake process / hard bake process are also performed to form the plurality of trenches 350.

[0069] Figure 3H FIG. is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure, where the mask 340 is removed in one of various fabrication stages. According to some embodiments, the mask 340 is removed by a cleaning process. As Figure 3HAs shown, the plurality of trenches 350 divide the dielectric layer 330 into a plurality of stacks 355. Each of the plurality of stacks 355 includes a dielectric material, such as a high-k dielectric material, and the high-k dielectric material includes: SiOx, SiNx, SiOxNy, ZrO2, Al2O3, HfOx, HfSiOx, ZrTiOx, TiO2, TaOx, etc. or any combination thereof.

[0070] Figure 3I FIG. 4 is a cross-sectional view of a semiconductor device including a plurality of contacts 360 according to some embodiments of the present disclosure. The plurality of contacts 360 are formed in the plurality of trenches 350 in one of various fabrication stages. According to some embodiments, each of the plurality of contacts 360 is formed by depositing a conductive material to fill the plurality of trenches 350. In some embodiments, the conductive material may be formed of a metal material (e.g., copper (Cu), aluminum (Al), tungsten (W), etc.). In this way, every two adjacent contacts 360 are separated by an insulator 355 including a dielectric material to form a MIM capacitor. Each of the plurality of contacts 360 is an electrode of the MIM capacitor. In one embodiment, the plurality of stacks or insulators 355 are coupled to each other to form an insulating structure in the dielectric layer 330.

[0071] Figure 3J FIG. 8 is a cross-sectional view of a semiconductor device 300 including a metal layer 370 according to some embodiments of the present disclosure. The metal layer 370 is formed on the plurality of contacts 360 in one of various fabrication stages. As Figure 3J shown, the plurality of contacts or electrodes 360 are divided into an interleaved set of first electrodes 362 and a set of second electrodes 364. According to some embodiments, the metal layer 370 is formed by depositing a metal material (e.g., aluminum, copper, etc.) onto the first electrodes 362 and the second electrodes 364. In one embodiment, as Figure 3J shown, the first electrodes 362 are connected to a logic high voltage through the metal layer 370; and the second electrodes 364 are connected to a logic low voltage through the metal layer 370. In another embodiment, the first electrodes 362 are connected to a logic low voltage through the metal layer 370; and the second electrodes 364 are connected to a logic high voltage through the metal layer 370.

[0072] Figure 4is a flowchart showing an exemplary method 400 of forming a semiconductor device having a vertical capacitor structure according to some embodiments of the present disclosure. At operation 402, a first oxide layer is deposited on a substrate. At operation 404, a nitride layer is deposited on the first oxide layer. At operation 406, a second oxide layer is deposited on the nitride layer. At operation 408, a dielectric layer is deposited on the second oxide layer. At operation 410, a patterned mask is formed on the dielectric layer.

[0073] At operation 412, the dielectric layer is etched based on the pattern to form a plurality of trenches. As described above, each of the plurality of trenches stops within the first oxide layer, the nitride layer, or the second oxide layer. At operation 414, the plurality of trenches are filled with a conductive material to form interdigitated first electrodes and second electrodes. Each two adjacent electrodes (i.e., the first electrode and the second electrode) are electrically isolated by an insulator located between the two adjacent electrodes and by an oxide layer or a nitride layer located under the two adjacent electrodes to form a capacitor. All the electrodes form a plurality of capacitors connected in series.

[0074] At operation 416, a metal layer is deposited on the first electrode and the second electrode. At operation 418, the first electrode is connected to a logic high voltage through the metal layer. At operation 420, the second electrode is connected to a logic low voltage through the metal layer. It is understood that the order of the operations shown in Figure 4 can be changed according to different embodiments of the present disclosure. The capacitor formed according to the disclosed method can achieve a high area density. The disclosed method does not require an additional mask or etching process to form the capacitor top metal (CTM) electrode.

[0075] In an embodiment, a semiconductor device is disclosed. The semiconductor device includes: an insulating layer; a first electrode having sidewalls and a bottom surface in contact with the insulating layer; a second electrode having sidewalls and a bottom surface in contact with the insulating layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to the sidewalls of the first electrode and coupled to the sidewalls of the second electrode.

[0076] In some embodiments, the first rectangular shape and the second rectangular shape have the same dimensions. In some embodiments, the insulating layer includes a plurality of sub-layers. In some embodiments, the plurality of sub-layers include: at least one nitride layer; and at least one oxide layer.

[0077] In another embodiment, a semiconductor device is disclosed. The semiconductor device includes: a substrate; an insulating layer located on the substrate; a dielectric layer located on the insulating layer; a plurality of first electrodes formed in the dielectric layer; and a plurality of second electrodes formed in the dielectric layer. The first electrodes and the second electrodes are interleaved with each other. The dielectric layer includes an insulating structure formed between the first electrodes and the second electrodes.

[0078] In some embodiments, each of the first electrodes and the second electrodes includes a conductive material; and the insulating structure includes a dielectric material. In some embodiments, each of the plurality of first electrodes has a sidewall and a bottom surface in contact with the insulating layer; each of the plurality of second electrodes has a sidewall and a bottom surface in contact with the insulating layer; and the insulating structure is coupled to the sidewalls of the first electrodes and the sidewalls of the second electrodes. In some embodiments, the interleaved first electrodes and second electrodes form a plurality of capacitors connected in series; and each of the plurality of capacitors stores electrical energy in an electric field having a direction parallel to the substrate. In some embodiments, the plurality of capacitors have an area density of at least 5 capacitors per 100 square micrometers.

[0079] In yet another embodiment, a method of forming a semiconductor device is disclosed. The method includes: forming an insulating layer on a substrate; depositing a dielectric layer on the insulating layer; and forming a plurality of electrodes in the dielectric layer. The plurality of electrodes include a first electrode and a second electrode, and the first electrode and the second electrode are interleaved with each other. The dielectric layer includes an insulating structure located between the first electrode and the second electrode.

[0080] In some embodiments, forming the plurality of electrodes includes: depositing a mask on the dielectric layer; forming a pattern on the mask; etching the dielectric layer based on the pattern to form a plurality of trenches; and filling the plurality of trenches with a conductive material to form the plurality of electrodes. In some embodiments, etching the dielectric layer includes: completely removing the second oxide layer at the bottom of each of the plurality of trenches; and at least partially removing the nitride layer at the bottom of each of the plurality of trenches. In some embodiments, the method further includes: depositing a metal layer on the first electrode and the second electrode; connecting the first electrode to a first voltage through the metal layer; and connecting the second electrode to a second voltage through the metal layer, wherein the first voltage is higher than the second voltage.

[0081] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: An insulating layer, comprising: A first oxide layer; A nitride layer located on the first oxide layer; and A second oxide layer located on the nitride layer; A first electrode having sidewalls partially surrounded by the nitride layer and the second oxide layer and a bottom surface in contact with the first oxide layer, A second electrode having sidewalls partially surrounded by the nitride layer and the second oxide layer and a bottom surface in contact with the first oxide layer, and An insulator formed between the first electrode and the second electrode and located on the second oxide layer, wherein the insulator is coupled to the sidewalls of the first electrode and coupled to the sidewalls of the second electrode, wherein: The first electrode is electrically connected to a logic high voltage, The second electrode is electrically connected to a logic low voltage.

2. The semiconductor device according to claim 1, further comprising: At least one metal layer located on the first electrode, the second electrode, and the insulator, wherein: The first electrode is electrically connected to the logic high voltage through the at least one metal layer, The second electrode is electrically connected to the logic low voltage through the at least one metal layer.

3. The semiconductor device according to claim 1, wherein: The sidewall of the first electrode has a first rectangular shape; and The sidewall of the second electrode has a second rectangular shape.

4. The semiconductor device according to claim 3, wherein: The first rectangular shape and the second rectangular shape have the same dimensions.

5. The semiconductor device according to claim 1, wherein: The bottom surface of the first electrode has a first rectangular shape; and The bottom surface of the second electrode has a second rectangular shape.

6. The semiconductor device according to claim 5, wherein: The first rectangular shape and the second rectangular shape have the same dimensions and the same area less than 25 square micrometers.

7. The semiconductor device according to claim 1, wherein: Each of the first electrode and the second electrode comprises tungsten.

8. A semiconductor device, comprising: A substrate; An insulating layer located on the substrate, wherein the insulating layer comprises a plurality of sub-layers, the plurality of sub-layers comprising two oxide layers and one nitride layer; A dielectric layer located on the plurality of sub-layers of the insulating layer; A plurality of first electrodes formed in the dielectric layer, wherein each of the plurality of first electrodes has sidewalls partially surrounded by one of the one nitride layer and the two oxide layers and a bottom surface in contact with the other of the two oxide layers; And A plurality of second electrodes formed in the dielectric layer, wherein each of the plurality of second electrodes has sidewalls partially surrounded by one of the one nitride layer and the two oxide layers and a bottom surface in contact with the other of the two oxide layers, wherein The first electrodes and the second electrodes are interlaced with each other and form an electrode array extending along a first direction, The top surface of the first electrode and the top surface of the second electrode have the same rectangular shape, and the rectangular shape has: a first dimension extending along the first direction, and a second dimension larger than the first dimension and extending along a second direction, the second direction being perpendicular to the first direction, and The dielectric layer includes an insulating structure formed between the first electrode and the second electrode.

9. The semiconductor device according to claim 8, further comprising: At least one metal layer located above the dielectric layer.

10. The semiconductor device according to claim 9, wherein: The first electrode is electrically connected to a first voltage through the at least one metal layer; The second electrode is electrically connected to a second voltage through the at least one metal layer; and The first voltage is higher than the second voltage.

11. The semiconductor device according to claim 8, wherein: Each of the first electrode and the second electrode includes a conductive material; and The insulating structure includes a dielectric material.

12. The semiconductor device according to claim 8, wherein: The insulating structure is coupled to the sidewalls of the first electrode and the sidewalls of the second electrode.

13. The semiconductor device according to claim 8, wherein: The interleaved first electrode and second electrode form a plurality of capacitors connected in series; and Each of the plurality of capacitors stores electrical energy in an electric field having a direction parallel to the substrate.

14. The semiconductor device according to claim 13, wherein: The plurality of capacitors have an area density of at least 5 capacitors per 100 square micrometers.

15. A method of forming a semiconductor device, comprising: Forming an insulating layer on a substrate, wherein forming the insulating layer includes: Depositing a first oxide layer on the substrate; Depositing a nitride layer on the first oxide layer; and Depositing a second oxide layer on the nitride layer; Depositing a dielectric layer on the second oxide layer; Etching the dielectric layer, including: Removing portions of the dielectric layer, removing portions of the second oxide layer, and removing portions of the nitride layer to form a plurality of trenches, wherein the bottoms of the plurality of trenches expose the upper surface of the first oxide layer; Filling the plurality of trenches with a conductive material to form a plurality of electrodes within the plurality of trenches, wherein The plurality of electrodes include a first electrode and a second electrode, the first electrode and the second electrode are interleaved with each other and form an electrode array extending along a first direction, and the first electrode and the second electrode have sidewalls partially surrounded by the nitride layer and the second oxide layer, the dielectric layer is coupled to the sidewalls of the first electrode and coupled to the sidewalls of the second electrode, and the first electrode and the second electrode have bottom surfaces in contact with the first oxide layer, The top surfaces of the plurality of electrodes have the same rectangular shape, and the same rectangular shape has: a first dimension extending along the first direction, and a second dimension larger than the first dimension and extending along a second direction, the second direction being perpendicular to the first direction, and The dielectric layer includes an insulating structure located between the first electrode and the second electrode.

16. The method according to claim 15, further comprising: Depositing a metal layer on the first electrode and the second electrode; Connecting the first electrode to a first voltage through the metal layer; And Connecting the second electrode to a second voltage through the metal layer, wherein the first voltage is higher than the second voltage.

17. A semiconductor device, comprising: A substrate; An insulating layer located on the substrate, wherein the insulating layer includes a plurality of sub-layers, and the plurality of sub-layers include two oxide layers and one nitride layer; A dielectric layer located on the plurality of sub-layers of the insulating layer; A plurality of first electrodes formed in the dielectric layer, wherein each of the plurality of first electrodes has a sidewall partially surrounded by the nitride layer and one of the two oxide layers, and a bottom surface in contact with the other of the two oxide layers; And A plurality of second electrodes formed in the dielectric layer, wherein each of the plurality of second electrodes has a sidewall partially surrounded by the nitride layer and one of the two oxide layers, and a bottom surface in contact with the other of the two oxide layers, wherein The first electrodes and the second electrodes are interlaced with each other and form an electrode array extending along a first direction, and The top surfaces of the first electrodes and the top surfaces of the second electrodes have the same rectangular shape, and the rectangular shape has: a first dimension extending along the first direction, and a second dimension larger than the first dimension and extending along a second direction, and the second direction is perpendicular to the first direction.

18. The semiconductor device according to claim 17, further comprising: At least one metal layer located on the dielectric layer.

19. The semiconductor device according to claim 18, wherein: The first electrode is electrically connected to a first voltage through the at least one metal layer; The second electrode is electrically connected to a second voltage through the at least one metal layer; and The first voltage is higher than the second voltage.

20. The semiconductor device according to claim 17, wherein: Each of the first electrode and the second electrode contains a conductive material; and The dielectric layer includes an insulating structure formed between the first electrode and the second electrode.

21. The semiconductor device according to claim 20, wherein: The insulating structure is coupled to the sidewalls of the first electrode and the sidewalls of the second electrode.

22. The semiconductor device according to claim 17, wherein: The interlaced first electrodes and second electrodes form a plurality of capacitors connected in series; and Each of the plurality of capacitors stores electrical energy in an electric field having a direction parallel to the substrate.

23. The semiconductor device according to claim 22, wherein: The plurality of capacitors have an area density of at least 5 capacitors per 100 square micrometers.

24. A method of forming a semiconductor device, comprising: An insulating layer is formed on a substrate, wherein forming the insulating layer includes: Depositing a first oxide layer on the substrate; Depositing a nitride layer on the first oxide layer; and Depositing a second oxide layer on the nitride layer; Depositing a dielectric layer on the second oxide layer; and Etching the dielectric layer, including: Removing a portion of the dielectric layer, removing a portion of the second oxide layer, and removing a portion of the nitride layer to form a plurality of trenches, wherein the bottom surfaces of the plurality of trenches expose the upper surface of the first oxide layer; Filling the plurality of trenches with a conductive material to form a plurality of electrodes within the plurality of trenches, wherein The plurality of electrodes include a first electrode and a second electrode, the first electrode and the second electrode are interleaved with each other and form an electrode array extending along a first direction, and the first electrode and the second electrode have sidewalls partially surrounded by the nitride layer and the second oxide layer, the dielectric layer is coupled to the sidewalls of the first electrode and the second electrode, and the first electrode and the second electrode have bottom surfaces in contact with the first oxide layer, The top surfaces of the plurality of electrodes have the same rectangular shape, the same rectangular shape having: a first dimension extending along the first direction, and a second dimension larger than the first dimension and extending along a second direction, the second direction being perpendicular to the first direction.

25. The method according to claim 24, further comprising: Depositing a metal layer on the first electrode and the second electrode; Connecting the first electrode to a first voltage through the metal layer; And Connecting the second electrode to a second voltage through the metal layer, wherein the first voltage is higher than the second voltage.

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