IC products including single active fin FINFET devices and electrically inactive fin stress reduction structures

Abstract

This invention relates to IC products including a single-active-fin FinFET device and an electrically neutralized fin stress-reducing structure. Exemplary devices disclosed herein include a semiconductor substrate and a FinFET transistor device positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active-fin structure. The device also includes an electrically neutralized dummy fin structure positioned adjacent to the single active-fin structure, wherein the electrically neutralized dummy fin structure is electrically neutral for the electrical operation of the FinFET transistor having a single active-fin.

Description

Technical Field

[0001] The present disclosure generally relates to various novel embodiments of integrated circuit (IC) products including a single active fin FinFET transistor device and an electrically inactive fin stress reduction structure, and methods of manufacturing such IC products. Background Art

[0002] Transistor devices have a variety of structures, such as planar devices, FinFET devices, vertical devices, etc. FinFET devices are commonly used in modern IC products. FinFET devices can include a single effective fin (i.e., a single semiconductor structure) or multiple fins (i.e., multiple semiconductor structures). Such a fin has a long axis that is substantially horizontally oriented relative to the upper surface of the semiconductor substrate on which the FinFET device is formed. Single-fin FinFET devices are becoming increasingly common in many IC products that focus on low power consumption (e.g., mobile phones and portable computing devices). However, at least some traditional manufacturing processes for forming devices with a single semiconductor structure (e.g., FinFET devices and vertical devices) may have a tendency to increase the formation of unwanted crystal defects in the fins of single-fin FinFET devices, which can lead to a decrease in the performance of the resulting device. More specifically, in some manufacturing techniques, an oxide material can be initially formed to overfill the trenches adjacent to the fins. However, in some cases, the oxide material can exert lateral or horizontal stress on the fins (along the gate width direction of the FinFET device) that attempts to pull the fins apart. This stress on the fins tends to cause the above-mentioned unwanted crystal defects to form in the fins.

[0003] The present disclosure generally relates to various novel embodiments of IC products including single active fin FinFET transistor devices and electrically inactive fin stress reduction structures, and methods of making such IC products, which may solve or at least mitigate one or more of the above-mentioned problems. Summary of the Invention

[0004] The following is a simplified summary of the present invention to provide a basic understanding of certain aspects of the present invention. This summary is not an exhaustive overview of the present invention. It is not intended to identify key or important elements of the present invention or to delineate the scope of the present invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the specific embodiments discussed later.

[0005] The present disclosure relates to various novel embodiments of an integrated circuit (IC) product including a single active fin FinFET transistor device and an electrically inactive fin stress reduction structure, and methods of manufacturing such an IC product. The exemplary device disclosed herein includes a semiconductor substrate and a FinFET transistor positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active fin structure. The device also includes an electrically inactive dummy fin structure positioned adjacent to the single active fin structure, wherein the electrically inactive dummy fin structure is electrically inactive for electrical operation of the FinFET transistor having the single active fin.

[0006] Another exemplary device disclosed herein includes a semiconductor substrate and a FinFET transistor positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active fin structure. The device further includes an electrically inactive dummy fin structure, wherein the electrically inactive dummy fin structure is electrically inactive for electrical operation of the FinFET transistor having the single active fin; and an isolation structure positioned in the semiconductor substrate between the electrically inactive dummy fin structure and the single active fin structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure may be understood by referring to the following description in conjunction with the accompanying drawings, in which like reference numerals represent like elements, and in which:

[0008] Figures 1 to 18 Various novel embodiments of IC products including a single active fin FinFET transistor device and an electrically inactive fin stress reduction structure, and methods of making such IC products are shown. The figures are not drawn to scale.

[0009] While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. However, it should be understood that the description herein of specific embodiments is not intended to limit the invention to the specific forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. DETAILED DESCRIPTION

[0010] Various illustrative embodiments of the present invention are described below. For the sake of clarity, not all features of an actual implementation are described in this specification. Of course, it should be understood that in the development of any such actual embodiment, many implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such development work may be complex and time-consuming, but will nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0011] The subject matter of the present invention will now be described with reference to the accompanying drawings. The various structures, systems and devices schematically depicted in the accompanying drawings are only for the purpose of explanation, so that the contents of the present disclosure are not confused by details known to those skilled in the art. However, the accompanying drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted as having meanings consistent with the understanding of these words and phrases by those skilled in the relevant art. The special definition of a term or phrase, i.e., a definition different from the common and customary meaning understood by those skilled in the art, is not intended to be implied by the consistent use of the term or phrase herein. In the case where a term or phrase is intended to have a special meaning (i.e., a meaning other than that understood by those skilled in the art), such a special definition will be clearly stated in the specification in a clear and explicit manner to provide the special definition of the term or phrase directly and clearly. After reading this application, it will be apparent to those skilled in the art that the method disclosed herein can be used to manufacture various products, including but not limited to logic products, storage devices, etc.

[0012] Those skilled in the art will also understand after a complete reading of this application that various doped regions, such as source / drain regions, halo injection regions, well regions, etc., are not shown in the accompanying drawings. Of course, the invention disclosed herein should not be considered to be limited to the illustrative examples shown and described herein. The various components, structures and material layers described herein can be formed using a variety of different materials and by performing a variety of known process operations (such as chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal growth processes, spin coating techniques, etc.). The thickness of these various material layers can also vary depending on the specific application. With reference to the accompanying drawings, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail. With reference to the accompanying drawings, various illustrative embodiments of the methods and products disclosed herein will now be described in more detail.

[0013] Figures 1 to 18 Various novel embodiments of an IC product 100 including a single active fin finFET transistor device and an electrically inactive fin stress reduction structure and methods of manufacturing such an IC product are shown. The IC product 100 is to be formed on and above a semiconductor substrate 102 (see FIG. Figure 2 ). The semiconductor substrate 102 may have various structures, such as a bulk silicon structure. The substrate 102 may also have a semiconductor-on-insulator (SOI) structure, which includes a base semiconductor layer, a buried insulating layer, and an active semiconductor layer located above the buried insulating layer, wherein transistor devices (not shown) formed on the substrate are formed in and above the active semiconductor layer. The substrate 102 may be made of silicon, or may be made of a material other than silicon. Therefore, the term "substrate" or "semiconductor substrate" should be understood to cover all semiconducting materials and all forms of such materials.

[0014] Figure 1 (Floor plan) and Figure 2 (Cross-sectional view) shows the IC product 100 after performing known manufacturing techniques to form a plurality of fins 104A-K (collectively referred to using the number 104) in the substrate 102. In one illustrative process flow, the fins 104 are formed across the entire substrate 102. To form the fins 104, a patterned fin-forming etch mask (not shown), such as a combination of a silicon dioxide layer (e.g., a pad oxide) and a silicon nitride layer (e.g., a pad nitride), is formed over the substrate 102. Thereafter, one or more etching processes are performed through the patterned fin-forming etch mask to define a plurality of fin-forming trenches 111 in the substrate 102. The etching process results in the formation of the fins 104. The patterned fin-forming etch mask will eventually be removed in subsequent processing operations.

[0015] Typically, the IC product 100 may include a plurality of FinFET transistor devices, each of which may include any desired number of fins 104. However, the IC product 100 also includes at least one FinFET transistor device, and the at least one FinFET transistor device has only a single active fin 104 that participates in the electrical activity of the FinFET device, that is, when the device is operating, carriers (electrons or holes) flow only through a single fin. The FinFET devices disclosed herein may be N-type or P-type devices. Of course, other devices and structures may also be present on the IC product, such as planar transistor devices, vertical transistor devices, resistors, etc.

[0016] The height and cross-sectional shape of the fin 104 may also vary depending on the specific application. In the example shown herein, the fin 104 will be depicted as having a simple rectangular cross-sectional shape having a substantially uniform lateral width (along the gate width direction) over the entire height of the fin 104. In actual devices, the fin 104 may have a tapered cross-sectional shape, wherein the upper surface width (i.e., top critical dimension) of the fin 104 in the gate width direction of the FinFET device is less than the bottom width of the fin 104 in the gate width direction. In addition, the axial length of the fin 104 may also vary depending on the specific application, for example, the axial lengths of the fins 104 on different transistor devices may be different from each other. Therefore, the size and shape of the fin 104 and how they are manufactured should not be considered to be limiting of the subject matter of the present disclosure. The fin 104 may be formed to have any desired fin pitch. Of course, the fins 104 on an IC product may all be formed to have a uniform pitch, or may be formed to have a non-uniform pitch, with some fins formed to have a first pitch and other fins formed to have a pitch different from the first pitch. More than two different fin pitches may be used on an IC product. Additionally, the gate structures of the FinFET devices disclosed herein may be fabricated using well-known gate-first or replacement gate fabrication techniques.

[0017] Figure 3 The IC product 100 is shown after a patterned fin-cut etch mask 106 (e.g., a patterned photoresist / BARC layer) is formed on the product 100 by performing conventional manufacturing techniques. The fin-cut etch mask 106 exposes portions of the fins 104 that need to be removed and areas in the substrate 102 where deep isolation structures will be formed. As will be described more fully below, in one illustrative embodiment, the fin 104E will be a single active fin 104E for each of the multiple single-fin FinFET devices, i.e., when the device is operating (i.e., turned on), carriers (electrons or holes) flow only through the single active fin 104E of the single-fin FinFET device.

[0018] Additionally, a portion of the fin 104F will be an electrically inactive or "dummy" fin stress reduction structure 108 (see FIG. Figure 4 ). The dummy fin stress reduction structure 108 is electrically ineffective with respect to the single-fin FinFET device in the sense that carriers (electrons or holes) will not flow through the dummy fin stress reduction structure 108 to any portion of the metallization system (or wiring system) on the IC product when the single-fin FinFET device is operating (i.e., turned on). Furthermore, the dummy fin stress reduction structure 108 is also electrically ineffective with respect to any other FinFET devices formed on the IC product, regardless of the number of fins those other FinFET devices may have.

[0019] Figure 4 (Floor plan) and Figure 5 (Cross-sectional view) shows the IC product 100 after performing several process operations. First, one or more etching processes are performed through the patterned fin cut etch mask 106 to remove the exposed portion of the fin 104 and form deep isolation trenches 112 in the substrate 102 (see FIG. Figure 5 ). Next, the fin cut etch mask 106 is removed. Then, a layer of insulating material 114 is formed to overfill the trenches 111 and 112 so that after the initial deposition, the upper surface of the layer of insulating material 114 is higher than the upper surface of the fin 104. The layer of insulating material 114 can be composed of, for example, a flowable oxide (FCVD), a spin-on oxide (SOD), silicon dioxide, HDP oxide, or HARP oxide. At this point, one or more planarization processes (e.g., CMP and / or etch-back processes) are performed to remove a portion of the layer of insulating material 114 and expose the upper surface of the fin 104. Next, a timed recess etch process is performed to remove a portion of the vertical thickness of the layer of insulating material 114. The recess etch process is performed for a sufficient time so that the layer of insulating material 114 has a substantially planar recessed upper surface 114R that is located at a desired height level within the trench 111. The amount of recess of the layer of insulating material 114 can vary depending on the specific application. The recess etching process exposes the desired final fin height of the fin 104 of the FinFET device. These process operations also result in the formation of a deep isolation structure 110 (including an insulating material 114) in the substrate 102 that electrically isolates adjacent transistor devices from each other. As will be understood by those skilled in the art, the deep isolation structure 110 includes an insulating material 114 positioned in and above the deep isolation trench 112. The deep isolation structure 110 extends to a depth below the depth of the fin-forming trench 111 in the substrate, and the vertical thickness of the insulating material 114 in the deep isolation structure 110 is greater than the vertical thickness of the portion of the insulating material 114 positioned above the fin-forming trench 111.

[0020] Continue to refer Figure 4 and Figure 5 , fins 104C, 104D, and 104G are completely removed from the shown portion of substrate 102. During the fin cutting process, a portion of the axial length of fins 104H-J is also removed. The gate length (GL) and gate width (GW) of the final transistor device are in the direction of Figure 4 and Figure 5 As described above, the fin 104E will be the single active fin for each of the plurality of single-fin FinFET devices, while a portion of the fin 104F will become an electrically inactive dummy fin stress reduction structure 108 for the single active fin 104E.

[0021] Given that the size of a single active fin is very small, especially in the gate width direction of the device, such a single active fin 104E is a relatively fragile structure. In addition, when the deep isolation structure 110 positioned adjacent to the single active fin 104E has a relatively large area, the insulating material 114 in the deep isolation structure 110 may exert a tensile stress on the fin 104E that tends to pull the fin 104E apart (e.g., Figure 5 117 in the fin 104E), and will result in the formation of stress-inducing defects (not shown) in the fin crystal structure of the fin 104E. Such stress-inducing defects in the single effective fin 104E may result in a degradation in the operating performance of the final FinFET device. More specifically, in some applications, one or more wet or dry annealing processes may be performed on the layer of insulating material 114 after the layer is formed. In some cases, the layer of insulating material 114 may shrink by approximately 5-15% during the performance of one or more of these annealing processes. The shrinkage of the layer of insulating material 114 results in a tensile stress 117 applied to the single effective fin 104E. The purpose of the dummy fin stress reduction structure 108 is to reduce the stress applied to the single effective fin 104E, thereby reducing the chance of forming stress-inducing defects in the single effective fin 104E. In Figure 4 and Figure 5 In the example shown, the dummy fin stress reduction structure 108 is located in the same cell as the single active fin 104E. However, as will be described more fully below, in some applications, the dummy fin stress reduction structure 108 may be located in a cell other than the cell containing the single active fin 104E.

[0022] refer to Figure 4 , there is a larger portion 110X of the deep isolation structure 110, which is positioned between the fin 104E and the fin 104K and between the cut ends of the fins 104H-J. Without the formation of the dummy fin stress reduction structure 108, the size (along the gate width direction) of the portion 110X of the deep isolation structure 110 that applies stress on the single active fin 104E would be size 110Y. However, due to the formation of the dummy fin stress reduction structure 108, the size (along the gate width direction) of the portion 110X of the deep isolation structure 110 that applies stress on the single active fin 104E is reduced to size 110W. In both cases, the size 110L (along the gate length direction) of the portion 110X of the deep isolation structure 110 is the same.

[0023] Because the dummy fin stress reduction structure 108 is formed between the single active fin 104E and the portion 110X of the deep isolation structure 110, the volume of the insulating material 114 in the portion 110X of the deep isolation structure 110 is reduced, thereby reducing the stress 117 applied to the single active fin 104E. The dummy fin stress reduction structure 108 also reduces the stress acting on the single active fin 104E by providing mechanical support to the single active fin 104E. That is, without the dummy fin stress reduction structure 108, the stress generated by the portion 110X of the deep isolation structure 110 would only act on the single active fin 104E. However, with the dummy fin stress reduction structure 108 in place, the stress generated by the portion 110X of the deep isolation structure 110 now acts on two fins—the single active fin 104E and the dummy fin stress reduction structure 108. In other words, the stress generated by portion 110X of deep isolation structure 110 remains unchanged, but the stress now acts over a larger area, thereby distributing the stress between the two fins. As a result, the strain in the single active fin 104E (and the dummy fin stress reduction structure 108) is reduced, which will lead to a reduction in strain-inducing defects in the single active fin 104E.

[0024] exist Figures 1 to 7 In the illustrative example shown, a single active fin 104E is formed with a first fin pitch, and the dummy fin stress reduction structure 108 is formed a single fin pitch away from the single active fin 104E. Figures 1 to 7 In the illustrated embodiment, simulation data indicates that the formation of the dummy fin stress reduction structure 108 can reduce the maximum strain energy density (MPa) on a single active fin 104E by up to about 10%, and can reduce the average strain energy density (MPa) on a single active fin 104E by about 14.5%. Furthermore, strain reduction can occur along the axial length (in the gate length direction) of the single active fin 104E over a dimension greater than the axial length 108L of the dummy fin stress reduction structure 108.

[0025] Of course, several different single-fin FinFET devices can be formed on a single effective fin 104E. The physical dimensions of the dummy fin stress reduction structure 108, such as its axial length 108L (in the gate length direction), can vary depending on the specific application. In one illustrative embodiment, the axial length 108L of the dummy fin stress reduction structure 108 can be substantially equal to the dimension 110L of the portion 110X (in the gate length direction) of the deep isolation structure 110. In other applications, the axial length 108L can be different from (i.e., less than or greater than) the dimension 110L. In this particular embodiment, the dummy fin stress reduction structure 108 is a portion of an adjacent fin (e.g., fin 104F) that is formed to be one fin pitch away from the single effective fin 104E, but this is not the case in all applications, as will be discussed more fully below.

[0026] exist Figure 4 In the example shown, a single active fin 104E includes opposing first and second sidewalls 104S1 and 104S2, wherein sidewall 104S1 is positioned closer to portion 110X of deep isolation structure 110 than second sidewall 104S2. In one embodiment, dummy fin stress reduction structure 108 may be formed adjacent to first sidewall 104S1 of single active fin 104E. In this case, at least a portion of dummy fin stress reduction structure 108 is positioned between single active fin 104E and portion 110X of deep isolation structure 110 when viewed from above. However, in other applications, dummy fin stress reduction structure 108 may be formed adjacent to opposite side 104S2 of single active fin 104E. In this latter case, dummy fin stress reduction structure 108 still reduces stress on single active fin 104E by providing mechanical support (i.e., reinforcing single active fin 104E) without reducing the volume of insulating material 114 located in portion 110X of deep isolation structure 110. In yet another application, electrically inactive dummy fin stress reduction structures 108 may also be formed adjacent to both sides 104S1, 104S2 of a single active fin 104E. In this case, the fin stress reduction structures 108 formed on two opposite sides of the fin 104E do not need to have the same physical dimensions, but this may be the case in some applications.

[0027] One skilled in the art will understand after fully reading this application that a conductive gate structure may or may not be formed over the electrically inactive dummy fin stress reduction structure 108 . Figure 6 (Floor plan) and Figure 7 (Cross-Sectional View) shows the IC product after forming a simplified depicted gate 130 on the IC product 100, where the gate 130B is formed over the dummy fin stress reduction structure 108 and the single active fin 104E. Figure 8(Plan view) shows an embodiment of an IC product in which gate 130B is formed only over a single active fin 104E (a cross-sectional view of this embodiment is not provided). As described above, the gate structure of gate 130 of the transistor device disclosed herein can be formed by performing gate-first or replacement gate manufacturing techniques. Figure 7 The gate 130 shown in the cross-sectional view shown has been labeled with reference numerals 130A to 130C for ease of reference. Figure 7 Each gate 130 includes a gate structure 131, a sidewall spacer 138, and a gate cap 136, as described more fully below. Figure 7 In one illustrative replacement gate fabrication technique, a so-called "dummy" or sacrificial gate structure (not shown) including an initial (or sacrificial) gate cap layer is initially formed over a substrate 102 and patterned. Thereafter, at least one sidewall spacer 138 is formed adjacent to the patterned dummy gate structure / cap layer. The dummy gate structure remains in place while a number of process operations are performed to form the device (e.g., to form elevated doped source / drain regions), allowing annealing processes to repair damage to the substrate, etc. At some point in such a replacement gate process flow, the initial gate cap layer is removed by performing a chemical mechanical polishing (CMP) process relative to an insulating material layer 140 to expose the dummy gate structure for further processing. Thereafter, one or more etching processes are performed to remove the dummy gate structure, which results in the formation of a gate cavity (not shown) laterally defined by the inner surfaces of the spacers 138.

[0028] Next, various process operations are performed to form the illustrative final gate structure 131 and final gate cap 136 for each FinFET device. For example, after removing the dummy gate, a conformal chemical vapor deposition (CVD) or atomic layer deposition (ALD) process can be performed to form a conformal gate insulation layer 132 composed of a layer of high-k insulating material (e.g., hafnium oxide, silicon dioxide, etc.) in the gate cavity. Thereafter, one or more metal or metal alloy layers and / or polysilicon layers (which will become gate electrodes 134) can be deposited in the gate cavity over the gate insulation layer 132. A CMP process is then performed to remove excess portions of the deposited material layers located outside the gate cavity and over the insulating material layer 140. These operations result in the schematically illustrated final gate structure 131. After the material of the final replacement gate structure 131 is formed in the gate cavity, a timed recess etch process is performed to recess the material of the final replacement gate structure 131, thereby leaving space for the final gate cap 136 to be formed in the replacement gate cavity over the recessed material of the final replacement gate structure 131. The gate cap 136 is formed by depositing a layer of gate cap material (e.g., silicon nitride) over the entire substrate and in the gate cavity above the recessed material of the final replacement gate structure 131, followed by a CMP process to remove excess gate cap material above the upper surface of the insulating material layer 140. Of course, the materials of construction of the gate structures 131 for NFET devices and PFET devices can be different. The gate structures 131 shown herein are intended to be representative in nature, as they are intended to represent any type of gate structure that can be formed on an IC product. Note that in one illustrative embodiment, the gate structure 131 is located around a single active fin 104E and around the dummy fin stress reduction structure 108.

[0029] Figures 9 to 11Another illustrative embodiment of an IC product 100 is shown in which the dummy fin stress reduction structure 108 is formed at a greater distance from a single active fin of a single active fin FinFET device. In this particular example, the IC product 100 includes a portion of a simplified depicted first cell 141A and a portion of a simplified depicted second cell 141B (collectively referred to using the numeral 141). In one illustrative example, each cell 141 includes multiple NFET and multiple PFET devices. As will be understood by those skilled in the art, an actual IC product 100 may include millions of such cells 141, and the cells 141 may have a variety of different configurations and physical sizes, such as small cells, large cells, and very large cells. In one embodiment, the cells 141 may be what is known as a standard cell. Such a standard cell is a collection or arrangement of multiple NFET and multiple PFET devices having a fixed height and a width that is a multiple of the contact pitch of the technology node. In certain applications, these cells are designed so that they can be aligned adjacent to each other without violating the lowest fundamental rules of the particular technology node. Those skilled in the art will understand, after fully reading this application, that in one illustrative embodiment, the dummy fin stress reduction structure 108 may be formed in any of a variety of different areas of an IC product, such as a power rail area inside a particular cell, a shared power rail area between two cells at a cell boundary, and a pickup area where gate structures contact, among others.

[0030] In one particular embodiment, a single electrically active fin 104 of a FinFET device will be formed in the first cell 141A, while the dummy fin stress reduction structure 108 for the single active fin 104E will be formed in the second cell 141B. Figure 9 The IC product 100 is shown after performing known manufacturing techniques to form a plurality of fins 104A-104P (collectively referred to using the numeral 104) in the substrate 102. The fins 104A-104F are formed within the illustrated portion of the first cell 141A, and the fins 104G-104P are formed within the illustrated portion of the second cell 141B. The fins 104 may be formed using the techniques described above.

[0031] Figure 10The IC product 100 is shown after a patterned fin-cut etch mask 120 (e.g., a patterned photoresist / BARC layer) is formed on the product 100 by performing conventional manufacturing techniques. As before, the fin-cut etch mask 120 exposes portions of the fins 104 that need to be removed and areas in the substrate 102 where deep isolation structures 110 will be formed. As will be described more fully below, in this illustrative embodiment, fin 104D (in cell 141A) will be a single active fin for each of the multiple single-fin FinFET devices, while a portion of fin 104K (in cell 141B) will be an electrically inactive dummy fin stress reduction structure 108 for the single active fin 104D.

[0032] Figure 11 The IC product 100 is shown after several process operations have been performed. First, one or more etching processes are performed through the patterned fin cut etch mask 120 to remove exposed portions of the fins 104 and form deep isolation trenches 112 (not shown) in the substrate 102. Next, the fin cut etch mask 120 is removed. Then, a layer of insulating material 114 is formed as described above and recessed as described above. This recess etch process exposes the desired final fin height of the fins 104 of the FinFET devices. As before, these process operations also result in the formation of deep isolation structures 110 in the substrate 102 that electrically isolate adjacent transistor devices from each other. Figure 10 In the illustrative example shown, a single active fin 104D is formed with a first fin pitch, and the dummy fin stress reduction structure 108 is formed a distance from the single active fin 104D, where the distance is equal to a multiple of the first fin pitch.

[0033] Continue to refer Figure 11 , fins 104B, 104C, 104F, 104G, 104J, 104L, 104M, and 104P are completely removed from the illustrated portion of substrate 102. During the fin cutting process, a portion of the axial length of fins 104E, 104H, 104I, 104K, 104N, and 104O is also removed. As described above, in this embodiment, fin 104D will be the single active fin for each of the multiple single-fin FinFET devices, while a portion of fin 104K is an electrically inactive dummy fin stress reduction structure 108 for the single active fin 104D.

[0034] As before, there is a larger portion 110X that is positioned adjacent to the single active fin 104D and between the cut ends of the fins 104H-I and 104N-O. Without the formation of the dummy fin stress reduction structure 108, the size of the entire portion 110X (in the gate width direction) of the deep isolation structure 110 that applies stress to the single active fin 104D would be size 110Y. However, due to the formation of the dummy fin stress reduction structure 108, the size of the portion 110X (in the gate width direction) of the deep isolation structure 110 that applies stress to the single active fin 104D is reduced to size 110W. That is, due to the formation of the dummy fin stress reduction structure 108, the portion 110X (e.g., the lower half) of the deep isolation structure 110 that applies stress to the single active fin 104D structure is positioned between the dummy fin stress reduction structure 108 and the single active fin 104E. As before, in both cases, the dimensions 110L of the portion 110X of the deep isolation structure 110 are the same. As before, forming the dummy fin stress reduction structure 108 between the fin 104D and the fin 104P effectively reduces the volume of the insulating material 114 in the portion 110X of the deep isolation structure 110 that exerts stress on the single active fin 104D, thereby exerting less stress 117 on the single active fin 104D.

[0035] Figures 12 to 18 Another illustrative embodiment of an IC product 100 including a dummy fin stress reduction structure 108 on the IC product 100 is shown, wherein the dummy fin stress reduction structure 108 is formed in a pickup region of the IC product. Additionally, this embodiment reflects the flexibility in positioning the dummy fin stress reduction structure 108 at various locations on the IC product without adversely affecting the performance of transistor devices. Figure 12 The IC product 100 is shown after performing known manufacturing techniques to form a plurality of fins 104A-K (collectively referred to using the numeral 104) in the substrate 102. The fins 104 may be formed using the techniques described above.

[0036] Figure 13 The IC product 100 is shown after a patterned fin-cut etch mask 122 (e.g., a patterned photoresist / BARC layer) is formed on the product 100 by performing conventional manufacturing techniques. As before, the fin-cut etch mask 122 exposes portions of the fins 104 that need to be removed and areas in the substrate 102 where deep isolation structures 110 will be formed. As will be described more fully below, in this illustrative embodiment, the fin 104E will be a single active fin for each of a plurality of single-fin FinFET devices, while a portion of the fin 104H will be an electrically inactive dummy fin stress reduction structure 108 for the single active fin 104E.

[0037] Figure 14 The IC product 100 is shown after performing several process operations. First, one or more etching processes are performed through the patterned fin-cut etch mask 122 to remove the exposed portions of the fins 104 and form deep isolation trenches 112 (not shown) in the substrate 102. Next, the fin-cut etch mask 122 is removed. Then, a layer of insulating material 114 is formed as described above and recessed as described above. This recess etching process exposes the desired final fin height of the fins 104 of the FinFET devices. As before, these process operations also result in the formation of deep isolation structures 110 in the substrate 102 that electrically isolate adjacent transistor devices from each other.

[0038] Continue to refer Figure 14 , fins 104C, 104D, 104G, and 104I are completely removed from the illustrated portion of substrate 102. During the fin cutting process, a portion of the axial length of fins 104F, 104H, 104J, and 104K is also removed. As described above, in this embodiment, fin 104E will be the single active fin for each of the multiple single-fin FinFET devices, while a portion of fin 104H is an electrically inactive dummy fin stress reduction structure 108 for the single active fin 104E.

[0039] As before, a larger portion 110X of the deep isolation structure 110 is present, which is positioned adjacent to the single active fin 104E and between the cut ends of the fins 104H and 104J-K. As before, due to the formation of the dummy fin stress reduction structure 108, the size of the portion 110X of the deep isolation structure 110 that applies stress on the single active fin 104E (in the gate width direction) is reduced to a size 110W. As before, the formation of the dummy fin stress reduction structure 108 effectively reduces the volume of the insulating material 114 in the portion 110X of the deep isolation structure 110 that applies stress on the single active fin 104E, resulting in less stress 117 being applied to the single active fin 104E.

[0040] Figure 15 FIG. 1 shows the IC product after the gate 130 is formed on the IC product 100. Typically, the gate 130 is initially formed as an elongated linear structure. At some point during the manufacturing process of the IC product 100, Figure 15 The initial gate 130 shown will be cut to the desired axial length to form individual gates for various transistor devices.

[0041] Accordingly, Figure 16 The location of the opening 132 in the potentially patterned gate cut mask layer (layer not shown) in which the gate 130 will be cut is shown. Figure 15As shown, the opening 132 is positioned over a portion of the dummy fin stress reduction structure 108. Therefore, if a gate cut operation is performed through the opening 132, the end of the gate 130 in the dashed area 143 will contact the dummy fin stress reduction structure 108. This situation will create an undesirable capacitor structure that charges and discharges each time the affected gate structure is energized, thereby degrading device performance. Therefore, performing a gate cut process operation through the opening 132 is unacceptable. In addition, forming a gate structure over the dummy fin stress reduction structure 108 may make the dummy fin stress reduction structure 108 at least somewhat electrically effective.

[0042] Accordingly, Figure 17 The IC product is shown after the location of the opening 132A into which the gate 130 will be cut and another potentially patterned gate cut mask layer (layer not shown).

[0043] Figure 18 The IC product is shown after removing the portion of the gate 130 exposed by the opening 132A. As depicted, the cut end of the gate 130 adjacent to the dummy fin stress reduction structure 108 has been moved a distance 144 further away from the dummy fin stress reduction structure 108, thereby eliminating the problem of forming an undesirable capacitor structure as described above. Figures 12 to 18 In the embodiment shown, simulation data indicates that the formation of the dummy fin stress reduction structure 108 can reduce the maximum strain energy density (MPa) on a single effective fin 104E by up to about 5%, and can reduce the average strain energy density (MPa) on a single effective fin 104E by about 7%. In addition, strain reduction can occur along the axial length (in the gate length direction) of a single effective fin 104E over a dimension greater than the axial length 108L of the dummy fin stress reduction structure 108 (see FIG. Figure 4 ).

[0044] As described above, in one illustrative embodiment, the dummy fin stress reduction structure 108 is electrically ineffective for current flow through one or more single-fin FinFET devices that include a single active fin, i.e., current will not flow through the dummy fin stress reduction structure 108 to any portion of the metallization system (or wiring system) on the IC product. The dummy fin stress reduction structure 108 is also electrically ineffective for current flow through any other FinFET devices on the IC product, regardless of the number of fins on those other FinFET devices.

[0045] The dummy fin stress reduction structure 108 may be rendered electrically inactive by a number of different techniques that may be employed individually and / or in combination. For example, the gate 130 may not be formed over the electrically inactive dummy fin stress reduction structure 108 (e.g., Figure 8In other cases, no conductive source / drain metallization structure (e.g., a trench silicide region not shown) is formed in contact with the electrically inactive dummy fin stress reduction structure 108 under any circumstances, so that carriers (e.g., electrons or holes) do not flow through the electrically inactive dummy fin stress reduction structure 108 when the single fin transistor device is turned on or when any other FinFET device on the IC product is turned on. Even in the case where an effective conductive gate structure 131 is formed above the dummy fin stress reduction structure 108 (e.g., Figure 6 and 7 ) nor does it form a conductive source / drain metallization structure (e.g., a trench silicide region not shown) in contact with the dummy fin stress reduction structure 108. To the extent that the active gate structure 131 is formed over the dummy fin stress reduction structure 108 and a capacitor is created between the dummy fin stress reduction structure 108 and the active gate structure 131, this situation should be understood as one in which the dummy fin stress reduction structure 108 remains electrically inactive with respect to the electrical operation of the single fin FinFET device, i.e., electrically inactive with respect to the flow of current through the single fin FinFET device. Therefore, as used herein and in the appended claims, the term "electrically inactive" should be understood to have the above meaning.

[0046] The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the present teachings. For example, the process steps described above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design shown herein except as described in the claims below. It is therefore apparent that the particular embodiments disclosed above may be changed or modified, and all such variations are considered within the scope and spirit of the invention. Please note that the use of terms such as "first," "second," "third," or "fourth" to describe various processes or structures in this specification and the appended claims serves merely as a shorthand reference to these steps / structures and does not necessarily imply that such steps / structures are performed / formed in such order. Of course, an ordered sequence of these processes may or may not be required, depending on the exact claim language. Accordingly, the protection sought herein is set forth in the claims below.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; a FinFET transistor device positioned above the semiconductor substrate, the FinFET transistor device having a single effective fin structure; an electrically inactive dummy fin structure positioned adjacent to the single active fin structure, the electrically inactive dummy fin structure being electrically inactive for electrical operation of the FinFET transistor having the single active fin structure; a gate structure positioned around the single active fin, wherein the gate structure is not positioned around the electrically inactive dummy fin structure; a first isolation structure comprising a first trench between the single active fin structure and the electrically inactive dummy fin structure of the FinFET transistor device, wherein the first trench is filled with an insulating material having a first vertical thickness; and A second isolation structure includes a second trench between the electrically inactive dummy fin structure and another fin structure, wherein the second trench is filled with an insulating material having a second vertical thickness greater than the first vertical thickness.

2. The semiconductor device according to claim 1, wherein The single active fin structure has opposite first and second sidewalls, wherein the first sidewall is closer to the second isolation structure than the second sidewall, and wherein the electrically inactive dummy fin structure is positioned adjacent to the first sidewall, wherein at least a portion of the electrically inactive dummy fin structure is located between the single active fin structure and the second isolation structure when viewed from above.

3. The semiconductor device according to claim 1, wherein The second isolation structure has a first length in a direction corresponding to a gate length direction of the FinFET transistor, and the electrically inactive dummy fin structure has a second length in a direction corresponding to the gate length direction of the FinFET transistor, and wherein the first length and the second length are substantially the same.

4. The semiconductor device according to claim 1, wherein: The second isolation structure has a first length in a direction corresponding to a gate length direction of the FinFET transistor, and the electrically inactive dummy fin structure has a second length in a direction corresponding to the gate length direction of the FinFET transistor, and wherein the first length and the second length are different.

5. The semiconductor device according to claim 1, wherein The second isolation structure has a first length in a direction corresponding to a gate length direction of the FinFET transistor, and the electrically inactive dummy fin structure has a second length in a direction corresponding to the gate length direction of the FinFET transistor, and wherein the first length is greater than the second length.

6. The semiconductor device according to claim 1, wherein The single active fin structure is formed to have a first fin pitch, and wherein the electrically inactive dummy fin structure is positioned a distance from the single active fin structure equal to the single first fin pitch.

7. The semiconductor device according to claim 1, wherein The electrically inactive dummy fin structure does not contact any conductive structure.

8. A semiconductor device comprising: Semiconductor substrate; a FinFET transistor device positioned above the semiconductor substrate, the FinFET transistor device having a single effective fin structure; an electrically inactive dummy fin structure, wherein the electrically inactive dummy fin structure is electrically inactive for electrical operation of the FinFET transistor having the single active fin structure; a first isolation structure comprising a first trench between the electrically inactive dummy fin structure and the single active fin structure of the FinFET transistor device, wherein the first trench is filled with an insulating material having a first vertical thickness; a second isolation structure comprising a second trench between the electrically inactive dummy fin structure and another fin structure, wherein the second trench is filled with an insulating material having a second vertical thickness greater than the first vertical thickness; and A gate structure is positioned around the single active fin, wherein the gate structure is not positioned around the electrically inactive dummy fin structure.

9. The semiconductor device according to claim 8, wherein: The electrically inactive dummy fin structure is positioned in a first cell of an integrated circuit product, and the single active fin structure is positioned in a second cell of the integrated circuit product.

10. The semiconductor device according to claim 8, wherein The second isolation structure has a first length in a direction corresponding to a gate length direction of the FinFET transistor, and the electrically inactive dummy fin structure has a second length in a direction corresponding to the gate length direction of the FinFET transistor, and wherein the first length and the second length are substantially the same.

11. The semiconductor device according to claim 8, wherein The second isolation structure has a first length in a direction corresponding to a gate length direction of the FinFET transistor, and the electrically inactive dummy fin structure has a second length in a direction corresponding to the gate length direction of the FinFET transistor, and wherein the first length and the second length are different.

12. The semiconductor device according to claim 8, wherein The second isolation structure has a first length in a direction corresponding to a gate length direction of the FinFET transistor, and the electrically inactive dummy fin structure has a second length in a direction corresponding to the gate length direction of the FinFET transistor, and wherein the first length is greater than the second length.

13. The semiconductor device according to claim 8, wherein: The single active fin structure is formed to have a first fin pitch, and wherein the electrically inactive dummy fin structure is positioned a distance from the single active fin structure equal to a multiple of the first fin pitch.

14. A semiconductor device comprising: Semiconductor substrate; a first isolation structure positioned in the semiconductor substrate; a second isolation structure positioned in the semiconductor substrate; a FinFET transistor device positioned above the semiconductor substrate, the FinFET transistor device having a single effective fin structure, wherein the single effective fin structure has opposite first and second sidewalls, and wherein the first sidewall is closer to the second isolation structure than the second sidewall; an electrically inactive dummy fin structure positioned adjacent to the first sidewall of the single active fin structure, the electrically inactive dummy fin structure being electrically inactive for electrical operation of the FinFET transistor having the single active fin structure; as well as a gate structure positioned around the single active fin, wherein the gate structure is not positioned around the electrically inactive dummy fin structure, wherein the first isolation structure comprises a first trench between the single valid fin structure and the electrically inactive dummy fin structure of the FinFET transistor device, wherein the first trench is filled with an insulating material having a first vertical thickness; and The second isolation structure includes a second trench between the electrically inactive dummy fin structure and another fin structure, wherein the second trench is filled with an insulating material having a second vertical thickness greater than the first vertical thickness.

15. The semiconductor device according to claim 14, wherein: When viewed from above, at least a portion of the electrically inactive dummy fin structure is located between the single active fin structure and the second isolation structure.

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