Compound semiconductor capacitor devices

Abstract

The present invention relates to the technical field of semiconductor manufacturing and discloses a compound semiconductor capacitor device comprising an upper plate, a lower plate, and a dielectric layer, the dielectric layer being disposed between the upper and lower plates, the lower plate comprising a substrate and a plurality of pre-deposited epitaxial layers, the pre-deposited epitaxial layers being disposed on the substrate via an epitaxial deposition process; the dielectric layer being disposed on the pre-deposited epitaxial layers, and the upper plate being disposed on the dielectric layer. Because the epitaxial deposition process provides stable concentrations and resistance values, and thus less susceptible to electrochemical properties, the resulting compound semiconductor capacitor device exhibits improved stability. Furthermore, the compound semiconductor capacitor device does not require the implantation of specific ions, nor does it require additional polycrystalline deposition or polycrystalline etching, simplifying the manufacturing process steps and reducing manufacturing costs.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a compound semiconductor capacitor device. Background Art

[0002] In the semiconductor industry, semiconductor chips are typically formed using semiconductor devices based on Group IV elements (e.g., silicon) and / or semiconductor devices based on germanium. Specifically, in the semiconductor industry, silicon-based semiconductors containing silicon, silicon-germanium alloys, or silicon-carbon alloys are typically available at low cost.

[0003] In traditional semiconductor technology, capacitors are formed by doping polysilicon and injecting ions into the substrate. This type of capacitor has poor stability and a complex manufacturing process. Summary of the Invention

[0004] The main purpose of the present invention is to provide a compound semiconductor capacitor device, aiming to solve the technical problems of poor capacitance stability and complex manufacturing process.

[0005] To achieve the above object, the present invention provides a compound semiconductor capacitor device, comprising an upper plate, a lower plate, and a dielectric layer, wherein the dielectric layer is disposed between the upper plate and the lower plate, and the lower plate comprises:

[0006] substrate;

[0007] A plurality of pre-deposited epitaxial layers are provided on the substrate through an epitaxial deposition process;

[0008] The dielectric layer is arranged on the preset epitaxial layer, and the upper electrode plate is arranged on the dielectric layer.

[0009] Furthermore, in one embodiment, the lower plate includes at least one capacitor block and at least one component block, and both the capacitor block and the component block include:

[0010] substrate;

[0011] A plurality of pre-deposited epitaxial layers are provided on the substrate through an epitaxial deposition process;

[0012] Wherein, the dielectric layer is arranged on the preset epitaxial layer; and the upper electrode plate is arranged on the dielectric layer of the capacitor block.

[0013] Furthermore, in one embodiment, the compound semiconductor capacitor device further includes:

[0014] a first via hole, disposed at a position corresponding to the capacitor block, the first via hole penetrating the dielectric layer;

[0015] The first metal layer is disposed in the first via hole and is connected to the preset epitaxial layer.

[0016] Furthermore, in one embodiment, the upper electrode plate is a second metal layer, and the first metal layer and the second metal layer are formed by an evaporation process.

[0017] Furthermore, in one embodiment, the first metal layer and the upper electrode plate are formed together.

[0018] Furthermore, in one embodiment, the compound semiconductor capacitor device further includes:

[0019] at least one second via hole, disposed at a position corresponding to the component block, the second via hole penetrating any one of the pre-deposited epitaxial layers, the first via hole and the second via hole being formed together;

[0020] at least one third metal layer, disposed in the second via hole and connected to the pre-deposited epitaxial layer;

[0021] The first metal layer, the third metal layer and the upper plate are formed together.

[0022] Furthermore, in one embodiment, the compound semiconductor capacitor device further includes:

[0023] an insulating layer, disposed on the dielectric layer and covering the upper plate, the first metal layer and the third metal layer;

[0024] A plurality of leads pass through the insulating layer and are respectively connected to the upper plate, the first metal layer and the third metal layer.

[0025] Furthermore, in one embodiment, the compound semiconductor capacitor device further includes an isolation layer, and the isolation layer is disposed between each block to isolate each block.

[0026] Furthermore, in one embodiment, the insulating layer comprises an inert gas.

[0027] Furthermore, in one embodiment, the plurality of pre-epitaxial layers include gallium and nitrogen.

[0028] In the technical solution provided by the present invention, multiple pre-set epitaxial layers are arranged on a substrate through an epitaxial deposition process to form a lower electrode, and a dielectric layer and an upper electrode are sequentially arranged on this lower electrode to form a compound semiconductor capacitor device. Since the concentration and resistance of the epitaxial deposition process are stable and the electrochemical properties are not easily affected, the stability of the formed compound semiconductor capacitor device is better. In addition, the compound semiconductor capacitor device does not require the implantation of specific ions and does not require additional polycrystallization deposition and polycrystallization corrosion, making the manufacturing process steps of the compound semiconductor capacitor device simpler and reducing the manufacturing process cost. In addition, the pre-set epitaxial layer in the lower electrode can be set according to the required function, and then other components can also be arranged on this lower electrode, so that the compound semiconductor capacitor device and other components can be formed together, thereby further simplifying the manufacturing process of the compound semiconductor capacitor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] One or more embodiments are exemplarily illustrated by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0030] Figure 1 A schematic structural diagram of a compound semiconductor capacitor device according to an embodiment of the present invention;

[0031] Figure 2 FIG. 1 is a schematic diagram of a manufacturing process of a compound semiconductor capacitor device according to an embodiment of the present invention.

[0032] Among them, 100, compound semiconductor capacitor device; 110, upper plate; 120, dielectric layer; 130, lower plate; 131, substrate; 132, pre-epitaxial layer; 133, capacitor block; 134, component block; 135, buffer layer; 136, collector layer; 137, base electrode layer; 138, two-dimensional electron gas layer; 139, emitter layer; 140, first via; 150, first metal layer; 160, second via; 170, third metal layer; 180, insulating layer; 190, lead; 200, isolation layer. DETAILED DESCRIPTION

[0033] To facilitate understanding of the present invention, the present invention is described in more detail below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly attached to the other element, or one or more elements can be interposed therebetween. When an element is described as being "connected to" another element, it can be directly connected to the other element, or one or more elements can be interposed therebetween. The terms "vertical," "horizontal," "left," "right," "inner," "outer," and similar expressions used in this specification are for illustrative purposes only. In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or implicitly specifying the number of technical features indicated. Therefore, unless otherwise specified, features specified as "first" or "second" may explicitly or implicitly include one or more of such features; "plurality" means two or more. The term "comprising" and any variations thereof are intended to be non-exclusive, and one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0034] In addition, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or internal communication between two components. All technical and scientific terms used in this specification have the same meaning as commonly understood by technicians in the technical field to which the present invention belongs. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.

[0035] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0036] Compound semiconductors generally refer to crystalline inorganic compound semiconductors, that is, compounds formed from two or more elements in a defined atomic ratio, exhibiting semiconductor properties such as a defined bandgap and energy band structure. These include crystalline inorganic compounds (such as III-V and II-VI compound semiconductors) and their solid solutions, amorphous inorganic compounds (such as glass semiconductors), organic compounds (such as organic semiconductors), and oxide semiconductors. Compound semiconductors generally refer to crystalline inorganic compound semiconductors.

[0037] The following is further described with reference to specific embodiments:

[0038] Please refer to Figure 1An embodiment of the present invention discloses a compound semiconductor capacitor device 100, which includes an upper plate 110, a lower plate 130 and a dielectric layer 120. The dielectric layer 120 is arranged between the upper plate 110 and the lower plate 130. The lower plate 130 includes a substrate 131 and a plurality of pre-deposited epitaxial layers 132; the plurality of pre-deposited epitaxial layers 132 are arranged on the substrate 131 through an epitaxial deposition process; the dielectric layer 120 is arranged on the pre-deposited epitaxial layers 132, and the upper plate 110 is arranged on the dielectric layer 120.

[0039] In this embodiment, a plurality of pre-deposited epitaxial layers 132 are arranged on a substrate 131 through an epitaxial deposition process to form a lower electrode 130, and a dielectric layer 120 and an upper electrode 110 are sequentially arranged on the lower electrode 130 to form a compound semiconductor capacitor device 100. Since the concentration and resistance of the epitaxial deposition process are stable and the electrochemical properties are not easily affected, the formed compound semiconductor capacitor device 100 has better stability. In addition, the compound semiconductor capacitor device 100 does not require the implantation of specific ions and does not require additional polycrystal deposition and polycrystal corrosion, making the manufacturing process steps of the compound semiconductor capacitor device 100 simpler and reducing the manufacturing process cost. In addition, the pre-deposited epitaxial layer 132 in the lower electrode 130 can be set according to the required function, and then other components can also be arranged on the lower electrode 130, so that the compound semiconductor capacitor device 100 and other components can be formed together, thereby further simplifying the manufacturing process of the compound semiconductor capacitor device 100.

[0040] In one embodiment, the lower plate 130 includes at least one capacitor block 133 and at least one component block 134, and both the capacitor block 133 and the component block 134 include a substrate 131 and a plurality of pre-deposited epitaxial layers 132; the plurality of pre-deposited epitaxial layers 132 are arranged on the substrate 131 through an epitaxial deposition process; wherein the dielectric layer 120 is arranged on the pre-deposited epitaxial layer 132; and the upper plate 110 is arranged on the dielectric layer 120 of the capacitor block 133.

[0041] The compound semiconductor capacitor device 100 further includes an isolation layer 200 disposed between each block to isolate the blocks. The isolation layer 200 comprises an inert gas, such as helium, which is injected between each block via high-energy ion implantation to form the isolation layer 200. The isolation layer 200 forms each block into an independent, mutually non-interfering component, enabling a variety of different functions.

[0042] The isolation layer 200 is a silicon nitride layer, and the upper plate 110 is a second metal layer. The silicon nitride layer can serve as both a dielectric layer 120 and a protective layer. It serves as the dielectric layer 120 when disposed on the capacitor block 133 and as a protective layer when disposed on the component block 134.

[0043] Specifically, the compound semiconductor capacitor device 100 includes a first via 140 and a first metal layer 150. The first via 140 is arranged at a position corresponding to the capacitor block 133, and the first via 140 passes through the dielectric layer 120; the first metal layer 150 is arranged in the first via 140 and is connected to the preset epitaxial layer 132.

[0044] The compound semiconductor capacitor device 100 further includes an insulating layer 180 and leads 190. The insulating layer 180 is disposed on the dielectric layer 120 and covers the first metal layer 150 and the top plate 110. The leads 190 pass through the insulating layer 180 and are connected to the first metal layer 150 and the top plate 110, respectively. The leads 190 are connected to the first metal layer 150 and the top plate 110, and the other ends of the leads 190 can be connected to external devices, thereby connecting the compound semiconductor capacitor device 100. The insulating layer 180 then separates the metal layers and leads 190, preventing interference between metal layers or between leads 190, such as short circuits.

[0045] The compound semiconductor capacitor device 100 also includes at least one second via 160 and at least one third metal layer 170. The second via 160 is arranged at a position corresponding to the component block 134. The second via 160 penetrates any of the pre-epitaxial layers 132. The first via 140 and the second via 160 are formed together; the third metal layer 170 is arranged in the second via 160 and is connected to the pre-epitaxial layer 132.

[0046] The insulating layer 180 also covers the third metal layer 170 , and the lead 190 passes through the insulating layer 180 and is connected to the third metal layer 170 .

[0047] By setting a second via 160 at the position of the component block 134, the second via 160 can be etched or photolithographically processed to the preset epitaxial layer 132 that needs to be connected according to the needs of the component to be set, and then a third metal layer 170 is set in the second via 160 to connect the corresponding preset epitaxial layer 132, and finally connected to the outside through the lead 190.

[0048] Furthermore, the first metal layer 150, the second metal layer, and the third metal layer 170 are formed together through an evaporation process. Forming the first metal layer 150, the second metal layer, and the third metal layer 170 together on the lower plate 130 through the evaporation process, thereby forming a capacitor and other components, greatly simplifies the manufacturing process steps. Furthermore, the evaporation process has the advantages of a simple film formation method, high film purity and density, and a unique film structure and performance. Using it to manufacture the compound semiconductor capacitor device 100 can improve the operational stability of the compound semiconductor capacitor device 100.

[0049] In this embodiment, when manufacturing the compound semiconductor capacitor device 100, a preset epitaxial layer 132 required for the function is pre-set. When manufacturing other components, the lower electrode plate 130 of the capacitor structure is separated by an isolation layer 200, and other commonly used components are directly generated on the separated lower electrode plate 130. In this way, the components can be directly generated together on the basis of manufacturing the capacitor structure, which greatly simplifies the steps of the manufacturing process of the compound semiconductor capacitor device 100. In simple terms, a lower electrode plate 130 that can be used together is first generated, and then the lower electrode plate 130 is isolated into different blocks, and then the capacitor structure and other components are jointly formed on the different blocks.

[0050] In one embodiment, the plurality of pre-epitaxial layers 132 are respectively a buffer layer 135, a collector layer 136, a base electrode layer 137, a two-dimensional electron gas layer 138 and an emitter layer 139. The buffer layer 135 is arranged on the substrate 131, the collector layer 136 is arranged on the buffer layer 135, the base electrode layer 137 is arranged on the collector layer 136, the two-dimensional electron gas layer 138 is arranged on the base electrode layer 137, and the emitter layer 139 is arranged on the two-dimensional electron gas layer 138.

[0051] The above-mentioned film layer is used as the lower electrode 130 of the compound semiconductor capacitor device 100. On the one hand, due to the stable concentration and resistance of the epitaxial deposition process, the electrochemical characteristics are not easily affected, so the stability of the compound semiconductor capacitor device 100 is better, and the compound semiconductor capacitor device 100 does not require the implantation of specific ions, and does not require additional recrystallization deposition and recrystallization corrosion, which makes the manufacturing process steps of the compound semiconductor capacitor device 100 simpler and reduces the manufacturing process cost; on the other hand, this lower electrode 130 can also support other components by providing an isolation layer 200, and can be made into two or more structures at one time, greatly simplifying the manufacturing process steps of the compound semiconductor capacitor device 100. Of course, it is not limited to the above-mentioned film layer and can be adjusted according to needs; and by providing a two-dimensional electrical layer between the base electrode layer 137 and the emitter electrode layer 139, the mobility of electrons is improved.

[0052] Specifically, the plurality of pre-epitaxial layers 132 include gallium and nitrogen elements. Specifically, the buffer layer 135 includes AlGaN, the collector layer 136 includes GaN, and the base electrode layer 137 includes GaN; the two-dimensional electron gas layer 138 includes AlGaN; the emitter electrode layer 139 includes GaN and / or InGaN; and the protective layer includes SiN.

[0053] Please refer to Figure 2 The present invention also discloses a method for manufacturing a compound semiconductor capacitor device, the method comprising the steps of:

[0054] S1. providing a substrate;

[0055] The substrate is made of a mixture of one or more of SiC, Al2O3 and Si.

[0056] S2, epitaxially depositing a buffer layer on the substrate;

[0057] The buffer layer is made of AlGaN and is used to adjust the lattice.

[0058] S3, epitaxially depositing a plurality of pre-deposited epitaxial layers on the buffer layer to form a lower electrode plate;

[0059] The pre-deposited epitaxial layer is deposited in a single lattice manner, so that it stably grows along the lattice to form a uniform and stable channel that is not affected by the outside world.

[0060] S4, forming a dielectric layer on the lower plate;

[0061] Specifically, in step S4, a dielectric layer is formed on the lower electrode plate by chemical vapor deposition, and the dielectric layer also serves as a protective layer. The material of the dielectric layer is SiN;

[0062] By setting a protective layer on the surface, the internal structure of the compound semiconductor is prevented from being damaged, such as scratched or corroded, which causes the performance of the compound semiconductor to weaken. By isolating the internal structure of the compound semiconductor from contact with the outside world, it prevents reactions from occurring that change the performance of the compound semiconductor. SiN is an inorganic substance and an important structural ceramic material. It has high hardness, inherent lubricity, and is wear-resistant. It is an atomic crystal. It is resistant to oxidation at high temperatures and can withstand thermal shocks. It can be heated to above 1000°C in air, rapidly cooled, and then rapidly heated without breaking. Therefore, setting SiN as a protective layer on the surface of the compound semiconductor can better protect the internal structure, extend the service life of the compound semiconductor, and ensure the performance of the compound semiconductor.

[0063] S5, dividing the lower plate into at least one capacitor block and at least one component block by photolithography and etching;

[0064] S6. Injecting an inert gas into the space created by photolithography or etching by high-energy ion implantation.

[0065] The shape and size of the resulting pattern can be precisely controlled through photolithography and etching processes, and the contours of the entire chip surface can be generated simultaneously. Multiple blocks are formed through photolithography and etching, and then an inert gas such as helium is injected between each block to block ion migration and form an isolation layer. This isolates each block from interfering with each other, allowing for a variety of different functions.

[0066] S7, forming a via hole on the dielectric layer to penetrate the pre-deposited epitaxial layer;

[0067] Specifically, a via hole is formed in the protective layer through photolithography and etching to penetrate the pre-deposited epitaxial layer. The shape and size of the formed pattern can be precisely controlled by the photolithography and etching process.

[0068] S8, forming a metal layer in the via hole by an evaporation process;

[0069] The evaporation process has the advantages of simple film formation, high film purity and density, unique film structure and performance, etc., and can be used to manufacture compound semiconductor capacitor devices to improve the stability of compound semiconductor capacitor devices. The evaporation process has the advantages of simple film formation, high film purity and density, unique film structure and performance, etc., and can be used to manufacture compound semiconductor capacitor devices to improve the stability of compound semiconductor capacitor devices.

[0070] S9, forming an insulating layer on the dielectric layer and covering the metal layer;

[0071] S10, forming a lead hole on the insulating layer to penetrate the metal layer;

[0072] S11, forming leads in the lead holes.

[0073] In the traditional silicon-based semiconductor manufacturing process, component channels are constructed by combining ion implantation with high-temperature diffusion. Multiple ion implantations in local areas damage the lattice at the implantation interface. In addition to achieving ion uniformity, high-temperature ion diffusion also causes the side effect of ion interpenetration between different dielectric layers, which ultimately leads to distortion, shortened lifespan, and reliability failure of semiconductor devices. In this solution, a multilayer structure is pre-placed on a substrate by epitaxial deposition, that is, the required pre-epitaxial layer is pre-placed on the substrate by epitaxial deposition, and then, according to the required function, a via is penetrated to the corresponding position in the pre-epitaxial layer to achieve the required function, thereby eliminating the mutual penetration of ions and damage between ions between different film layers caused by the traditional ion implantation plus high-temperature diffusion method, thereby stabilizing the component characteristics, improving the performance reliability of the semiconductor device, avoiding the influence of signal distortion, achieving more stable power output, and realizing stable application in high-frequency and high-power devices; then, the lattice is adjusted by a buffer layer, and the pre-epitaxial layer is grown according to the adjusted lattice; finally, a protective layer is provided on the pre-epitaxial layer to prevent the structure of the compound semiconductor capacitor device from being damaged, such as scratching or corrosion, which leads to a decrease in the performance of the compound semiconductor capacitor device, and at the same time, the internal structure of the compound semiconductor capacitor device is isolated from contact with the outside world to prevent reactions that change the performance of the compound semiconductor capacitor device.

[0074] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Under the concept of the present invention, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of the present invention as described above. For the sake of simplicity, they are not provided in detail. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in this field should understand that it is still possible to modify the technical solutions described in the above embodiments, or to make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A compound semiconductor capacitor device, comprising an upper plate, a lower plate, and a dielectric layer, wherein the dielectric layer is disposed between the upper plate and the lower plate, wherein: The lower plate comprises: substrate; A plurality of pre-deposited epitaxial layers are provided on the substrate through an epitaxial deposition process; The plurality of pre-deposited epitaxial layers are respectively a buffer layer, a collector layer, a base electrode layer, a two-dimensional electron gas layer and an emitter layer; the buffer layer is arranged on the substrate, the collector layer is arranged on the buffer layer, the base electrode layer is arranged on the collector layer, the two-dimensional electron gas layer is arranged on the base electrode layer, and the emitter layer is arranged on the two-dimensional electron gas layer; The buffer layer comprises AlGaN, the collector layer comprises GaN, the base electrode layer comprises GaN, the two-dimensional electron gas layer comprises AlGaN, and the emitter layer comprises GaN and / or InGaN; The dielectric layer is arranged on the preset epitaxial layer, and the upper electrode plate is arranged on the dielectric layer.

2. The compound semiconductor capacitor device according to claim 1, wherein The lower plate includes at least one capacitor block and at least one component block, and both the capacitor block and the component block include: substrate; A plurality of pre-deposited epitaxial layers are provided on the substrate through an epitaxial deposition process; Wherein, the dielectric layer is arranged on the preset epitaxial layer; and the upper electrode plate is arranged on the dielectric layer of the capacitor block.

3. The compound semiconductor capacitor device according to claim 2, wherein: The compound semiconductor capacitor device further includes: a first via hole, disposed at a position corresponding to the capacitor block, the first via hole penetrating the dielectric layer; The first metal layer is disposed in the first via hole and is connected to the preset epitaxial layer.

4. The compound semiconductor capacitor device according to claim 3, wherein: The upper electrode plate is a second metal layer, and the first metal layer and the second metal layer are formed by an evaporation process.

5. The compound semiconductor capacitor device according to claim 3, wherein: The first metal layer and the upper plate are formed together.

6. The compound semiconductor capacitor device according to claim 3, wherein: The compound semiconductor capacitor device further includes: at least one second via hole, disposed at a position corresponding to the component block, the second via hole penetrating any one of the pre-deposited epitaxial layers, the first via hole and the second via hole being formed together; at least one third metal layer, disposed in the second via hole and connected to the pre-deposited epitaxial layer; The first metal layer, the third metal layer and the upper plate are formed together.

7. The compound semiconductor capacitor device according to claim 6, wherein: The compound semiconductor capacitor device further includes: an insulating layer, disposed on the dielectric layer and covering the upper plate, the first metal layer and the third metal layer; A plurality of leads pass through the insulating layer and are respectively connected to the upper plate, the first metal layer and the third metal layer.

8. The compound semiconductor capacitor device according to claim 2, wherein: The compound semiconductor capacitor device further includes an isolation layer, which is disposed between each block and is used to isolate each block.

9. The compound semiconductor capacitor device according to claim 8, wherein: The insulating layer includes an inert gas.

10. The compound semiconductor capacitor device according to claim 1, wherein The plurality of pre-epitaxial layers all include gallium and nitrogen.

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