Integrated circuit automated logic synthesis system, method, device and medium

Abstract

The present application discloses an integrated circuit automated logic synthesis system, method, device and medium, the system comprising: an environment configuration module for obtaining synthesis parameters; a synthesis optimization module for performing logic synthesis on the RTL code file to be synthesized according to the synthesis parameters to obtain a preliminary synthesis result; a report generation module for generating a corresponding preliminary synthesis report; a report automatic analysis module for analyzing the preliminary synthesis report and determining the optimization control parameters; an iterative optimization command automatic generation module for optimizing the preliminary synthesis result according to the optimization control parameters to obtain the optimized synthesis result, and calling the report generation module and the report automatic analysis module to update the optimization control parameters, and iteratively optimizing the optimized synthesis result according to the updated optimization control parameters until the preset output conditions are met; and a result output module for outputting the target synthesis result. This saves design costs and is conducive to the rapid listing of integrated circuits.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an integrated circuit automated logic synthesis system, method, device and medium. Background Art

[0002] With the continuous development of information technology, people's lives and working methods have undergone tremendous changes, and the core supporting these changes is integrated circuits with various functions. The structure of current integrated circuits is becoming more and more complex, and EDA (Electronic Design Automation) tools are needed to complete integrated circuit design. Logic synthesis is the process of converting RTL (Register Transfer Level) code into a gate-level netlist. It is an extremely important step in the entire integrated circuit design process, and its design cycle is directly related to the design cost.

[0003] In existing integrated circuit design, after obtaining the initial synthesis results, logic synthesis requires manual review of reports and finding timing violations, and then manual input of commands for incremental iterations. This greatly prolongs the logic synthesis cycle, increases design costs, and is extremely detrimental to the rapid launch of integrated circuits. Summary of the invention

[0004] In view of this, the purpose of this application is to provide an integrated circuit automated logic synthesis system, method, device and medium, which can automatically analyze the preliminary synthesis report after the first logic synthesis, determine the optimization control parameters, and automatically optimize the preliminary synthesis results, without manually checking the report and entering commands, but using an automated method to implement the integrated circuit logic synthesis iteration process, greatly shortening the design cycle, saving design costs, and facilitating the rapid listing of integrated circuits. The specific scheme is as follows:

[0005] In a first aspect, the present application discloses an integrated circuit automated logic synthesis system, comprising:

[0006] Environment configuration module, used to obtain comprehensive parameters;

[0007] A synthesis optimization module, used for performing logic synthesis on the RTL code file to be synthesized according to the synthesis parameters to obtain a preliminary synthesis result;

[0008] A report generation module, used for generating a preliminary comprehensive report according to the preliminary comprehensive results;

[0009] An automatic report analysis module is used to analyze the preliminary comprehensive report and determine the optimized control parameters;

[0010] an iterative optimization command automatic generation module, used to optimize the paths in the preliminary synthesis result according to the optimization control parameters to obtain an optimized synthesis result, and call the report generation module and the report automatic analysis module to update the optimization control parameters according to the optimized synthesis result, and iteratively optimize the optimized synthesis result according to the updated optimization control parameters until the preset output conditions are met to obtain a target synthesis result;

[0011] The result output module is used to output the target comprehensive result.

[0012] Optionally, the environment configuration module includes:

[0013] A path information acquisition submodule, used to obtain the path of the RTL code file to be synthesized, the path of the synthesis constraint file and the path of the library file;

[0014] A first comprehensive variable setting submodule is used to obtain optimization parameter thresholds, wherein the optimization parameter thresholds include a preset maximum iteration time, a preset maximum violation threshold of a timing sequence, a violation value ratio threshold, a maximum utilization rate of an LVT standard cell, a maximum increment of an LVT standard cell per iteration, a maximum utilization rate of an ULVT standard cell, and a maximum increment of an ULVT standard cell per iteration;

[0015] The second comprehensive variable setting submodule is used to obtain comprehensive parameters other than the optimization parameter threshold.

[0016] Optionally, the comprehensive optimization module includes:

[0017] A design reading submodule is used to read the RTL code file to be synthesized, the synthesis constraint file and the library file according to the path of the RTL code file to be synthesized, the path of the synthesis constraint file and the path of the library file;

[0018] The path group setting submodule is used to obtain the preset number of path groups;

[0019] The synthesis execution submodule is used to perform logic synthesis on the RTL code file to be synthesized according to the synthesis parameters, the synthesis constraint file, and the library file to obtain the preliminary synthesis result, wherein the preliminary synthesis result includes several path groups of the preset path group.

[0020] Optionally, the report generation module is used to:

[0021] The preliminary synthesis report is generated by using the setup time timing violation value of each path in each path group in the preliminary synthesis result, the current utilization rate of the LVT standard cell, the current utilization rate of the ULVT standard cell, and the synthesis consumed time.

[0022] Optionally, the report automatic analysis module includes:

[0023] A report information analysis submodule, configured to determine a maximum value of a setup time sequence violation and an average value of a setup time sequence violation of each path group according to the setup time sequence violation value of each path;

[0024] An analysis result output submodule, used for determining the optimization control variable tag of each path according to the violation value ratio of each path and the violation value ratio threshold, and outputting the optimization control variable tag, the maximum value of the establishment time sequence violation, the current utilization rate of the LVT standard unit, the current utilization rate of the ULVT standard unit, and the comprehensive consumed time as optimization control parameters;

[0025] Among them, the violation value ratio of any path is the ratio of the establishment time timing violation value of the path to the average establishment time timing violation value of the path group to which the path belongs. The optimization control variable tag is 1, indicating that the violation value ratio of the corresponding path is greater than the violation value ratio threshold. The optimization control variable tag is 0, indicating that the violation value ratio of the corresponding path is not greater than the violation value ratio threshold.

[0026] Optionally, the iterative optimization command automatic generation module includes:

[0027] The optimization control submodule is used to determine whether the optimization control variable tag is all 0 when the maximum value of the establishment time sequence violation is not less than the preset maximum violation threshold of the establishment time sequence;

[0028] A path group generation submodule, used for setting the path whose optimization control variable is 1 as a new path group when the optimization control variable tag is not all 0;

[0029] The optimization control submodule is used to determine whether the current utilization rate of the LVT standard unit is less than the maximum utilization rate of the LVT standard unit when all the optimization control variables tag are 0;

[0030] An LVT standard cell utilization setting submodule is used to set the optimized LVT standard cell utilization according to the LVT standard cell maximum utilization, the maximum increment of each iteration of the LVT standard cell and the current utilization of the LVT standard cell when the current utilization of the LVT standard cell is less than the maximum utilization of the LVT standard cell;

[0031] The optimization control submodule is used to determine whether the current utilization rate of the ULVT standard cell is less than the maximum utilization rate of the ULVT standard cell when the current utilization rate of the LVT standard cell is not less than the maximum utilization rate of the LVT standard cell;

[0032] A ULVT standard cell utilization setting submodule, configured to set an optimized ULVT standard cell utilization according to the ULVT standard cell maximum utilization, the maximum increment of each iteration of the ULVT standard cell and the ULVT standard cell current utilization when the ULVT standard cell current utilization is less than the ULVT standard cell maximum utilization;

[0033] The incremental optimization synthesis execution submodule is used to optimize the establishment time timing violation of the new path group when the synthesis consumed time is less than the preset maximum iteration time, and optimize the path in the preliminary synthesis result according to the optimized LVT standard cell utilization and the optimized ULVT standard cell utilization to obtain the optimized synthesis result.

[0034] Optionally, the LVT standard cell utilization setting submodule is used to:

[0035] The sum of the maximum increment of each iteration of the LVT standard cell and the current utilization of the LVT standard cell is used as the preselected LVT standard cell utilization;

[0036] The optimized LVT standard cell utilization is set as the maximum value between the LVT standard cell maximum utilization and the pre-selected LVT standard cell utilization.

[0037] In a second aspect, the present application discloses an integrated circuit automated logic synthesis method, comprising:

[0038] Get comprehensive parameters;

[0039] Performing logic synthesis on the RTL code file to be synthesized according to the synthesis parameters to obtain a preliminary synthesis result;

[0040] generating a preliminary comprehensive report based on the preliminary comprehensive results;

[0041] Analyze the preliminary comprehensive report to determine the optimal control parameters;

[0042] Optimizing the paths in the preliminary synthesis result according to the optimization control parameters to obtain an optimized synthesis result, updating the optimization control parameters according to the optimized synthesis result, and iteratively optimizing the optimized synthesis result according to the updated optimization control parameters until a preset output condition is met to obtain a target synthesis result;

[0043] Output the target comprehensive result.

[0044] In a third aspect, the present application discloses an electronic device, comprising:

[0045] Memory and processor;

[0046] Wherein, the memory is used to store computer programs;

[0047] The processor is used to execute the computer program to implement the aforementioned integrated circuit automatic logic synthesis method disclosed above.

[0048] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the aforementioned disclosed method for automated logic synthesis of integrated circuits.

[0049] It can be seen that the present application discloses an integrated circuit automated logic synthesis system, comprising: an environment configuration module, used to obtain synthesis parameters; a synthesis optimization module, used to perform logic synthesis on the RTL code file to be synthesized according to the synthesis parameters to obtain a preliminary synthesis result; a report generation module, used to generate a preliminary synthesis report according to the preliminary synthesis result; a report automatic analysis module, used to analyze the preliminary synthesis report and determine the optimization control parameters; an iterative optimization command automatic generation module, used to optimize the path in the preliminary synthesis result according to the optimization control parameters to obtain an optimized synthesis result, and call the report generation module and the report automatic analysis module to update the optimization control parameters according to the optimized synthesis result, and iteratively optimize the optimized synthesis result according to the updated optimization control parameters until the preset output conditions are met to obtain the target synthesis result; a result output module, used to output the target synthesis result. It can be seen that in this application, after the comprehensive optimization module performs preliminary logic synthesis on the RTL code file to be synthesized and obtains the preliminary synthesis result, a preliminary synthesis report can be generated based on the preliminary synthesis result, and then the report automatic analysis module analyzes the preliminary synthesis report to determine the optimization control parameters, and then the iterative optimization command automatic generation module optimizes the preliminary synthesis result according to the optimization control parameters, and after each optimization, the report generation module and the report automatic analysis module are called back to update the optimization control parameters, and the optimized synthesis result is iterated according to the updated optimization control parameters until it meets the preset output conditions, and the result output module can output the final target synthesis result, so that after the first logic synthesis, the preliminary synthesis report can be automatically analyzed to determine the optimization control parameters, thereby automatically optimizing the preliminary synthesis result, without manually checking the report and entering commands, but using an automated method to implement the iterative logic synthesis process of the integrated circuit, which greatly shortens the design cycle, saves design costs, and is conducive to the rapid listing of integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0051] Figure 1 A schematic diagram of the structure of an integrated circuit automated logic synthesis system disclosed in this application;

[0052] Figure 2 A schematic diagram of a specific integrated circuit automated logic synthesis system disclosed in this application;

[0053] Figure 3 A specific integrated circuit automated logic synthesis system workflow diagram disclosed in this application;

[0054] Figure 4 A flowchart of a specific integrated circuit automated logic synthesis method disclosed in this application;

[0055] Figure 5 This is a schematic diagram of the structure of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0057] See also Figure 1 As shown, the embodiment of the present application discloses an integrated circuit automated logic synthesis system, the system comprising:

[0058] An environment configuration module 11 is used to obtain comprehensive parameters;

[0059] A synthesis optimization module 12, used for performing logic synthesis on the RTL code file to be synthesized according to the synthesis parameters to obtain a preliminary synthesis result;

[0060] A report generating module 13, used for generating a preliminary comprehensive report according to the preliminary comprehensive result;

[0061] The report automatic analysis module 14 is used to analyze the preliminary comprehensive report and determine the optimization control parameters;

[0062] An iterative optimization command automatic generation module 15 is used to optimize the paths in the preliminary synthesis result according to the optimization control parameters to obtain an optimized synthesis result, and call the report generation module and the report automatic analysis module to update the optimization control parameters according to the optimized synthesis result, and iteratively optimize the optimized synthesis result according to the updated optimization control parameters until the preset output conditions are met to obtain a target synthesis result;

[0063] The result output module 16 is used to output the target comprehensive result.

[0064] It can be seen that the present application discloses an integrated circuit automated logic synthesis system, comprising: an environment configuration module, used to obtain synthesis parameters; a synthesis optimization module, used to perform logic synthesis on the RTL code file to be synthesized according to the synthesis parameters to obtain a preliminary synthesis result; a report generation module, used to generate a preliminary synthesis report according to the preliminary synthesis result; a report automatic analysis module, used to analyze the preliminary synthesis report and determine the optimization control parameters; an iterative optimization command automatic generation module, used to optimize the path in the preliminary synthesis result according to the optimization control parameters to obtain an optimized synthesis result, and call the report generation module and the report automatic analysis module to update the optimization control parameters according to the optimized synthesis result, and iteratively optimize the optimized synthesis result according to the updated optimization control parameters until the preset output conditions are met to obtain the target synthesis result; a result output module, used to output the target synthesis result. It can be seen that in this application, after the comprehensive optimization module performs preliminary logic synthesis on the RTL code file to be synthesized and obtains the preliminary synthesis result, a preliminary synthesis report can be generated based on the preliminary synthesis result, and then the report automatic analysis module analyzes the preliminary synthesis report to determine the optimization control parameters, and then the iterative optimization command automatic generation module optimizes the preliminary synthesis result according to the optimization control parameters, and after each optimization, the report generation module and the report automatic analysis module are called back to update the optimization control parameters, and the optimized synthesis result is iterated according to the updated optimization control parameters until it meets the preset output conditions, and the result output module can output the final target synthesis result, so that after the first logic synthesis, the preliminary synthesis report can be automatically analyzed to determine the optimization control parameters, thereby automatically optimizing the preliminary synthesis result, without manually checking the report and entering commands, but using an automated method to implement the iterative logic synthesis process of the integrated circuit, which greatly shortens the design cycle, saves design costs, and is conducive to the rapid listing of integrated circuits.

[0065] In practical applications, the integrated circuit automated logic synthesis system needs to include an environment configuration module for obtaining the synthesis parameters required for the logic synthesis process input by the user. Specifically, the environment configuration module may include: a path information acquisition submodule for obtaining the path of the RTL code file to be synthesized, the path of the synthesis constraint file, and the path of the library file; a first synthesis variable setting submodule for obtaining the optimization parameter threshold, wherein the optimization parameter threshold includes the preset maximum iteration time, the preset maximum violation threshold of the establishment time sequence, the violation value ratio threshold, the maximum utilization of the LVT (Low Voltage Threshold) standard unit, the maximum increment of each iteration of the LVT standard unit, the maximum utilization of the ULVT (UltraLow ​​Voltage Threshold) standard unit, and the maximum increment of each iteration of the ULVT standard unit; a second synthesis variable setting submodule for obtaining synthesis parameters other than the optimization parameter threshold.

[0066] That is, the environment configuration module first needs to include a path information acquisition submodule, which is used to obtain the path of the RTL code file to be synthesized, the path of the synthesis constraint file and the path of the library file, and can also obtain the path of the generated log storage, the path of the report storage and the path of the target synthesis result storage. In other words, the path setting submodule is used to obtain the information of the path where the required files exist and the path where the generated files need to be stored. It also includes a first synthesis variable setting submodule, which is used to obtain the preset maximum iteration time T max , preset maximum violation threshold M of the setup time sequence, violation value ratio threshold R, maximum utilization rate P% of the LVT standard cell, maximum increment P of each iteration of the LVT standard cell step %, maximum utilization of ULVT standard unit Q%, maximum increment of ULVT standard unit per iteration Q step % and other optimization parameter thresholds. And the second comprehensive variable setting submodule is used to obtain comprehensive parameters other than the above optimization parameter thresholds, such as the number of CPU cores and the maximum fan-out.

[0067] Of course, the integrated circuit automated logic synthesis system also includes: the synthesis optimization module, which is used to perform logic synthesis on the RTL code file to be synthesized according to the synthesis parameters to obtain a preliminary synthesis result. Specifically, the synthesis optimization module may include a design reading submodule, which is used to read the RTL code file to be synthesized, the synthesis constraint file and the library file according to the path of the RTL code file to be synthesized, the path of the synthesis constraint file and the path of the library file; a path group setting submodule, which is used to obtain a preset number of path groups; a synthesis execution submodule, which is used to perform logic synthesis on the RTL code file to be synthesized according to the synthesis parameters, the synthesis constraint file and the library file to obtain the preliminary synthesis result, wherein the preliminary synthesis result includes the preset number of path groups.

[0068] That is, the design reading submodule first reads the RTL code file to be synthesized, the synthesis constraint file and the library file according to the path of the RTL code file to be synthesized, the path of the synthesis constraint file and the path of the library file, and then the path group setting submodule obtains the preset number of path groups S to improve the timing performance. Then the synthesis execution submodule can perform logic synthesis on the RTL code file to be synthesized according to the synthesis parameters, the synthesis constraint file and the library file to obtain the preliminary synthesis result, wherein the preliminary synthesis result includes the preset number of path groups S.

[0069] After obtaining the preliminary synthesis result, since it is uncertain whether the preliminary synthesis result meets the requirements, the integrated circuit automatic logic synthesis system also needs to include a report generation module for generating a preliminary synthesis report according to the preliminary synthesis result. Specifically, the report generation module uses the setup time timing violation value of each path in each path group in the preliminary synthesis result, the current utilization rate P of the LVT standard unit, and the now %, ULVT standard unit current utilization rate Q now %, Comprehensive elapsed time T now The preliminary comprehensive report is generated, wherein the setup time timing violation value of each path in each path group can be written into the preliminary comprehensive report in descending order.

[0070] After obtaining the preliminary comprehensive report, the report automatic analysis module needs to analyze the preliminary comprehensive report to determine the optimization control parameters. Specifically, the report automatic analysis module includes: a report information analysis submodule, which is used to determine the maximum value of the establishment time sequence violation and the average value of the establishment time sequence violation of each path group according to the establishment time sequence violation value of each path; an analysis result output submodule, which is used to determine the optimization control variable tag of each path according to the violation value ratio of each path and the violation value ratio threshold, and output the optimization control variable tag, the maximum value of the establishment time sequence violation, the current utilization of the LVT standard unit, the current utilization of the ULVT standard unit, and the comprehensive consumed time as optimization control parameters; wherein, the violation value ratio of any path is the ratio of the establishment time sequence violation value of the path to the average value of the establishment time sequence violation of the path group to which the path belongs, and the optimization control variable tag is 1, indicating that the violation value ratio of the corresponding path is greater than the violation value ratio threshold, and the optimization control variable tag is 0, indicating that the violation value ratio of the corresponding path is not greater than the violation value ratio threshold.

[0071] That is, the report information analysis submodule in the report automatic analysis module first determines the maximum value of the setup time sequence violation and the average value of the setup time sequence violation of each path group according to the setup time sequence violation value of each path. The total number of paths with setup time sequence violations in the sth path group is recorded as C s The average value of the timing violation value of the sth path group establishment time is recorded as a s , the setup time timing violation value of the dth path in the sth path group is denoted as v sd , the optimization control variable of the dth path in the sth path group is denoted as tag sd The maximum violation value of the setup time sequence of all paths is V max , where 1≤s≤S, 1≤d≤C s The report information analysis submodule uses the preliminary comprehensive report to calculate v sd 、a s , and V max The analysis result output submodule of the report automatic analysis module is compared with v sd / a s With the size of R, when v sd / a s When it is greater than R, the optimization control variable tag of the dth path in the sth path group in the report sd Set to 1, otherwise set to 0, traverse all violation paths in the report to complete the setting of all optimization control variables, and output tag sd 、V max , LVT standard unit current utilization Pnow %, ULVT standard unit current utilization rate Q now %, Comprehensive elapsed time T now That is, the optimization control parameters include tag sd 、V max , LVT standard unit current utilization P now %, ULVT standard unit current utilization rate Q now %, Comprehensive elapsed time T now .

[0072] Then, the iterative optimization command automatic generation module can optimize the paths in the preliminary comprehensive result according to the optimization control parameters to obtain the optimized comprehensive result. After each optimization, the report generation module and the report automatic analysis module are called to update the optimization control parameters according to the optimized comprehensive result, and the optimized comprehensive result is iteratively optimized according to the updated optimization control parameters until the preset output conditions are met to obtain the target comprehensive result. That is, after each optimization, the iterative optimization command automatic generation module calls the report generation module back to generate an optimization comprehensive report corresponding to the optimized comprehensive result, calls the report automatic analysis module to analyze the optimization comprehensive report, so as to update the optimization control parameters to obtain the updated optimization control parameters, and iteratively optimizes the optimized comprehensive result according to the updated optimization control parameters until the preset output conditions are met to obtain the target comprehensive result, wherein the preset output conditions include the comprehensive consumed time T now Reach the preset maximum iteration time T max , the maximum violation value of the establishment time sequence is V max is smaller than the preset maximum violation threshold M of the establishment time sequence.

[0073] It can be understood that after obtaining the target synthesis result, the result output module can output the target synthesis result, wherein the target synthesis result includes a gate-level netlist, a constraint file, and a synthesis report.

[0074] See also Figure 2 As shown, the iterative optimization command automatic generation module 15 includes:

[0075] The optimization control submodule 151 is used to determine whether the optimization control variable tag is all 0 when the maximum value of the establishment time sequence violation is not less than the preset maximum violation threshold of the establishment time sequence;

[0076] A path group generation submodule 152 is used to set the path whose optimization control variable is 1 as a new path group when the optimization control variable tag is not all 0;

[0077] The optimization control submodule is used to determine whether the current utilization rate of the LVT standard unit is less than the maximum utilization rate of the LVT standard unit when all the optimization control variables tag are 0;

[0078] The LVT standard cell utilization setting submodule 153 is used to set the optimized LVT standard cell utilization according to the LVT standard cell maximum utilization, the maximum increment of each iteration of the LVT standard cell and the current utilization of the LVT standard cell when the current utilization of the LVT standard cell is less than the maximum utilization of the LVT standard cell;

[0079] The optimization control submodule is used to determine whether the current utilization rate of the ULVT standard cell is less than the maximum utilization rate of the ULVT standard cell when the current utilization rate of the LVT standard cell is not less than the maximum utilization rate of the LVT standard cell;

[0080] The ULVT standard cell utilization setting submodule 154 is used to set the optimized ULVT standard cell utilization according to the ULVT standard cell maximum utilization, the maximum increment of each iteration of the ULVT standard cell and the ULVT standard cell current utilization when the current utilization of the ULVT standard cell is less than the maximum utilization of the ULVT standard cell;

[0081] The incremental optimization synthesis execution submodule 155 is used to optimize the establishment time timing violation of the new path group when the synthesis consumed time is less than the preset maximum iteration time, and optimize the path in the preliminary synthesis result according to the optimized LVT standard cell utilization and the optimized ULVT standard cell utilization to obtain the optimized synthesis result.

[0082] Specifically, the optimization control submodule in the iterative optimization command automatic generation module 16 first determines the maximum value V of the timing violation of the establishment time. max Is it not less than the preset maximum violation threshold M of the establishment time sequence? If not, it means that the preliminary synthesis result has met the requirements and the preliminary synthesis result can be directly output as the target synthesis result. maxIf it is not less than the preset maximum violation threshold M of the establishment time sequence, it means that optimization is still needed. Specifically, it can be determined whether the optimization control variable tag is all 0. The path group generation submodule is used to set the path with the optimization control variable of 1 as a new path group when the optimization control variable tag is not all 0. Specifically, each path with the optimization control variable tag not being 0 is separately regarded as a path group. For example, the number of path groups S in the preliminary comprehensive result is 5, and there are 3 paths with the optimization control variable tag not being 0 in each path group. Then each of the 3 paths is regarded as a path group separately, and 3 new path groups are set, which becomes a total of 8 path groups. The optimization control submodule also needs to determine the current utilization rate P of the LVT standard unit when the optimization control variable tag is all 0. now % is less than the maximum utilization rate P% of the LVT standard unit. The LVT standard unit utilization setting submodule determines whether the current utilization rate P% of the LVT standard unit is less than the maximum utilization rate P% of the LVT standard unit. now % is less than the maximum utilization rate P% of the LVT standard unit, according to the maximum utilization rate P% of the LVT standard unit, the maximum increment P% of each iteration of the LVT standard unit step % and the current utilization rate of the LVT standard unit P now % Set the utilization rate of the LVT standard unit after optimization. The optimization control submodule, in the current utilization rate P of the LVT standard unit now % is not less than the maximum utilization rate P% of the LVT standard unit, it is also necessary to determine the current utilization rate Q of the ULVT standard unit now % is less than the maximum utilization rate Q% of the ULVT standard cell. The ULVT standard cell utilization rate setting submodule 154 sets the current utilization rate Q% of the ULVT standard cell. now % is less than the maximum utilization rate Q% of the ULVT standard cell, the optimized ULVT standard cell utilization rate is set according to the maximum utilization rate of the ULVT standard cell, the maximum increment of each iteration of the ULVT standard cell and the current utilization rate of the ULVT standard cell.

[0083] Then, the incremental optimization synthesis execution submodule 155 can be used to perform the synthesis. now Less than the preset maximum iteration time T max When the new path group is optimized for setup time timing violation, the paths in the preliminary synthesis result are optimized according to the optimized LVT standard cell utilization and the optimized ULVT standard cell utilization to obtain the optimized synthesis result.

[0084] The LVT standard cell utilization setting submodule is used to: take the sum of the maximum increment of each iteration of the LVT standard cell and the current utilization of the LVT standard cell as the pre-selected LVT standard cell utilization; and set the maximum value of the maximum utilization of the LVT standard cell and the pre-selected LVT standard cell utilization as the optimized LVT standard cell utilization. step %+P now %P%) sets the optimized LVT standard cell utilization. Correspondingly, the ULVT standard cell utilization setting submodule 154 sets max(Q step %+Q now %, Q%) sets the utilization rate of the ULVT standard unit after optimization.

[0085] See also Figure 3 As shown, it is a workflow diagram of the integrated circuit automated logic synthesis system. First, the data path is set, that is, the path information acquisition submodule in the aforementioned environment configuration module obtains the path of the RTL code file to be synthesized, the path of the integrated constraint file and the path of the library file. Then the traditional integrated variable setting is performed, that is, the aforementioned environment configuration module obtains the integrated parameters other than the optimization parameter threshold. It is also necessary to perform automated integrated parameter setting, that is, the first integrated variable setting submodule in the aforementioned environment configuration module obtains the optimization parameter threshold.

[0086] Then you can read in the design, set up the path group, perform the first optimization synthesis, generate the synthesis report, calculate v sd 、a s , and V max , and set the optimization control variable tag sd . Determine V max Is it less than M? If so, the comprehensive result can be directly output. If not, determine whether to optimize the control variable tag sd All are 0, if not all are 0, then tag sd Set a new path group for each path corresponding to 1, and now Less than T max When , perform incremental comprehensive optimization. If all are 0, then judge P now % is less than P%, if P now % is less than P%, then the utilization of the LVT standard unit is set to max(P step %+P now %, P%), if P now % is not less than P%, then Q now % is less than Q%, if Q now % is less than Q%, then the utilization of the ULVT standard unit is set to max(Qstep %+Q now %, Q%), and then execute judgment T now Is it less than T ma Steps in T now Less than T max When the preset output conditions are met, the comprehensive results are output.

[0087] See also Figure 4 As shown, the embodiment of the present application discloses a specific integrated circuit automated logic synthesis method, the method comprising:

[0088] Step S11: Obtain comprehensive parameters.

[0089] Step S12: performing logic synthesis on the RTL code file to be synthesized according to the synthesis parameters to obtain a preliminary synthesis result.

[0090] Step S13: Generate a preliminary comprehensive report according to the preliminary comprehensive results.

[0091] Step S14: Analyze the preliminary comprehensive report to determine the optimal control parameters.

[0092] Step S15: Optimize the paths in the preliminary synthesis result according to the optimization control parameters to obtain an optimized synthesis result, update the optimization control parameters according to the optimized synthesis result, and iteratively optimize the optimized synthesis result according to the updated optimization control parameters until the preset output conditions are met to obtain the target synthesis result.

[0093] Step S16: Output the target comprehensive result.

[0094] The specific execution of each of the above steps may refer to the contents disclosed in the aforementioned embodiments, which will not be described in detail here.

[0095] Figure 5 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include but is not limited to a laptop computer or a desktop computer.

[0096] Generally, the electronic device 20 in this embodiment includes: a processor 21 and a memory 22 .

[0097] Among them, the processor 21 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. The processor 21 may be implemented using at least one of DSP (digital signal processing), FPGA (field-programmable gate array), and PLA (programmable logic array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (central processing unit); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a GPU (graphics processing unit), which is responsible for rendering and drawing images that need to be displayed on the display screen. In some embodiments, the processor 21 may include an AI (artificial intelligence) processor, which is used to process computing operations related to machine learning.

[0098] The memory 22 may include one or more computer-readable storage media, which may be non-transitory. The memory 22 may also include a high-speed random access memory and a non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In this embodiment, the memory 22 is at least used to store the following computer program 221, wherein after the computer program is loaded and executed by the processor 21, the steps of the integrated circuit automated logic synthesis method disclosed in any of the aforementioned embodiments can be implemented.

[0099] In some embodiments, the electronic device 20 may further include a display screen 23 , an input / output interface 24 , a communication interface 25 , a sensor 26 , a power source 27 , and a communication bus 28 .

[0100] Those skilled in the art will understand that Figure 5 The structure shown in the figure does not constitute a limitation on the electronic device 20, and may include more or fewer components than shown in the figure.

[0101] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the integrated circuit automated logic synthesis method disclosed in any of the aforementioned embodiments.

[0102] Among them, the specific process of the above-mentioned integrated circuit automatic logic synthesis method can refer to the corresponding content disclosed in the above-mentioned embodiment, and will not be repeated here.

[0103] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0104] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0105] Finally, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a series of processes, methods, articles or equipment containing other elements include not only those elements, but also other elements not explicitly listed, or also include elements inherent to such processes, methods, articles or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or equipment that includes the elements.

[0106] The above is a detailed introduction to an integrated circuit automated logic synthesis system, method, device and medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An integrated circuit automated logic synthesis system, characterized in that: include: Environment configuration module, used to obtain comprehensive parameters; A synthesis optimization module, used for performing logic synthesis on the RTL code file to be synthesized according to the synthesis parameters to obtain a preliminary synthesis result; A report generation module, used for generating a preliminary comprehensive report according to the preliminary comprehensive results; An automatic report analysis module is used to analyze the preliminary comprehensive report and determine the optimized control parameters; an iterative optimization command automatic generation module, used to optimize the paths in the preliminary synthesis result according to the optimization control parameters to obtain an optimized synthesis result, and call the report generation module and the report automatic analysis module to update the optimization control parameters according to the optimized synthesis result, and iteratively optimize the optimized synthesis result according to the updated optimization control parameters until the preset output conditions are met to obtain a target synthesis result; A result output module, used to output the target comprehensive result; The comprehensive optimization module comprises: A design reading submodule is used to read the RTL code file to be synthesized, the synthesis constraint file and the library file according to the path of the RTL code file to be synthesized, the path of the synthesis constraint file and the path of the library file; The path group setting submodule is used to obtain the preset number of path groups; A synthesis execution submodule, used for performing logic synthesis on the RTL code file to be synthesized according to the synthesis parameters, the synthesis constraint file, and the library file to obtain the preliminary synthesis result, wherein the preliminary synthesis result includes the preset path group and several path groups; The report automatic analysis module comprises: A report information analysis submodule, configured to determine a maximum value of a setup time sequence violation and an average value of a setup time sequence violation of each path group according to the setup time sequence violation value of each path; An analysis result output submodule is used to determine the optimization control variable tag of each path according to the violation value ratio of each path and the violation value ratio threshold, and output the optimization control variable tag, the maximum value of the establishment time sequence violation, the current utilization rate of the LVT standard unit, the current utilization rate of the ULVT standard unit, and the comprehensive consumed time as optimization control parameters; Among them, the violation value ratio of any path is the ratio of the establishment time sequence violation value of the path to the average value of the establishment time sequence violation of the path group to which the path belongs, and the optimization control variable tag is 1, indicating that the violation value ratio of the corresponding path is greater than the violation value ratio threshold, and the optimization control variable tag is 0, indicating that the violation value ratio of the corresponding path is not greater than the violation value ratio threshold; The iterative optimization command automatic generation module includes: The optimization control submodule is used to determine whether the optimization control variable tag is all 0 when the maximum value of the establishment time sequence violation is not less than the preset maximum violation threshold of the establishment time sequence; A path group generation submodule, used for setting the path whose optimization control variable is 1 as a new path group when the optimization control variable tag is not all 0; The optimization control submodule is used to determine whether the current utilization rate of the LVT standard unit is less than the maximum utilization rate of the LVT standard unit when all the optimization control variables tag are 0; An LVT standard cell utilization setting submodule is used to set the optimized LVT standard cell utilization according to the LVT standard cell maximum utilization, the maximum increment of each iteration of the LVT standard cell and the current utilization of the LVT standard cell when the current utilization of the LVT standard cell is less than the maximum utilization of the LVT standard cell; The optimization control submodule is used to determine whether the current utilization rate of the ULVT standard cell is less than the maximum utilization rate of the ULVT standard cell when the current utilization rate of the LVT standard cell is not less than the maximum utilization rate of the LVT standard cell; A ULVT standard cell utilization setting submodule, configured to set an optimized ULVT standard cell utilization according to the ULVT standard cell maximum utilization, the maximum increment of each iteration of the ULVT standard cell and the ULVT standard cell current utilization when the ULVT standard cell current utilization is less than the ULVT standard cell maximum utilization; The incremental optimization synthesis execution submodule is used to optimize the establishment time timing violation of the new path group when the synthesis consumed time is less than the preset maximum iteration time, and optimize the path in the preliminary synthesis result according to the optimized LVT standard cell utilization and the optimized ULVT standard cell utilization to obtain the optimized synthesis result.

2. The integrated circuit automated logic synthesis system according to claim 1, characterized in that: The environment configuration module includes: A path information acquisition submodule, used to obtain the path of the RTL code file to be synthesized, the path of the synthesis constraint file and the path of the library file; A first comprehensive variable setting submodule is used to obtain optimization parameter thresholds, wherein the optimization parameter thresholds include a preset maximum iteration time, a preset maximum violation threshold of a timing sequence, a violation value ratio threshold, a maximum utilization rate of an LVT standard cell, a maximum increment of an LVT standard cell per iteration, a maximum utilization rate of an ULVT standard cell, and a maximum increment of an ULVT standard cell per iteration; The second comprehensive variable setting submodule is used to obtain comprehensive parameters other than the optimization parameter threshold.

3. The integrated circuit automated logic synthesis system according to claim 1, characterized in that: The report generation module is used to: The preliminary synthesis report is generated by using the setup time timing violation value of each path in each path group in the preliminary synthesis result, the current utilization rate of the LVT standard cell, the current utilization rate of the ULVT standard cell, and the synthesis consumed time.

4. The integrated circuit automated logic synthesis system according to claim 3, characterized in that: The LVT standard cell utilization setting submodule is used to: The sum of the maximum increment of each iteration of the LVT standard cell and the current utilization rate of the LVT standard cell is used as the preselected LVT standard cell utilization rate; The optimized LVT standard cell utilization is set as the maximum value between the LVT standard cell maximum utilization and the pre-selected LVT standard cell utilization.

5. An integrated circuit automated logic synthesis method, characterized in that: The integrated circuit automated logic synthesis system as claimed in claim 1 comprises: Get comprehensive parameters; Performing logic synthesis on the RTL code file to be synthesized according to the synthesis parameters to obtain a preliminary synthesis result; generating a preliminary comprehensive report based on the preliminary comprehensive results; Analyze the preliminary comprehensive report to determine the optimal control parameters; Optimizing the paths in the preliminary synthesis result according to the optimization control parameters to obtain an optimized synthesis result, updating the optimization control parameters according to the optimized synthesis result, and iteratively optimizing the optimized synthesis result according to the updated optimization control parameters until a preset output condition is met to obtain a target synthesis result; Output the target comprehensive result.

6. An electronic device, characterized in that: include: Memory and processor; Wherein, the memory is used to store computer programs; The processor is used to execute the computer program to implement the integrated circuit automatic logic synthesis method according to claim 5.

7. A computer-readable storage medium, characterized in that: Used to store a computer program, wherein when the computer program is executed by a processor, the method for automatic logic synthesis of integrated circuits as claimed in claim 5 is implemented.

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