Composite power element and method for manufacturing the same

Abstract

The present invention discloses a composite power element and a manufacturing method thereof, wherein the power element comprises a substrate structure, an insulating layer, a dielectric layer, a metal oxide semiconductor field effect transistor, and a Zener diode. The metal oxide semiconductor field effect transistor is formed in a transistor forming region of the substrate structure. The Zener diode is formed in a circuit element forming region of the substrate structure and comprises a Zener diode doping structure formed on the insulating layer and covered by the dielectric layer. The Zener diode doping structure comprises a P-type doping region and an N-type doping region connected to each other. The Zener diode further comprises a Zener diode metal structure, which is formed on the dielectric layer and partially penetrates the dielectric layer to electrically connect the P-type doping region and the N-type doping region of the Zener diode doping structure. The Zener diode is configured to receive a reverse bias when the composite power element is powered on. Thereby, the process complexity of the composite power element can be simplified, and the volume of the terminal product can also be reduced.

Description

Technical Field

[0001] The invention relates to a power element, in particular to a composite power element and a manufacturing method thereof. Background Art

[0002] In existing power components, such as metal oxide semiconductor field effect transistors (MOSFETs) and bipolar junction transistors (BJTs), if other circuit elements (such as resistors or Zener diodes) need to be added to the circuit design to form an electronic circuit with specific functions, these circuit elements need to be electrically connected to the power components by welding. However, this connection method between the circuit elements and the power components will increase the complexity of product manufacturing and cannot effectively reduce the volume of the product.

[0003] Therefore, the inventors of the present invention felt that the above-mentioned deficiencies could be improved, and therefore devoted themselves to research and applied scientific theories, and finally proposed the present invention which has a reasonable design and effectively improves the above-mentioned deficiencies. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a composite power element and a manufacturing method thereof in view of the deficiencies in the prior art.

[0005] The embodiment of the present invention discloses a composite power element, comprising: a substrate structure, including a substrate layer and an epitaxial layer formed on the substrate layer; wherein the epitaxial layer is recessed with at least one groove, and the substrate structure defines a transistor forming region and a circuit element forming region adjacent to the transistor forming region along its length direction, and the groove is located in the transistor forming region; an insulating layer, extendedly formed on the epitaxial layer and on the inner wall of the groove; wherein the portion of the insulating layer located on the inner wall of the groove is defined as a groove insulating layer, which surrounds a groove, and the remaining portion of the insulating layer is defined as a covering insulating layer; a dielectric layer, formed on the insulating layer; a metal oxide semiconductor field effect transistor, located in the transistor forming region and comprising: a gate filling structure, formed in the groove of the trench insulating layer ; a base doping structure formed in the epitaxial layer and located in the surrounding area of ​​the groove; a source metal structure formed on the dielectric layer and partially penetrated through the dielectric layer to electrically connect to the base doping structure; and a drain metal structure formed on a bottom surface of the base layer; and a Zener diode located in the circuit element formation area and comprising: a Zener diode doping structure formed on the covering insulating layer and covered by the dielectric layer; wherein the Zener diode doping structure includes a P-type doping region and an N-type doping region connected to each other; and a Zener diode metal structure formed on the dielectric layer and partially penetrated through the dielectric layer to electrically connect to the P-type doping region and the N-type doping region of the Zener diode doping structure; wherein the Zener diode is configured to receive a reverse bias when the composite power element is powered on.

[0006] Preferably, in the Zener diode, the Zener diode metal structure includes two metal pins, the two metal pins are arranged at an interval from each other and both partially penetrate the dielectric layer to be electrically connected to the N-type doping region and the P-type doping region of the Zener diode doping structure, respectively; wherein, when the composite power element is energized, the potential of the metal pin connected to the P-type doping region is lower than the potential of the metal pin connected to the N-type doping region, thereby generating the reverse bias.

[0007] Preferably, the composite power element further includes: a resistor, located in the circuit element forming area and spaced apart from the Zener diode, and the resistor includes: a resistor doping structure, formed on the coating insulating layer and covered by the dielectric layer; wherein the resistor doping structure is a P-type doped semiconductor or an N-type doped semiconductor; and a resistor metal structure, formed on the dielectric layer and partially penetrates the dielectric layer to be electrically connected to the resistor doping structure, and the resistor is configured to generate a resistance when the composite power element is powered on.

[0008] Preferably, the composite power element further includes: a conventional diode, located in the circuit element forming area and spaced apart from the Zener diode, and the conventional diode includes: a conventional diode doping structure, formed on the coating insulating layer and covered by the dielectric layer; wherein the conventional diode doping structure includes a P-type doping region and an N-type doping region connected to each other; and a conventional diode metal structure, formed on the dielectric layer and partially penetrating the dielectric layer to be electrically connected to the P-type doping region and the N-type doping region of the conventional diode doping structure; wherein the conventional diode is configured to receive a forward bias; wherein the conventional diode is arranged adjacent to the metal oxide semiconductor field effect transistor.

[0009] Preferably, in the conventional diode, the conventional diode metal structure includes two metal pins, the two metal pins are arranged at an interval from each other, and the two metal pins both partially penetrate the dielectric layer to be electrically connected to the N-type doping region and the P-type doping region of the conventional diode doping structure, respectively; wherein, when the composite power element is energized, the potential of the metal pin connected to the P-type doping region is higher than the potential of the metal pin connected to the N-type doping region, thereby generating the forward bias.

[0010] Preferably, in the conventional diode, the metal pin connected to the P-type doped region is configured to be electrically connected to the gate filling structure of the metal oxide semiconductor field effect transistor through a wire, and the metal pin connected to the N-type doped region is configured to be electrically connected to the source metal structure of the metal oxide semiconductor field effect transistor through a wire.

[0011] Preferably, there are a plurality of conventional diodes, and the plurality of conventional diodes are arranged on the coating insulating layer in a manner of being connected in series with each other.

[0012] Preferably, in any two adjacent conventional diodes connected in series with each other, the metal pin of one of the conventional diodes connected to the P-type doping region is directly in contact with and electrically connected to the metal pin of the other conventional diode connected to the N-type doping region; and the conventional diode doping structure of one of the conventional diodes is not directly in contact with the conventional diode doping structure of the other conventional diode.

[0013] Preferably, among the multiple conventional diodes connected in series, the metal pin of the first conventional diode connected to the P-type doped region can be electrically connected to the gate filling structure of the metal oxide semiconductor field effect transistor through a wire, and the metal pin of the last conventional diode connected to the N-type doped region can be electrically connected to the source metal structure of the metal oxide semiconductor field effect transistor through a wire.

[0014] An embodiment of the present invention also discloses a method for manufacturing a composite power element, comprising: providing a substrate structure, which includes a substrate layer and an epitaxial layer formed on the substrate layer; wherein the epitaxial layer is recessed with at least one groove, and the substrate structure defines a transistor forming region and a circuit element forming region adjacent to the transistor forming region along its length direction, and the groove is located in the transistor forming region; extendingly forming an insulating layer on the epitaxial layer and the inner wall of the groove; wherein the portion of the insulating layer located on the inner wall of the groove is defined as a trench insulating layer, which surrounds a groove, and the remaining portion of the insulating layer is defined as a covering insulating layer; forming a dielectric layer on the insulating layer; forming a metal oxide semiconductor field effect transistor in the transistor forming region of the substrate structure; wherein the metal oxide semiconductor field effect transistor includes: a gate filling structure, a base doping structure, a source metal structure, and a drain metal structure ; wherein the gate filling structure is formed in the groove of the trench insulating layer; the base doping structure is formed in the epitaxial layer and is located in the surrounding area of ​​the trench; the source metal structure is formed on the dielectric layer and partially penetrates the dielectric layer to electrically connect the base doping structure; and the drain metal structure is formed on a bottom surface of the base layer; and a Zener diode is formed in the circuit element formation area of ​​the base structure; wherein the Zener diode includes: a Zener diode doping structure and a Zener diode metal structure; wherein the Zener diode doping structure is formed on the capping insulating layer and covered by the dielectric layer, and the Zener diode doping structure includes a P-type doping region and an N-type doping region connected to each other; the Zener diode metal structure is formed on the dielectric layer and partially penetrates the dielectric layer to electrically connect the P-type doping region and the N-type doping region of the Zener diode doping structure.

[0015] The beneficial effect of the present invention is that the composite power element and the manufacturing method thereof provided by the present invention can form the required power element by integrating the formation of different electronic components (such as Zener diodes, resistors, conventional diodes) into the process of metal oxide semi-conductor field effect transistors (especially the process after depositing polysilicon), without adding additional processes, thereby simplifying the process complexity and reducing the volume of the terminal product.

[0016] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, such description and drawings are only used to illustrate the present invention and are not intended to limit the protection scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figures 1A to 1HFIG. 1 is a schematic flow chart of a method for manufacturing a composite power device according to a first embodiment of the present invention.

[0018] Figure 2 FIG. 1 is a cross-sectional schematic diagram of a composite power device according to a first embodiment of the present invention (indicating an equivalent circuit corresponding to the device structure).

[0019] Figure 3 FIG. 4 is an equivalent circuit diagram of a composite power element according to a first embodiment of the present invention.

[0020] Figure 4 FIG. 4 is a partial schematic diagram of a composite power component according to a second embodiment of the present invention.

[0021] Figure 5 FIG. 4 is an equivalent circuit diagram of a composite power element according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following is an explanation of the disclosed embodiments of the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual sizes. The following embodiments will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention.

[0023] It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0024] [First embodiment]

[0025] See also Figures 1A to 1H , Figure 2 and Figure 3 As shown, the first embodiment of the present invention provides a method for manufacturing a composite power device 100. The method for manufacturing a composite power device includes steps S110 to S180. Figures 1A to 1H is a schematic diagram of a manufacturing method of a composite power element according to a first embodiment of the present invention, Figure 2 is a cross-sectional schematic diagram of a composite power element according to a first embodiment of the present invention (indicating an equivalent circuit corresponding to the element structure), and Figure 3FIG. 4 is an equivalent circuit diagram of a composite power element according to a first embodiment of the present invention.

[0026] It must be noted that the sequence of the steps described in this embodiment and the actual operation method can be adjusted according to needs and are not limited to those described in this embodiment.

[0027] The composite power device 100 of the present embodiment is a power device based on a metal-oxide-semiconductor field-effect transistor (MOSFET). In other words, the composite power device 100 of the present embodiment is a power device improved based on a metal-oxide-semiconductor field-effect transistor. Furthermore, the composite power device 100 of the present embodiment can be applied to a high voltage regulator, for example, but the present invention is not limited thereto.

[0028] This embodiment first describes the manufacturing method of the composite power element. For ease of understanding, this embodiment takes a unit area of ​​the manufacturing method of the composite power element as an example and describes it with a cross-sectional view. Please refer to the drawings corresponding to each step and refer to the drawings of other steps as needed. The specific steps of the manufacturing method of the composite power element are described as follows.

[0029] like Figure 1A As shown, the step S110 includes: providing a substrate structure 1. The substrate structure 1 includes: a substrate layer 11 and an epitaxial layer 12 formed on the substrate layer 11, and two surfaces of the substrate structure 1 located on opposite sides are respectively defined as a top surface 101 and a bottom surface 102. More specifically, the side surface of the epitaxial layer 12 opposite to the substrate layer 11 is the top surface 101, and the side surface of the substrate layer 11 opposite to the epitaxial layer 12 is the bottom surface 102.

[0030] The material of the base layer 11 may be, for example, an N+ doped semiconductor or a P+ doped semiconductor. The epitaxial layer 12 may be, for example, formed on the base layer 11 by an epitaxial process, and the conductive form of the epitaxial layer 12 may be, for example, the same as the conductive form of the base layer 11 (e.g., N+ doping or P+ doping).

[0031] In this embodiment, the substrate layer 11 is an N+ type doped semiconductor (i.e., N+Substrate), and the epitaxial layer 12 is an N-type doped semiconductor (i.e., N-EPI). The doping concentration of the substrate layer 11 is higher than the doping concentration of the epitaxial layer 12, that is, the substrate layer 11 is a heavily doped region, and the epitaxial layer 12 is a lightly doped region, but the present invention is not limited thereto.

[0032] Specifically, the substrate structure 1 defines a transistor forming region A and a circuit element forming region B adjacent to the transistor forming region A along its length direction D. The circuit element forming region B can be further divided into a zener diode forming region B1, a resistor forming region B2, and a normal diode forming region B3.

[0033] In this embodiment, the resistor forming region B2 is located between the Zener diode forming region B1 and the conventional diode forming region B3, the Zener diode forming region B1 is farther away from the transistor forming region A relative to the resistor forming region B2, and the conventional diode forming region B3 is closer to the transistor forming region A relative to the resistor forming region B2, but the present invention is not limited to this.

[0034] like Figure 1B As shown, the step S120 includes: forming a plurality of grooves 13 in a recessed manner on the epitaxial layer 12, and the plurality of grooves 13 are all located in the transistor formation region A. The plurality of grooves 13 can be formed, for example, by etching. More specifically, the plurality of grooves 13 are recessed at intervals along the length direction D on the side surface of the epitaxial layer 12 opposite to the base layer 11, and the bottoms of the plurality of grooves 13 are not in contact with the base layer 11, but are spaced a distance from the base layer 11. From another perspective, the plurality of grooves 13 are recessed from the top surface 101 of the substrate structure 1, and are not in contact with the base layer 11 of the substrate structure 1.

[0035] In the present embodiment, a groove depth of each of the grooves 13 is generally between 0.5 micrometers and 3 micrometers, and preferably between 1 micrometer and 2 micrometers, but the present invention is not limited thereto.

[0036] It should be noted that the above-mentioned multiple grooves 13 are described from the perspective of cross-section views for grooves 13 at different locations in the epitaxial layer 12. From a holistic perspective, the grooves 13 may be connected or separated, and the present invention is not limited thereto.

[0037] like Figure 1C As shown, the step S130 includes: extendingly forming an insulating layer 2 (or oxide layer) on a surface of the epitaxial layer 12 opposite to the base layer 11 (that is, the top surface 101 of the substrate structure 1) and on the inner walls of the plurality of trenches 13. The insulating layer 2 can be formed, for example, by a low temperature oxide deposition (LTO deposition) process or a thermal oxidation process, but the present invention is not limited thereto.

[0038] In this embodiment, the thickness of the insulating layer 2 is approximately between 5 nanometers and 100 nanometers, and the material of the insulating layer 2 may be, for example, a silicon compound. For example, the material of the insulating layer 2 may be, for example, silicon dioxide, but the present invention is not limited thereto.

[0039] Furthermore, the portion of the insulating layer 2 located on the inner wall of each trench 13 is defined as a trench insulating layer 21 (or trench oxide layer), and each trench insulating layer 21 surrounds a groove 22. In other words, a plurality of trench insulating layers 21 are formed on the inner walls of a plurality of trenches 13, and a plurality of trench insulating layers 21 surround a plurality of grooves 22. In addition, the remaining portion of the insulating layer 2 (that is, the portion of the insulating layer 2 located on the top surface 101 of the epitaxial layer 12) is defined as a capping insulating layer 23 (or capping oxide layer).

[0040] The plurality of trench insulating layers 21 are all located in the transistor forming region A, and the cap insulating layer 23 is extendedly located in the transistor forming region A and the circuit element forming region B.

[0041] like Figure 1DAs shown, the step S140 includes: forming a polysilicon material M on a surface of the insulating layer 2 opposite to the epitaxial layer 12, so that the polysilicon material M covers the capping insulating layer 23 and fills the plurality of grooves 22 surrounded by the plurality of trench insulating layers 21. The polysilicon material M can be formed, for example, by a low pressure chemical vapor deposition (LPCVD) process of silane (SiH4), but the present invention is not limited thereto.

[0042] In the present embodiment, the polysilicon material M is deposited on the insulating layer 2 to a certain thickness, so that the outer surface of the polysilicon material M (that is, the surface of the polysilicon material M opposite to the base layer 11) is a flat surface. More specifically, the outer surface of the polysilicon material M located above the plurality of grooves 22 and above the covering insulating layer 23 is substantially flush with each other, but the present invention is not limited thereto.

[0043] like Figure 1E As shown, the step S150 includes: performing a lithography imaging operation and an etching operation on the polysilicon material M to remove a portion of the polysilicon material M, thereby forming a plurality of polysilicon filled structures M1 (poly-silicon filled structures) in the plurality of grooves 22 surrounded by the plurality of trench insulating layers 21, and forming a plurality of polysilicon block structures M2 (poly-silicon block structures) on the coating insulating layer 23.

[0044] In this embodiment, the polysilicon filling structures M1 are respectively formed in the grooves 22 surrounded by the trench insulating layers 21. Therefore, the polysilicon filling structures M1 are the same as the trench insulating layers 21, and are both located in the transistor forming region A.

[0045] Furthermore, after the etching operation, the exposed surfaces of the polysilicon filling structures M1 (ie, Figure 1E The top surface of the polysilicon filling structure M1 in the embodiment of the present invention is lower than the outer surface of the capping insulating layer 23 (that is, Figure 1E The surface of the coating insulating layer 23 opposite to the epitaxial layer 12 is used as the cover), but the present invention is not limited thereto.

[0046] Furthermore, the multiple polysilicon block structures M2 are all formed on the surface of the side of the covering insulating layer 23 opposite to the epitaxial layer 12, and the multiple polysilicon block structures M2 are all located in the above-mentioned circuit element formation area B so as to be made into different circuit elements (such as: Zener diodes, resistors, and conventional diodes, etc.) in the subsequent manufacturing process.

[0047] Specifically, the plurality of polysilicon block structures M2 are arranged at intervals on the capping insulating layer 23. In the present embodiment, the number of the plurality of polysilicon block structures M2 is three, and the three polysilicon block structures M2 are respectively located in the Zener diode forming region B1, the resistor forming region B2, and the conventional diode forming region B3 of the circuit element forming region B.

[0048] In addition, it is worth mentioning that in the present embodiment, the raw material M of the polysilicon filling structure M1 and the polysilicon block structure M2 is formed in the same polysilicon deposition process, but the present invention is not limited thereto. The raw material M of the polysilicon filling structure M1 and the polysilicon block structure M2 can also be formed by multiple polysilicon deposition processes (e.g., 2, 3, or more) according to process requirements.

[0049] like Figure 1F As shown, the step S160 includes: performing an ion implantation process so that the multiple polysilicon filling structures M1 located in the transistor forming region A are respectively formed into multiple gate filling structures 31 (or doped polysilicon filling structures), the portion of the epitaxial layer 12 located between any two adjacent trenches 13 is formed into a matrix doped structure 32 (matrix doped structure), the polysilicon block structure M2 located in the Zener diode forming region B1 is formed into a Zener diode doped structure 41, the polysilicon block structure M2 located in the resistor forming region B2 is formed into a resistor doped structure 51, and the polysilicon block structure M2 located in the conventional diode forming region B3 is formed into a conventional diode doped structure 61. It is worth mentioning that in this embodiment, in order to perform different doping (such as P-type doping or N-type doping) on ​​the polysilicon material and the epitaxial layer, the ion implantation process can, for example, include multiple ion implantation procedures (such as P-type doping ion implantation procedures and N-type doping ion implantation procedures).

[0050] Furthermore, each of the gate filling structures 31 can be, for example, one of a P-type doped semiconductor and an N-type doped semiconductor, which is not limited in the present invention.

[0051] Each of the base doping structures 32 includes a P-type doping region 32P and an N-type doping region 32N formed on the P-type doping region 32P. That is, in each of the base doping structures 32, the N-type doping region 32N and the P-type doping region 32P are stacked one above the other. The P-type doping region 32P is located at the lower side and abuts against the epitaxial layer 12, and the N-type doping region 32N is located at the upper side and abuts against the capping insulating layer 23. It is worth mentioning that the conductive form of the P-type doping region 32P is different from the conductive form of the above-mentioned base layer 11 (N+ type doped semiconductor) and also different from the conductive form of the above-mentioned epitaxial layer 12 (N- type doped semiconductor). That is to say, the multiple P-type doping regions 32P of the present embodiment are P-type doped semiconductors, and the implanted ion species can be, for example, boron ions (B+), but the present invention is not limited thereto.

[0052] The Zener diode doping structure 41 includes a P-type doping region 41P and a P-type doping region 41P located on one side (eg, Figure 1F In other words, in the Zener diode doping structure 41, the N-type doping region 41N and the P-type doping region 41P are arranged left and right and connected to each other. Furthermore, the N-type doping region 41N and the P-type doping region 41P are both formed on the covering insulating layer 23 and contact the covering insulating layer 23.

[0053] The resistor doping structure 51 may be, for example, one of a P-type doped semiconductor and an N-type doped semiconductor. In this embodiment, the P-type doped semiconductor is preferred, but the present invention is not limited thereto. Furthermore, the doping concentration of the resistor doping structure 51 is lower than the doping concentration of the Zener diode doping structure 41 or the doping concentration of the conventional diode doping structure 61 to produce a resistor effect.

[0054] The conventional diode doping structure 61 is similar to the Zener diode doping structure 41 and includes a P-type doping region 61P and a P-type doping region 61P located on one side (eg, Figure 1F In other words, in the conventional diode doping structure 61, the N-type doping region 61N and the P-type doping region 61P are arranged left and right and connected to each other. Furthermore, the N-type doping region 61N and the P-type doping region 61P are both formed on the capping insulating layer 23 and contact the capping insulating layer 23.

[0055] It should be noted that the ion types used in the ion implantation process described herein may be, for example, boron ions (B + ), zinc ion (Zn 2+ ), fluoride ion (F - ), nitrogen ions (N- ), oxygen ions (O 2- ), carbon ions (C 4+ ), Argon ions (Ar + ), phosphorus ion (P + ), arsenic ions (As + ), or antimony ions (Sb 2+ ).

[0056] like Figure 1G As shown, the step S170 includes: forming a dielectric layer 7 (inter layer dielectric, ILD) on the substrate structure 1, so that the insulating layer 2, multiple gate filling structures 31, the base doping structure 32, the Zener diode doping structure 41, the resistor doping structure 51, and the conventional diode doping structure 61 are covered by the dielectric layer 7.

[0057] The dielectric layer 7 may be formed by a chemical vapor deposition process, but the present invention is not limited thereto. For example, the dielectric layer 7 may also be formed by a physical vapor deposition process or other suitable deposition processes. Furthermore, the material of the dielectric layer 7 may be a silicon compound or other dielectric material.

[0058] Furthermore, the outer surface of the dielectric layer 7 may be planarized by, for example, a chemical mechanical polishing (CMP) process, but the present invention is not limited thereto.

[0059] like Figure 1H As shown, the step S180 includes: performing a metallization process to form a source metal structure 33 (source metal), a Zener diode metal structure 42, a resistor metal structure 52, and a conventional diode metal structure 62 on the dielectric layer 7, and forming a drain metal structure 34 (drain metal) on the bottom surface 102 of the substrate structure 1. It should be noted that the "metal structure" mentioned in this article can be formed by deposition, and the "metal structure" can be an integrated structure formed by aluminum / silicon / copper alloy, but in practical applications, it is not limited to this.

[0060] The source metal structure 33 is located in the transistor forming region A. The source metal structure 33 is formed on a surface of the dielectric layer 7 opposite to the base layer 11 and partially penetrates the dielectric layer 7 to be electrically connected to at least one of the plurality of base doping structures 32 .

[0061] In this embodiment, the source metal structure 33 includes: a source metal conductive part 331 and two source metal contact plugs 332 connected to the source metal conductive part 331. The source metal conductive part 331 is formed on a surface of the dielectric layer 7 opposite to the base layer 11. The two source metal contact plugs 332 are arranged at intervals from each other and penetrate the dielectric layer 7 respectively, so that the source metal conductive part 331 can be electrically connected to two adjacent base doping structures 32 among the multiple base doping structures 32 through the two source metal contact plugs 332.

[0062] In addition, the width of each source metal contact plug 332 is smaller than the width of the base doping structure 32 to which it is connected, and each source metal contact plug 332 passes through the N-type doping region 32N in the corresponding base doping structure 32 and partially extends into the P-type doping region 32P. Thus, the two source metal contact plugs 332 are set at the same potential compared to the two base doping structures 32 to which they are electrically connected.

[0063] The drain metal structure 34 is formed on the bottom surface 102 of the substrate structure 1. In other words, the drain metal structure 34 is formed on the surface of the base layer 11 opposite to the epitaxial layer 12. In this embodiment, the drain metal structure 34 fully covers the bottom surface 102 of the substrate structure 1, but the present invention is not limited thereto.

[0064] According to the above configuration, if Figure 2 As shown, the source metal structure 33 can be used to electrically connect a source wire 33L to define a source S (source) of the metal oxide semi-conductor field effect transistor. The drain metal structure 34 can be used to electrically connect a drain wire 34L to define a drain D (drain) of the metal oxide semi-conductor field effect transistor. Furthermore, one of the gate filling structures 31 (such as Figure 2 The rightmost gate filling structure in the figure can be used to electrically connect a gate wire 31L to define the gate G (gate) of the MOSFET. The above-mentioned components located in the transistor forming area A (such as: source metal structure 33, drain metal structure 34, gate filling structure 31, etc.) can form a MOSFET 3, and its equivalent circuit is as follows: Figure 3 shown.

[0065] Please continue reading Figure 1H As shown, the Zener diode metal structure 42 , the resistor metal structure 52 , and the conventional diode metal structure 62 are all located in the circuit element forming region B.

[0066] The Zener diode metal structure 42 is located in the Zener diode forming region B1, and the Zener diode metal structure 42 is formed on a surface of the dielectric layer 7 opposite to the base layer 11, and partially penetrates the dielectric layer 7 to be electrically connected to the Zener diode doping structure 41. The Zener diode metal structure 42 and the Zener diode doping structure 41 can be matched with each other to form a Zener diode 4 (Vz). The Zener diode 4 is configured to receive a reverse bias, and the Zener diode 4 can withstand a voltage between 5 volts and 6 volts.

[0067] In this embodiment, the Zener diode metal structure 42 includes two metal pins 421. The two metal pins 421 of the Zener diode metal structure 42 are spaced apart from each other and partially penetrate the dielectric layer 7 to be electrically connected to the N-type doping region 41N and the P-type doping region 41P of the Zener diode doping structure 41, respectively, so as to form the Zener diode 4. Among them, in the Zener diode 4, the potential of the metal pin 421 connected to the P-type doping region 41P is "lower" than the potential of the metal pin 421 connected to the N-type doping region 41N, so as to generate a "reverse bias" when the power element is powered on.

[0068] The resistor metal structure 52 is located in the resistor forming region B2, and is formed on a surface of the dielectric layer 7 opposite to the base layer 11, and partially penetrates the dielectric layer 7 to be electrically connected to the resistor doping structure 51. The resistor metal structure 52 and the resistor doping structure 51 can be matched with each other to form a resistor 5 (resistor, R).

[0069] In this embodiment, the resistor metal structure 52 includes two metal pins 521. The two metal pins 521 of the resistor metal structure 52 are spaced apart from each other and partially penetrate the dielectric layer 7 to be electrically connected to the resistor doping structure 51 (e.g., P-type doped semiconductor). The doping concentration of the resistor doping structure 51 is lower than the doping concentration of the Zener diode doping structure 41 and also lower than the doping concentration of the conventional diode doping structure 61, so as to generate a resistor effect when the power element is powered on.

[0070] The normal diode metal structure 62 is located in the normal diode forming region B3, and the normal diode metal structure 62 is formed on the surface of the dielectric layer 7 opposite to the base layer 11, and partially penetrates the dielectric layer 7 to be electrically connected to the normal diode doping structure 61. The normal diode metal structure 62 and the normal diode doping structure 61 can be matched with each other to form a normal diode 6 (VD ). The conventional diode 6 is configured to receive a forward bias voltage, and the conventional diode 6 can withstand a voltage between 0 volts and 0.7 volts.

[0071] In this embodiment, the conventional diode metal structure 62 includes two metal pins 621. The two metal pins 621 of the conventional diode metal structure 62 are spaced apart from each other and partially penetrate the dielectric layer 7 to be electrically connected to the N-type doping region 61N and the P-type doping region 61P of the conventional diode doping structure 61, respectively, so as to form the conventional diode 6. In the conventional diode 6, the potential of the metal pin 621 connected to the P-type doping region 61P is "higher" than the potential of the metal pin 621 connected to the N-type doping region 61N, so as to generate a "forward bias" when the power element is powered on.

[0072] It is worth mentioning that in the present embodiment, in the conventional diode 6, the metal pin 621 connected to the P-type doping region 61P can be electrically connected to one of the gate filling structures 31 (such as Figure 2 Furthermore, the metal pin 621 connected to the N-type doping region 61N can be electrically connected to the source metal structure 33 of the MOSFET 3 through a wire (not shown), but the present invention is not limited thereto.

[0073] It is worth mentioning that in this embodiment, the N-type doping region 32N of the substrate doping structure 32, the N-type doping region 41N of the Zener diode 4, and the N-type doping region 61N of the conventional diode are completed in the same ion implantation process, but the present invention is not limited thereto.

[0074] After implementing the above steps S110 to S180, the following steps can be completed: Figure 1H and Figure 2 The composite power device 100 (or trench power device) shown in FIG. 1 is an equivalent circuit diagram of the composite power device 100 of this embodiment. Figure 3 It should be emphasized that in practical applications, each step may be replaced by a reasonable variation.

[0075] Furthermore, it should be emphasized that the above steps are described from a cross-sectional view perspective, and the possibility of implementing the present invention with various design layouts is not excluded under the premise of complying with the above steps. In other words, if viewed from a top view, the composite power device 100 of this embodiment can have different design layout types.

[0076] According to the above configuration, the manufacturing method of the composite power element provided in the embodiment of the present invention can integrate the formation of different electronic components (such as Zener diodes, resistors, conventional diodes) into the process of metal oxide semi-conductor field effect transistors (especially the process after depositing polysilicon) to form the required power elements without adding additional processes, thereby simplifying the process complexity.

[0077] The above is a description of the manufacturing method of the composite power element of the embodiment of the present invention, and the specific structure of the composite power element of this embodiment is described below. It must be noted that although the composite power element of this embodiment is manufactured by the above manufacturing method, the present invention is not limited thereto. In other words, the composite power element of the present invention can also be manufactured by other manufacturing methods.

[0078] like Figure 1H Please match with Figure 2 and Figure 3 The present embodiment further discloses a composite power device 100, which comprises: a substrate structure 1, an insulating layer 2, a dielectric layer 7, a metal oxide semi-conductor field effect transistor 3 (MOSFET), a Zener diode 4 (V Z ), a resistor 5 (R), and a conventional diode 6 (V D ).

[0079] The substrate structure 1 includes a base layer 11 and an epitaxial layer 12 formed on the base layer 11. The epitaxial layer 12 is recessed with at least one groove 13. The substrate structure 1 defines a transistor forming region A and a circuit element forming region B adjacent to the transistor forming region A along its length direction D, and the groove 13 is located in the transistor forming region A.

[0080] The insulating layer 2 is extendedly formed on the epitaxial layer 12 and the inner wall of the trench 13. The portion of the insulating layer 2 located on the inner wall of the trench 13 is defined as a trench insulating layer 21, which surrounds a groove 22, and the remaining portion of the insulating layer 2 is defined as a covering insulating layer 23. Furthermore, the dielectric layer 7 is formed on the insulating layer 2.

[0081] The MOSFET 3 is located in the transistor formation region A and includes: a gate filling structure 31, a base doping structure 32, a source metal structure 33, and a drain metal structure 34. The gate filling structure 31 is formed in the groove 22 of the trench insulating layer 21. The base doping structure 32 is formed in the epitaxial layer 12 and is located in the surrounding area of ​​the trench 13. The source metal structure 33 is formed on the dielectric layer 7 and partially penetrates the dielectric layer 7 to electrically connect the base doping structure 32. The drain metal structure 34 is formed on a bottom surface of the base layer 11.

[0082] The Zener diode 4 is located in the circuit element forming area B and includes: a Zener diode doping structure 41 and a Zener diode metal structure 42. The Zener diode doping structure 41 is formed on the capping insulating layer 23 and is covered by the dielectric layer 7. The Zener diode doping structure 41 includes a P-type doping region 41P and an N-type doping region 41N connected to each other. The Zener diode metal structure 42 is formed on the dielectric layer 7 and partially penetrates the dielectric layer 7 to be electrically connected to the P-type doping region 41P and the N-type doping region 41N of the Zener diode doping structure 41. The Zener diode 4 is configured to receive a reverse bias when the composite power device 100 is powered on.

[0083] The resistor 5 is located in the circuit element forming area B and is spaced apart from the Zener diode 4, and the resistor 5 includes: a resistor doping structure 51 and a resistor metal structure 52. The resistor doping structure 51 is formed on the coating insulating layer 23 and is covered by the dielectric layer 7. The resistor doping structure 51 is a P-type doped semiconductor or an N-type doped semiconductor. The resistor metal structure 52 is formed on the dielectric layer and partially penetrates the dielectric layer 7 to be electrically connected to the resistor doping structure 51, and the resistor 5 is configured to generate a resistance when the composite power device 100 is powered on.

[0084] The conventional diode 6 is located in the circuit element forming area B and is spaced apart from the Zener diode 4, and the conventional diode 6 includes: a conventional diode doping structure 61 and a conventional diode metal structure 62. The conventional diode doping structure 61 is formed on the capping insulating layer 23 and is covered by the dielectric layer 7. The conventional diode doping structure 61 includes a P-type doping region 61P and an N-type doping region 61N connected to each other. The conventional diode metal structure 62 is formed on the dielectric layer 7 and partially penetrates the dielectric layer 7 to be electrically connected to the P-type doping region 61P and the N-type doping region 61N of the conventional diode doping structure 61. The conventional diode is configured to receive a forward bias. The conventional diode 6 is disposed adjacent to the above-mentioned metal oxide semiconductor field effect transistor 3.

[0085] [Second embodiment]

[0086] See also Figure 4 and Figure 5 As shown, the second embodiment of the present invention also provides a composite power device 100 ′. Figure 4 is a partial schematic diagram of a composite power element according to a second embodiment of the present invention, and Figure 5 FIG. 4 is an equivalent circuit diagram of a composite power element according to a second embodiment of the present invention.

[0087] The structure design of the composite power element 100' in the second embodiment of the present invention is substantially the same as that of the first embodiment, except that the composite power element 100' in this embodiment has a plurality of conventional diodes 6 (V D1 To V DN ).

[0088] like Figure 4 More specifically, in this embodiment, the number of the conventional diodes 6 is multiple, and the multiple conventional diodes 6 (V D1 To V DN ) are arranged in series on the cover insulating layer 23 and are located in the conventional diode forming region B3 of the circuit element forming region B. The number of the plurality of conventional diodes 6 can be, for example, two or more.

[0089] More specifically, the plurality of conventional diodes 6 connected in series are arranged in an alternating manner of "N-type doping region / P-type doping region / N-type doping region / P-type doping region ..." Among any two adjacent conventional diodes 6 connected in series, the metal pin 621 of one of the conventional diodes 6 connected to the P-type doping region 61P is directly in contact with and electrically connected to the metal pin 621 of another conventional diode 6 connected to the N-type doping region 61N. Furthermore, the conventional diode doping structure 61 of one of the conventional diodes 6 is not directly in contact with the conventional diode doping structure 61 of another conventional diode 6.

[0090] Further, if Figure 4 As shown, among the plurality of conventional diodes 6 connected in series, the first conventional diode V D1 (like Figure 4 The rightmost conventional diode V D1 ) connected to the P-type doped region 61P can be electrically connected to one of the gate filling structures 31 (such as Figure 2 Furthermore, the Nth conventional diode V DN (like Figure 4 The metal pin 621 of the leftmost conventional diode 6 connected to the N-type doped region 61N can be electrically connected to the source metal structure 33 of the MOSFET 3 through a wire (not shown), but the present invention is not limited thereto.

[0091] like Figure 5 As shown, since the composite power element 100' of this embodiment has a plurality of conventional diodes 6 (V D1 To V DN ), so the number of conventional diodes 6 can be adjusted to change V GS , and then controlling the driving voltage of the composite power element 100 ′ to achieve the feasibility of driving various power field effect transistors Power MOSFET.

[0092] Based on this, the concept of this structural design can arbitrarily integrate various power field effect transistors Power MOSFET with different voltages / currents according to the application requirements of the terminal product. Among them, the output voltage can be, for example, V OUT =V G -V D =V Z -(V D1 +V D2 +…V DN ).

[0093] [Beneficial Effects of Embodiments]

[0094] The beneficial effect of the present invention is that the

[0095] The provided method for manufacturing a composite power element can form the required power element by integrating the formation of different electronic components (such as Zener diodes, resistors, conventional diodes) into the process of metal oxide semi-conductor field effect transistors (especially the process after depositing polysilicon). It does not require adding additional processes, thereby simplifying the process complexity and reducing the size of the terminal product.

[0096] Furthermore, since the composite power element of this embodiment can be designed with a plurality of conventional diodes (V D1 To V DN ), so the number of conventional diodes can be adjusted to change V GS , and then control the driving voltage of the composite power element to achieve the feasibility of driving various power field effect transistors Power MOSFET.

[0097] In addition, the structural design of the composite power device of this embodiment can reduce the number of electronic components required to be placed on the system circuit board because some of the electronic components are integrated into the integrated device manufacturing process of the present invention, thereby reducing the size of the terminal product.

[0098] The contents disclosed above are only preferred feasible embodiments of the present invention, and are not intended to limit the scope of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention's specification and drawings are included in the scope of the present invention.

Claims

1. A composite power element, characterized in that: The composite power element comprises: A substrate structure, comprising a substrate layer and an epitaxial layer formed on the substrate layer; wherein the epitaxial layer is recessed with at least one groove, the substrate structure is defined along its length direction with a transistor forming region and a circuit element forming region adjacent to the transistor forming region, and the groove is located in the transistor forming region; an insulating layer, extendedly formed on the epitaxial layer and the inner wall of the trench; wherein the portion of the insulating layer located on the inner wall of the trench is defined as a trench insulating layer, which surrounds a groove, and the remaining portion of the insulating layer is defined as a covering insulating layer; a dielectric layer formed on the insulating layer; A metal oxide semi-conductor field effect transistor is located in the transistor forming region and comprises: a gate filling structure formed in the groove of the trench insulating layer; a substrate doping structure formed in the epitaxial layer and located in the surrounding area of ​​the trench; wherein the substrate doping structure comprises a P-type doping region and an N-type doping region stacked up and down, the P-type doping region is located at the lower side and abuts against the epitaxial layer, and the N-type doping region is located at the upper side and abuts against the capping insulating layer; a source metal structure formed on the dielectric layer and partially penetrates the dielectric layer to electrically connect to the base doping structure; wherein the source metal structure comprises: a source metal conductive portion and two source metal contact plugs connected to the source metal conductive portion, the source metal conductive portion is formed on the dielectric layer, the two source metal contact plugs are arranged at intervals from each other and respectively penetrate the dielectric layer to electrically connect to the base doping structure, wherein each source metal contact plug passes through the N-type doping region of the base doping structure and partially extends into the P-type doping region of the base doping structure; and a drain metal structure formed on a bottom surface of the base layer; and a Zener diode located in the circuit element forming region and comprising: a Zener diode doping structure formed on the capping insulating layer and covered by the dielectric layer; wherein the Zener diode doping structure includes a P-type doping region and an N-type doping region connected to each other; and a Zener diode metal structure formed on the dielectric layer and partially penetrating the dielectric layer to be electrically connected to the P-type doping region and the N-type doping region of the Zener diode doping structure; The Zener diode metal structure includes two metal pins spaced apart from each other, both of which penetrate the dielectric layer and partially extend into the N-type doping region and the P-type doping region of the Zener diode doping structure, respectively, wherein the Zener diode metal structure is spaced apart from the source metal structure; The Zener diode is configured to receive a reverse bias voltage when the composite power element is powered on.

2. The composite power element according to claim 1, characterized in that: When the composite power element is powered on, the potential of the metal pin connected to the P-type doping region is lower than the potential of the metal pin connected to the N-type doping region, thereby generating the reverse bias.

3. The composite power element according to claim 1, characterized in that: The composite power element further comprises: a resistor located in the circuit element forming region and spaced apart from the Zener diode, and comprising: a resistor doping structure formed on the capping insulating layer and covered by the dielectric layer; Wherein, the resistor doping structure is a P-type doped semiconductor or an N-type doped semiconductor; and A resistor metal structure is formed on the dielectric layer and partially penetrates the dielectric layer to be electrically connected to the resistor doping structure. The resistor is configured to generate a resistance when the composite power element is powered on.

4. The composite power element according to claim 3, characterized in that: The composite power element further comprises: a conventional diode located in the circuit element forming region and spaced apart from the Zener diode, and comprising: a conventional diode doping structure formed on the capping insulating layer and covered by the dielectric layer; wherein the conventional diode doping structure comprises a P-type doping region and an N-type doping region connected to each other; and a conventional diode metal structure formed on the dielectric layer and partially penetrating the dielectric layer to electrically connect the P-type doped region and the N-type doped region of the conventional diode doping structure; wherein the conventional diode is configured to receive a forward bias; Wherein, the conventional diode is arranged adjacent to the metal oxide semi-conductor field effect transistor.

5. The composite power element according to claim 4, characterized in that: In the conventional diode, the conventional diode metal structure includes two metal pins, the two metal pins are arranged at an interval from each other, and the two metal pins both partially penetrate the dielectric layer to be electrically connected to the N-type doping region and the P-type doping region of the conventional diode doping structure respectively; wherein, when the composite power element is energized, the potential of the metal pin connected to the P-type doping region is higher than the potential of the metal pin connected to the N-type doping region, thereby generating the forward bias.

6. The composite power element according to claim 4, characterized in that: In the conventional diode, the metal pin connected to the P-type doped region is configured to be electrically connected to the gate filling structure of the metal oxide semiconductor field effect transistor through a wire, and the metal pin connected to the N-type doped region is configured to be electrically connected to the source metal structure of the metal oxide semiconductor field effect transistor through a wire.

7. The composite power element according to claim 4, characterized in that: The number of the conventional diodes is multiple, and the multiple conventional diodes are arranged on the covering insulating layer in a manner of being connected in series.

8. The composite power element according to claim 7, characterized in that: In any two adjacent conventional diodes connected in series, the metal pin of one of the conventional diodes connected to the P-type doping region is directly in contact with and electrically connected to the metal pin of the other conventional diode connected to the N-type doping region; and the conventional diode doping structure of one of the conventional diodes is not directly in contact with the conventional diode doping structure of the other conventional diode.

9. The composite power device according to claim 7, characterized in that: Among the multiple conventional diodes connected in series, the metal pin of the first conventional diode connected to the P-type doped region can be electrically connected to the gate filling structure of the metal oxide semiconductor field effect transistor through a wire, and the metal pin of the last conventional diode connected to the N-type doped region can be electrically connected to the source metal structure of the metal oxide semiconductor field effect transistor through a wire.

10. A method for manufacturing a composite power element, characterized in that: The manufacturing method of the composite power element comprises: A substrate structure is provided, comprising a substrate layer and an epitaxial layer formed on the substrate layer; wherein the epitaxial layer is recessed with at least one groove, the substrate structure is defined along its length direction with a transistor forming region and a circuit element forming region adjacent to the transistor forming region, and the groove is located in the transistor forming region; Extendingly forming an insulating layer on the epitaxial layer and on the inner wall of the trench; wherein the portion of the insulating layer located on the inner wall of the trench is defined as a trench insulating layer, which surrounds a groove, and the remaining portion of the insulating layer is defined as a covering insulating layer; forming a dielectric layer on the insulating layer; A metal oxide semiconductor field effect transistor is formed in the transistor forming area of ​​the substrate structure; wherein the metal oxide semiconductor field effect transistor includes: a gate filling structure, a base doping structure, a source metal structure, and a drain metal structure; wherein the gate filling structure is formed in the groove of the trench insulating layer; the base doping structure is formed in the epitaxial layer and is located in the surrounding area of ​​the trench; wherein the base doping structure includes a P-type doping region and an N-type doping region stacked up and down, the P-type doping region is located at the lower side and abuts against the epitaxial layer, and the N-type doping region is located at the upper side and abuts against the covering insulating layer; the source metal The source metal structure is formed on the dielectric layer and partially penetrates the dielectric layer to be electrically connected to the base doping structure; wherein the source metal structure comprises: a source metal conductive part and two source metal contact plugs connected to the source metal conductive part, the source metal conductive part is formed on the dielectric layer, the two source metal contact plugs are arranged at intervals from each other and respectively penetrate the dielectric layer to be electrically connected to the base doping structure, wherein each source metal contact plug passes through the N-type doping region of the base doping structure and partially extends into the P-type doping region; and the drain metal structure is formed on a bottom surface of the base layer; and A Zener diode is formed in the circuit element forming region of the substrate structure; wherein the Zener diode comprises: a Zener diode doping structure and a Zener diode metal structure; wherein the Zener diode doping structure is formed on the capping insulating layer and covered by the dielectric layer, and the Zener diode doping structure comprises a P-type doping region and an N-type doping region connected to each other; the Zener diode metal structure is formed on the dielectric layer and partially penetrates the dielectric layer to be electrically connected to the P-type doping region and the N-type doping region of the Zener diode doping structure, and the Zener diode is configured to receive a reverse bias when powered on; wherein the Zener diode metal structure comprises two metal pins spaced apart from each other, both of the two metal pins penetrate the dielectric layer and partially extend into the N-type doping region and the P-type doping region of the Zener diode doping structure, and wherein the Zener diode metal structure is spaced apart from the source metal structure.

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