Integrated circuit power management method and corresponding integrated circuit

Abstract

The present disclosure relates to a power management method for an integrated circuit and a corresponding integrated circuit. For example, an integrated circuit includes: a first node for biasing at a first voltage; a second node for biasing at a second voltage and having a non-negligible capacitive coupling with the first node. The power management device includes a voltage booster, which is configured to increase the power supply voltage and includes a boost stage configured to generate an intermediate voltage on an intermediate node. The compatibility detection circuit is configured to detect compatibility between one of the intermediate voltages and a second voltage, and if the second voltage is compatible with the intermediate voltage, at least one second node is coupled to a compatible intermediate node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from French Patent Application No. 2005283, filed on May 20, 2020, which is incorporated herein by reference. Technical Field

[0003] Embodiments and implementations relate generally to integrated circuits and related methods, and more particularly, to management of integrated circuit power. Background Art

[0004] Some nodes in an integrated circuit can reach high voltages (eg, greater than 10V (volts)), while other nodes remain at a constant lower voltage.

[0005] However, these nodes may have a large capacitive coupling, so that when the voltage in the node reaching the high voltage increases, a parasitic current is injected into the node at the constant low voltage through the capacitive effect.

[0006] Specifically, the parasitic current simply discharges to ground and is therefore lost.

[0007] This type of parasitic current is particularly likely to occur in large network structures such as memory planes or pixel arrays, where the number of nodes that can reach high voltages or be held at lower constant voltages can be numerous and variable depending on the use of the circuit. Summary of the invention

[0008] Structurally adapting the architecture of an integrated circuit so as to limit capacitive coupling between nodes is often very restrictive, for example in terms of congestion.

[0009] In general, it is desirable to avoid energy losses, such as the leakage of parasitic capacitance currents mentioned above, especially in devices with low energy consumption, for example "contactless" type devices, such as devices using RFID ("Radio Frequency Identification") or NFC ("Near Field Communication") technology associated with standards familiar to those skilled in the art.

[0010] According to one aspect, a method for managing power of an integrated circuit is provided, the method comprising: distributing a first voltage on at least one first node; distributing a second voltage on at least one second node, the at least one second node having a capacitive coupling with the at least one first node; and boosting the power supply voltage using a boost stage having an intermediate voltage on an intermediate node. The method also comprises: detecting compatibility between the second voltage and at least one intermediate voltage; and if the second voltage is compatible with the at least one intermediate voltage, coupling the at least one second node to the intermediate node having the compatible intermediate voltage.

[0011] For example, the second voltage is compatible with the intermediate voltage means that the value of the second voltage is equal to or close to 5% of the value of the intermediate voltage. More generally, if any difference between the second voltage and the intermediate voltage does not impair the function of the circuit on the second node or the function of the circuit on the intermediate node, they can be considered compatible.

[0012] In other words, it is suggested that, in the case where the parasitic capacitance current flows from the first node to the second node, the parasitic capacitance current is reintroduced into the voltage boosting circuit to supply power to the voltage boosting circuit.

[0013] On the one hand, the compatibility of detecting the voltage on one of the intermediate nodes and the second node allows flexibility in the selection of the second node in the architecture of the integrated circuit and in the selection of the intermediate node in the boosting stage.

[0014] Therefore, energy recovery by reintroducing parasitic capacitive current into the boost circuit can be optimized in terms of the number of events generating capacitive parasitic current to be reintroduced and the efficiency of energy recovery.

[0015] Indeed, the choice of the second node makes it possible to multiply the parasitic current reintroduction and the choice of the intermediate node allows to optimize the level of the intermediate stage.

[0016] Since boosting the power supply voltage is usually implemented by a charge pump type boost circuit, the higher the level of the intermediate stage, the greater the energy gain on the power supply.

[0017] The boost circuit may be configured to boost a power supply voltage (eg, between 1 V and 3 V (volts)) to a first voltage level (eg, greater than 10 V).

[0018] According to an embodiment, the distributing of the second voltage comprises regulating the second voltage by a second regulator circuit, and if the second voltage is compatible with at least one intermediate voltage, the method comprises disconnecting the connection between at least one second node and the second regulator circuit.

[0019] This allows in particular to avoid conflicts with parasitic currents flowing between the ground terminal and the intermediate node of the regulator circuit.

[0020] According to one embodiment, the coupling of the at least one second node to the intermediate node is performed before a charging phase of the first node, which charging phase includes an increase in the voltage at the first node to the level of the first voltage.

[0021] According to one embodiment, a compatibility check is performed on a digital control signal controlling the value of the second voltage and the value of the at least one intermediate voltage.

[0022] In fact, the compatibility check may be programmed to check on the digital control signal a parameterization of the integrated circuit in which the value of the second voltage will be compatible with at least one intermediate voltage, for example specific to the architecture of the integrated circuit and the operation of its functions.

[0023] For example, the distribution of the first voltage includes a first adjustment, the distribution of the second voltage includes a second adjustment, and the digital control signal includes at least one of the following signals: a signal for controlling voltage boost, a signal for controlling the first adjustment, and a signal for controlling the second adjustment.

[0024] Advantageously, upon detection of compatibility, coupling of the at least one second node with the intermediate node is delayed by allowing a delay in charging the at least one second node to the second voltage.

[0025] In fact, the voltages generated by analog devices (such as regulators and boosters) generally have a reaction time relative to their digital control. Therefore, the delay added before the effective coupling of the second node with the intermediate node allows not to apply a sudden voltage drop caused by a transient voltage on the second node to the intermediate node from a level lower than that of the intermediate voltage.

[0026] According to another embodiment, detecting the compatibility comprises an analog comparison of instantaneous measurements of voltages present at nodes of the integrated circuit.

[0027] This implementation has the advantage of measuring a real signal, so it is very reliable in return for the analog design which is usually more cumbersome than a digital design.

[0028] For example, the instantaneous measurement includes at least one of the following voltages: a voltage present on at least one intermediate node; a voltage present on at least one first node; a voltage present on at least one second node.

[0029] According to another aspect, an integrated circuit is provided, comprising: at least one first node for biasing at a first voltage; at least one second node for biasing at a second voltage and having a capacitive coupling with the at least one first node; and a power management device, comprising a voltage boost circuit configured to boost a power supply voltage and comprising a boost stage configured to generate an intermediate voltage at an intermediate node. The power management device also includes a compatibility detection circuit configured to detect compatibility between at least one intermediate voltage and the second voltage, and if at least one intermediate voltage is compatible with the second voltage, coupling at least one second node to the intermediate node having a compatible intermediate voltage.

[0030] According to one embodiment, the integrated circuit includes a second regulator circuit configured to regulate a second voltage, and the power management device is configured to disconnect at least one second node and the regulator circuit if the second voltage is compatible with at least one intermediate voltage.

[0031] According to one embodiment, the power management device is configured to couple at least one second node to the intermediate node before a charging phase of the first node, wherein the charging phase of the first node includes increasing the voltage on the first node to a level of the first voltage.

[0032] According to one embodiment, the power management device is configured to detect compatibility of a digital control signal controlling a value of the second voltage and a value of the at least one intermediate voltage.

[0033] For example, the digital control signal includes at least one of the following signals: a signal to control a voltage boost circuit; a signal to control a first regulator circuit configured to regulate a first voltage; a signal to control a second regulator circuit configured to regulate a second voltage.

[0034] Advantageously, the power management device is configured to, upon detecting compatibility, couple the at least one second node to the intermediate node after a delay allowing the at least one second node to be charged to the second voltage.

[0035] According to one embodiment, the power management device is configured to detect compatibility between the second voltage and at least one intermediate voltage by measuring instantaneous values ​​of voltages present at nodes of the integrated circuit and by comparing the measured values.

[0036] For example, the power management device is configured to measure an instantaneous value of at least one of the following voltages: a voltage present on at least one intermediate node; a voltage present on at least one first node; a voltage present on at least one second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Other advantages and features of the present invention will become apparent after examining the detailed description of embodiments and non-limiting embodiments, namely the accompanying drawings, in which:

[0038] Figure 1 An integrated circuit is shown in an initial mode, including a voltage booster and a compatibility detection circuit;

[0039] Figure 2 An integrated circuit is shown in an energy recovery mode, including a voltage booster and a compatibility detection circuit;

[0040] Figure 3 showing curves of voltage and parasitic current of the first and second nodes as a function of time;

[0041] Figure 4 An integrated circuit having a compatibility detection circuit capable of selecting an intermediate node that is compatible with a second voltage is shown; and

[0042] Figure 5 An integrated circuit is shown having a compatible transformer detection circuit configured to read a digital control signal in order to detect compatibility between a second voltage and at least one intermediate voltage. DETAILED DESCRIPTION

[0043] Figure 1 and Figure 2 An integrated circuit CI is shown, which specifically includes a voltage booster ELV and a compatibility detection circuit CMPTB, which is configured to reintroduce a parasitic capacitance current Ip flowing from a first node N1 to a second node N2 to the voltage booster circuit ELV.

[0044] Figure 3 Curves G1 , G2 , G3 are shown which illustrate the development of the voltage V1 , V2 on the first and second node N1 , N2 and of the parasitic current Ip as a function of time t, in particular with respect to the instants t0 , t1 , t2 defined below.

[0045] Figure 1 shows the integrated circuit CI in an initial mode (or normal mode) between times t0 and t1, and Figure 2 The integrated circuit CI is shown in an energy recovery mode between the instants t1 and t2 .

[0046] Specifically, the following will be described in connection with each other Figure 1 , Figure 2 and Figure 3 , in order to illustrate a method for managing the power supply of the integrated circuit CI, in which the parasitic capacitance current Ip flowing from the first node N1 to the second node N2 is reintroduced into the voltage boosting circuit ELV.

[0047] Reintroducing the parasitic current Ip into the voltage boost circuit ELV allows reducing the energy consumption of the integrated circuit CI, which is advantageous in itself.

[0048] This allows in particular to relieve the pressure on the power supply stage ALM of the integrated circuit CI, which may have limited energy resources, for example in the case of a "contactless" powered integrated circuit, as defined for example in the standards associated with the technologies known as RFID and NFC (respectively for "Radio Frequency Identification" and "Near Field Communication" associated with standards familiar to those skilled in the art).

[0049] For example, the first node N1 and the second node N2 of the integrated circuit CI belong to a device ARY comprising a matrix array of relatively large size, such as a memory plane of a typical non-volatile memory or a matrix of photosensitive or photoemitter pixels.

[0050] In fact, this type of matrix array ARY device usually has parasitic capacitive coupling between nodes of the circuit, which is also difficult to avoid in terms of structural architecture.

[0051] The first node N1 and the second node N2 are selected to have, for example, a non-zero capacitive coupling Cp.

[0052] Advantageously, the first node N1 and the second node N2 are chosen to have a non-negligible capacitive coupling Cp, that is to say a capacitive coupling Cp which results in a significant current leakage relative to the output current of the voltage boost circuit ELV (relative to the values ​​of the first voltage V1 and the second voltage V2 belonging to normal conditions of use of the integrated circuit CI). For example, "significant" means "at least of the same order of magnitude".

[0053] The voltage boost circuit ELV is configured to boost the power supply voltage provided by the power supply ALM to a higher level (referred to as a high voltage HV).

[0054] For example, the power supply ALM provides a low power supply voltage (for example, 1 V to 3 V (volts)), and the voltage boosting circuit ELV provides a high voltage HV (for example, on the order of 10 V).

[0055] For example, the boost circuit ELV is of charge pump type and comprises boost stages STG1, STG2, STG3, STG4, STG5 connected in series, each of which is configured to boost the input voltage from a base level. Therefore, the output of each stage STG1-STG5 is at a corresponding intermediate voltage at a corresponding intermediate node, in particular an intermediate voltage V3 at a node N3 at the output of stage STG3.

[0056] Each boost stage STG1 - STG5 cannot generate power, and the input current I2 (for stage STG3 ) is necessarily higher than the output current I3 (for stage STG3 ).

[0057] According to a simplified operating principle, if each boost stage STGk (1≤k≤5) can provide a current Ik at the output that is equal to half of the current Ik-1 received at the input, the currents I0-I5 decrease in a quadratic manner as the number of boost stages.

[0058] The input and output currents I0, I1, I2, I3, I4 of each boost stage are shown by arrows, the size of which is proportional to the strength of the corresponding current.

[0059] For example, the current I0 provided by the power supply ALM to the voltage boost circuit ELV is budgeted to be 0.9 mA.

[0060] For example, the first voltage V1 is distributed on the first node N1 via the first regulator circuit REG1, which is configured to regulate the high voltage HV leaving the boost circuit ELV. For example, the first voltage V1 leaving the regulator REG1 is regulated to the same level as the high voltage HV, such as 10V.

[0061] For example, the second voltage V2 is distributed to the second node N2 via the second regulator circuit REG2, which is configured to regulate the high voltage HV leaving the boost circuit ELV. The second voltage V2 leaving the regulator REG2 is regulated to a level lower than that of the first voltage V1, for example, a level between 5V and 7V.

[0062] Alternatively, the second voltage V2 may be distributed by the second regulator circuit REG2 from other nodes other than the output HV of the voltage boost circuit ELV (eg, from an intermediate node of the voltage boost circuit or the first node N1 ).

[0063] exist Figure 1 In the initial mode t0 - t1 shown, the second node N2 is coupled to the output of the regulator REG2 through the switch SW2 controlled to be on (ie, closed) by the compatibility detection circuit CMPTB.

[0064] Also, in the initial mode t0 - t1 , another switch SW1 connected between the second node N2 and the middle node N3 of the voltage boosting circuit ELV is controlled to be disconnected (ie, opened) by the compatibility detection circuit CMPTB.

[0065] refer to Figure 3 and Figure 1 .

[0066] At time t0 of the operation of the integrated circuit, the distribution of the first voltage V1 at level HV and the second voltage V2 at level LV is controlled. The control comes from a conventional control circuit such as a microcontroller or an automaton usually called a state machine.

[0067] The first voltage V1 and the second voltage V2 do not rise to the corresponding stable levels HV, LV immediately, but have a charging time during which the voltages V1, V2 gradually increase before reaching the controlled levels HV, LV.

[0068] As shown by the curve G2 , the second voltage V2 reaches the level LV at the time t1 ; and as shown by the curve G1 , the first voltage V1 reaches the level HV at the time t2 after t1 .

[0069] The charging time (t2-t0) of the first voltage V1 and the charging time (t1-t0) of the second voltage V2 depend in particular on the analog functions of the voltage step-up circuit ELV and the regulator circuits REG1, REG2.

[0070] In this example, the shapes of the slopes of the first voltage V1 and the second voltage V2 are identical between the instants t0 and t1, in particular because the first voltage V1 and the second voltage V2 come from regulators REG1, REG2 which are supplied by the same voltage HV from the boost stage ELV. The shapes of the slopes of the first voltage V1 and the second voltage V2 may also result from the fact that the output of the boost circuit ELV is current limited.

[0071] Thus, as shown in the curve G3 , the difference ΔV (ΔV= V1 − V2 ) between the first voltage V1 and the second voltage V2 is zero between the times t0 and t1 .

[0072] Therefore, according to the equation Ip=C*dV / dt (C is the capacitance value of the parasitic capacitor Cp, dV / dt is the variance of ΔV), it is zero between the times t0 and t1.

[0073] On the other hand, from time t1 to time t2, the second voltage V2 is stabilized at the level LV, while the first voltage V1 continues to rise to the level HV.

[0074] The difference ΔV follows a linear variation, and between times t1 and t2 , a constant parasitic capacitance current Ip has flowed from the first node N1 to the second node N2 .

[0075] After time t2 , the first voltage V1 remains constant at the controlled level HV, the difference ΔV also remains constant, and the parasitic current Ip is zero.

[0076] When the parasitic current Ip is already flowing, that is, between the time t1 and t2, if the power management device PWM is kept at Figure 1 In the mode shown, the parasitic current Ip will be evacuated to the ground GND of the integrated circuit through the second regulator REG2.

[0077] However, as mentioned above, the compatibility detection circuit CMPTB is configured to reintroduce the parasitic capacitance current Ip into the voltage boosting circuit ELV.

[0078] Regarding this, see Figure 2 and Figure 3 .

[0079] Figure 2 The integrated circuit CI is shown in an energy recovery mode between instants t1 and t2 , ie when a parasitic capacitance current Ip is generated between the nodes N1 , N2 of the integrated circuit CI.

[0080] The compatibility detection circuit CMPTB is configured to detect compatibility between the second voltage V2 and at least one intermediate voltage of the boost circuit ELV. An example will be considered where a single intermediate voltage V3 leaves the third-to-last (before the second-to-last) boost stage STG3 at the intermediate node N3.

[0081] And if the actual value of the second voltage V2 is detected to be compatible with the intermediate voltage V3, the compatibility detection circuit CMPTB is configured to couple at least one second node N2 to the intermediate node N3. Advantageously, the compatibility detection circuit CMPTB is configured to simultaneously disconnect the second node N2 from the output of the regulator REG2.

[0082] In this regard, the compatibility detection circuit CMPTB controls the switch SW1 to be turned on (closed) and advantageously controls the switch SW2 to be turned off (open).

[0083] In order to be compatible with the intermediate voltage V3, the second voltage V2 stabilized at the controlled level LV must be similar to the intermediate voltage V3, that is, substantially equal, for example, equal to 5%. Of course, the similarity threshold between the second voltage and the intermediate voltage will depend on the architecture of the integrated circuit and the function of the signal on the nodes N2 and N3 according to the specific situation. Those skilled in the art should know how to determine the similarity threshold accordingly.

[0084] In fact, on the one hand, the second voltage V2 must not interfere with the function of the boost circuit ELV, for example, too low a second voltage V2 may cause a voltage drop on the intermediate node N3, and on the other hand, the intermediate voltage V3 also does not interfere with the function of the circuit ARY including the second node N2.

[0085] Therefore, the selection of the second node N2 will advantageously take into account this parameter, namely the compatibility with at least one intermediate node N3 of the boost circuit.

[0086] exist Figure 1 and Figure 2 In the example of FIG. 4 , the compatibility detection circuit CMPTB includes a first analog input IANA2 coupled to the output node ( N2 ) of the regulator REG2 and a second analog input IANA3 coupled to the intermediate node N3 .

[0087] In this exemplary embodiment and implementation, in order to evaluate the compatibility between the second voltage V2 and the intermediate voltage V3, the compatibility detection circuit CMPTB is configured to measure the instantaneous values ​​of the voltages present at the nodes of the integrated circuit CI, in particular, the second voltage V2 present at the second node N2, the intermediate voltage V3 present at the intermediate node N3, and optionally the first voltage V1 present at the first node N1.

[0088] The compatibility detection circuit CMPTB is configured to compare measurement values in order to identify the equality or similarity of voltage values.

[0089] In this example, the compatibility detection circuit CMPTB includes a comparator circuit (e.g., a typical operational amplifier type), which is configured to perform an all-or-nothing type of comparison of the level of a second voltage V2 on input IANA2 with the level of an intermediate voltage V3 on input IANA3. Thus, the digital output signals of the comparator can control switches SW2 and SW1 in opposite directions to each other.

[0090] Alternatively, the compatibility detection circuit CMPTB may include a dynamic comparator circuit based on the conventional function of comparison sampling, which is more energy-efficient.

[0091] Although analog comparator technology is relatively energy-consuming traditionally, its advantage is reliability because it is based on the measurement of the voltages actually present at the nodes of the integrated circuit IC.

[0092] Therefore, the compatibility detection circuit CMPTB is capable of detecting the moment t1 when the second voltage V2 is compatible with the intermediate voltage V3 of the boost circuit ELV, thereby placing the power management device PWM in the energy recovery mode t1 - t2.

[0093] In the energy recovery mode t1 - t2, as Figure 2 shown, the parasitic capacitance current Ip is injected into the intermediate node N3 via the on-state switch SW3.

[0094] Also, the currents I0, I1, I2, I3, I4, Ip existing in the boost circuit ELV are again indicated by arrows, the size of the arrows being proportional to the intensity of the corresponding currents.

[0095] The current Ip thus injected into the intermediate node N3 is added to the current I3b leaving stage STG3, and the upper stage STG4 benefits from a current of intensity I3b + Ip. Therefore, stage STG3 provides a current I3b (I3b = I3 - Ip) lower than the current I3 in the traditional mode as Figure 1 shown. Thus, compared with the traditional mode, stage STG3 consumes a lower current I2b (I2b < I2) generated by the lower stage STG2 at its input. Similarly, compared with the traditional mode, the lower stage STG2 consumes a lower current I1b (I1b < I1) generated by the first stage STG1, and the first stage STG1 also consumes a current I0b, which is lower than the current I0 provided by the power supply ALM in the traditional mode.

[0096] Due to the secondary reduction in current consumption explained above, each reduction in the current I3b - I1b at the output of each boost stage STG3 - STG1 is amplified by the gain at the input.

[0097] In other words, the difference between the current I2b and the conventional current I2 is greater than the difference I3b-I3, I2b-I2>I3b-I3, similarly, I1b-I1>I2b-I2, and therefore I0b-I0>I1b-I1. Therefore, the gain of the current I0b provided by the power supply ALM is much greater than the total strength of the parasitic current Ip injected into the boost circuit ELV (I0b-I0>>Ip).

[0098] For example, for a parasitic current Ip of approximately 13 μA (microamperes) re-injected into the output of the second stage of a three-stage boost circuit, this reflects a gain on power supply ALM of 150 μA. For a 0.9 mA budget, a 150 μA gain represents greater than 15% of the budget.

[0099] The higher the parasitic current Ip is injected into the intermediate node N3 of the series of boost stages STG1-STG5, the greater the gain of the power supply ALM.

[0100] Therefore, the choice of the second node will advantageously take this parameter into account, ie be able to have a voltage level corresponding to a high intermediate node of the voltage boosting circuit ELV.

[0101] In general, the selection of the second node N2 will take into account the various parameters mentioned above, namely having a capacitive coupling with the first node capable of generating parasitic currents of interest and compatibility with at least one intermediate node N3 of the boost circuit, and advantageously being as high as possible.

[0102] refer to Figure 4 .

[0103] Figure 4 Shown with the previous reference Figure 1 and Figure 2 The described integrated circuit corresponds to an embodiment in which the compatibility detection circuit CMPTB is capable of selecting an intermediate node compatible with the second voltage V2 from among the plurality of intermediate nodes N3, N4 of the voltage boosting circuit ELV.

[0104] exist Figure 4 In the example of , two intermediate nodes can be selected, one is the node N3 on the output of the second-to-last (second from the back) boost stage STG4, and the other is the node N4 on the output of the third-to-last (before the second-to-last) boost stage STG4. In another example, other intermediate nodes can be selected, such as all intermediate nodes of the boost circuit ELV.

[0105] This allows a multiplication example, in which, depending on the different levels of the second voltage V2 , a parasitic current Ip is generated, thereby being able to be reinjected into different intermediate nodes N3 , N4 of the voltage boosting circuit ELV.

[0106] In this embodiment, the compatibility detection circuit CMPTB comprises an additional analog input IANA4, which is coupled to an additional intermediate node N4 (in this example at the output of the penultimate boosting stage STG4).

[0107] Depending on whether compatibility between the second voltage V2 and the voltage on the additional intermediate node N4 is detected, the additional switch SW4 connected between the second node N2 and the additional intermediate node N4 is controlled to be in an on or off state.

[0108] In this example, compatibility is checked by comparing the Figure 1 and Figure 2 The simulation comparison described is performed.

[0109] Of course, in the case where other intermediate nodes (nodes other than the shown nodes N3 and N4) can be selected, the compatibility detection circuit CMPTB can couple another intermediate node compatible with the second voltage V2 by coupling other additional switches between the corresponding other intermediate nodes and the second node N2.

[0110] Multiplying the number of analog inputs IANA3, IANA4 and the number of analog comparator circuits within the compatibility detection circuit CMPTB may be cumbersome and energy-intensive. Therefore, it will be advantageous to select a limited number of intermediate nodes that are as high as possible in the series of boosting stages of the boosting circuit ELV (such as the output nodes of the second-to-last and third-to-last boosting stages SGT4, SGT3).

[0111] Figure 5 A preferred embodiment is shown, wherein the compatibility detection circuit CMPTB is configured to read the digital control signals DC1 , DC11 - DC15 , DC2 in order to detect the compatibility between the second voltage V2 and at least one intermediate voltage V3 , V4 of the voltage boost circuit ELV.

[0112] In addition to the functions of the compatibility detection circuit CMPTB, the integrated circuit CI has the functions mentioned above. Figures 1 to 3 The examples of the described architectures are such that identical elements have the same reference numerals and are not described in detail again.

[0113] For example, the compatibility detection circuit CMPTB is incorporated into a control and management circuit of the device ARY, such as a state machine or a microcontroller (such as a programmer).

[0114] The first regulator REG1 receives a first digital control signal DC1 , for example defining a stable level HV of the first voltage V1 , and the second regulator REG2 receives a second digital control signal DC2 , for example defining a stable level LV of the second voltage V2 .

[0115] Furthermore, in this example, in order to define the level of the high voltage HV, it is also considered to receive the first digital control signal DC1 through the voltage boosting circuit ELV.

[0116] The boosting stages STG1 - STG5 are generally equipped with internal regulation loops, from which internal digital regulation signals DC11 - DC15 representing the voltage levels at the corresponding intermediate nodes (especially N3, N4) can be output.

[0117] In fact, when the voltage boosting circuit ELV includes regulating the intermediate nodes N3, N4, it is generally considered that digital signals DC13, DC14 for controlling the levels of the regulated intermediate voltages are present at the intermediate nodes N3, N4.

[0118] For example, the internal regulation digital signals DC11 - DC15 are of the "on / off" type. That is to say, when the output nodes of the boosting stages STG1 - STG5 reach the target voltage, that stage stops pumping (its internal clock is cut off). That stage does not resume pumping until the output voltage drops below the threshold.

[0119] Moreover, knowing the functions of the routines of the integrated circuit CI and the control (or setting) of the voltage boosting circuit ELV and the regulators REG1, REG2, it is possible to know when the second node N2 and one of the intermediate nodes N3, N4 are equal without making any analog measurements.

[0120] In this example, it is known that the regulator REG2 controls the second voltage V2 under the following conditions (refer to Figure 3 ):

[0121] Condition 1: When V1 < LV, V2 = V1;

[0122] Condition 2: When V1 > LV, V2 = LV (~V3).

[0123] By simply observing the digital control signals DC1, DC2 from the regulators REG1, REG2 and the digital internal regulation signals DC11 - DC15 of the stages STG1 - STG5 of the voltage boosting circuit ELV, Condition 2 can be detected.

[0124] In this example, in this regard, the compatibility detection circuit CMPTB includes a first input INUM1 for receiving the digital control signal DC1 and the digital internal regulation signals DC11 - DC15, and a second input INUM2 for receiving the digital control signal DC2 of the second regulator REG2.

[0125] In fact, if the digital control DC1 of the first regulator REG1 controls the first voltage V1 to be greater than the intermediate voltage LV at the intermediate node N3 (controlled by the digital internal regulation signal DC13), then Condition 2 is recognized.

[0126] Then, the compatibility detection circuit CMPTB may connect the second node N2 to the corresponding middle node N3 and disconnect the second node N2 from the output of the second regulator REG2.

[0127] Of course, in the context of different routines of the functionality of the integrated circuit or of selecting the second node N2 at another location of the device ARY, the compatibility detection device CMPTB is configured to connect the second node N2 with another intermediate node N4, in particular detecting through the corresponding digital internal adjustment signal DC14 that its intermediate voltage is compatible with the second voltage V2.

[0128] However, since analog circuits such as regulators and boosters may take time to react to digital control, a delay may be added between detection of the condition made by the digital signal and the effective connection of the second node N2 and intermediate nodes N3, N4 (whose voltages are compatible with the second node V2).

[0129] Therefore, the compatibility detection circuit CMPTB is advantageously configured to detect the compatibility condition t0 at a delay t1-t0 ( Figure 3 ) after which the second node N2 is connected to the compatible intermediate node N3. The delay t1-t0 is determined so as to allow the at least one second node N2 to be charged to the second voltage V2 at a stable level (LV).

[0130] In addition, and with reference to Figure 1-Figure 4 and Figure 5 In a general manner of describing the embodiments and implementations, at the instant t1, marked as the beginning of the charging phase t2-t1 of the first node N1, the compatibility detection circuit CMPTB is configured to couple the second node N2 to the intermediate node N3 detected as compatible. The charging phase of the first node N1 consists in increasing the voltage on the first node N1 to the level of the first voltage V1 (HV), while the second voltage V2 is stable (LV). In fact, during the charging phase t2-t1, the potential difference ΔV between the first node N1 and the second node N2 varies, thereby generating a parasitic capacitance current Ip.

[0131] In summary, the above-described embodiments and implementations are advantageously related to integrated circuits powered by low voltages (e.g., less than 3V), while some internal functions (such as non-volatile memory or image sensors) require high internal voltages. In order to generate the high internal voltages, voltage boost circuits divided into multiple stages (such as charge pumps) are used. However, these circuits, which can consume a large amount of current, can cause problems for low-energy applications such as contactless products, Internet of Things products, etc. In applications including storage networks or image sensors, the nodes controlled to perform the functions targeted by the network usually have significant parasitic coupling due to the size of the network.

[0132] The above-described embodiments and implementations allow energy to be saved by utilizing the current caused by parasitic coupling. When possible and useful, this parasitic capacitance current is re-injected into the intermediate stage of the appropriate boost circuit through the compatibility detection circuit. Thus, the lower stage of the boost circuit requires less input current to maintain the voltage of the upper intermediate stage, which reduces overall energy consumption.

[0133] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art with reference to the description of the present invention. Therefore, the appended claims include any such modifications or embodiments.

Claims

1. A method for managing power supply of an integrated circuit, comprising: distributing a first voltage across at least one first node; distributing a second voltage on at least one second node, the at least one second node having a capacitance coupled to the at least one first node; boosting the supply voltage using a boost stage having an intermediate voltage at an intermediate node; detecting compatibility between at least one of the intermediate voltages and the second voltage; as well as In response to at least one of the intermediate voltages being compatible with the second voltage, the at least one second node is coupled to a compatible intermediate node having a compatible intermediate voltage.

2. The method according to claim 1, wherein distributing the second voltage comprises regulating the second voltage by a second regulator circuit; and The method further comprises disconnecting the at least one second node from the second regulator circuit.

3. The method of claim 1, wherein coupling the at least one second node with the compatible intermediate node is performed before a charging phase of the first node, the charging phase comprising increasing the voltage on the first node to the level of the first voltage. 4 . The method of claim 1 , wherein the detecting of the compatibility is performed on a digital control signal that controls a value of at least one of the intermediate voltages and a value of the second voltage.

5. The method of claim 4, wherein distributing the first voltage comprises a first adjustment, distributing the second voltage comprises a second adjustment, and the digital control signal comprises at least one of: a signal to control a voltage boost, a signal to control the first adjustment, or a signal to control the second adjustment.

6. The method of claim 4, wherein coupling of the at least one second node to the compatible intermediate node is delayed by allowing a delay in charging the at least one second node to the second voltage.

7. The method of claim 1, wherein detecting the compatibility comprises an analog comparison of instantaneous measurements of voltages present at nodes of the integrated circuit.

8. The method of claim 7, wherein the instantaneous measurement comprises at least one of: a voltage present on at least one of the intermediate nodes, a voltage present on the at least one first node, or a voltage present on the at least one second node.

9. An integrated circuit comprising: at least one first node configured to be biased at a first voltage; at least one second node having a capacitance coupled to the at least one first node and configured to be biased at a second voltage; a voltage boost circuit configured to boost a supply voltage and including a boost stage configured to generate an intermediate voltage at an intermediate node; as well as The compatibility detection circuit is configured as follows: detecting compatibility between at least one of the intermediate voltages and the second voltage; as well as In response to at least one of the intermediate voltages being compatible with the second voltage, the at least one second node is coupled to a compatible intermediate node having a compatible intermediate voltage.

10. The integrated circuit of claim 9, further comprising a second regulator circuit configured to regulate the second voltage, wherein the compatibility detection circuit is configured to disconnect the at least one second node from the second regulator circuit.

11. The integrated circuit of claim 9, wherein the compatibility detector circuit is configured to couple the at least one second node to the compatible intermediate node prior to a charging phase of the first node, wherein the charging phase includes increasing a voltage on the first node to a level of the first voltage.

12. The integrated circuit of claim 9, wherein the compatibility detection circuit is configured to detect the compatibility of a digital control signal that controls a value of at least one of the intermediate voltages and a value of the second voltage.

13. The integrated circuit of claim 12, wherein the digital control signal comprises at least one of: a signal to control the voltage boost circuit; a signal to control a first regulator circuit configured to regulate the first voltage; or a signal to control a second regulator circuit configured to regulate the second voltage.

14. The integrated circuit of claim 12, wherein the compatibility detection circuit is configured to couple the at least one second node to the compatible intermediate node after a delay that allows the at least one second node to be charged to the second voltage.

15. The integrated circuit of claim 9 , wherein the compatibility detection circuit is configured to detect compatibility between at least one of the intermediate voltages and the second voltage by measuring instantaneous values ​​of voltages present at nodes of the integrated circuit and by comparing the measured instantaneous values.

16. An integrated circuit according to claim 15, wherein the compatibility detection circuit is configured to measure an instantaneous value of at least one of the following: a voltage present on at least one of the intermediate nodes, a voltage present on the at least one first node, or a voltage present on the at least one second node.

17. A method for managing power of an integrated circuit, comprising: distributing a first voltage on a first node; distributing a second voltage on a second node, the second node having a capacitance coupled to the first node; boosting the supply voltage using a boost stage having an intermediate voltage at an intermediate node; detecting compatibility between the second voltage and a compatible intermediate voltage; as well as In response to the second voltage being compatible with the compatible intermediate voltage, coupling the second node to a compatible intermediate node having the compatible intermediate voltage.

18. The method according to claim 17, wherein distributing the second voltage comprises regulating the second voltage by a second regulator circuit; and The method further comprises disconnecting the second node from the second regulator circuit.

19. The method of claim 17, wherein coupling the second node to the compatible intermediate node is performed before a charging phase of the first node, the charging phase comprising increasing the voltage on the first node to the level of the first voltage. 20 . The method of claim 17 , wherein the detecting of the compatibility is performed on a digital control signal that controls a value of the second voltage and a value of the intermediate voltage.

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