camera device

Abstract

One aspect of this disclosure relates to an imaging device comprising a semiconductor substrate and a plurality of pixels. Each of the plurality of pixels includes a first capacitor element, the first capacitor element including a first electrode disposed above the semiconductor substrate, a second electrode disposed above the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode. At least one of the first electrode and the second electrode has: a first electrical contact electrically connected to a first electrical element, and a second electrical contact electrically connected to a second electrical element different from the first electrical element. The first capacitor element includes at least one trench portion having a trench shape.

Description

Technical Field

[0001] This disclosure relates to camera devices. Background Technology

[0002] An imaging device with the following structure has been proposed: a photoelectric conversion layer is disposed above a semiconductor substrate on which a CCD (Charge Coupled Device) circuit or a CMOS (Complementary Metal Oxide Semiconductor) circuit is formed. An imaging device having a photoelectric conversion layer above a semiconductor substrate is also called a stacked imaging device. For example, Patent Document 1 discloses a solid-state imaging element having such a stacked structure.

[0003] A stacked imaging device stores the charge generated by photoelectric conversion in a charge storage region, and then reads out the stored charge by a readout circuit containing CCD or CMOS circuitry. The photoelectric conversion layer is typically disposed on an insulating layer covering a semiconductor substrate on which the readout circuitry is formed. The photoelectric conversion layer on the insulating layer is electrically connected to the readout circuitry via a connector disposed within the insulating layer.

[0004] Prior art literature

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2018-195803 Summary of the Invention

[0007] The problem to be solved by the present invention

[0008] In the field of camera devices, noise reduction is required.

[0009] Methods for solving problems

[0010] One aspect of this disclosure relates to an imaging device comprising a semiconductor substrate and a plurality of pixels. Each of the plurality of pixels includes a first capacitor element, the first capacitor element including a first electrode disposed above the semiconductor substrate, a second electrode disposed above the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode. At least one of the first electrode and the second electrode has: a first electrical contact electrically connected to the first electrical element, and a second electrical contact electrically connected to the second electrical element, which is different from the first electrical element. The first capacitor element includes at least one trench portion having a trench shape.

[0011] A general or specific approach can also be achieved through components, devices, systems, integrated circuits, or methods. Furthermore, a general or specific approach can also be achieved through any combination of components, devices, apparatuses, systems, integrated circuits, and methods.

[0012] Invention Effects

[0013] According to one aspect of this disclosure, a camera device capable of further reducing noise is provided. Attached Figure Description

[0014] Figure 1 This is a diagram illustrating an exemplary circuit configuration of the camera device according to Embodiment 1.

[0015] Figure 2 This diagram illustrates an example of the circuit configuration of the pixels in the camera device according to Embodiment 1.

[0016] Figure 3 This is a schematic cross-sectional view of the pixels of the camera device according to Embodiment 1.

[0017] Figure 4 This is a schematic plan view showing an example of the layout of each element included in the pixels of the camera device according to Embodiment 1.

[0018] Figure 5 This is a schematic plan view showing an example of the shape and arrangement of the first capacitor element and the groove portion included in the pixel of the camera device according to Embodiment 1.

[0019] Figure 6A This is a schematic cross-sectional view used to illustrate the via formation process included in the manufacturing method of the camera device according to Embodiment 1.

[0020] Figure 6B This is a schematic cross-sectional view used to illustrate the process of forming an insulating layer in the manufacturing method of the camera device according to Embodiment 1.

[0021] Figure 6C This is a schematic cross-sectional view used to illustrate the trench formation process included in the manufacturing method of the camera device according to Embodiment 1.

[0022] Figure 6D This is a schematic cross-sectional view illustrating the formation process of the lower electrode included in the manufacturing method of the camera device according to Embodiment 1.

[0023] Figure 6E This is a schematic cross-sectional view used to illustrate the dielectric layer formation process included in the manufacturing method of the camera device according to Embodiment 1.

[0024] Figure 6F This is a schematic cross-sectional view illustrating the formation process of the upper electrode included in the manufacturing method of the camera device according to Embodiment 1.

[0025] Figure 6G This is a schematic cross-sectional view illustrating the process of the insulating layer included in the manufacturing method of the camera device according to Embodiment 1.

[0026] Figure 6H This is a schematic cross-sectional view used to illustrate the via and wiring layer formation process included in the manufacturing method of the camera device according to Embodiment 1.

[0027] Figure 6I This is a schematic cross-sectional view illustrating the formation processes of the insulating layer, vias, and wiring layer included in the manufacturing method of the camera device according to Embodiment 1.

[0028] Figure 7 This is a schematic cross-sectional view of the pixels of the camera device involved in the variation of Embodiment 1.

[0029] Figure 8 This is a schematic cross-sectional view of the pixels of the camera device according to Embodiment 2.

[0030] Figure 9 This is a schematic plan view showing an example of the shape and arrangement of the first capacitor element and the groove portion included in the pixel of the camera device according to Embodiment 2.

[0031] Figure 10 This is a schematic plan view showing an example of the shape and arrangement of the first capacitor element and the trench portion included in the pixel of the camera device according to the modified example of embodiment 2.

[0032] Figure 11 This diagram illustrates an example of the circuit configuration of the pixels in the camera device according to Embodiment 3.

[0033] Figure 12 This is a schematic cross-sectional view of the pixels of the camera device according to Embodiment 3.

[0034] Figure 13 This is a schematic cross-sectional view of the pixels of the camera device according to Embodiment 4.

[0035] Figure 14 This is a schematic cross-sectional view of the pixels of the camera device according to Embodiment 5.

[0036] Figure 15This is a schematic cross-sectional view of the pixels of the camera device according to a variation of Embodiment 5.

[0037] Figure 16 This is a schematic cross-sectional view of the pixels of the camera device involved in other variations of Embodiment 1. Detailed Implementation

[0038] (Summary of this disclosure)

[0039] According to a non-limiting exemplary embodiment of this disclosure, the following approach is provided.

[0040] One aspect of this disclosure relates to an imaging device comprising a semiconductor substrate and a plurality of pixels. Each of the plurality of pixels includes a first capacitor element, the first capacitor element including a first electrode disposed above the semiconductor substrate, a second electrode disposed above the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode. At least one of the first electrode and the second electrode has: a first electrical contact electrically connected to the first electrical element, and a second electrical contact electrically connected to the second electrical element, which is different from the first electrical element. The first capacitor element includes at least one trench portion having a trench shape.

[0041] Therefore, by providing two or more electrical contacts in the first capacitor element, the flexibility in the layout of the wiring that connects the first capacitor element to multiple electrical components is increased. Thus, for example, even within small pixel areas, the wiring can be arranged in a way that minimizes parasitic capacitance between wirings, thereby reducing noise. In this way, an imaging device with further noise reduction can be realized. Furthermore, by increasing the flexibility in wiring layout, the pixel area can be reduced, thus achieving miniaturization of the imaging device.

[0042] Alternatively, for example, at least one of the first electrical contact and the second electrical contact may be disposed in the at least one trench portion. Alternatively, for example, at least one of the first electrical contact and the second electrical contact may be disposed on the bottom surface of the at least one trench portion. Alternatively, for example, the first electrical contact may be disposed in the at least one trench portion, and the second electrical contact may be disposed outside the at least one trench portion.

[0043] In this way, electrical connections to electrical components can be made using the bottom or side surface of the groove. That is, electrical contacts can be provided not only on the flat portion of the first capacitor element but also outside the flat portion, thus increasing the flexibility of wiring layout.

[0044] Alternatively, for example, the at least one groove portion may include a plurality of groove portions, the plurality of groove portions including groove portions where the first electrical contact and the second electrical contact are not provided.

[0045] Therefore, it is possible to suppress the increase in the area occupied by the first capacitor element in the planar diagram and to increase the capacitance value of the first capacitor element. In other words, it is possible to set a first capacitor element with a large capacitance value in a small pixel area.

[0046] Alternatively, for example, the first electrode may be positioned closer to the semiconductor substrate than the second electrode, and may have the first electrical contact and the second electrical contact.

[0047] Therefore, for example, by exposing the exposed portion of the via or wiring to plasma during trench formation, the exposed portion can be activated. By connecting the exposed portion to the first electrode of the first capacitor element using a contact, the contact resistance between the via or wiring and the first electrode can be reduced. By reducing the contact resistance, the unevenness (deviation) of contact resistance between pixels can be reduced, thus suppressing graininess in the image generated by the imaging device. In this way, an imaging device that further reduces noise can be realized.

[0048] Alternatively, for example, the second electrode may be configured to be further away from the semiconductor substrate than the first electrode, and may have the first electrical contact and the second electrical contact.

[0049] Therefore, the electrodes for setting electrical contacts are not limited to the first electrode, thus further increasing the freedom of wiring layout.

[0050] Alternatively, for example, the first electrode and the second electrode may also contain TiN or TaN.

[0051] As a result, a first electrode and a second electrode with small surface roughness can be formed. Therefore, the unevenness (deviation) in the spacing between the first electrode and the second electrode is suppressed, and thus the unevenness (deviation) in the capacitance value of the first capacitor element can also be suppressed.

[0052] Alternatively, for example, the imaging device according to one aspect of this disclosure may also include a plurality of wiring layers disposed above the semiconductor substrate, wherein the number of wiring layers located above the first capacitor element is greater than the number of wiring layers located below the first capacitor element.

[0053] Impurity regions are mostly formed in the semiconductor substrate, and these impurity regions function as part of a charge storage region for accumulating signal charges generated by the photoelectric conversion unit. This reduces the number of wiring layers close to the semiconductor substrate, thus suppressing potential fluctuations in the charge storage region caused by parasitic capacitance components resulting from the wiring layers. Therefore, it is possible to realize an imaging device that further reduces noise.

[0054] Alternatively, for example, both the first electrical contact and the second electrical contact may be connected to a via.

[0055] Thus, for example, by exposing the upper end of the via to plasma during trench formation, the upper end of the via is activated. Therefore, metal bonding between the upper end of the via and the electrode of the first capacitor element is easily achieved, thereby reducing the contact resistance between the via and the electrode of the first capacitor element.

[0056] Alternatively, for example, each of the plurality of pixels may further include: a photoelectric conversion unit and an impurity region electrically connected to the photoelectric conversion unit and disposed within the semiconductor substrate, wherein, in a plan view, the first capacitor element overlaps with at least a portion of the impurity region.

[0057] Therefore, when the first electrode or the second electrode is formed using a light-shielding material, the first capacitor element can suppress light incident on the imaging device from reaching the impurity region. Thus, the generation of unwanted charges in the impurity region can be suppressed, further reducing noise.

[0058] Alternatively, for example, each of the plurality of pixels may further include: a photoelectric conversion unit, an impurity region electrically connected to the photoelectric conversion unit and disposed within the semiconductor substrate, a transistor electrically connected to the impurity region, and a second capacitor element, wherein the transistor is one of the first electrical contact and the second electrical contact, and the second capacitor element is the other of the first electrical contact and the second electrical contact. Alternatively, for example, the transistor may be a reset transistor that resets the charge generated by the photoelectric conversion unit and accumulated in the impurity region.

[0059] Therefore, the first electrode or the second electrode can be made to have the same potential as one of the electrodes of the second capacitor element and the source or drain region of the transistor. For example, the first electrode or the second electrode, one of the electrodes of the second capacitor element, and the source or drain region of the transistor can be used as a reset drain node.

[0060] Alternatively, for example, the second capacitor element may also be electrically connected to the impurity region via the first electrode or the second electrode.

[0061] Therefore, the first electrode or the second electrode of the first capacitor element can be used as part of the wiring. As a result, the dedicated wiring required for electrical connections can be reduced, thus increasing the space within the pixel and further improving the flexibility of other wiring layouts.

[0062] Alternatively, for example, each of the plurality of pixels may further include: a photoelectric conversion unit and an impurity region electrically connected to the photoelectric conversion unit and disposed within the semiconductor substrate, wherein the first electrode is disposed closer to the semiconductor substrate than the second electrode and is electrically connected to the impurity region, and the second electrode is electrically connected to a pad to which a predetermined voltage value is applied.

[0063] Therefore, the potential of the first capacitor element can be adjusted by applying voltage to the pad.

[0064] Alternatively, for example, the camera device may also include: a sensitivity adjustment line electrically connected to the pad and the second electrode, for adjusting the sensitivity of the camera device.

[0065] Therefore, the sensitivity can be adjusted accordingly to the amount of light incident on the camera device, thus expanding the dynamic range of the camera device from dark scenes to bright scenes.

[0066] The additional effects and advantages of the disclosed embodiments become clear from the specification and drawings. Effects and / or advantages are provided by each of the various embodiments or features disclosed in the specification and drawings, and it is not necessary to obtain more than one of them, but all of them.

[0067] The embodiments are described in detail below with reference to the accompanying drawings.

[0068] Furthermore, the embodiments described below are all general or specific examples. The numerical values, shapes, materials, structural elements, the arrangement and connection methods of structural elements, steps, and the order of steps shown in the following embodiments are examples and are not intended to limit this disclosure. In addition, any constituent elements in the following embodiments that are not described in the independent claims are described as arbitrary constituent elements.

[0069] Furthermore, these figures are schematic diagrams and not necessarily precise representations. Therefore, for example, the scales and other parameters may not be consistent across figures. Additionally, substantially identical components are given the same labels across figures, and repetitive descriptions are omitted or simplified.

[0070] Furthermore, in this specification, terms such as parallel or perpendicular to indicate the relationship between elements, terms indicating the shape of elements, and numerical ranges do not only represent strict meanings, but also imply that they include substantially equivalent ranges, such as differences of a few percent.

[0071] Furthermore, in this specification, the terms "above," "upper part," "above," "below," "lower part," and "below" do not refer to the absolute spatial direction of upward (vertical above) and downward (vertical below), but are used as terms that define the stacking order in a layered structure through relative positional relationships. In addition, the terms "above" and "below" are used not only in cases where two structural elements are spaced apart and other structural elements exist between them, but also in cases where two structural elements are closely connected and adjoining.

[0072] In addition, in this specification, "plan view" refers to a view viewed from a direction perpendicular to the main surface of the semiconductor substrate.

[0073] (Implementation Method 1)

[0074] [1. Circuit Structure]

[0075] Figure 1 This is a diagram illustrating an exemplary circuit configuration of the imaging device 100 according to this embodiment. For example... Figure 1 As shown, the camera device 100 includes a plurality of pixels 10 and peripheral circuitry. The plurality of pixels 10 are arranged, for example, in a two-dimensional configuration to form a pixel region RA. For simplicity, in... Figure 1 In the image, four pixels 10 are extracted from the multiple pixels 10 and represented, while the other pixels 10 are omitted.

[0076] For example, if the camera device 100 conforms to the VGA (Video Graphics Array) standard, then the camera device 100 has approximately 300,000 pixels 10 arranged in a matrix. Alternatively, if the camera device 100 conforms to the 8K standard, then the camera device 100 has approximately 36 million pixels 10 arranged in a matrix. The aforementioned peripheral circuitry is disposed in the peripheral region outside the pixel region RA.

[0077] Obviously, the number and configuration of pixels 10 are not limited to this example. The arrangement of pixels 10 can also be one-dimensional. In this case, the camera device 100 can be used as a line sensor.

[0078] Each pixel 10 of the plurality of pixels 10 is connected to a power supply wiring 22. When the imaging device 100 is operating, a predetermined power supply voltage AVDD is supplied to each pixel 10 of the plurality of pixels 10 via the power supply wiring 22. Additionally, an accumulation control line 17 is connected to each pixel 10 of the plurality of pixels 10. As detailed below, each pixel 10 of the plurality of pixels 10 includes: a photoelectric conversion unit that performs photoelectric conversion on incident light, and a signal detection circuit that detects the signal generated by the photoelectric conversion unit. In a typical embodiment, the accumulation control line 17 applies a predetermined voltage to the photoelectric conversion units of each pixel 10 in a common manner.

[0079] exist Figure 1 In the illustrated configuration, the peripheral circuitry of the imaging device 100 includes a vertical scanning circuit 16, multiple load circuits 19, multiple column signal processing circuits 20, multiple inverting amplifiers 24, and a horizontal signal readout circuit 21. The load circuits 19, column signal processing circuits 20, and inverting amplifiers 24 are arranged in each column of the pixels 10 arranged in a two-dimensional configuration. Furthermore, the vertical scanning circuit is also referred to as a row scanning circuit. The column signal processing circuit is also referred to as a row signal accumulation circuit. The horizontal signal readout circuit is also referred to as a column scanning circuit.

[0080] An address signal line 30 and a reset signal line 26 are connected to the vertical scanning circuit 16. The vertical scanning circuit 16 selects multiple pixels 10 arranged in each row by applying a predetermined voltage to the address signal line 30. By selecting multiple pixels 10 by row, the signal voltage of the selected pixel 10 is read out, and the signal charge is reset as described later.

[0081] In the illustrated example, a feedback control line 28 and a sensitivity adjustment line 32 are also connected to the vertical scanning circuit 16. The vertical scanning circuit 16 applies a predetermined voltage to the feedback control line 28, thereby forming a feedback loop that provides negative feedback to the output of the pixel 10. Additionally, the vertical scanning circuit 16 can supply a predetermined voltage to multiple pixels 10 via the sensitivity adjustment line 32.

[0082] The camera device 100 has vertical signal lines 18 arranged in each column of a plurality of pixels 10. A load circuit 19 is electrically connected to each vertical signal line 18. Each of the plurality of pixels 10 is electrically connected to a column signal processing circuit 20 via its corresponding vertical signal line 18.

[0083] The column signal processing circuit 20 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion. A horizontal signal readout circuit 21 is electrically connected to each column of the column signal processing circuit 20, which corresponds to each column of the multiple pixels 10. The horizontal signal readout circuit 21 sequentially reads signals from the multiple column signal processing circuits 20 onto the horizontal common signal line 23.

[0084] like Figure 1 As shown, power supply wiring 22, feedback line 25, and vertical signal line 18 are located in... Figure 1 The pixels 10 extend in the vertical direction, i.e., in the column direction. Each feedback line 25 of the feedback line 25 and each vertical signal line 18 of the vertical signal line 18, arranged in each column of the pixels 10, are connected to each pixel 10 of the pixels 10 arranged along the column direction. On the other hand, the accumulation control line 17, reset signal line 26, feedback control line 28, address signal line 30, and sensitivity adjustment line 32 extend, for example, in the row direction of the pixels 10. These signal lines are connected to each pixel 10 of the pixels 10 arranged along the row direction. Furthermore, the accumulation control line 17 and sensitivity adjustment line 32 can also extend in the column direction of the pixels 10. The accumulation control line 17 and sensitivity adjustment line 32 can also be connected to each pixel 10 of the pixels 10 arranged along the column direction.

[0085] exist Figure 1 In the illustrated configuration, an inverting amplifier 24 is provided corresponding to each column of the plurality of pixels 10. The negative input terminal of the inverting amplifier 24 is connected to the corresponding vertical signal line 18, and the positive input terminal of the inverting amplifier 24 is supplied with a predetermined voltage Vref. The voltage Vref is, for example, a positive voltage of 1V or close to 1V. The output terminal of the inverting amplifier 24 is connected to the pixel 10 connected to the negative input terminal of the inverting amplifier 24 via one of the plurality of feedback lines 25 provided corresponding to the plurality of columns of pixels 10. The inverting amplifier 24 constitutes part of a feedback circuit that provides negative feedback from the output of the pixel 10. The inverting amplifier 24 may also be referred to as a feedback amplifier.

[0086] Figure 2 This diagram illustrates an example of the circuit configuration of the pixels 10 included in the camera device 100 according to this embodiment. In this embodiment, the plurality of pixels 10 included in the camera device 100 have identical configurations.

[0087] like Figure 2 As shown, pixel 10 includes a photoelectric conversion unit 15 and a signal detection circuit SC. Figure 2 In the illustrated configuration, the camera device 100 includes a feedback circuit FC that provides negative feedback to the output of the signal detection circuit SC.

[0088] The photoelectric conversion unit 15 includes a first electrode 15a, a photoelectric conversion layer 15b, and a second electrode 15c, which serves as a pixel electrode. The first electrode 15a of the photoelectric conversion unit 15 is connected to an accumulation control line 17. The second electrode 15c of the photoelectric conversion unit 15 is connected to a charge accumulation node 44. By controlling the potential of the first electrode 15a via the accumulation control line 17, one of the positive charges (specifically holes) and negative charges (specifically electrons) generated in the photoelectric conversion layer 15b through photoelectric conversion can be collected towards the second electrode 15c. For example, when holes are used as signal charges, the potential of the first electrode 15a can be made higher than that of the second electrode 15c. Hereinafter, the case of using holes as signal charges is illustrated. For example, a voltage of about 10V is applied to the first electrode 15a via the accumulation control line 17. As a result, the signal charge is accumulated at the charge accumulation node 44. Electrons can also be used as signal charges.

[0089] The signal detection circuit SC includes a signal detection transistor 34 that amplifies and outputs the signal generated by the photoelectric conversion unit 15, and a first capacitor element 41. In the illustrated example, the signal detection circuit SC also includes a reset transistor 36, a feedback transistor 38, a second capacitor element 42 having a capacitance value smaller than that of the first capacitor element 41, and an address transistor 40. Thus, in this embodiment, each of the plurality of pixels 10 has one or more capacitor elements within the pixel. As explained in detail later, the first capacitor element 41 having a relatively large capacitance value can, for example, effectively reduce kTC noise. Hereinafter, an example using an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as the signal detection transistor 34 and other transistors will be described.

[0090] The gate of the signal detection transistor 34 is connected to the charge accumulation node 44. In other words, the gate of the signal detection transistor 34 is connected to the second electrode 15c. The drain of the signal detection transistor 34 is connected to the power supply wiring 22, which serves as the power supply for the source follower, and the source is connected to the vertical signal line 18 via the address transistor 40. The signal detection transistor 34 and in Figure 2 Load circuit 19 (not shown in the figure) Figure 1 This constitutes a source follower circuit.

[0091] exist Figure 2In the example shown, an address transistor 40 is connected between the source of the signal detection transistor 34 and the vertical signal line 18. The gate of the address transistor 40 is connected to the address signal line 30. When signal charge is accumulated in the charge accumulation node 44, a voltage corresponding to the amount of accumulated signal charge is applied to the gate of the signal detection transistor 34. The signal detection transistor 34 amplifies the voltage applied to its gate. With the address transistor 40 turned on, the voltage amplified by the signal detection transistor 34 is selectively read out as a signal voltage. Alternatively, the address transistor 40 can also be connected between the drain of the signal detection transistor 34 and the power supply line 22. That is, the drain of the signal detection transistor 34 can also be connected to the power supply line 22 via the address transistor 40.

[0092] exist Figure 2 In the illustrated configuration, one of the pair of electrodes of the first capacitor element 41 is connected to the sensitivity adjustment line 32. A pad is connected to the sensitivity adjustment line 32, and the potential of the sensitivity adjustment line 32 is adjusted by applying a voltage to the pad. For example, when the imaging device 100 is operating, the potential of the sensitivity adjustment line 32 is fixed at a certain potential, such as 0V. The sensitivity adjustment line 32 can be used to control the potential of the charge accumulation node 44. The other of the pair of electrodes of the first capacitor element 41 is connected to one of the pair of electrodes of the second capacitor element 42. Hereinafter, the node including the connection point of the first capacitor element 41 and the second capacitor element 42 will sometimes be referred to as the reset drain node 46.

[0093] The other electrode of the pair of electrodes in the second capacitor element 42 is connected to the charge accumulation node 44. That is, the electrode of the pair of electrodes in the second capacitor element 42 that is not connected to the reset drain node 46 is electrically connected to the second electrode 15c of the photoelectric conversion unit 15. Furthermore, in Figure 2 In the example shown, the reset transistor 36 is connected in parallel with the second capacitor element 42. The gate of the reset transistor 36 is connected to the reset signal line 26.

[0094] exist Figure 2 In the illustrated configuration, pixel 10 includes a feedback transistor 38. As shown, one of the source and drain of the feedback transistor 38 is connected to the reset drain node 46. The other of the source and drain of the feedback transistor 38 is connected to the feedback line 25. The gate of the feedback transistor 38 is connected to the feedback control line 28.

[0095] [2. Device structure of pixels]

[0096] Next, refer to Figures 3 to 5 This illustrates an example of a device construction with 10 pixels.

[0097] Figure 3This is a schematic cross-sectional view of the pixels 10 provided in the camera device 100 according to this embodiment. Figure 4 This is a schematic plan view illustrating an example of the layout of each element included in the pixel 10 of the imaging device 100 according to this embodiment. Furthermore, Figure 3 Indicative representation Figure 4 The cross section at line III-III shown.

[0098] In addition, Figure 3 In the diagram, the shading of insulating layers 4a, 4b, 4c, 4d, 4e, and 4f, which are included in interlayer insulating layer 4, is not shown in terms of cross-section. (The following is a separate section.) Figures 6A to 6I , Figure 7 , Figure 8 , Figures 12 to 15 The same applies.

[0099] like Figure 4 As shown, the imaging device 100 includes a semiconductor substrate 2. For example, a silicon substrate can be used as the semiconductor substrate 2. The semiconductor substrate 2 is not limited to a substrate that is entirely semiconductor. For example, the semiconductor substrate 2 can also be an insulating substrate on which a semiconductor layer is provided. Here, a p-type silicon substrate is used as an example of the semiconductor substrate 2.

[0100] Each of the plurality of pixels 10 is formed on the semiconductor substrate 2. Each of the plurality of pixels 10 is electrically separated from the other pixels 10 by an element separation region 2t formed on the semiconductor substrate 2. The element separation region 2t is formed, for example, by ion implantation of a acceptor based on specified implantation conditions.

[0101] exist Figure 3 In the example shown, an interlayer insulating layer 4 covering the semiconductor substrate 2 is disposed between the semiconductor substrate 2 and the photoelectric conversion unit 15. The interlayer insulating layer 4 has a stacked structure of insulating layers 4a, 4b, 4c, 4d, 4e, and 4f. Each of the insulating layers 4a, 4b, 4c, 4d, 4e, and 4f is, for example, an insulating layer formed of silicon dioxide. In this example, the photoelectric conversion unit 15 is located on the insulating layer 4f, which is furthest from the semiconductor substrate 2.

[0102] Impurity regions 2a, 2b, and 2c are formed on the semiconductor substrate 2. These impurity regions 2a, 2b, and 2c are, for example, regions diffused with N-type dopant. On the main surface of the semiconductor substrate 2, in the region between impurity regions 2a and 2b, the gate insulating layer 36g and gate electrode 36e of the reset transistor 36 are sequentially disposed. Additionally, on the main surface of the semiconductor substrate 2, in the region between impurity regions 2b and 2c, the gate insulating layer 38g and gate electrode 38e of the feedback transistor 38 are sequentially disposed. Furthermore, the main surface of the semiconductor substrate 2 is the surface among the multiple surfaces of the semiconductor substrate 2 on the side where the interlayer insulating layer 4 and the photoelectric conversion unit 15 are disposed. The main surface of the semiconductor substrate 2 is covered by the insulating layer 4a of the interlayer insulating layer 4.

[0103] Impurity region 2a functions as one of the drain and source regions of reset transistor 36. Impurity region 2b functions as the other of the drain and source regions of reset transistor 36. Figure 3 In the example shown, the reset transistor 36 and the feedback transistor 38 are electrically connected to each other by sharing the impurity region 2b. That is, the impurity region 2b also functions as one of the drain and source regions of the feedback transistor 38.

[0104] The impurity region 2c functions as the other of the drain and source regions of the feedback transistor 38. The impurity region 2c is connected to the feedback line 25 spanning multiple pixels 10 via plugs, vias, and wiring layers disposed in the interlayer insulating layer 4. Figure 1 As shown, feedback line 25 is a signal line that extends to the outside of pixel region RA.

[0105] exist Figure 3 In the illustrated configuration, the portion of the feedback line 25 within the pixel of interest 10 is included in a wiring layer 51 located between the second electrode 15c of the photoelectric conversion unit 15 and the semiconductor substrate 2. Furthermore, a wiring layer 52, located on the same layer as wiring layer 51, includes the portion of the vertical signal line 18 within the pixel of interest 10. In other words, in this example, the vertical signal line 18 and the feedback line 25 are located on the same layer within the pixel 10. The vertical signal line 18 is also a signal line that extends to the outside of the pixel region RA, just like the feedback line 25.

[0106] Furthermore, "same layer" means located on a common insulating layer. In this case, when the common insulating layer is a planarization film, the heights from the main surface of the semiconductor substrate 2 are substantially equal.

[0107] In addition, the signal lines extending to the outside of the pixel region RA include not only the vertical signal line 18 and the feedback line 25, but also the reset signal line 26, the feedback control line 28, the address signal line 30, and the sensitivity adjustment line 32. At least one of the wiring layers 51 and 52 may also include a portion of the reset signal line 26, the feedback control line 28, the address signal line 30, or the sensitivity adjustment line 32 as control lines for driving two or more pixels.

[0108] On the main surface of the semiconductor substrate 2, a gate insulating layer 34g and a gate electrode 34e of a signal detection transistor 34 are sequentially disposed. (See reference...) Figure 4 It can be seen that the drain region and source region of the signal detection transistor 34 are located at... Figure 3 The front and inner sides of the paper. Furthermore, in Figure 3 In the example shown, the group of reset transistor 36 and feedback transistor 38 is connected to signal detection transistor 34 and address transistor 40 (in... Figure 3 The group (not shown) is separated by the component separation region 2u. The component separation region 2u, for example, like the component separation region 2t, can be formed by ion implantation of the acceptor based on specified implantation conditions. Both component separation regions 2t and 2u can also be insulating regions formed by an STI (Shallow Trench Isolation) process. Furthermore, the component separation region 2t and the component separation region 2u are integrally formed within the pixel region.

[0109] like Figure 3 As shown, each pixel 10 has a connection portion 50 within the interlayer insulating layer 4 that electrically connects the impurity region 2a of the semiconductor substrate 2 to the second electrode 15c of the photoelectric conversion unit 15. The impurity region 2a is an example of an impurity region electrically connected to the photoelectric conversion unit 15. The impurity region 2a functions as at least a portion of a charge accumulation region that accumulates signal charge generated by the photoelectric conversion unit 15.

[0110] The connection portion 50 includes plugs P1 and P2, and wiring portion 50a. The lower end of plug P1 is connected to the impurity region 2a of the semiconductor substrate 2, and its upper end is connected to wiring portion 50a. The lower end of plug P2 is connected to the gate electrode 34e of the signal detection transistor 34, and its upper end is connected to wiring portion 50a. Wiring portion 50a connects plugs P1 and P2 to each other. Through plugs P1, P2, and wiring portion 50a, the impurity region 2a and the gate electrode 34e are electrically connected to each other. In other words, the impurity region 2a, which functions as the drain or source region of the reset transistor 36, and the gate electrode 34e of the signal detection transistor 34, are electrically connected to the second electrode 15c of the photoelectric conversion portion 15 via the connection portion 50.

[0111] The plugs P1 and P2 and the wiring portion 50a are formed using a conductive material. For example, the plugs P1 and P2 and the wiring portion 50a are formed using polysilicon, which is made conductive by doping with impurities. Alternatively, at least one of the plugs P1 and P2 and the wiring portion 50a may also be formed using a metallic material such as copper.

[0112] The connection portion 50 also includes wiring layers 50b and 50c, and vias 50d, 50e, and 50f. Between the wiring portion 50a and the second electrode 15c, vias 50d, 50b, 50e, 50c, and 50f are sequentially disposed from the semiconductor substrate 2 side. Wiring layers 50b and 50c, and vias 50d, 50e, and 50f are formed, for example, using a metallic material such as copper. Alternatively, wiring layers 50b and 50c, and vias 50d, 50e, and 50f may also be formed using a conductive material other than a metallic material, such as polysilicon, which has been given conductivity.

[0113] like Figure 3 As shown, wiring layer 50b is located in the same layer as wiring layers 51 and 52. For example, wiring layer 50b, wiring layer 51, and wiring layer 52 can be formed simultaneously. In this case, the thickness and material of wiring layer 50b, wiring layer 51, and wiring layer 52 are the same. Therefore, wiring layers 51 and 52 can also be formed of metals such as copper.

[0114] Furthermore, the number of wiring layers disposed in interlayer insulation layer 4 and the number of insulation layers in interlayer insulation layer 4 are not limited to Figure 3 The number of layers shown can be set arbitrarily.

[0115] The photoelectric conversion unit 15 supported on the semiconductor substrate 2 includes a first electrode 15a, a photoelectric conversion layer 15b, and a second electrode 15c. The photoelectric conversion unit 15 has a structure in which the photoelectric conversion layer 15b is spaced between the first electrode 15a and the second electrode 15c.

[0116] The first electrode 15a of the photoelectric conversion unit 15 is disposed on the side where light from the subject is incident. The first electrode 15a is formed of a transparent conductive material such as ITO (indium tin oxide). The first electrode 15a can be formed directly on the photoelectric conversion layer 15b, or other layers can be disposed between the first electrode 15a and the photoelectric conversion layer 15b.

[0117] The photoelectric conversion layer 15b receives incident light and generates positive and negative charges, specifically electron-hole pairs. The photoelectric conversion layer 15b is formed of organic materials or inorganic materials such as amorphous silicon. The photoelectric conversion layer 15b may also comprise layers made of organic materials and layers made of inorganic materials.

[0118] The second electrode 15c is located closer to the semiconductor substrate 2 than the first electrode 15a and the photoelectric conversion layer 15b. The second electrode 15c is separated from each pixel 10. Specifically, the second electrode 15c is spatially separated from the second electrodes 15c of adjacent pixels 10, thereby achieving electrical separation from them. The second electrode 15c collects the charge generated by photoelectric conversion in the photoelectric conversion layer 15b. The second electrode 15c is formed, for example, from metals such as aluminum and copper, metal nitrides, or polycrystalline silicon that has been made conductive by doping with impurities.

[0119] The first electrode 15a and the photoelectric conversion layer 15b are formed, for example, across multiple pixels 10. Alternatively, at least one of the first electrode 15a and the photoelectric conversion layer 15b may also be spatially separated from each other among multiple pixels 10, similar to the second electrode 15c.

[0120] In this embodiment, the first capacitor element 41 is disposed within the interlayer insulating layer 4 between the photoelectric conversion unit 15 and the semiconductor substrate 2. Specifically, the first capacitor element 41 is located between the wiring layers 51 and 52, including at least a portion of the signal lines connected to two or more pixels 10, and the semiconductor substrate 2. Figure 3 In the illustrated configuration, the first capacitor element 41 is located between the wiring layer 52, which includes a portion of the vertical signal line 18, and the semiconductor substrate 2, which includes a portion of the feedback line 25. In other words, in this embodiment, the first capacitor element 41 is configured to be located closer to the semiconductor substrate 2 than the wiring layer including a portion of the signal line connected to two or more pixels 10. That is, in this embodiment, the number of wiring layers above the first capacitor element 41 among the multiple wiring layers provided in the imaging device 100 is greater than the number of wiring layers below the first capacitor element 41. Alternatively, no wiring layer may be provided below the first capacitor element 41.

[0121] The first capacitor element 41 has an upper electrode 41a, a lower electrode 41c, and a dielectric layer 41b disposed between the upper electrode 41a and the lower electrode 41c. The upper electrode 41a is an example of the second electrode. Figure 3 In the cross-sectional view shown, it is located between the wiring layer 52 and the semiconductor substrate 2. The lower electrode 41c is an example of the first electrode, located between the upper electrode 41a and the semiconductor substrate 2.

[0122] A lower electrode 41c, a dielectric layer 41b, and an upper electrode 41a are sequentially stacked from the semiconductor substrate 2 side. The dielectric layer 41b contacts and covers the entire lower electrode 41c. The lower electrode 41c is not exposed to the outside because it is covered by the dielectric layer 41b. The upper electrode 41a contacts and covers the dielectric layer 41b. The upper electrode 41a and the lower electrode 41c do not contact each other because the dielectric layer 41b is disposed therebetween.

[0123] The first capacitor element 41 is a trench capacitor. Specifically, the first capacitor element 41 includes at least one trench portion. Figure 3 In the example shown, the first capacitor element 41 includes a flat portion 41d and two trench portions 41e and 41f. The two trench portions 41e and 41f are arranged such that they are separated by a connecting portion 50 in the cross-sectional view.

[0124] The flat portion 41d is the portion of the first capacitor element 41 located on the upper surface of the insulating layer 4c. The trench portion 41e is the portion of the first capacitor element 41 located within the trench 4t provided in the insulating layer 4c. The trench portion 41f is the portion of the first capacitor element 41 located within the trench 4u provided in the insulating layer 4c. On each of the flat portion 41d and the trench portions 41e and 41f, the lower electrode 41c and the dielectric layer 41b are formed with approximately equal film thicknesses. The upper electrode 41a is provided to fill the trenches 4t and 4u. Alternatively, the upper electrode 41a may also be formed with approximately equal film thicknesses.

[0125] With this configuration, not only the flat portion 41d but also the trench portions 41e and 41f contribute to the capacitance value of the first capacitor element 41. Compared to a parallel plate capacitor without trench portions 41e and 41f, the capacitance value of the first capacitor element 41 increases by an amount equivalent to the surface area of ​​the walls of the trenches 4t and 4u. In this way, by including trench portions 41e and 41f in the first capacitor element 41, the increase in the area occupied in the planar view can be suppressed, and the capacitance value can be increased. Furthermore, the first capacitor element 41 may also have only one of the trench portions 41e and 41f.

[0126] In this embodiment, at least one of the lower electrode 41c and the upper electrode 41a has two or more electrical contacts. These two or more electrical contacts are respectively electrically connected to different electrical components. Figure 3 In the example shown, the lower electrode 41c has two contacts 41g and 41h. The two contacts 41g and 41h are respectively disposed in the trench portions 41e and 41f.

[0127] Specifically, contact 41g is provided on the bottom surface of trench portion 41e. Furthermore, the bottom surface is the side of trench portion 41e closest to semiconductor substrate 2 (specifically, the lower surface). Contact 41g is a contact with via v1 located on the bottom surface of trench portion 41e. Via v1 is connected to impurity region 2b via plug P3. That is, contact 41g is electrically connected to reset transistor 36 and feedback transistor 38. Reset transistor 36 and feedback transistor 38 are each examples of electrical components electrically connected to contact 41g. In this way, one contact of the first capacitor element can also be connected to multiple electrical components.

[0128] Contact 41h is provided on the bottom surface of trench portion 41f. Contact 41h is a contact with via v2 at the bottom surface of trench portion 41f. Via v2 is connected to electrode 42a. Electrode 42a overlaps with gate electrode 34e through insulating film 42b. That is, the second capacitor element 42 is formed by electrode 42a and gate electrode 34e. The second capacitor element 42 is an example of an electrical component electrically connected to contact 41h. In this way, contacts 41g and 41h are connected to different electrical components.

[0129] Furthermore, the desired capacitance value for the second capacitor element 42 can be achieved by adjusting the material or thickness of the insulating film 42b, or the area of ​​overlap between the electrode 42a and the gate electrode 34e.

[0130] The method for forming the first capacitor element 41 will be described later. By providing the contacts 41g and 41h of the lower electrode 41c on the bottom surfaces of the trench portions 41e and 41f, the contact resistance between the lower electrode 41c and the vias v1 and v2 can be reduced. As a result, the unevenness (deviation) of the contact resistance value of each pixel 10 can be suppressed.

[0131] The lower electrode 41c of the first capacitor element 41, via v1, plug P3, via v2, and electrode 42a constitute part of the reset drain node 46. Figure 2 As shown, the charge storage node 44 is electrically coupled to the reset drain node 46 via the second capacitor element 42. Therefore, the potential of the charge storage node 44 may change as the potential of the reset drain node 46 changes.

[0132] That is, when the contact resistance between the lower electrode 41c and each of the vias v1 and v2 is uneven (deviation) among the pixels 10, it causes a change in the potential of the reset drain node 46. For example, even if the same amount of light is incident on each pixel 10 and the same amount of charge is generated from the photoelectric conversion unit 15, if the potential of the reset drain node 46 changes, the potential of the charge accumulation node 44 will not be the same in each pixel 10. Therefore, the resulting image appears to have noise (also known as graininess).

[0133] In this embodiment, by reducing the resistance value of the reset drain node 46, the potential of the reset drain node 46 in all pixels 10 can be made close to a certain value.

[0134] The upper electrode 41a of the first capacitor element 41 may be part of the wiring layer located between the second electrode 15c of the photoelectric conversion section 15 and the gate electrode 34e of the signal detection transistor 34. Figure 3 Electrical connections to pads not shown in the diagram. Pads are, for example, portions to which a specified voltage is applied. For example, a pad is connected to the upper electrode 41a via a sensitivity adjustment line 32. The upper electrode 41a is as follows... Figure 5 As shown, it extends in a plane parallel to the main surface of the semiconductor substrate 2. The lower electrode 41c and dielectric layer 41b are the same.

[0135] The upper electrode 41a and the lower electrode 41c are each formed using a conductive material such as a metal or a metal compound. As the conductive material, single metals such as titanium (Ti), aluminum (Al), gold (Au), or platinum (Pt), or alloys of two or more of these metals, can be used. Alternatively, conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), or hafnium nitride (HfN) can also be used. The upper electrode 41a and the lower electrode 41c can be formed using the same type of material or different types of materials.

[0136] The dielectric layer 41b is formed using a so-called high-k material with a higher dielectric constant than silicon oxide. Specifically, the dielectric layer 41b contains hafnium (Hf) or zirconium (Zr) oxide as the main component.

[0137] As described above, the first capacitor element 41 has a "MIM (Metal-Insulator-Metal) structure" in which a dielectric material is separated between two electrodes formed of metal or a metal compound. Here, in order to make the potential of the reset drain node 46 uniform across the pixels 10, it is desirable to minimize the leakage current flowing between the upper electrode 41a and the lower electrode 41c. This is because if the leakage current is large, the charge of the reset drain node 46 will flow to the sensitivity adjustment line 32 connected to the upper electrode 41a.

[0138] Theoretically, there should be no leakage current flowing through the dielectric layer 41b located between the upper electrode 41a and the lower electrode 41c. However, in this embodiment, in order to increase the capacitance value of the first capacitor element 41, a high-k (high dielectric) material with a high refractive index is used as the dielectric layer 41b. Therefore, the band gap of the dielectric layer 41b is narrowed. In addition, for the same purpose, the film thickness of the dielectric layer 41b is made thinner in the range of approximately 5 nm or more and approximately 40 nm or less. Due to these factors, the leakage current tends to increase in practice.

[0139] To suppress leakage current, the surface roughness of the upper electrode 41a and the lower electrode 41c can be reduced. There is a relationship between leakage current and the surface roughness of each electrode; the greater the surface roughness, the greater the leakage current. For example, when the surface roughness of the upper electrode 41a and the lower electrode 41c is large, the thickness of the dielectric layer 41b becomes uneven. The electric field tends to concentrate in the thinner parts of the dielectric layer 41b, thus increasing the leakage current.

[0140] In contrast, in this embodiment, TiN or TaN is used, for example, as the conductive material for forming the upper electrode 41a and the lower electrode 41c. This reduces the surface roughness during film formation using TiN or TaN, thereby suppressing leakage current in the first capacitor element 41. Furthermore, achieving uniform surface roughness in the upper electrode 41a and the lower electrode 41c also helps suppress uneven capacitance values ​​(deviations) in the first capacitor elements 41 of each pixel 10. Additionally, the low film resistance of TiN or TaN reduces the resistive component generated in the reset drain node 46.

[0141] Figure 5 This is a schematic plan view illustrating an example of the shape and arrangement of the first capacitor element 41 and the groove portions 41e and 41f included in the pixel 10 of the imaging device 100 according to this embodiment. Specifically, Figure 5 This illustrates an example of the positional relationship between the upper electrode 41a, trench portions 41e and 41f, vias v1 and v2, impurity regions 2b and 2c, and the second capacitor element 42 when viewed from the normal direction of the main surface of the semiconductor substrate 2 after removing the photoelectric conversion unit 15 from the pixel 10.

[0142] exist Figure 5 In the example shown, vias v1 and v2 are formed approximately at the center of each of the trenches 41e and 41f. Furthermore, the outlines of the trenches 41e and 41f are indicated by thick solid lines. Via v1 is located directly above the impurity region 2b, which serves as the connection destination. Via v2 is located directly above the electrode 42a. Furthermore, the arrangement and shape of the trenches 41e and 41f are not particularly limited.

[0143] like Figure 5 As illustrated, according to this embodiment, the first capacitor element 41 of a pixel 10 has two or more trench portions 41e and 41f. On the bottom surface of each of the trench portions 41e and 41f, as shown... Figure 3 The circuit includes contacts 41g and 41h. By electrically connecting contacts 41g and 41h to different electrical components, the reset drain node 46 can be designed according to the circuit diagram with the shortest path. Furthermore, the reset drain node 46 is formed in a layer lower than the wiring layer 51, which includes the feedback line 25 spanning multiple pixels 10, and the wiring layer 52, which includes the vertical signal line 18. Therefore, the reset drain node 46 has a structure less susceptible to noise, reducing the impact of parasitic capacitance.

[0144] like Figure 5 As shown, the first capacitor element 41 is arranged to occupy most of pixel 10 in the plan view. The plan view shape of the first capacitor element 41 is approximately rectangular, with an opening AP in the center. Furthermore, the plan view shape of the first capacitor element 41 is approximately the same as that of the upper electrode 41a. The opening AP is a through hole for the connection portion 50 to pass through. The location of the opening AP is not particularly limited.

[0145] In addition, in this embodiment, as referred to Figure 3 It can be seen that the first capacitor element 41 overlaps with at least a portion of the impurity region 2a in the plan view. Specifically, at least one of the upper electrode 41a and the lower electrode 41c overlaps with the impurity region 2a. For example, both the upper electrode 41a and the lower electrode 41c cover the entire impurity region 2a. That is, in the plan view, the entire impurity region 2a is located inside the upper electrode 41a and the lower electrode 41c.

[0146] The upper electrode 41a and the lower electrode 41c each have light-shielding properties. Therefore, light incident on the imaging device 100 that travels within the interlayer insulating layer 4 without being photoelectrically converted by the photoelectric conversion unit 15 is blocked by either the upper electrode 41a or the lower electrode 41c. This suppresses light reaching the impurity region 2a. When light is incident on the impurity region 2a, it may generate charge and cause noise. By suppressing light reaching the impurity region 2a, noise can be reduced.

[0147] [3. Manufacturing method]

[0148] Next, regarding the manufacturing method of the imaging device 100 according to this embodiment, particularly the process of manufacturing the first capacitor element 41, using... Figures 6A to 6I Please provide an explanation. Figures 6A to 6IThese are cross-sectional views illustrating the multiple processes included in the manufacturing of the first capacitor element 41. Hereinafter, the description focuses on one trench portion 41e, but the same applies to trench portion 41f.

[0149] First, such as Figure 6A As shown, vias v1 and v3 are formed in the insulating layer 4b deposited above the semiconductor substrate 2 (not shown). At this time, in Figure 6A Although not illustrated, vias v2 are also formed simultaneously. Specifically, firstly, a silicon oxide film is deposited as an insulating layer 4b using methods such as plasma CVD (chemical vapor deposition). Subsequently, the insulating layer 4b is patterned using photolithography and etching to form contact holes h1 and h3. Next, tungsten (W) or copper (Cu) and other metal materials are filled into the contact holes h1 and h3 using methods such as evaporation, sputtering, CVD, or electroplating to form vias v1 and v3.

[0150] Via v1 is, for example, a conductive via connected to the lower electrode 41c of the first capacitor element 41. Figure 6A In the example shown, in addition to via v1, via v3 is also formed. Via v3 is part of via 50d included in the connection portion 50 that connects to the second electrode 15c of the photoelectric conversion unit 15.

[0151] Next, as Figure 6B As shown, insulating layers 71 and 4c are sequentially formed on the entire surface of insulating layer 4b using plasma CVD. Insulating layer 71 is, for example, a silicon carbonitride (SiCN) film. Insulating layer 4c is, for example, a silicon oxide film. The silicon carbonitride film can suppress the diffusion of metals contained in vias v1 and v3. Furthermore, in Figure 3 The diagram of insulating layer 71 is omitted. Furthermore, the formation of insulating layer 71 is not mandatory and can be omitted.

[0152] Next, as Figure 6C As shown, a trench 4t is formed through the insulating layer 71 and the insulating layer 4c by dry etching. The trench 4t is a through hole used to expose the via v1. When the first capacitor element 41 includes multiple trench portions, multiple trenches are formed simultaneously. For example, trench 4t and trench 4u are formed simultaneously.

[0153] Next, as Figure 6DAs shown, the lower electrode 41c is formed. Specifically, firstly, a conductive thin film such as a titanium nitride film is formed. The titanium nitride film is formed, for example, by ALD (Atomic Layer Deposition) or plasma CVD. Next, after forming a photoresist mask on the conductive thin film, a portion of the conductive thin film is removed, for example, by dry etching with chlorine (Cl2) gas, and the photoresist mask is removed by oxygen ashing. Thus, as... Figure 6D As shown, a lower electrode 41c is formed with a specified shape.

[0154] Furthermore, by continuously performing the trench 4t formation process and the conductive film deposition process constituting the lower electrode 41c, the contact resistance between the lower electrode 41c and the via v1 can be reduced. In the trench 4t formation process, the surface of the via v1 needs to be exposed to the plasma, thus activating the state of the exposed surface of the via v1. Based on this, by forming the conductive film, metallic bonding is easily formed between the conductive film and the via v1, thereby suppressing contact resistance.

[0155] Next, as Figure 6E As shown, a dielectric layer 41b is formed. Specifically, a dielectric film is first formed on the entire surface of the insulating layer 4c, covering the lower electrode 41c. The dielectric film is, for example, a hafnium oxide film. The hafnium oxide film is formed, for example, by ALD or plasma CVD. Next, after forming a photoresist mask on the dielectric film, a portion of the dielectric film is removed, for example, by dry etching with chlorine gas, and the photoresist mask is removed by oxygen ashing. Thus, as... Figure 6E As shown, a dielectric layer 41b is formed with a predetermined shape. At this time, by leaving a larger residual dielectric layer 41b than the lower electrode 41c, the lower electrode 41c can be completely covered by the dielectric layer 41b in a manner that prevents the end of the lower electrode 41c from being exposed.

[0156] Next, as Figure 6F As shown, an upper electrode 41a is formed. Specifically, a conductive thin film, such as a titanium nitride film, is first formed on the entire surface of the insulating layer 4c, covering the dielectric layer 41b. The titanium nitride film is formed, for example, by an ALD method or a plasma CVD method. Next, after forming a photoresist mask on the conductive thin film, a portion of the conductive thin film is removed, for example, by dry etching with chlorine gas. Thus, as... Figure 6F As shown, an upper electrode 41a is formed with a predetermined shape. At this time, by leaving the upper electrode 41a larger than the dielectric layer 41b, the dielectric layer 41b can be completely covered by the upper electrode 41a in a way that the ends of the dielectric layer 41b are not exposed.

[0157] Alternatively, after forming the lower electrode 41c, the dielectric film and the conductive film can be continuously formed. Or, after continuously forming the dielectric film and the conductive film, the conductive film and the dielectric film can be patterned sequentially to form an upper electrode 41a and a dielectric layer 41b of a predetermined shape. In this case, the ends of the upper electrode 41a and the dielectric layer 41b are approximately coplanar, and the planar shapes of the upper electrode 41a and the dielectric layer 41b are approximately the same.

[0158] After the above processes, a first capacitor element 41 comprising a flat portion 41d and a groove portion 41e is formed.

[0159] Next, as Figure 6G As shown, the insulating layer 4d is formed on the entire surface in such a way that it covers the upper electrode 41a of the first capacitor element 41. The insulating layer 4d is, for example, a silicon oxide film.

[0160] Next, as Figure 6H As shown, vias v4 and v5 and wiring layers 50b and 53 are formed. The formation of vias v4 and v5 is performed in the same manner as that of vias v1 and v3. That is, after the contact holes are formed by photolithography and etching, vias v4 and v5 are formed by filling the formed contact holes with metal material.

[0161] Via v4 is part of via 50d included in the connecting portion 50. Figure 3 Although not illustrated, via v5 and wiring layer 53 are the parts that make the electrical connection between the upper electrode 41a of the first capacitor element 41 and the sensitivity adjustment line 32. Figure 6H In the middle, a through hole v5 is provided in such a way that it passes through the upper electrode 41a, but the through hole v5 can also contact the upper surface of the upper electrode 41a.

[0162] Furthermore, such as Figure 6I As shown, insulating layer 4e, vias 50e and v6, and wiring layers 50c and 54 are formed. Specifically, the forming method is the same as the forming method of insulating layer 4d, and the forming methods of vias v4 and v5 and wiring layers 50b and 53.

[0163] By repeatedly forming insulating layers, vias, and wiring layers, an interlayer insulating layer 4 with a desired number of layers can be formed. This allows various signal lines, including the sensitivity adjustment line 32, to be routed out of the pixel area.

[0164] [4. Variations]

[0165] Here, variations of implementation 1 are used. Figure 7 Please provide an explanation.

[0166] Figure 7This is a schematic cross-sectional view of the pixel 11 of the imaging device involved in this variation. Figure 7 As shown, an electrical contact 41i is provided on the side of the trench portion 41f of the first capacitor element 41. Specifically, the lower electrode 41c of the first capacitor element 41 has an electrical contact 41i. The electrical contact 41i is the junction portion between the lower electrode 41c and the wiring layer 55.

[0167] In this modified example, the trench portion 41f is provided in a manner that penetrates the insulating layers 4c and 4g. The insulating layer 4g is the insulating layer located between the insulating layers 4b and 4c. By providing the trench portion 41f in a manner that penetrates multiple insulating layers 4c and 4g, a wiring layer 55 can be provided between the insulating layers 4c and 4g. As a result, a contact 41i can be formed on the side of the trench portion 41f.

[0168] Furthermore, the number of insulating layers penetrating the trench portion 41f is not limited to two layers, but can also be three or more layers. Therefore, multiple electrical contacts can be provided at different heights on the side of the trench portion 41f.

[0169] The wiring layer 55 is electrically connected to the upper end of the via v2. The wiring layer 55 is formed to expose the side of the trench 4u provided in the insulating layers 4c and 4g. Thus, by forming a lower electrode 41c along the side of the trench 4u, the wiring layer 55 can be electrically connected to the lower electrode 41c. The first capacitor element 41 is connected to the electrode 42a of the second capacitor element 42 via the electrical contact 41i of the lower electrode 41c, the wiring layer 55, and the via v2.

[0170] As described above, the electrical contacts of the lower electrode 41c of the first capacitor element 41 may not be located at the bottom of the trench portion 41f, but may be located on the side of the trench portion 41f. Alternatively, the electrical contacts of the lower electrode 41c may be located on the flat portion 41d of the first capacitor element 41.

[0171] (Implementation Method 2)

[0172] Next, implementation method 2 will be described.

[0173] In the imaging device according to Embodiment 2, the number of groove portions included in the first capacitor element is different compared to that according to Embodiment 1. Hereinafter, the description will focus on the differences from Embodiment 1, and the description of common points will be omitted or simplified.

[0174] Figure 8 This is a schematic cross-sectional view of the pixel 110 of the camera device according to this embodiment. Figure 9This is a schematic plan view showing an example of the shape and arrangement of the first capacitor element 141 and the groove portion included in the pixel 110 of the camera device according to this embodiment.

[0175] like Figure 8 As shown, pixel 110 differs from pixel 10 in Embodiment 1 in that it has a first capacitor element 141 instead of the first capacitor element 41. The first capacitor element 141 includes three or more trench portions. Specifically, the first capacitor element 141 is as follows: Figure 9 As shown, it includes six grooves: 41e, 41f, 141a, 141b, 141c and 141d.

[0176] In the grooves 41e and 41f, such as Figure 8 As shown, electrical contacts 41g and 41h are provided similarly to those in Embodiment 1. No electrical contacts are provided in the trench portions 141a, 141b, 141c, and 141d. The bottom and side surfaces of the trench portion 141a are in contact with and covered by the insulating layers 4b and 4c, respectively. Figure 9 As shown in the plan view, no through holes are provided that overlap with the groove portion 141a. The same applies to the groove portions 141b, 141c, and 141d.

[0177] In this embodiment, the first capacitor element 141 includes numerous trenches, which increases the capacitance value. The capacitance value of the first capacitor element 141 varies depending on the type of image sensor. For example, when capturing a bright scene, the reset transistor 36 is turned on, using both the charge accumulation node 44 and the reset drain node 46 as charge accumulation sections. In this case, the larger the capacitance value of the first capacitor element 141, the less the gate potential of the signal detection transistor 34 will rise, even with a large amount of charge accumulated. Therefore, the conversion gain can be switched, providing an unexposed image even in bright scenes.

[0178] Furthermore, the number of grooves without electrical contacts is not limited to four. The number of grooves without electrical contacts can be one, two, three, or more than five. Conversely, the number of grooves with electrical contacts is not limited to two; it can be one, three, or more than three.

[0179] Furthermore, in this embodiment, such as Figure 8 and Figure 9 As shown, wiring layers 51 and 52 are provided above the first capacitor element 141. As described above, wiring layers 51 and 52 include, for example, vertical signal lines 18 and feedback lines 25.

[0180] At this time, parasitic capacitance is generated between the upper electrode 41a of the first capacitor element 141 and the wiring layers 51 and 52. In particular, the potentials of the vertical signal line 18 and the feedback line 25 change over time due to the brightness of each pixel 10. Therefore, the parasitic capacitance component is detected as noise component of the vertical signal line 18 and the feedback line 25.

[0181] The parasitic capacitance is proportional to the dielectric constant of the insulating film between wiring layers 51 and 52 and the upper electrode 41a, and the differential voltage generated between them. In contrast, to reduce the parasitic capacitance, it is also possible to... Figure 10 As shown, the upper electrode 41a of the first capacitor element 141 does not overlap with the wiring layers 51 and 52. This allows for the suppression of noise components based on parasitic capacitance. Figure 10 This is a schematic plan view showing an example of the shape and arrangement of the first capacitor element 141 and the groove portion included in the pixel 111 of the imaging device according to the modified embodiment 2.

[0182] In this variation, as compared Figure 8 and Figure 10 As can be seen, in the planar view, the area occupied by the first capacitor element 141 within the pixel becomes smaller. Therefore, the capacitance value of the flat portion 41d of the first capacitor element 141 becomes smaller.

[0183] On the other hand, in order for the first capacitor element 141 to achieve the desired capacitance value, in the plan view, the first capacitor element 141 needs to ensure a certain electrode area. Ensuring this electrode area is in a trade-off with suppressing overlap with the wiring layer. That is, if the electrode area is increased, it is difficult to avoid overlap with the wiring layer.

[0184] In contrast, in the first capacitor element 141 of this modified example, by avoiding overlap with the wiring layer in the plan view and providing multiple trench portions 41e, 41f, 141a, 141b, 141c, and 141d, the electrode area can be effectively increased by utilizing the sidewalls of these trench portions. This suppresses noise components caused by parasitic capacitance and increases the capacitance value of the first capacitor element 141.

[0185] (Implementation Method 3)

[0186] Next, implementation method 3 will be described.

[0187] The camera device according to Embodiment 3 has a different circuit configuration compared to the camera devices according to Embodiments 1 and 2. Hereinafter, the description will focus on the differences from Embodiments 1 and 2, and the description of common points will be omitted or simplified.

[0188] Figure 11This diagram illustrates an example of the circuit configuration of the pixel 210 in the imaging device according to this embodiment. Figure 11 As shown, pixel 210 differs from pixel 10 in Embodiment 1 in that it lacks the second capacitor element 42 and the feedback transistor 38. Pixel 210 does not have a reset drain node 46. Furthermore, in pixel 210, the reset transistor 36 is disposed between one of the pair of electrodes of the first capacitor element 41 and the feedback line 25. That is, the reset transistor 36 is disposed in the same position as the feedback transistor 38 in Embodiment 1.

[0189] like Figure 11 As shown, the charge accumulation node 44 is connected to one of the pairs of electrodes of the first capacitor element 41. Therefore, the first capacitor element 41 functions as a charge accumulation section. That is, the signal charge generated in the photoelectric conversion section 15 is also accumulated in the first capacitor element 41. As a result, the amount of signal charge accumulated in the pixel 210 can be increased, thus suppressing overexposure even in bright scenes.

[0190] Figure 12 This is a schematic cross-sectional view of the pixel 210 provided in the camera device according to this embodiment. Figure 12 As shown, alternative Figure 3 The feedback transistor 38 shown has a reset transistor 36 located at the same position. That is, the impurity region 2b is one of the source and drain regions of the reset transistor 36. The impurity region 2c is the other of the source and drain regions of the reset transistor 36.

[0191] In addition, such as Figure 12 As shown, pixel 210 has a connecting portion 250 instead of connecting portion 50. Connecting portion 250 does not have... Figure 3 The plug P1 and wiring section 50a are shown. The connecting section 250 electrically connects the second electrode 15c of the photoelectric conversion section 15 to the gate electrode 34e of the signal detection transistor 34.

[0192] The gate electrode 34e is connected to the via v2 via the plug P4 and the wiring portion 250a. The via v2 is connected to the lower electrode 41c of the first capacitor element 41, similar to that in Embodiment 1. With this configuration, as... Figure 12As shown, the second electrode 15c of the photoelectric conversion unit 15 is connected to the impurity region 2b via the connection portion 250, the gate electrode 34e, the plug P4, the wiring portion 250a, the via v2, the lower electrode 41c of the first capacitor element 41, the via v1, and the plug P3. In other words, the second electrode 15c, the connection portion 250, the gate electrode 34e, the plug P4, the wiring portion 250a, the via v2, the lower electrode 41c of the first capacitor element 41, the via v1, the plug P3, and the impurity region 2b function as a charge accumulation node 44.

[0193] As described above, in this embodiment, the capacitance of the charge storage unit that stores the signal charge generated in the photoelectric conversion unit 15 can be increased, thus suppressing overexposure even in bright scenes.

[0194] (Implementation Method 4)

[0195] Next, implementation method 4 will be described.

[0196] In the imaging device according to Embodiment 4, the difference from the imaging devices according to Embodiments 1 to 3 is that the electrical contacts are provided on the upper electrode. Hereinafter, the description will focus on the differences from Embodiments 1 to 3, and the description of common points will be omitted or simplified.

[0197] Figure 13 This is a schematic cross-sectional view of the pixel 310 provided in the camera device according to this embodiment. Figure 13 As shown, pixel 310 has a connecting portion 350 instead of connecting portion 50, compared to pixel 10 in Embodiment 1.

[0198] The connection portion 350 includes a plug P5, a wiring portion 350a, an electrode 342a, vias v7, 350d, 50e, and 50f, and wiring layers 50b and 50c. The connection portion 350 electrically connects the second electrode 15c of the photoelectric conversion unit 15 to the gate electrode 34e of the signal detection transistor 34. Additionally, although in Figure 13 Not shown in the figure, the gate electrode 34e is electrically connected to the impurity region 2a.

[0199] In addition, such as Figure 13 As shown, compared with the pixel 10 according to Embodiment 1, pixel 310 has a first capacitor element 341 and a second capacitor element 342 instead of the first capacitor element 41 and the second capacitor element 42. The first capacitor element 341 has an upper electrode 341a, a dielectric layer 41b and a lower electrode 41c.

[0200] The upper electrode 341a of the first capacitor element 341 has an electrode portion 342b. The electrode portion 342b is provided such that it extends from the upper electrode 341a toward the upper surface of the insulating layer 4c. Specifically, in a plan view, the electrode portion 342b overlaps with a portion of the electrode 342a included in the connecting portion 350. Thus, the second capacitor element 342 is formed by the electrode portion 342b and a portion of the electrode 342a.

[0201] Additionally, the upper electrode 341a of the first capacitor element 341 has contacts 341g and 341h. Contacts 341g and 341h are disposed on a portion extending from the insulating layer 4c of the upper electrode 341a.

[0202] Contact 341g is disposed on the bottom surface of the upper electrode 341a. Contact 341g is connected to via v8 and connected to impurity region 2b via via v8 and plug P3. That is, contact 341g is connected to reset transistor 36 and feedback transistor 38. In this embodiment, as in embodiment 1, reset transistor 36 and feedback transistor 38 are examples of electrical components electrically connected to contact 341g.

[0203] Contact 341h is the connection portion between the upper electrode 341a and the electrode portion 342b. That is, contact 341h is connected to the second capacitor element 342. In this embodiment, the second capacitor element 342 is an example of an electrical component electrically connected to contact 341h.

[0204] In addition, Figure 13 In the example shown, a contact 41g is also provided on the lower electrode 41c. Contact 41g is connected to the via v1. Although in Figure 13 As not shown in the diagram, contact 41g is connected to the sensitivity adjustment line 32 via via v1.

[0205] As described above, in the imaging device according to this embodiment, two contacts 341g and 341h are provided on the upper electrode 341a of the first capacitor element 341. Furthermore, contacts 341g and 341h are provided in the portion of the first capacitor element 341 other than the groove portion 41e. Alternatively, contacts 341g and 341h may also be provided on the upper surface of the upper electrode 341a. That is, the via provided on the first capacitor element 341 can also be electrically connected to the upper electrode 341a.

[0206] Alternatively, at least one contact may also be provided in the upper electrode 341a within the trench portion 41e. For example, in Figure 13In this configuration, the upper electrode 341a is provided to fill the trench 4t. However, the upper electrode 341a may also be formed with a uniform film thickness within the trench 4t, and may have the same curved shape along the bottom and side surfaces of the trench 4t as the dielectric layer 41b and the lower electrode 41c. In this case, the contact may also be provided in the trench portion 41e on the bottom surface inside the upper electrode 341a. Alternatively, the contact may be provided on the side surface inside the upper electrode 341a of the trench portion 41e.

[0207] (Implementation Method 5)

[0208] Next, implementation method 5 will be described.

[0209] In the imaging device according to Embodiment 5, the difference from the imaging devices according to Embodiments 1 to 4 is that the photoelectric conversion unit is disposed within a semiconductor substrate. Hereinafter, the description will focus on the differences from Embodiments 1 to 4, omitting or simplifying the description of commonalities.

[0210] Figure 14 This is a schematic cross-sectional view of the pixel 410 of the camera device according to this embodiment.

[0211] like Figure 14 As shown, pixel 410 has a photodiode PD instead of photoelectric conversion unit 15. The photodiode PD is an example of a photoelectric conversion unit, such as a photodiode with a PN junction. The photodiode PD is formed from impurity regions or the like formed in the semiconductor substrate 2.

[0212] The imaging device described in this embodiment is a back-illuminated CMOS image sensor. Furthermore, the back side is one of the two main surfaces of the semiconductor substrate 2, and is the side opposite to the main surface where the interlayer insulating layer 4 is disposed. In the imaging device described in this embodiment, light originates from the back side of the semiconductor substrate 2, i.e. Figure 14 The light is incident above the surface of the paper.

[0213] Furthermore, the camera device according to this embodiment has a chip stacking structure. Specifically, the camera device includes a first chip 410a and a second chip 410b. The first chip 410a and the second chip 410b are arranged to overlap vertically, i.e., they are stacked.

[0214] like Figure 14As shown, the first chip 410a includes a semiconductor substrate 2 and an interlayer insulating layer 4. The second chip 410b includes a semiconductor substrate 402 and an interlayer insulating layer 404. After the first chip 410a and the second chip 410b are manufactured, they are stacked to form an imaging device with pixels 410. Specifically, the interlayer insulating layer 4 formed on the main surface of the semiconductor substrate 2 is bonded to the interlayer insulating layer 404 formed on the main surface of the semiconductor substrate 402. Furthermore, in Figure 14 In the diagram, the bonding surface is schematically represented by a dashed line. In this embodiment, the interlayer insulating layer 4 has five insulating layers 4a, 4b, 4c, 4d, and 4e. The interlayer insulating layer 404 has two insulating layers 404a and 404b. The number of layers of each of the interlayer insulating layers 4 and 404 is not limited thereto.

[0215] exist Figure 14 In the example shown, a reset transistor 36, a feedback transistor 38, and a first capacitor element 141 are provided in the first chip 410a. A signal detection transistor 34 and an address transistor 40 are provided in the second chip 410b. The second capacitor element 42 can be disposed within either the interlayer insulating layer 4 or the interlayer insulating layer 404. The components included in the signal detection circuit SC of pixel 410 can be disposed in either the first chip 410a or the second chip 410b.

[0216] like Figure 14 As shown, a conductive terminal portion 60 is provided on the uppermost layer (the lower layer on the paper surface) of the interlayer insulating layer 4e. Similarly, a conductive terminal portion 460 is provided on the uppermost layer of the interlayer insulating layer 404b. By contacting and connecting the terminal portions 60 and 460, electrical connections can be made between the components disposed on the semiconductor substrate 2 and the components disposed on the semiconductor substrate 402.

[0217] In this embodiment, a contact 41g is provided on the bottom surface of the trench portion 41e of the first capacitor element 141. The contact 41g is connected to the reset transistor 36 via a via v1.

[0218] Additionally, a contact 41h is provided on the bottom surface of the trench portion 41f of the first capacitor element 141. Figure 14 Although not shown in the figure, contact 41h is electrically connected to the second capacitor element 42. The second capacitor element 42 is, for example, disposed within the first chip 410a. In this way, two or more electrical components connected to the two or more electrical contacts of the first capacitor element 141 are disposed in the first chip 410a on which the first capacitor element 141 is disposed.

[0219] Furthermore, the two or more electrical components connected to the two or more electrical contacts of the first capacitor element 141 may not be housed in the first chip 410a. At least one or all of the electrical components may also be connected to the second chip 410b.

[0220] Figure 15 This is a schematic cross-sectional view of the pixel 411 of the imaging device involved in this variation. Figure 15 In pixel 411 shown, a reset transistor 36 and a first capacitor element 141 are provided in the first chip 410a. A feedback transistor 38 is provided in the second chip 410b. The signal detection transistor 34, the address transistor 40, and the second capacitor element 42 can be provided in either the first chip 410a or the second chip 410b.

[0221] like Figure 15 As shown, pixel 411 includes a first capacitor element 341. The upper electrode 341a of the first capacitor element 341 includes contacts 341g and 341i. Contact 341g is electrically connected to a reset transistor 36. That is, the reset transistor 36 is an example of an electrical component. Contact 341i is electrically connected to a feedback transistor 38. That is, the feedback transistor 38 is an example of an electrical component.

[0222] In this way, two or more electrical components connected to two or more contacts of the first capacitor element 341 can also be respectively disposed on the first chip 410a and the second chip 410b. That is, the contacts and electrical components can also be electrically connected by stacking the first chip 410a and the second chip 410b.

[0223] (Other implementation methods)

[0224] The above description relates to one or more imaging devices based on various embodiments, but this disclosure is not limited to these embodiments. Various modifications conceived by those skilled in the art to these embodiments, as well as combinations of structural elements from different embodiments, are also included within the scope of this disclosure, provided they do not depart from its spirit.

[0225] Figure 16 This is a schematic cross-sectional view of the pixel 12 of the imaging device involved in other variations of Embodiment 1. For example... Figure 16 As shown, in pixel 12, the upper electrode 41a of the first capacitor element 41 is electrically connected to the sensitivity adjustment line 32 via a via. The sensitivity adjustment line 32 extends from within the pixel area to outside the pixel area. Outside the pixel area, the sensitivity adjustment line 32 is electrically connected to the pad 70 via a via. Therefore, the upper electrode 41a is electrically connected to the pad 70 via the sensitivity adjustment line 32.

[0226] For example, in the above embodiments, the number of insulating layers and wiring layers included in the interlayer insulating layer of the imaging device is not particularly limited. Furthermore, the position of the capacitor element within the interlayer insulating layer is not particularly limited.

[0227] Alternatively, for example, the number of trench portions included in the first capacitor element may be only one. It is also possible that no electrical contacts are provided in any of the trench portions included in the first capacitor element. In this case, two or more electrical contacts may be provided on either the upper electrode of the flat portion of the first capacitor element or on the lower electrode of the flat portion. The electrical contacts may be provided on either the upper or lower surface of the upper or lower electrode.

[0228] Alternatively, for example, the dielectric layer 41b may not be a thin film made of high-k (high dielectric) material, but rather an insulating film such as a silicon oxide film or a silicon nitride film.

[0229] Alternatively, for example, the transistors included in the signal detection circuit SC of the camera device can be P-channel MOSFETs. Furthermore, the transistors can also be bipolar transistors instead of FETs.

[0230] Furthermore, the above embodiments can be modified, substituted, added, omitted, etc., within the scope of the claims or their equivalents.

[0231] Industrial applicability

[0232] The imaging device disclosed herein is useful for, for example, image sensors, digital cameras, etc. For instance, the imaging device disclosed herein can be used in medical cameras, robotic cameras, security cameras, and cameras used in vehicles, etc.

[0233] Explanation of reference numerals in the attached figures:

[0234] 2. 402 Semiconductor Substrate

[0235] Impurity regions 2a, 2b, 2c

[0236] 2t, 2u component separation area

[0237] 4. 404 interlayer insulation layer

[0238] Insulation layers 4a, 4b, 4c, 4d, 4e, 4f, 4g, 71, 404a, 404b

[0239] 4t, 4u trench

[0240] 10, 11, 110, 111, 210, 310, 410, 411 pixels

[0241] 15. Photoelectric Conversion Unit

[0242] 15a First Electrode

[0243] 15b Photoelectric conversion layer

[0244] 15c, second electrode

[0245] 16 Vertical Scanning Circuit

[0246] 17. Accumulation Control Line

[0247] 18 Vertical signal lines

[0248] 19 Load Circuit

[0249] 20-column signal processing circuits

[0250] 21 Horizontal Signal Readout Circuit

[0251] 22 Power wiring

[0252] 23 Horizontal Common Signal Line

[0253] 24 Inverting Amplifier

[0254] 25 Feedback Line

[0255] 26 Reset signal line

[0256] 28 Feedback control line

[0257] 30 Address Signal Lines

[0258] 32 Sensitivity Adjustment Line

[0259] 34 Signal detection transistor

[0260] 34e, 36e, 38e gate electrodes

[0261] 34g, 36g, 38g gate insulating layer

[0262] 36 Reset transistor

[0263] 38 feedback transistors

[0264] 40 Address Transistors

[0265] 41, 141, 341 First capacitor element

[0266] 41a, 341a upper electrode

[0267] 41b Dielectric layer

[0268] 41c Lower electrode

[0269] 41d Flat section

[0270] 41e, 41f, 141a, 141b, 141c, 141d Grooves

[0271] 41g, 41h, 41i, 341g, 341h, 341i contacts

[0272] 42, 342 Second capacitor element

[0273] 42a and 342a electrodes

[0274] 42b Insulating Film

[0275] 44 Charge accumulation nodes

[0276] 46. ​​Reset drain node

[0277] 50, 250, 350 connecting parts

[0278] 50a, 250a, 350a Wiring Department

[0279] 50b, 50c, 51, 52, 53, 54, 55 wiring layers

[0280] 50d, 50e, 50f, 350d, v1, v2, v3, v4, v5, v6, v7, v8 vias

[0281] 60, 460 terminal section

[0282] 100 camera devices

[0283] 342b Electrode Section

[0284] 410a First Chip

[0285] 410b Second Chip

[0286] h1, h3 contact holes

[0287] AP opening

[0288] FC feedback circuit

[0289] P1, P2, P3, P4, P5 plugs

[0290] PD photodiode

[0291] RA pixel area

[0292] SC signal detection circuit

Claims

1. A camera device, comprising: Semiconductor substrates; and Multiple pixels, Each of the plurality of pixels includes a first capacitor element, the first capacitor element including a first electrode disposed above the semiconductor substrate, a second electrode disposed above the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode. At least one selected from the group consisting of the first electrode and the second electrode has: a first electrical contact electrically connected to the first electrical element, and a second electrical contact electrically connected to a second electrical element different from the first electrical element. The first capacitor element includes a first trench portion and a second trench portion having a trench shape. The first electrical contact is disposed in the first groove portion. The second electrical contact is disposed in the second trench.

2. The camera device as described in claim 1, The first electrical contact is disposed on the bottom surface of the first groove; or The second electrical contact is disposed on the bottom surface of the second groove; or The first electrical contact is disposed on the bottom surface of the first groove portion and the second electrical contact is disposed on the bottom surface of the second groove portion.

3. The camera device as described in claim 1 or 2, The first capacitor element also includes a third trench portion. No electrical contacts are provided in the third groove.

4. The camera device as described in claim 1 or 2, The first electrode is positioned closer to the semiconductor substrate than the second electrode, and has the first electrical contact and the second electrical contact.

5. The camera device as described in claim 1 or 2, The second electrode is positioned further away from the semiconductor substrate than the first electrode, and has the first electrical contact and the second electrical contact.

6. The camera device as described in claim 1 or 2, The first electrode and the second electrode contain TiN or TaN.

7. The camera device as described in claim 1 or 2, The camera device also includes multiple wiring layers disposed above the semiconductor substrate. The number of wiring layers located above the first capacitor element is greater than the number of wiring layers located below the first capacitor element.

8. The camera device as described in claim 1 or 2, Both the first electrical contact and the second electrical contact are connected to vias.

9. The camera device as described in claim 1 or 2, Each pixel in the plurality of pixels also includes: The photoelectric conversion unit converts light into electrical charge; as well as Impurity regions accumulate the charge, are electrically connected to the photoelectric conversion unit, and are disposed within the semiconductor substrate. In the plan view, the first capacitor element completely overlaps with the impurity region.

10. The camera device as described in claim 1 or 2, Each pixel in the plurality of pixels also includes: The photoelectric conversion unit converts light into electrical charge; Impurity regions accumulate the charge, are electrically connected to the photoelectric conversion unit, and are disposed within the semiconductor substrate; A transistor, electrically connected to the impurity region; as well as Second capacitor element, The transistor is one of the first electrical contact and the second electrical contact. The second capacitor element is the other of the first electrical contact and the second electrical contact.

11. The camera device as claimed in claim 10, The transistor is a reset transistor that resets the charge.

12. The camera device as claimed in claim 10, The second capacitor element is electrically connected to the impurity region via the first electrode or the second electrode.

13. The camera device as described in claim 1 or 2, Each pixel in the plurality of pixels also includes: The photoelectric conversion unit converts light into electrical charge; as well as Impurity regions accumulate the charge, are electrically connected to the photoelectric conversion unit, and are disposed within the semiconductor substrate. The first electrode is positioned closer to the semiconductor substrate than the second electrode and is electrically connected to the impurity region. The second electrode is electrically connected to the pad to which a specified voltage value is applied.

14. The camera device as claimed in claim 13, The camera device also includes: A sensitivity adjustment line, electrically connected to the pad and the second electrode, is used to adjust the sensitivity of the camera device.

15. The camera device as described in claim 1 or 2, The camera device also includes a signal line connected to the plurality of pixels, and the signal line has a voltage that varies over time. Each of the plurality of pixels further includes an impurity region, which accumulates charge generated by photoelectric conversion and is disposed within the semiconductor substrate. One of the first trench portion and the second trench portion is located between the impurity region and the signal line and on a line connecting at least a portion of the impurity region and the signal line.

16. The camera device as described in claim 1 or 2, The camera device also includes a signal line connected to the plurality of pixels, and the signal line has a voltage that varies over time. Each pixel in the plurality of pixels also includes: The photoelectric conversion unit converts light into electrical charge; The first via connects the semiconductor substrate to the photoelectric conversion unit; as well as The second via connects the signal line to the semiconductor substrate. One of the first groove portion and the second groove portion is located between the first through hole and the second through hole and on the line connecting the first through hole and the second through hole.

17. The camera device as described in claim 1 or 2, The camera device also includes a signal line connected to the plurality of pixels, and the signal line has a voltage that varies over time. Each of the plurality of pixels further includes a second via, which connects the signal line to the semiconductor substrate. In the plan view, the first capacitor element does not overlap with the second via.

18. The camera device as described in claim 1 or 2, Each pixel in the plurality of pixels also includes: The photoelectric conversion unit converts light into electrical charge; as well as The first via connects the semiconductor substrate to the photoelectric conversion unit. In the cross-sectional view, the first through hole is located between the first groove portion and the second groove portion.

Images