VCSEL arrays with tight pitch and high efficiency

Abstract

The present invention discloses an optoelectronic device (20, 120) comprising a semiconductor substrate (24). A first set of thin film layers is disposed on the substrate and defines a lower distributed Bragg reflector (DBR) stack (42). A second set of thin film layers (40, 46) is disposed above the lower DBR stack and defines an optical emission region (43), which is contained in a table defined by a plurality of grooves (28, 128) that are disposed around the optical emission region without completely surrounding the optical emission region. A third set of thin film layers is disposed above the optical emission region and defines an upper DBR stack (44, 124). An electrode (30, 130) is disposed around the table in the gaps between the grooves and is configured to apply an excitation current to the optical emission region.

Description

Technical Field

[0001] The present invention relates generally to optoelectronic devices and, more particularly, to solid state emitter arrays and methods of making the same. Background Art

[0002] In a vertical cavity surface emission layer (VCSEL) array known in the art, multiple VCSELs are formed on a common substrate. The optical emission region of each VCSEL (which typically includes a quantum well structure) is contained in a table surrounded by one or more grooves. The optical aperture of the VCSEL is defined by an oxide confinement layer surrounding the optical emission region. The metal anode contact of each VCSEL is typically formed above the table in the form of a ring that surrounds the optical aperture of the VCSEL. A common cathode contact is formed on the opposite side of the substrate.

[0003] The concentric arrangement of optical holes surrounded by anode contacts (which in turn are surrounded by trenches) sets a lower limit on the pitch of the VCSEL array: the distance between adjacent VCSELs includes both the width of the trenches and the width of the metal anode contacts. Summary of the invention

[0004] Embodiments of the present invention described below provide improved solid state emitter arrays and methods of making the same.

[0005] According to an embodiment of the present invention, an optoelectronic device including a semiconductor substrate is thus provided. A first group of thin film layers is disposed on the substrate and defines a lower distributed Bragg reflector (DBR) stack. A second group of thin film layers is disposed above the lower DBR stack and defines an optical emission region, which is accommodated in a table defined by a plurality of grooves, which are disposed around the optical emission region without completely surrounding the optical emission region. A third group of thin film layers is disposed above the optical emission region and defines an upper DBR stack. An electrode is disposed around the table in the gap between the grooves and is configured to apply an excitation current to the optical emission region.

[0006] In a disclosed embodiment, the device includes a transparent conductive layer in electrical contact with the electrode and extending across the mesa above at least the second set of thin film layers.

[0007] In some embodiments, the third set of thin-film layers includes a dielectric layer. Typically, the electrode includes a metal deposited in a via extending through the third set of thin-film layers.

[0008] Additionally or alternatively, the third set of thin film layers includes an epitaxial semiconductor layer.In the disclosed embodiments, electrodes are deposited over the third set of thin film layers.

[0009] In some embodiments, the first, second, and third groups of thin film layers and the electrodes are disposed on an upper side of the semiconductor substrate, and the device includes a cathode layer on a lower side of the semiconductor substrate opposite the upper side.

[0010] According to an embodiment of the present invention, there is also provided an optoelectronic device including a semiconductor substrate. A first group of thin film layers is disposed on the substrate and defines a lower distributed Bragg reflector (DBR) stack. A second group of thin film layers is disposed above the lower DBR stack and defines a plurality of optical emission regions, which are accommodated in corresponding mesas defined by a plurality of grooves, which are disposed around each optical emission region in the optical emission region without completely surrounding the optical emission region. A third group of thin film layers is disposed above each optical emission region in the optical emission region and defines an upper DBR stack. An electrode is disposed in the gap between the grooves around each of the mesas and is configured to apply an excitation current to each optical emission region in the optical emission region.

[0011] In a disclosed embodiment of the present invention, at least one of the grooves is common to a pair of adjacent mesas. Additionally or alternatively, at least one of the electrodes is common to a pair of adjacent mesas.

[0012] In some embodiments, a first group of thin film layers, a second group of thin film layers, and a third group of thin film layers and electrodes are disposed on an upper side of a semiconductor substrate, and the device includes a cathode layer on a lower side of the semiconductor substrate opposite to the upper side, wherein the cathode layer is common to multiple optical emission regions.

[0013] According to an embodiment of the present invention, a method for manufacturing an optoelectronic device is further provided. The method includes depositing a first group of thin film layers on a semiconductor substrate to define a lower distributed Bragg reflector (DBR) stack. A second group of thin film layers is deposited above the lower DBR stack to define an optical emission region. A plurality of grooves are formed around the optical emission region without completely surrounding the optical emission region, thereby defining a table that accommodates the optical emission region. A third group of thin film layers is deposited above the optical emission region to define an upper DBR stack. Electrodes are deposited around the table in the gaps between the grooves. Electrical contacts are coupled to the electrodes to apply an excitation current to the optical emission region.

[0014] The present invention will be more fully understood from the following detailed description of embodiments of the present invention in conjunction with the accompanying drawings, in which: BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic front view of an optoelectronic device including a VCSEL array according to an embodiment of the present invention;

[0016] Figure 2A and Figure 2B are respectively a schematic front view and a schematic cross-sectional view of a pair of VCSELs in an array according to an embodiment of the present invention;

[0017] Figure 3A and Figure 3B are respectively a schematic front view and a schematic cross-sectional view of a pair of VCSELs in an array according to an alternative embodiment of the present invention;

[0018] FIG. 4A to FIG. 4G are schematic cross-sectional views showing successive stages in the fabrication of a VCSEL array according to an embodiment of the present invention;

[0019] Figure 5A and Figure 5B are respectively a schematic front view and a schematic cross-sectional view of a pair of VCSELs in an array according to another embodiment of the present invention;

[0020] Fig. 6A and Figure 6B are a schematic front view and a schematic cross-sectional view, respectively, of a pair of VCSELs in an array according to a further alternative embodiment of the present invention; and

[0021] 7A to 7F are schematic cross-sectional views showing successive stages in the fabrication of a VCSEL array according to another embodiment of the present invention. DETAILED DESCRIPTION

[0022] Overview

[0023] Embodiments of the invention described herein provide a new design in which the minimum pitch between emitters in a VCSEL array is significantly reduced by moving the metal contact ring completely out of the emitter mesa. The grooves defining the mesa are arranged around the optical emission area of ​​the VCSEL without completely surrounding the optical emission area. Electrodes (e.g., configured as metal anode contact members) are arranged around the mesa in the gaps between the grooves.

[0024] Using this design approach, the pitch of the VCSEL array can be reduced relative to devices known in the art, and the density of emitters on the chip can be increased. This innovation makes it possible to increase the total radiant flux emitted from a chip of a given size, as well as to generate higher resolution patterns when the VCSEL beam is used to produce patterned illumination. Although the accompanying drawings show VCSELs with a certain number of grooves and electrodes arranged symmetrically in a ring around the table, the principles of the present invention may alternatively be implemented using a larger or smaller number of grooves and electrodes, which can have the same relative sizes or different relative sizes in both symmetrical and asymmetrical arrangements.

[0025] Changes in VCSEL geometry and reductions in electrode size associated with embodiments of the present invention tend to increase the resistance of the VCSEL circuit and, therefore, can reduce the electrical efficiency of the VCSEL array. To counteract such effects, in some embodiments, a transparent conductive layer in electrical contact with the electrode extends across the mesa above the optical emission region. For example, this layer comprising indium tin oxide (ITO) can be formed above or below the metal layer of the electrode. This layer can be used to reduce device resistance and improve power conversion efficiency from electrical power to optical power.

[0026] The principles of the present invention can be implemented in a variety of different device technologies. For example, a VCSEL in an array may have an upper reflector that includes a distributed Bragg reflector (DBR) composed of multiple dielectric layers or composed of multiple epitaxial P-type layers. In addition, the principles of the present invention can be applied to other types of VCSEL arrays, as well as other types of solid-state emitter arrays, which will be apparent to those skilled in the art after reading this specification. All of these alternative implementations are considered to be within the scope of the present invention.

[0027] Figure 1 is a schematic front view of an optoelectronic device 20 including an array of VCSELs 22 according to an embodiment of the present invention. The structures shown in this overview figure and their fabrication process are described in more detail below.

[0028] The VCSELs 22 are formed on a semiconductor substrate 24, such as a GaAs wafer. Each VCSEL 22 emits optical radiation (typically in the near infrared range) from an optical emission region through an aperture 26 defined by an oxide confinement layer within the mesa of the VCSEL. The VCSELs 22 are physically and electrically separated from their neighbors by trenches 28 surrounding the mesa. The trenches 28 are disposed around the optical emission region of each VCSEL 22 without completely surrounding the optical emission region. Therefore, electrodes 30 can be disposed around the mesa in the gaps between the trenches 28. These electrodes serve as anodes to apply an excitation current to the optical emission region of the VCSEL. (A cathode, not shown in this figure, is located on the underside of the substrate 24.)

[0029] Figure 1 The design shown is advantageous in that the electrodes 30 are located outside the area of ​​the VCSEL mesas, thereby reducing the overall diameter 34 of each VCSEL relative to designs known in the art. The trenches 28 or electrodes 30 of adjacent VCSELs may overlap, meaning that a certain trench or electrode is common to each pair of adjacent VCSELs. This overlap enables an array of VCSELs 22 to be formed on substrate 24 with a pitch 32 that is substantially smaller than the diameter 34. Figure 1An array with overlapping grooves 28 is shown, but arrangements including overlapping electrodes are also shown in subsequent figures.)

[0030] exist Figure 1 And in the subsequent figures, some of the grooves 28 and electrodes 30 are schematically shown as having an arcuate shape that overlaps with some of the grooves and electrodes of the adjacent VCSEL 22. This feature is shown only for ease of explanation. In implementation, the grooves 28 that overlap each other actually constitute a single groove shared by the adjacent VCSELs. The two overlapping electrodes 30 can actually be formed as a single electrode shared by the adjacent VCSELs; or, the two overlapping electrodes can alternatively be limited in size so that they do not overlap, in which case each electrode only serves its own VCSEL.

[0031] although Figure 1 A linear array of VCSELs is shown, with four trenches of the same size and four electrodes surrounding each VCSEL, but in alternative embodiments (not shown in the drawings), different numbers, sizes, and arrangements of trenches may be used, as well as other sizes and shapes of electrodes in the gaps between the trenches surrounding the mesas. Such an arrangement may also support different array geometries of VCSELs, such as a hexagonal array.

[0032] VCSEL array with dielectric DBR

[0033] Figure 2A and Figure 2B Schematic front and cross-sectional views, respectively, of a pair of VCSELs 22 in an array 36 according to an embodiment of the present invention. Figure 2B The cross-section in the figure is along Figure 2A The image was taken along the line marked “IIB-IIB” in FIG. Figure 3B , Figure 5B and Figure 6B The section views in are defined by similar hatching in the corresponding front view. Figure 2A In , VCSELs 22 are oriented so that electrodes 30 of adjacent VCSELs overlap; and in Figure 3A In the embodiment, the overlap occurs between the grooves 28 (e.g. Figure 1 shown).

[0034] Array 36 is formed of thin film layers deposited on the upper side of semiconductor substrate 24. (For convenience, the terms "upper" and "lower" are used arbitrarily to indicate the order of the layers in the views shown in the cross-sectional views.) A first set of thin film layers (typically N-type epitaxial layers having different respective refractive indices) on substrate 24 define a lower distributed Bragg reflector (DBR) stack 42. A second set of thin film layers deposited over lower DBR stack 42 includes a multi-quantum well (MQW) layer 40 and a capping oxide layer 46. Trench 28 is etched through MQW layer 40 to define a mesa (e.g., a VCSEL) of each VCSEL 22. Figure 3B ). The oxide layer 46 is etched in each mesa to form a hole 26, which in turn defines an optical emission region 43 within each mesa.

[0035] A third set of thin film layers is formed over the MQW layer 40 (and therefore over the optical emission region 43) to define an upper DBR stack 44. In this embodiment, the upper DBR stack 44 includes alternating dielectric layers having different respective refractive indices. Vias are etched through the upper DBR 44 and then the vias are filled with metal to form electrodes 30 in the gaps between the trenches 28.

[0036] In the illustrated embodiment, transparent conductive layer 50 extends across the mesa of VCSEL 22 above MQW layer 40 and oxide layer 46 and is in electrical contact with electrode 30. Layer 50 may include, for example, indium tin oxide (ITO). Figure 3B 4 (shown) may be coated with a passivation layer 48. Alternatively or in addition, the trenches may be filled with one or more of the dielectric materials deposited to form the upper DBR stack 44.

[0037] Finally, metal contact pads 54 are formed on the upper surface of upper DBR stack 44, contacting electrode 30, and a common metal cathode layer 52 is formed on the lower surface of substrate 24. (Typically, substrate 24 is thinned prior to application of cathode layer 52.) When an excitation current is applied between pads 54 and cathode layer 52, it produces emission of a corresponding beam 56 of radiation from optical emission region 43 of VCSEL 22.

[0038] Figure 3A and Figure 3B 2 are schematic front and cross-sectional views, respectively, of a pair of VCSELs 22 in an array 58 according to an alternative embodiment of the present invention. The VCSELs 22 in this embodiment are substantially the same as those shown and described above; and similar elements in this and subsequent figures are labeled with reference numerals that correspond to the reference numerals. Figure 2A and Figure 2BHowever, in array 58, trenches 28 of adjacent VCSELs overlap each other, as compared to array 36 where electrodes 30 overlap. Thus, Figure 3B The cross-sectional view of 40 shows the trench 28 extending through the MQW layer 40 to the upper portion of the lower DBR stack 42 and separating the mesas of adjacent VCSELs.

[0039] FIG. 4A to FIG. 4G is a schematic cross-sectional view showing successive stages in manufacturing an array of VCSELs 22 (such as array 36 or array 58) according to an embodiment of the present invention. For compact illustration, Figures 4C to 4G Combined with Figure 2B and Figure 3B This means that the electrodes 30 are shown as if they overlap the trenches 28, rather than showing two different cross-sections at each stage. For simplicity, the passivation layer 48 is omitted in these figures.

[0040] In preparation for VCSEL formation, a series of epitaxial layers are deposited on a substrate 24, such as Figure 4A As shown, it starts with the N-type lower DBR stack 42, followed by the MQW layer 40. An oxide hole layer 60 is formed above the MQW layer. As a base for depositing the electrodes 30, a metal contact layer 62 is deposited above the layer 60 at the desired location of each electrode, as shown in FIG. Figure 4B A transparent conductive layer 50 is then deposited over the contact layer 62. Alternatively, the order of deposition of the layers 50 and 62 may be reversed.

[0041] Next, if Figure 4C As shown, trenches 28 are etched through layers 50, 60, and 40, down to lower DBR stack 42, thereby defining respective mesas 64 for each VCSEL 22 to be formed in the array. In addition, to increase the electrical efficiency of the VCSELs, protons may be implanted outside the mesa regions to provide electrical isolation between the mesas, thereby reducing current leakage through the regions between the mesas and forcing all current to pass through emission region 43. Oxide aperture layer 60 is processed, for example, by etching laterally inward from trenches 28 to produce oxide layer 46 defining apertures 26, as shown in FIG. Figure 4D The oxide layer 46 provides confinement for both current flow to the emission region 43 and the resulting optical emission from the emission region within each mesa 64 .

[0042] Alternating dielectric layers are now deposited over the transparent conductive layer 50 to form the upper DBR stack 44, as shown in FIG. Figure 4E The vias are etched through the upper DBR stack 44 and down to the contact layer 62. These vias are filled with metal to form the electrodes 30, as shown in FIG. Figure 4FA metal contact pad 54 is deposited over the upper surface of the upper DBR stack 44 to connect to the electrode 30. At this stage, the substrate 24 is typically thinned, such as by etching or polishing (not shown in the drawings), and a metal cathode layer 52 is deposited on the back side of the substrate, such as Figure 4G Application of current between contact pad 54 and cathode layer 52 will now result in laser emission through aperture 26.

[0043] VCSEL array with semiconductor DBR

[0044] Figure 5A and Figure 5B 1 and 2 are schematic front and cross-sectional views, respectively, of a pair of VCSELs 122 in an array 120 according to another embodiment of the present invention. Figure 2A / Figure 2B The embodiment shown and described above differs in that the upper DBR stack 124 in the VCSEL 122 comprises a stack of alternating P-type epitaxial layers. Due to the conductivity of these layers, the electrode 130 can be deposited on the upper surface of the upper DBR stack 124, rather than being deposited in a via through the stack as in the previous embodiment.

[0045] Aside from these differences, VCSEL 122 is similar to VCSEL 22 described above, and similar elements in this and subsequent figures are labeled with reference numerals that correspond to those of FIG. Figure 2A and Figure 2B The same as in. Figure 2A As shown, the VCSELs 122 in the array 120 are oriented so that the electrodes 130 of adjacent VCSELs overlap. The electrodes 130 are disposed in the gaps between the trenches 128 around the mesas of the respective VCSELs.

[0046] Fig. 6A and Figure 6B 1 and 2 are schematic front and cross-sectional views of a pair of VCSELs 122 in an array 132 according to an alternative embodiment of the present invention. The VCSELs 122 in this embodiment are similar to those described above with reference to FIG. Figure 5A / Figure 5B The electrodes 130 are substantially the same as those shown and described above. However, in array 132, the trenches 128 of adjacent VCSELs overlap one another, as compared to array 120 where the electrodes 130 overlap. Thus, Figure 6B The cross-sectional view of FIG. 1 shows a trench 128 extending through the upper DBR stack 124 and the MQW layer 40 to the upper portion of the lower DBR stack 42 and separating the mesas of adjacent VCSELs. The trench 128 may be filled, for example, with the passivation layer 48, such as Figure 6B As shown, or alternatively or additionally, filled with metal from a layer of contact pad 54 .

[0047] 7A to 7F 1 is a schematic cross-sectional view showing successive stages of manufacturing an array of VCSELs 122 (such as array 120 or array 132) according to an embodiment of the present invention. Again, for compactness, FIG. 7C to FIG. 7F Combined with Figure 5B and Figure 6B This means that the electrodes 130 are shown as if they overlap the trenches 128, rather than showing two different cross-sections at each stage. For simplicity, the passivation layer 48 is omitted in these figures.

[0048] In preparation for VCSEL formation, a series of epitaxial layers are deposited on a substrate 24, such as Fig. 7A As shown, starting with the N-type lower DBR stack 42, followed by the MQW layer 40. An oxide hole layer 60 is formed over the MQW layer, and a P-type upper DBR stack 124 is deposited over layer 60. As a base for depositing the electrodes 130, a metal contact layer 62 is deposited over the upper DBR stack 124 at the desired location of each electrode, as shown in FIG. Figure 7B A transparent conductive layer 50 is then deposited over the contact layer 62. Alternatively, the order of deposition of the layers 50 and 62 may be reversed.

[0049] Next, if Figure 7C As shown, trench 128 etches through layer 50, upper DBR stack 124, and layers 60 and 40, down to lower DBR stack 42. Trench 128 thus defines mesas 64 for each VCSEL 122 to be formed in the array. Protons may be implanted in the regions between the mesas to improve electrical efficiency, as described above. Oxide hole layer 60 is processed, for example, by etching laterally inward from trench 28 to produce oxide layer 46, thereby defining holes 26, as shown in FIG. Fig.7D shown.

[0050] Next, if Figure 4E As shown, metal electrode 130 is deposited over contact layer 62, and contact pad 54 is deposited over the upper surface of upper DBR stack 124 to connect with electrode 130. At this stage, substrate 24 is typically thinned, such as by etching or polishing (not shown in the drawings), and metal cathode layer 52 is deposited on the back side of the substrate, such as Figure 7F Application of current between contact pad 54 and cathode layer 52 will now result in laser emission through aperture 26.

[0051] Although the embodiments shown in the drawings and described above are explicitly directed to VCSELs, the principles of the present invention are similarly applicable to other types of surface emitting solid-state devices, such as resonant cavity light emitting diodes (RCLEDs). It should be understood, therefore, that the above embodiments are cited by way of example, and the present invention is not limited to what is specifically shown and described above. On the contrary, the scope of the present invention includes the various features described above, as well as combinations and sub-combinations of variations and modifications thereof not disclosed in the prior art that would occur to a person skilled in the art after reading the above description.

Claims

1. An optoelectronic device, comprising: Semiconductor substrates; a first set of thin film layers disposed on the substrate and defining a lower distributed Bragg reflector (DBR) stack; a second set of thin film layers disposed over the lower DBR stack and defining an optical emission region housed in a mesa defined by a plurality of trenches disposed about the optical emission region without completely surrounding the optical emission region; a third set of thin film layers disposed above the optically emitting region and defining an upper DBR stack; a transparent conductive layer disposed between the optically emitting region and the upper DBR stack and extending across the mesa at least above the second set of thin film layers; and An electrode is disposed around the mesa in the gap between the grooves in electrical contact with the transparent conductive layer and is configured to apply an excitation current to the optical emission region through the transparent conductive layer. 2 . The device according to claim 1 , wherein the transparent conductive layer comprises indium tin oxide (ITO).

3. The apparatus of claim 1, wherein the third set of thin-film layers comprises a dielectric layer.

4. The apparatus of claim 3, wherein the electrodes comprise metal deposited in vias extending through the third set of thin film layers.

5. The apparatus of claim 1, wherein the third set of thin film layers comprises epitaxial semiconductor layers.

6. The apparatus of claim 5, wherein the electrode is deposited over the third set of thin film layers.

7. The device according to any one of claims 1 to 6, wherein the first group of thin film layers, the second group of thin film layers, the third group of thin film layers and the electrodes are arranged on the upper side of the semiconductor substrate, and the device includes a cathode layer on the lower side of the semiconductor substrate opposite to the upper side.

8. An optoelectronic device, comprising: Semiconductor substrates; a first set of thin film layers disposed on the substrate and defining a lower distributed Bragg reflector (DBR) stack; a second set of thin film layers disposed over the lower DBR stack and defining a plurality of optical emitting regions housed in respective mesas defined by a plurality of trenches disposed about each of the optical emitting regions without completely surrounding the optical emitting regions; a third set of thin film layers disposed over each of the optically emitting regions and defining an upper DBR stack; a transparent conductive layer disposed between the optically emitting region and the upper DBR stack and extending across the mesa at least above the second set of thin film layers; and An electrode electrically contacting the transparent conductive layer, disposed around each of the mesas in the gaps between the grooves and configured to apply an excitation current to each of the optical emission regions, wherein at least one of the electrodes is common to a pair of adjacent mesas and is shared to provide the excitation current to both of the pair of mesas.

9. The apparatus of claim 8, wherein at least one of the grooves is common to a pair of adjacent mesas.

10. A device according to claim 8 or 9, wherein the first group of thin film layers, the second group of thin film layers, the third group of thin film layers and the electrodes are arranged on the upper side of the semiconductor substrate, and the device includes a cathode layer on the lower side of the semiconductor substrate opposite to the upper side, wherein the cathode layer is common to the multiple optical emission regions.

11. A method for manufacturing an optoelectronic device, the method comprising: depositing a first set of thin film layers on a semiconductor substrate to define a lower distributed Bragg reflector (DBR) stack; depositing a second set of thin film layers over the lower DBR stack to define an optically emitting region; forming a plurality of grooves around the optical emission region without completely surrounding the optical emission region, thereby defining a mesa that accommodates the optical emission region; depositing a third set of thin film layers over the optically emitting region to define an upper DBR stack; depositing electrodes around the mesas in the gaps between the trenches; depositing a transparent conductive layer in electrical contact with the electrode, between the optically emitting region and the upper DBR stack, and extending across the mesa at least above the second set of thin film layers; as well as An electrical contact is coupled to the electrode to apply an excitation current through the transparent conductive layer to the optically emissive region. 12 . The method according to claim 11 , wherein the transparent conductive layer comprises indium tin oxide (ITO).

13. The method of claim 11, wherein the third set of thin-film layers comprises a dielectric layer.

14. The method of claim 13, wherein depositing the electrode comprises etching vias through the third set of thin film layers and filling the vias with metal.

15. The method of claim 11, wherein the third set of thin film layers comprises epitaxial semiconductor layers.

16. The method of claim 15, wherein the electrode is deposited over the third set of thin film layers.

17. The method according to any one of claims 11 to 16, wherein the first group of thin film layers, the second group of thin film layers, the third group of thin film layers and the electrode are deposited on the upper side of the semiconductor substrate, and the method includes depositing a cathode layer on the lower side of the semiconductor substrate opposite to the upper side.

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