Data access control circuit, method, electronic device and computer readable storage medium

Abstract

The disclosed embodiment discloses a data access control circuit, method, electronic device and computer-readable storage medium. The data access control circuit includes: a connection circuit, the connection circuit includes multiple first interfaces and multiple second interfaces; wherein the multiple first interfaces correspond one-to-one to the multiple processing cores; the multiple second interfaces correspond one-to-one to the multiple storage blocks; a control circuit, which is used to control the connection relationship between the first interface and the second interface in the connection circuit based on the received task update instruction to connect the processing core and the corresponding storage block, and the task update instruction is sent by the processing core. The above-mentioned data access control circuit controls the connection circuit through the task update instruction, so that the processing core and the storage block are connected one-to-one, which solves the technical problem of waste of storage space or waste of processing core computing power caused by the use of shared memory in the prior art.

Description

Technical Field

[0001] The present disclosure relates to the field of processors, and in particular to a task allocation method, device, electronic device, and computer-readable storage medium. Background Art

[0002] With the development of science and technology, human society is rapidly entering the intelligent era. An important feature of the intelligent era is that people obtain more and more types of data, the amount of data obtained is increasing, and the speed of processing data is getting higher and higher. Chips are the cornerstone of task allocation, which fundamentally determines people's ability to process data. From the perspective of application fields, there are two main routes for chips: one is the general chip route, such as CPU, etc., which can provide great flexibility, but the effective computing power is relatively low when processing algorithms in specific fields; the other is the dedicated chip route, such as TPU, etc., which can play a higher effective computing power in certain specific fields, but in the face of flexible and changeable more general fields, their processing capabilities are relatively poor or even unable to process. Due to the wide variety and huge amount of data in the intelligent era, chips are required to have both extremely high flexibility, able to process algorithms in different fields and changing with each passing day, and extremely strong processing capabilities, able to quickly process huge and rapidly growing amounts of data.

[0003] In neural network calculations, multi-core or multi-core chips are often used. How to make many processing cores efficiently exert their computing power is the key to determining the performance of the entire chip. The computing power of each processing core depends on many factors, such as how the processing core efficiently accesses the tasks to be executed (including the parameters of the tasks). For example, in the application scenario of image recognition, the chip has N processing cores, all of which process images independently and in parallel, and the programs and parameters executed by each core are the same; in order to maximize the computing power of the chip and consume the least delay and power consumption, all processing cores share the same program and parameters.

[0004] In the prior art, the following scheme is generally used to enable the processing cores to perform the above processing in parallel:

[0005] like Figure 1The figure shows a shared storage solution in the prior art. In this solution, the processing cores in the chip read the tasks they need from the SM (Shared Memory) individually. After the processing cores read the tasks, they execute the tasks independently and complementary to each other. However, this solution has the following disadvantages: 1. If the processing cores need to execute tasks independently and in parallel, multiple copies of the tasks need to be stored in the SM, that is, each processing core needs to correspond to a completely identical task, which will cause a waste of SM storage space; 2. If only one copy of the task is stored in the SM, each processing core needs to read the SM serially to obtain the task, and the computing power of the processing core cannot be fully utilized, which wastes computing power and reduces chip performance. Summary of the invention

[0006] This summary is provided to introduce concepts in a brief form that will be described in detail in the detailed description below. This summary is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0007] In order to solve the technical problems of inflexible task allocation and complex control of processing cores in the prior art, the embodiments of the present disclosure propose the following technical solutions:

[0008] In a first aspect, an embodiment of the present disclosure provides a task allocation method for a chip including multiple processing cores, wherein the data access control circuit includes:

[0009] A connection circuit, the connection circuit comprising a plurality of first interfaces and a plurality of second interfaces;

[0010] Wherein, the plurality of the first interfaces correspond one-to-one to the plurality of the processing cores; the plurality of the second interfaces correspond one-to-one to the plurality of storage blocks;

[0011] The control circuit is used to control the connection relationship between the first interface and the second interface in the connection circuit based on the received task update instruction to connect the processing core and the corresponding storage block, and the task update instruction is sent by the processing core.

[0012] Furthermore, the control circuit is also used for:

[0013] When the control circuit is initialized, the connection relationship between the first interface and the second interface is controlled according to a pre-configuration.

[0014] Further, the connecting circuit includes:

[0015] A switch array is provided between a plurality of the first interfaces and a plurality of the second interfaces, so that the first interfaces are connected or disconnected with corresponding second interfaces.

[0016] In a second aspect, an embodiment of the present disclosure provides a data access control method, including:

[0017] The processing core reads a first task to be executed from a first storage block;

[0018] performing the first task;

[0019] A task update instruction is sent, where the task update instruction is used to instruct the processing core to connect to a second storage block, where the second storage block is a storage block storing a second task to be executed by the processing core in a next synchronization cycle.

[0020] Furthermore, the task update instruction includes:

[0021] An identifier of the processing core and an identifier of the second storage block.

[0022] Furthermore, after sending the task update instruction, the method further includes:

[0023] Send a synchronization request signal.

[0024] Furthermore, before reading the to-be-executed task from the first storage block, the method further includes:

[0025] receiving a synchronization signal;

[0026] The step of reading the first task to be executed from the first storage block comprises:

[0027] The first task to be executed is read from the first storage block according to the synchronization signal.

[0028] Further, after receiving the synchronization signal, the method further includes:

[0029] The processing core determines the first task or the second task to be executed according to the number of the synchronization signal.

[0030] In a third aspect, an embodiment of the present disclosure provides a chip, including:

[0031] The data access control circuit as described in any one of the first aspects;

[0032] Multiple processing cores;

[0033] a memory, the memory comprising a plurality of memory blocks; and

[0034] Synchronous signal generation module.

[0035] Furthermore, the synchronization signal generating module is used for:

[0036] A synchronization signal is sent after receiving the synchronization request signals sent by the multiple processing cores.

[0037] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, comprising: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, so that when the processor is executed, any data access control method described in the first aspect is implemented.

[0038] In a fifth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute any data access control method described in the first aspect.

[0039] In a sixth aspect, an embodiment of the present disclosure provides a computer program product, characterized in that it includes computer instructions, and when the computer instructions are executed by a computing device, the computing device can execute any of the data access control methods described in the first aspect.

[0040] In a seventh aspect, an embodiment of the present disclosure provides a computing device, characterized in that it comprises one or more chips described in the third aspect.

[0041] The disclosed embodiment discloses a data access control circuit, method, electronic device and computer-readable storage medium. The data access control circuit includes: a connection circuit, the connection circuit includes multiple first interfaces and multiple second interfaces; wherein the multiple first interfaces correspond one-to-one to the multiple processing cores; the multiple second interfaces correspond one-to-one to the multiple storage blocks; a control circuit, which is used to control the connection relationship between the first interface and the second interface in the connection circuit based on the received task update instruction to connect the processing core and the corresponding storage block, and the task update instruction is sent by the processing core. The above-mentioned data access control circuit controls the connection circuit through the task update instruction, so that the processing core and the storage block are connected one-to-one, which solves the technical problem of waste of storage space or waste of processing core computing power caused by the use of shared memory in the prior art.

[0042] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0044] Figure 1 It is a schematic diagram of the prior art of the present disclosure;

[0045] Figure 2 A schematic diagram of the structure of a data access control circuit provided by an embodiment of the present disclosure;

[0046] Figure 3 A schematic diagram of the working process of the data access control circuit provided by the embodiment of the present disclosure;

[0047] Figure 4 A flow chart of a data access control method provided by an embodiment of the present disclosure;

[0048] Figure 5a is a neural network structure diagram in an embodiment of the present disclosure;

[0049] Figure 5b The structure of the chip that performs the neural network task in the embodiment of the present disclosure;

[0050] Figure 5c A timing diagram of a chip executing a task according to an embodiment of the present disclosure;

[0051] Figure 5d is the connection state of the connection circuit when the first synchronization signal is received in the embodiment of the present disclosure;

[0052] Figure 5e is a connection state of the connection circuit when a second synchronization signal is received in an embodiment of the present disclosure;

[0053] Figure 5f It is the connection state of the connection circuit when the third synchronization signal is received in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0055] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0056] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0057] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0058] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0059] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0060] Figure 2 A schematic diagram of a data access control circuit provided in an embodiment of the present disclosure. The data access control circuit 200 provided in this embodiment is used in a chip including multiple processing cores, wherein the data access control circuit 200 includes:

[0061] The connection circuit 201 includes a plurality of first interfaces 203 and a plurality of second interfaces 204; wherein the plurality of first interfaces correspond one-to-one to the plurality of processing cores, and the plurality of second interfaces correspond one-to-one to the plurality of storage blocks. Figure 2 As shown, each of the processing cores C1, C2, ... CN is connected to a first interface, and each of the memory blocks M1, M2, ... MK is connected to a second interface.

[0062] The control circuit 202 is used to control the connection relationship between the first interface and the second interface in the connection circuit based on the received task update instruction to connect the processing core and the corresponding storage block, and the task update instruction is sent by the processing core. The processing core sends the task update instruction Refresh to the control circuit 202. After receiving the task update instruction, the control circuit 202 parses and runs the instruction and sends a control signal C_F to the connection circuit to control the connection relationship between the first interface and the second interface in the connection circuit 201, thereby connecting a processing core to a corresponding storage block. Optionally, the multiple processing cores and the multiple storage blocks are in a one-to-one correspondence, that is, each storage block is only connected to one processing core in each synchronization cycle, so that the processing core can read the tasks stored in the storage block in parallel.

[0063] Optionally, the multiple processing cores and the control circuit 202 are connected to a synchronization signal generating module SG, and SG sends a synchronization signal Sync to the processing cores and the control circuit so that the processing cores and the control circuit can work in coordination with each other. Specifically, each time after receiving a synchronization signal sent by SG, the multiple processing cores read the tasks to be executed in the current cycle from the storage blocks corresponding to the current synchronization cycle; each time after receiving a synchronization signal sent by SG, the control circuit receives a task update instruction sent by the processing core.

[0064] Optionally, the control circuit 202 controls the connection relationship between the first interface and the second interface according to a pre-configuration during the initialization phase. The pre-configuration is a configuration in an initialization program, and exemplarily, the processing core that needs to execute a task in the first synchronization cycle and the storage block that stores the task to be executed are pre-set. During the initialization phase, the first interface and the second interface in the connection circuit are connected according to the pre-settings, so that the processing core that has a task to be executed in the first synchronization cycle can read the task to be executed from the corresponding storage block when the first synchronization signal arrives.

[0065] Optionally, the connection circuit 201 includes: a switch array, the switch array is arranged between a plurality of the first interfaces and a plurality of the second interfaces, so that the first interface is connected or disconnected with the corresponding second interface. The switch array includes a plurality of switches, and each of the first interfaces is connected with each of the second interfaces through a switch element. Exemplarily, there are N first interfaces and K second interfaces, then N switches are set, and each switch has K+1 states, wherein K states represent connection with one of the K second interfaces, and one state represents no connection with each second interface.

[0066] Figure 3FIG. 1 is a schematic diagram of the operation of the data access control circuit in the embodiment of the present disclosure. Figure 3 As shown, in this example, a synchronization signal generating module is included, and the synchronization signal generating module is connected to each processing core and a data access control circuit. Each processing core performs different tasks in a certain time period determined by the synchronization signal, wherein the task can be a complete task or a part of a complete task, such as a computing task of a certain layer in a neural network task; the task is stored in different storage blocks of SM, and the tasks stored in each storage block are different, and each storage block can be accessed independently. Each processing core C1, C2, ... CN can read a task in a certain storage block in a certain time period.

[0067] Exemplarily, in a certain synchronization cycle, all processing cores have tasks to be executed. At this time, when the synchronization signal sent by SG is received, C1, C2, ... CN execute the task reading instruction to read the tasks to be executed from the corresponding storage blocks through the first interface and the second interface. Exemplarily, the tasks to be executed include the programs to be executed and / or the parameters corresponding to the programs to be executed. After reading the tasks to be executed, each processing core starts to execute the tasks to be executed. After executing the tasks to be executed, each processing core sends a task update instruction to the data access control circuit. After receiving the task update instruction, the data access control circuit parses and executes the task update instruction to control the connection circuit to connect each processing core to the storage block storing the tasks to be executed in the next cycle, so that when the next synchronization signal is received, the processing core can directly obtain the tasks to be executed in the current synchronization signal from the corresponding storage block.

[0068] The above embodiment discloses a connection circuit, the connection circuit includes a plurality of first interfaces and a plurality of second interfaces; wherein the plurality of first interfaces correspond one-to-one to the plurality of processing cores; the plurality of second interfaces correspond one-to-one to the plurality of storage blocks; and the control circuit is used to control the connection relationship between the first interface and the second interface in the connection circuit based on the received task update instruction to connect the processing core and the corresponding storage block, wherein the task update instruction is sent by the processing core. The above data access control circuit controls the connection circuit through the task update instruction, so that the processing core and the storage block are connected one-to-one, which solves the technical problem of waste of storage space or waste of processing core computing power caused by the use of shared memory in the prior art.

[0069] Figure 4 Flow chart of the data access control method provided by the embodiment of the present disclosure. Figure 4 As shown, the method comprises the following steps:

[0070] Step S401, the processing core reads a first task to be executed from a first storage block;

[0071] Exemplarily, in a certain time period, the processing core has a task to be executed. After the time period arrives, the processing core reads the first task to be executed from the first storage block corresponding to it, wherein the connection relationship between the processing core and the first storage block is pre-set in the previous time period. Therefore, when the time arrives, the processing core directly reads the first task from the first storage block.

[0072] Step S402, executing the first task;

[0073] In this step, the processing core executes the first task. Exemplarily, the first task is a computing task of a certain layer in a neural network task, and the processing core obtains the input data required for the computing task of this layer, and calculates the input data according to the first task to obtain output data. In the present disclosure, the input data is a part of the complete input data, which is related to the processing core that executes the task. Each processing core of the task to be executed processes different input data. The input data is obtained from an external memory. The external memory address of the input data to be processed by each processing core is set during the initialization phase of the processing core. After that, when the processing core executes the task to be executed, the input data is obtained from the external memory address. It can be understood that the method of obtaining input data can be any known method, which will not be elaborated in this article.

[0074] Step S403: Send a task update instruction, wherein the task update instruction is used to instruct the processing core to connect to a second storage block, where the second storage block is a storage block storing a second task to be executed by the processing core in the next synchronization cycle.

[0075] After executing the first task, the processing core sends a task update instruction Refresh to the data access control circuit. Exemplarily, the task update instruction includes the identifier of the processing core that sends the task update instruction and the identifier of the second storage block. The data access control circuit determines that the processing core needs to read the task to be executed from the second storage block in the next synchronization cycle according to the identifier of the processing core and the identifier of the second storage block, so as to connect the corresponding first interface and second interface.

[0076] Optionally, each processing core can determine whether it has a task to be executed in the next synchronization cycle through a pre-configured program, and if so, determine the storage block storing the task to be executed. Exemplarily, in the initialization phase, the identifiers of the storage blocks of the various tasks to be executed by the processing core during the task execution process are arranged in the execution order and stored in the processing core. After the processing core completes the current task to be executed, it directly obtains the identifier of the storage block of the next task to be executed, and sends the identifier of the storage block through the task update instruction.

[0077] Optionally, in each synchronization cycle, multiple processing cores can be divided into the following types: a first processing core, which has tasks to be executed in the current synchronization cycle and also has tasks to be executed in the next synchronization cycle; a second processing core, which has tasks to be executed in the current synchronization cycle and has no tasks to be executed in the next synchronization cycle; a third processing core, which has no tasks to be executed in the current synchronization cycle and has tasks to be executed in the next synchronization cycle; and a fourth processing core, which has no tasks to be executed in both the current synchronization cycle and the next synchronization cycle.

[0078] For the first processing core, after executing the task in the current synchronization cycle, a task update instruction is sent; for the second processing core, after executing the task in the current synchronization cycle, no task update instruction is sent; for the third processing core, in the current synchronization cycle, it directly sends a task update instruction; for the fourth processing core, in the current synchronization cycle, it may not execute the task or execute other tasks.

[0079] Optionally, after sending the task update instruction, the processing core also sends a synchronization request signal. In this optional embodiment, the synchronization signal generating module sends a synchronization signal to each processing core and the data access control circuit. The synchronization signal generating module can determine the processing cores of the tasks to be executed in each synchronization cycle through pre-configuration during the initialization phase. In subsequent synchronization cycles, after receiving the synchronization request signal sent by each processing core of the tasks to be executed in the synchronization cycle, a new synchronization signal is generated and sent to all processing cores and the data access control circuit.

[0080] In this optional embodiment, the processing core is the first processing core and the second processing core, that is, the processing core that has tasks to be executed in the current synchronization cycle. The processing core sends a synchronization request signal to indicate that the processing core has completed the tasks to be executed in the current synchronization cycle. When the synchronization signal generating module receives the synchronization request signal from each processing core that has tasks to be executed in the current cycle, it indicates that the processing cores that have tasks to be executed in the current synchronization cycle have completed the tasks to be executed. At this time, the synchronization signal generating module sends a new synchronization signal.

[0081] Optionally, before step S401, the method further includes: receiving a synchronization signal; and reading the first task to be executed from the first storage block includes: reading the first task to be executed from the first storage block according to the synchronization signal. In this optional embodiment, the synchronization signal is used to synchronize the work of each processing core, and whenever a synchronization signal is received, the processing core executes a read instruction to read the task to be executed in the synchronization cycle determined by the synchronization signal from the storage block connected thereto.

[0082] Optionally, after receiving the synchronization signal, the method further includes: the processing core determining the first task or the second task to be executed according to the number of synchronization signals.

[0083] Optionally, when the storage block stores task parameters, after receiving the synchronization signal, the first task to be executed is determined by the number of synchronization signals. At this time, each processing core has a complete task stored in its own storage space. The first task to be executed in the current synchronization cycle can be determined through pre-configuration. The processing core then directly obtains the first task from its own storage space, and reads the parameters for executing the first task from the storage block, and then executes the first task. After executing the first task, the second task is determined according to the number of synchronization signals to send the task update instruction.

[0084] Optionally, when the storage block stores tasks and parameters, after receiving the synchronization signal, the first task and parameters are directly obtained from the storage block, and then the first task is executed. At this time, after executing the first task, it is necessary to determine the second task by the number of synchronization signals to send the task update instruction.

[0085] Optionally, when the storage block stores tasks, after receiving the synchronization signal, the first task to be executed is determined by the number of synchronization signals. At this time, the complete task parameters are stored in the storage space of each processing core. The parameters of the first task to be executed in the current synchronization cycle can be determined through pre-configuration. The processing core then directly obtains the parameters of the first task from its own storage space, and reads and executes the first task from the storage block, and then executes the first task. After executing the first task, the second task is determined according to the number of synchronization signals to send the task update instruction.

[0086] In the above, although the various steps in the above method embodiment are described in the above order, those skilled in the art should be aware that the steps in the embodiments of the present disclosure are not necessarily executed in the above order, and they may also be executed in other orders such as reverse order, parallel order, and cross order. Moreover, on the basis of the above steps, those skilled in the art may also add other steps. These obvious variations or equivalent replacement methods should also be included in the protection scope of the present disclosure and will not be repeated here.

[0087] The present disclosure also provides a chip, which includes: the data access control circuit described in the above embodiment; multiple processing cores; a memory, which includes multiple storage blocks; and a synchronization signal generation module. The overall structure of the chip is shown in FIG. Figure 3The structure shown in . The synchronization signal generating module is used to send a synchronization signal after receiving the synchronization request signal sent by the multiple processing cores. The working process of each part in the chip can refer to the description in the embodiments of the above-mentioned data access control circuit and data access control method, which will not be repeated here.

[0088] The following describes the working process of the data access control circuit in the embodiment of the present disclosure using an actual application scenario. Figure 5a As shown in FIG. 1 , the tasks to be performed by the processing core in the application scenario are: a neural network, which includes two layers, Layer 1 and Layer 2, and the programs and parameters of each layer in the neural network are stored in a storage block in the shared memory SM; the structure of the chip that performs the neural network computing task is as follows Figure 5b As shown, it includes two processing cores C1 and C2, including a control circuit and a connection circuit of switches 1 and 2, including a shared memory SM containing two storage blocks M1 and M2, and a synchronization signal generating module SG connecting the two processing cores and the data access control circuit. The storage block M1 is used to store tasks and parameters corresponding to Layer1, and the storage block M2 is used to store tasks and parameters corresponding to Layer2. Each of the processing cores C1 and C2 will perform a complete neural network task, that is, execute the tasks corresponding to Layer1 and Layer2 in time periods, and access the corresponding storage blocks M1 and M2 in time periods. Optionally, the time period is a synchronization period, which is divided by the synchronization signal Sync generated by the synchronization signal generating module SG.

[0089] Figure 5c This is the task execution sequence diagram in the above application scenario. Figure 5c As shown, after receiving the first synchronization signal, the first synchronization cycle t1 is entered. In the synchronization cycle t1, the processing core C1 reads the storage block M1 storing the task corresponding to Layer1 to obtain the first task and parameters corresponding to Layer1; then the processing core C1 obtains the corresponding input data and executes the first task. It can be understood that the input data of C1 in t1 is part of the input data of the neural network. After executing the first task, the processing core C1 sends a task update instruction to the control circuit F_ctrl in the data access control circuit according to the number of current synchronization signals. The task update instruction includes the ID of the processing core C1: C1 and the identifier M2 of the storage block of the second task to be executed by C1 in the next synchronization cycle. The second task is the task corresponding to Layer2. Then the processing core C1 enters the state of waiting for the synchronization signal. After receiving the task update instruction, the control circuit parses and executes the task update instruction to connect the processing cores C1 and M2.

[0090] In t1, C2 does not execute the task, but C2 determines the first task to be executed in the next synchronization cycle through the number of synchronization signals received. Therefore, in t1, C2 directly sends a task update instruction to the control circuit in the data access control circuit, and then the processing core C2 enters a state of waiting for the synchronization signal; after receiving the task update instruction, the control circuit parses and executes the task update instruction to connect the processing core C2 and M1.

[0091] Figure 5d It indicates the connection state between the first interface and the second interface in the data access control circuit when the first synchronization signal is received, and the connection state enables the processing core C1 to directly read the first task and parameters from M1 in t1.

[0092] Figure 5e The connection status of the first interface and the second interface in the data access control circuit when the second synchronization signal is received. In t1, the data access control circuit connects C1 and M2 according to the data update instruction of C1, and connects C2 and M1 according to the data update instruction of C2. After receiving the second synchronization signal, in the synchronization period t2, C1 reads the second task and parameters corresponding to Layer2 from M2, and C2 reads the first task and parameters corresponding to Layer1 from M1, and then C1 and C2 obtain their respective input data and execute their respective tasks to be executed. It can be understood that in t2, the input data of C1's second task is the output data of its execution of the first task; the input data of C2's first task is part of the original input data of the neural network.

[0093] After C1 completes the second task, it sends a data update instruction to the control circuit, so that the control circuit connects C1 with M1; after C2 completes the first task, it sends a data update instruction to the control circuit, so that the control circuit connects C2 with M2. Figure 5f Indicates the connection status of the first interface and the second interface in the data access control circuit when the third synchronization signal is received. The subsequent steps are similar to the above steps, and the control circuit continuously changes the connection status of the connection circuit according to the data update instruction sent by C1 and / or C2, so that C1 and / or C2 reads the task to be executed from the corresponding storage block in the next synchronization cycle until the complete task is executed.

[0094] In the above embodiment, each part of the complete task, such as the calculation program of each layer in a two-layer neural network, only needs to be stored in the memory, which reduces the area of ​​the shared memory and further reduces the area of ​​the chip; all processing cores can run in parallel, and the computing power of each processing core can be fully utilized; a unified data access control circuit is used to control the access of the processing core to the memory, and there is no need to design a control circuit for each processing core, which saves the chip area and reduces the difficulty of circuit design.

[0095] An embodiment of the present disclosure provides an electronic device, comprising: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, so that when the processors are executed, any of the data access control methods in the embodiments is implemented.

[0096] The embodiment of the present disclosure also provides a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute any of the data access control methods described in the aforementioned embodiments.

[0097] The disclosed embodiment also provides a computer program product, which is characterized in that it includes computer instructions. When the computer instructions are executed by a computing device, the computing device can execute any of the data access control methods in the aforementioned embodiments.

[0098] The disclosed embodiments further provide a computing device, characterized in that it comprises any chip described in the embodiments.

[0099] The flowcharts and block diagrams in the accompanying drawings of the present disclosure illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, task segment, or a part of the code, which contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0100] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, limit the unit itself.

[0101] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0102] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Claims

1. A data access control circuit, used in a chip including a plurality of processing cores, wherein the data access control circuit comprises: A connection circuit, the connection circuit comprising a plurality of first interfaces and a plurality of second interfaces; Wherein, the plurality of first interfaces correspond one-to-one to the plurality of processing cores; the plurality of second interfaces correspond one-to-one to the plurality of storage blocks, the processing cores access different storage blocks in different synchronization cycles to obtain different tasks, the storage blocks are independently accessible storage blocks in the shared memory, and each storage block stores different tasks; A control circuit is used to control the connection relationship between the first interface and the second interface based on a received task update instruction, so as to control the processing core to switch from a currently connected storage block to a storage block corresponding to a task to be executed in the next cycle thereof, wherein the task update instruction is sent by the processing core.

2. The data access control circuit according to claim 1, characterized in that: The control circuit is also used for: When the control circuit is initialized, the connection relationship between the first interface and the second interface is controlled according to a pre-configuration.

3. The data access control circuit according to claim 1, wherein: The connecting circuit comprises: A switch array is provided between the plurality of the first interfaces and the plurality of the second interfaces, and is used for controlling the connection or disconnection between the first interfaces and the corresponding second interfaces.

4. A data access control method, applicable to a chip including a plurality of processing cores and a data access control circuit, characterized in that: include: The processing core reads a first task to be executed from a first storage block; performing the first task; Sending a task update instruction, wherein the task update instruction is used to instruct the processing core to switch from the currently connected first storage block to the second storage block corresponding to the task to be executed in the next cycle thereof, wherein the task update instruction is sent by the processing core, and the second storage block is a storage block storing the second task to be executed by the processing core in the next synchronization cycle; Among them, the processing core accesses different storage blocks in different synchronization cycles to obtain different tasks, the first storage block and the second storage block are storage blocks that can be accessed independently in the shared memory, and the first storage block and the second storage block respectively store different tasks.

5. The data access control method according to claim 4, wherein the task update instruction comprises: An identifier of the processing core and an identifier of the second storage block.

6. The data access control method according to claim 4, wherein after sending the task update instruction, it also includes: Send a synchronization request signal.

7. The data access control method according to claim 4, wherein before reading the task to be executed from the first storage block, it also includes: receiving a synchronization signal; The step of reading the first task to be executed from the first storage block comprises: The first task to be executed is read from the first storage block according to the synchronization signal.

8. The data access control method according to claim 7, wherein after receiving the synchronization signal, the method further comprises: The processing core determines the first task or the second task to be executed according to the number of the synchronization signal.

9. A chip, characterized in that: include: The data access control circuit according to any one of claims 1 to 3; Multiple processing cores; A memory, the memory comprising a plurality of storage blocks; as well as Synchronous signal generation module.

10. The chip according to claim 9, characterized in that: The synchronization signal generating module is used for: A synchronization signal is sent after receiving synchronization request signals sent by all the processing cores executing tasks among the multiple processing cores.

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