Signal processing system and operation method of signal processing system

Abstract

The present disclosure relates to a signal processing system and an operation method of the signal processing system. The signal processing system includes a digital signal processing circuit, a power management unit and a digital control circuit. The power management unit provides a first voltage to the digital signal processing circuit. The digital control circuit includes a non-volatile memory. In a calibration mode, the digital control circuit controls the power management unit so that the first voltage has a minimum preset value, controls the digital signal processing circuit to operate at a calibration target frequency, and triggers the digital signal processing circuit to perform a built-in self-test. When the result of the built-in self-test is a failure, the digital control circuit increases the value of the first voltage and triggers the digital signal processing circuit to perform a built-in self-test again. When the result of the built-in self-test is a success, the digital control circuit stores the value of the first voltage and the calibration target frequency in the non-volatile memory.

Description

Technical Field

[0001] The present invention relates to a signal processing system, and in particular to a signal processing system capable of performing frequency and voltage calibration. Background Art

[0002] As multimedia applications become more and more widespread, consumers are demanding higher quality multimedia applications. Since multimedia applications, such as images and sound effects, often involve a large number of complex and repetitive calculations, it is necessary to use the computing power of digital signal processors to achieve the function of real-time presentation of images and sounds.

[0003] Generally speaking, the maximum operating frequency that a digital signal processor can achieve is related to the power supply voltage it receives. For example, when the digital signal processor receives a voltage of 1.1V, the maximum operating frequency of the digital signal processor may be 200MHz, but when the digital signal processor receives a voltage of 1.2V, the maximum operating frequency of the digital signal processor may be increased to 300MHz. Therefore, in order to enable the digital signal processor to operate at the required operating frequency under reasonable voltage conditions, the manufacturer of the digital signal processor will record the power supply voltage value corresponding to each operating frequency before shipment to ensure that the digital signal processor can meet the user's needs at the recommended voltage value. However, differences in process will inevitably cause differences in the characteristics of different digital signal processors. Therefore, the corresponding relationship between the operating frequency and voltage of each digital signal processor may be different, and the power management unit used to provide the power supply voltage may also be different, making the testing process very complicated. Summary of the invention

[0004] An embodiment of the present invention provides a signal processing system, which includes a digital signal processing circuit, a power management unit and a digital control circuit.

[0005] The power management unit is coupled to the digital signal processing circuit, and the power management unit provides a first voltage to the digital signal processing circuit. The digital control circuit is coupled to the digital signal processing circuit and the power management unit. The digital control circuit includes a non-volatile memory. In the calibration mode, the digital control circuit controls the power management unit so that the first voltage has a minimum preset value, controls the digital signal processing circuit to operate at a calibration target frequency, and triggers the digital signal processing circuit to perform a built-in self-test. When the result of the built-in self-test is a failure, the digital control circuit increases the value of the first voltage and triggers the digital signal processing circuit to perform the built-in self-test again. When the result of the built-in self-test is a success, the digital control circuit stores the value of the first voltage and the calibration target frequency in the non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a signal processing system according to an embodiment of the present invention.

[0007] Figure 2 It is a flow chart of an operation method of a signal processing system in a calibration mode according to an embodiment of the present invention.

[0008] Figure 3 It is a flow chart of an operation method of a signal processing system in an application mode according to an embodiment of the present invention. DETAILED DESCRIPTION

[0009] Figure 1 1 is a schematic diagram of a signal processing system 100 according to an embodiment of the present invention. The signal processing system 100 includes a digital signal processing circuit 110 , a power management unit (PMU) 120 , and a digital control circuit 130 .

[0010] The power management unit 120 may be coupled to the digital signal processing circuit 110, and may provide a first voltage V1 to the digital signal processing circuit 110 as a power supply for the digital signal processing circuit 110. In addition, the power management unit 120 may also be coupled to the digital control circuit 130, and may provide a second voltage V2 to the digital control circuit 130 as a power supply for the digital control circuit 130.

[0011] The digital control circuit 130 may be coupled to the digital signal processing circuit 110 and the power management unit 120. In some embodiments, the digital control circuit 130 may control the value of the first voltage V1 output by the power management unit 120, that is, the digital control circuit 130 may control the magnitude of the power supply voltage received by the digital signal processing circuit 110. In addition, the digital control circuit 130 may also control the operating frequency of the digital signal processing circuit 110. For example, the digital control circuit 130 may be coupled to the clock generator 112 in the digital signal processing circuit 110, and control the clock generator 112 to generate a clock signal having a desired operating frequency, and the digital signal processor 114 in the digital signal processing circuit 110 may operate according to the clock signal generated by the clock generator 112.

[0012] In some embodiments, the digital control circuit 130 can be used to calibrate the voltage value required by the digital signal processing circuit 110 at a specific operating frequency, and the digital control circuit 130 can include a non-volatile memory 132, and the specific operating frequency and its corresponding voltage value are recorded in the non-volatile memory 132. In this way, in actual application operation, the voltage value required for the target operating frequency can be read from the non-volatile memory 132, so that the digital signal processing circuit 110 can work normally at the target frequency. In some embodiments, the non-volatile memory 132 can be a one-time write non-volatile memory to prevent the user from accidentally overwriting the voltage recorded in the non-volatile memory 132 in subsequent operations. However, the present invention does not limit the non-volatile memory 132 to a one-time write non-volatile memory, but can also be a multiple write non-volatile memory.

[0013] Figure 2 FIG. 2 is a flow chart of an operation method 200 of the signal processing system 100 in a calibration mode according to an embodiment of the present invention. In the calibration mode, the method 200 may include steps S210 to S290.

[0014] S210 : The digital control circuit 130 controls the power management unit 120 to output the first voltage V1 having a minimum preset value to the digital signal processing circuit 110 ;

[0015] S220: The digital control circuit 130 controls the digital signal processing circuit 110 to operate at the calibration target frequency;

[0016] S230: The digital control circuit 130 triggers the digital signal processing circuit 110 to perform a built-in self-test;

[0017] S240: Whether the result of the built-in self-test is successful, if it is a failure, executing step S250; if it is a success, executing step S260;

[0018] S250: the digital control circuit 130 controls the power management unit 120 to increase the value of the first voltage V1, and executes step S230;

[0019] S260 : the digital control circuit 130 stores the value of the first voltage V1 and the calibrated target frequency in the non-volatile memory 132 ;

[0020] S270: Whether other frequencies need to be calibrated, if yes, execute step S280, if no, execute step S290;

[0021] S280: Update the calibration target frequency and proceed to step S210;

[0022] S290: End calibration.

[0023] In step S210, the digital control circuit 130 may control the power management unit 120 to make the first voltage V1 have a minimum preset value, such as but not limited to 1V. In step S220, the digital control circuit 130 may control the digital signal processing circuit 110 to operate at the calibration target frequency F1. Then in step S230, the digital control circuit 130 may further trigger the digital signal processing circuit 110 to perform a built-in self-test (BIST), and may determine whether the test result is successful or failed.

[0024] For example, the digital control circuit 130 may further include a first control unit 134. The first control unit 134 may be coupled to the digital signal processing circuit 110 and the power management unit 120. The first control unit 134 may output a voltage control signal SIG CTRLV To the power management unit 120 to adjust the value of the first voltage V1 and output the frequency control signal SIG CTRLF The clock generator 112 of the digital signal processing circuit 110 controls the operating frequency of the digital signal processing circuit 110 and determines whether the result of the built-in self test is a failure or a success.

[0025] exist Figure 1 In the embodiment, the digital signal processor 114 in the digital signal processing circuit 110 may include an internal dynamic random access memory 1141 and a built-in self-test unit 1142. When the digital signal processor 114 performs calculations, the internal dynamic random access memory 1141 may be used to store data immediately required for the calculations. The built-in self-test unit 1142 may be coupled to the internal dynamic random access memory 1141. In some embodiments, the digital control circuit 130 may trigger the built-in self-test unit 1141 to perform a built-in self-test. At this time, the built-in self-test unit 1142 may read out the data stored in the internal dynamic random access memory 1141 and transmit it to the digital control circuit 130, and the digital control circuit 130 may determine whether the digital signal processing circuit 110 has successfully completed the built-in self-test according to the read data.

[0026] In addition, Figure 1In the embodiment of the present invention, the digital signal processing circuit 110 may further include a static random access memory 116 and a built-in self-test unit 118. The static random access memory 116 and the digital signal processor 114 may be coupled via a bus BUS and may be used to store a larger amount of data that may be required for calculation. The built-in self-test unit 118 may be coupled to the static random access memory 116. In this case, the digital control circuit 130 may also trigger the built-in self-test unit 118 to perform a built-in self-test. That is, in step S230, the digital control circuit 130 may trigger the built-in self-test units 1142 and 118 to check the data stored in the internal dynamic random access memory 1141 and the static random access memory 116, and determine the test result accordingly.

[0027] In step S240, if the built-in self-test result of the digital signal processing circuit 110 is a failure, it means that the current value of the first voltage V1 is not enough to allow the digital signal processing circuit 110 to work normally under the calibration target frequency F1. Therefore, in step S250, the digital control circuit 130 can control the power management unit 120 to increase the value of the first voltage V1, and enter step S230 again to trigger the digital signal processing circuit 110 to perform the built-in self-test. In this way, before the digital signal processing circuit 110 successfully performs the built-in self-test, the value of the first voltage V1 will gradually increase. In some embodiments, the first voltage V1 can be fixedly increased by a fixed value, such as 0.05V, each time in step S250, but the present invention is not limited to this.

[0028] When the result of the built-in self-test of the digital signal processing circuit 110 is successful, it means that the current value of the first voltage V1 is sufficient to allow the digital signal processing circuit 110 to operate at the calibrated target frequency F1 and successfully complete the built-in self-test. In this case, the digital control circuit 130 can store the current value of the first voltage V1 and the calibrated target frequency F1 in the non-volatile memory 132.

[0029] In step S270, it is determined whether the voltage of other operating frequencies needs to be calibrated. If the voltage of other operating frequencies needs to be calibrated, the calibrated calibration target frequency F1 can be updated to the calibration target frequency F2 to be calibrated next in step S280. Then, step S210 is entered again to restore the first voltage V1 to the minimum preset value, and in step S220, the digital signal processing circuit 110 is operated at the calibration target frequency F2, and then the digital signal processing circuit 110 is triggered to perform a built-in self-test, and the aforementioned operation is repeated until the result of the built-in self-test is successful, and the value of the first voltage V1 and the calibration target frequency F2 can be stored in the non-volatile memory 132.

[0030] In this way, the value of the first voltage V1 required for different operating frequencies can be calibrated in the calibration mode through the method 200. Since the digital control circuit 130 can control the power management unit 120 to find the appropriate voltage value required by the digital signal processing circuit 110 at the target operating frequency by increasing the first voltage V1, even if the digital signal processing circuit 110 and the power management unit 120 in each signal processing system 100 may have different characteristics, each signal processing system 100 can still find its own appropriate voltage value. In addition, since the operating frequency and the corresponding first voltage V1 value can be stored in the non-volatile memory 132, the signal processing system 100 can repeatedly access the corresponding voltage value without losing the record due to power failure.

[0031] Figure 3 FIG. 3 is a flow chart of an operation method 300 of the signal processing system 100 in an application mode according to an embodiment of the present invention. In the application mode, the method 300 may include steps S310 to S330.

[0032] S310: The digital control circuit 130 reads out the correction value of the first voltage V1 corresponding to the applied target frequency from the non-volatile memory 132;

[0033] S320: The digital control circuit 130 controls the power management unit 120 so that the first voltage V1 has a corrected value;

[0034] S330 : The digital control circuit 130 controls the digital signal processing circuit 110 to operate at an application target frequency.

[0035] That is, in the application mode, when the user determines the application target frequency of the digital signal processing circuit 110, the digital control circuit 130 can read the calibration value of the first voltage V1 corresponding to the application target frequency from the non-volatile memory 132 in step S310, and make the power management unit 120 output the first voltage V1 with the calibration value in step S320. In this way, in step S330, the digital signal processing circuit 110 can operate normally under the application target frequency.

[0036] exist Figure 1In the embodiment, the digital control circuit 130 may further include a second control unit 136. The second control unit 136 may be coupled to the first control unit 134, and may receive a system instruction and accordingly switch the first control unit 134 between the calibration mode and the application mode. For example, when the second control unit 136 receives a system instruction INS1, the first control unit 134 may enter the calibration mode according to the system instruction INS1, and set the calibration target frequency F1 corresponding to the calibration mode; and when the second control unit 136 receives a system instruction INS2, the first control unit 134 may enter the application mode according to the system instruction INS2, and may set the application target frequency corresponding to the application mode.

[0037] exist Figure 1 Although the digital control circuit 130 may include two first control units 134 and 136 to control different circuits respectively, in some embodiments, the digital control circuit 130 may also perform the required operations through a single control unit according to actual needs of the system.

[0038] In summary, the signal processing system and the operating method of the signal processing system provided by the embodiments of the present invention can calibrate the voltage values ​​corresponding to each operating frequency, so that the digital signal processing circuit can receive the appropriate power supply voltage and can operate normally at the required operating frequency. In addition, since each signal processing system can gradually adjust the value of the power supply voltage output by its power management unit in the calibration mode, even if different signal processing systems have different characteristics, each signal processing system can still find its own appropriate voltage value. In this way, not only can the manual detection process be simplified, but it can also ensure that the digital signal processing circuit can operate normally at the required operating frequency, thereby improving the yield of the signal processing system.

[0039] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0040]

Explanation of symbols

[0041] 100:Signal Processing System

[0042] 110: Digital signal processing circuit

[0043] 120: Power Management Unit

[0044] 130: Digital control circuit

[0045] 112: Clock generator

[0046] 114: Digital Signal Processor

[0047] 1141: Internal dynamic random access memory

[0048] 1142, 118: Built-in self-test unit

[0049] 116: Static Random Access Memory

[0050] 132: Non-volatile memory

[0051] 134: First control unit

[0052] 136: Second control unit

[0053] V1: first voltage

[0054] V2: Second voltage

[0055] SIG CTRLV :Voltage control signal

[0056] SIG CTRLF :Frequency control signal

[0057] INS1, INS2: system instructions

[0058] BUS: Bus

[0059] 200, 300: Method

[0060] S210 to S290, S310 to S330: Steps

Claims

1. A signal processing system comprising: a digital signal processing circuit; a power management unit, coupled to the digital signal processing circuit, for providing a first voltage to the digital signal processing circuit; and A digital control circuit is coupled to the digital signal processing circuit and the power management unit, and includes a non-volatile memory. The digital control circuit is used in a calibration mode to: Controlling the power management unit so that the first voltage has a minimum preset value; Controlling the digital signal processing circuit to operate at a first calibration target frequency; triggering the digital signal processing circuit to perform a built-in self-test; When the result of the built-in self-test is failure, increasing the value of the first voltage; triggering the digital signal processing circuit to execute the built-in self test again; and When the result of the built-in self-test is successful, the value of the first voltage and the first calibrated target frequency are stored in the non-volatile memory, The digital control circuit comprises: a first control unit, coupled to the digital signal processing circuit and the power management unit, for outputting a voltage control signal to the power management unit to adjust the value of the first voltage, outputting a frequency control signal to a clock generator of the digital signal processing circuit to control an operating frequency of the digital signal processing circuit, and determining whether the result of the built-in self-test is a failure or a success; and A second control unit is coupled to the first control unit, and is used to make the first control unit enter the calibration mode and set the first calibration target frequency corresponding to the calibration mode according to a first system instruction, and to make the first control unit enter an application mode and set an application target frequency corresponding to the application mode according to a second system instruction.

2. The signal processing system according to claim 1, wherein the digital control circuit is further configured to: Reading a calibration value of the first voltage corresponding to an application target frequency from the non-volatile memory; controlling the power management unit so that the first voltage has the calibration value; and The digital signal processing circuit is controlled to operate at the application target frequency. 3 . The signal processing system as claimed in claim 1 , wherein the power management unit is further configured to provide a second voltage to the digital control circuit.

4. The signal processing system according to claim 1, wherein the digital signal processing circuit further comprises: A digital signal processor comprises an internal dynamic random access memory and a first built-in self-test unit, wherein the first built-in self-test unit is coupled to the internal dynamic random access memory; The digital control circuit at least triggers the first built-in self-test unit to perform the built-in self-test.

5. The signal processing system according to claim 4, wherein the digital signal processing circuit further comprises: A static random access memory and a second built-in self-test unit, the second built-in self-test unit is coupled to the static random access memory; The digital control circuit triggers the first built-in self-test unit and the second built-in self-test unit to perform the built-in self-test. 6 . The signal processing system of claim 1 , wherein the non-volatile memory is a write-once non-volatile memory.

7. The signal processing system according to claim 1, wherein the digital control circuit is further configured to, in the calibration mode, after storing the value of the first voltage and the first calibration target frequency in the non-volatile memory: Controlling the power management unit so that the first voltage has the minimum preset value; Controlling the digital signal processing circuit to operate at a second calibration target frequency; triggering the digital signal processing circuit to execute the built-in self-test; When the result of the built-in self-test is failure, increasing the value of the first voltage; triggering the digital signal processing circuit to execute the built-in self test again; and When the result of the built-in self-test is successful, the value of the first voltage and the second calibrated target frequency are stored in the non-volatile memory.

8. An operating method of a signal processing system, the signal processing system comprising a digital signal processing circuit, a power management unit and a digital control circuit, the digital control circuit comprising a non-volatile memory, the method comprising: In a calibration mode: The digital control circuit controls the power management unit to output a first voltage having a minimum preset value to the digital signal processing circuit; The digital control circuit controls the digital signal processing circuit to operate at a first calibration target frequency; The digital control circuit triggers the digital signal processing circuit to perform a built-in self-test; When the result of the built-in self-test is failure, the digital control circuit controls the power management unit to increase the value of the first voltage; The digital control circuit triggers the digital signal processing circuit to execute the built-in self-test again; and When the result of the built-in self-test is successful, the digital control circuit stores the value of the first voltage and the first calibrated target frequency in the non-volatile memory. The digital control circuit comprises: a first control unit, coupled to the digital signal processing circuit and the power management unit, for outputting a voltage control signal to the power management unit to adjust the value of the first voltage, outputting a frequency control signal to a clock generator of the digital signal processing circuit to control an operating frequency of the digital signal processing circuit, and determining whether the result of the built-in self-test is a failure or a success; and A second control unit is coupled to the first control unit, and is used to make the first control unit enter the calibration mode and set the first calibration target frequency corresponding to the calibration mode according to a first system instruction, and to make the first control unit enter an application mode and set an application target frequency corresponding to the application mode according to a second system instruction.

9. The method according to claim 8, further comprising in the application mode: The digital control circuit reads a calibration value of the first voltage corresponding to an applied target frequency from the non-volatile memory; The digital control circuit controls the power management unit so that the first voltage has the calibration value; and The digital control circuit controls the digital signal processing circuit to operate at the application target frequency.

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