Method for calculating data dependency relationships in a computing program and computer-readable storage medium

Abstract

The present disclosure relates to a method for data dependency in a computing program and a computer-readable storage medium, which are applied to a computing device. The computing device is included in an integrated circuit device, and the integrated circuit device includes a general-purpose interconnect interface and other processing devices. The computing device interacts with other processing devices to jointly complete a computing operation specified by a user. The integrated circuit device may further include a storage device, which is respectively connected to the computing device and other processing devices for data storage of the computing device and other processing devices.

Description

Technical Field

[0001] The present disclosure generally relates to the field of computers. More specifically, the present disclosure relates to methods for data dependency relationships in computing programs and computer-readable storage media. Background Art

[0002] Accurate data flow analysis is the basis for enabling efficient compilation optimization. The static single assignment (SSA) form is an efficient data flow analysis technique that can currently be applied to almost all modern compilers. The static single assignment form is an intermediate representation (IR) in which each variable is assigned a value only once, making its use-define chain very clear and helping to simplify the compiler's algorithms.

[0003] When a memory range may be assigned a value by multiple instructions, it is difficult for the prior art to analyze the data dependency relationships between instructions, making it impossible to effectively simplify the compilation process and resulting in a waste of computing resources. Therefore, a new method for analyzing data dependency relationships between memories is urgently needed. Summary of the Invention

[0004] To at least partially solve the technical problems mentioned in the background art, the solution of the present disclosure provides a method for data dependency relationships in a computing program and a computer-readable storage medium.

[0005] In one aspect, the present disclosure discloses a method for data dependency relationships in a computing program, the method comprising: constructing the program into a control flow graph in static single assignment form, the control flow graph including a plurality of nodes; setting initial information of memory descriptors of the plurality of nodes, the initial information being the value assignment information and kill set information of all memory descriptors of the immediate dominator node; and performing iterations based on the control flow graph, each iteration performing the following steps: traversing the plurality of nodes, calculating and updating the value assignment information and kill set information of the memory descriptor of each node, and updating the data dependency relationship of the instruction. Wherein the data dependency relationship of the instruction is used as reference information for instruction compilation optimization.

[0006] In another aspect, the present disclosure discloses a computer-readable storage medium having stored thereon computer program code for data dependency relationships in a computing program, which, when run by a processor, executes the foregoing method.

[0007] The present disclosure analyzes the memory ranges for value assignment and use of each instruction or intermediate code through a compiler, calculates the data dependencies between instructions, and simultaneously establishes a definition-use chain and a use-definition chain for instructions with a definition-use relationship to simplify the data dependencies between memories and accelerate the calculation of image, voice, and text data. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] By referring to the drawings and reading the following detailed description, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understandable. In the drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0009] Figure 1A Showing an exemplary source code and control flow graph;

[0010] Figure 1B Showing an equivalent static single assignment form and control flow graph;

[0011] Figure 2 Showing an exemplary control flow graph;

[0012] Figure 3 Showing a flowchart of an embodiment of the present disclosure;

[0013] Figure 4 Showing a flowchart of another embodiment of the present disclosure;

[0014] Figure 5 Showing a flowchart of another embodiment of the present disclosure;

[0015] Figure 6 Showing a flowchart of another embodiment of the present disclosure;

[0016] Figure 7 Showing a flowchart when another embodiment of the present disclosure performs placement;

[0017] Figure 8 Showing a flowchart of another embodiment of the present disclosure;

[0018] Figure 9 is a structural diagram of an integrated circuit device showing an embodiment of the present disclosure; and

[0019] Figure 10 is a structural diagram of a board card showing an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0021] It should be understood that the terms "first", "second", "third", "fourth", etc. in the claims, the description and the drawings of the present disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "including" and "comprising" used in the description and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations.

[0022] It should also be understood that the terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. As used in the description and claims of the present disclosure, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms. It should be further understood that the term "and / or" used in the description and claims of the present disclosure refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0023] As used in this specification and the claims, the term "if" may be interpreted as "when" or "once" or "in response to determining" or "in response to detecting" depending on the context.

[0024] Next, the specific implementation manners of the present disclosure will be described in detail in conjunction with the accompanying drawings.

[0025] The present disclosure is a control flow graph using static single assignment form, which analyzes the memory intervals defined and used by each instruction through a compiler, and calculates the data dependency relationships between various instructions. For instructions with a definition and use relationship, a definition-use chain and a use-definition chain are established.

[0026] A control flow graph is an abstract data structure used in compilers, representing all the paths that a program will traverse during execution, and reflecting the possible flow directions of all basic blocks (BBs) within a procedure in the form of a flow chart. A control flow graph consists of nodes and the relationships between nodes. The nodes are the basic blocks, which are sequences of statements that are executed sequentially to the maximum extent within a program. Each basic block has only one entry and one exit, and execution starts from its entry and ends at its exit. The characteristic of a basic block is that as long as the first instruction within the basic block is executed, all the instructions within the basic block will be executed in sequence until all the instructions in the basic block have been executed.

[0027] The main purpose of static single assignment form is to adjust variables so that each variable will only be assigned a value once, in order to achieve better computing efficiency. For example, for the following three lines of code:

[0028] y := 1

[0029] y := 2

[0030] x := y

[0031] In the first line, the variable y is assigned the value 1. In the second line, the variable y is assigned the value 2. In the third line, the value of the variable y is assigned to the variable x. Since the variable y is assigned a value for the second time in the second line, covering the assignment in the first line, and the value of the variable y is used in the third line, the first line is unnecessary. In static single assignment form, the aforementioned code will be converted into the following intermediate code:

[0032] y 1 := 1

[0033] y 2 := 2

[0034] x 1 := y 2

[0035] Taking Figure 1 as an example again, Figure 1A shows the exemplary source code and control flow graph. First, the value of the input data is assigned to the variable x. Then, it is judged whether the value of the variable x is 42. If it is, the variable y is assigned the value 1. If not, the variable y is predicated as x + 2. Finally, the value of the variable y is printed. Figure 1B shows the equivalent static single assignment form and control flow graph. The variable y is rewritten as y 1 and y 2 in the two branches. The static single assignment form uses the Ф (PHI) function to merge the y 1 and y 2 values from different branches at the control flow intersection, indicating that one of the y 1 and y 2 values will be obtained and then assigned to y3 , finally print y 3 From Figure 1B It can be seen that the static single assignment form will adjust each variable in the source code so that a variable is assigned only once.

[0036] The static single assignment form is characterized by: the source variable is divided according to the activity range (from the variable's first value to its use), and a new variable with a digital suffix is ​​generated. Each variable is only assigned a value once, such as the y variable above is adjusted to y 1 and 2 ; At the intersection of control flows, there is a PHI function to merge the values ​​from different paths. The PHI function represents a parallel operation, selecting an assignment based on the path being run.

[0037] The static single assignment form simplifies two types of link relationships: the use-def chain and the def-use chain. The use-def chain is a data structure that contains a def-valued (or defined) variable and a collection of all its uses. In contrast, the def-use chain contains a use variable and a collection of all its def-values. Since variables in the non-static single assignment form are defined more than once, the def-use chain for each variable is very complex. In the static single assignment form, there are no variables with the same name, and each variable is defined only once, so uses of the same name belong to its def-use chain, and each variable is defined only once before use, so the use-def chain is one-to-one. It can be seen that both the use-def chain and the def-use chain in the static single assignment form have been simplified.

[0038] The static single assignment form brings the following benefits: for scalars, each variable has only one unique value, making data flow analysis and optimization algorithms simpler; the memory space occupied by the use-value relationship chain is reduced from exponential growth to linear growth; the relationship between use and value is more intuitive; several unrelated uses of the same variable in the source program will be converted into uses of different variables in the static single assignment form, thus avoiding the execution of unnecessary redundant instructions.

[0039] For tensors, each variable can be defined by a memory descriptor. A memory descriptor is used to describe a memory range. It has three types of information: variable name, offset, and size. For example, MD1 (var: A, offset: 0, size: 128) means that the memory descriptor numbered 1 contains the data of variable A, which is stored in the 128 consecutive address spaces [0: 127] starting from the address with offset 0.

[0040] If there is also an MD2 (var: A, offset: 32, size: 32), obviously, there is an intersection between MD2 and MD1 in the memory range [32, 63]. Then, when an instruction defines MD1, it may also affect the memory range corresponding to MD2. In this case, the definition of this instruction for MD1 is a must define, while for other memory descriptors (such as MD2) that intersect with MD1, it is a may define. Similarly, there are similar definitions for used memory descriptors, namely must use and may use. In other words, "must" refers to the inevitable description of the range, while "may" refers to any other range that intersects with "must".

[0041] Furthermore, if the offset and size of a memory descriptor are both exact values or ranges, then the memory descriptor is "exact", otherwise it is not. For example: MD3[0, 127] is exact, while MD4[32, X] is not exact (X is unknown).

[0042] In addition, still taking the aforementioned MD1 and MD2 as examples, if the definition of MD2 is earlier than that of MD1, then regardless of the value of the definition of MD2, it will be "killed" by the subsequent MD1, that is, overwritten; if the definition of MD2 is later than that of MD1, then the definition of MD2 will kill a part of the definition range of MD1, that is, [32, 63]. This killed range information is called kill set information. That is to say, the kill set of a memory descriptor records the ranges that will be killed by other instructions, and the definitions of the memory descriptor are invalid for these ranges.

[0043] There are so-called dominator, strictly dominator, and immediate dominator in the control flow graph. Figure 2An exemplary control flow graph is shown to illustrate these nodes. For example, for node H, the starting point of the path is node A, which then passes through node E. There is a branch after node E, which may go to node F or node G. Regardless of whether node F or node G is followed, node H will be passed after the end. A dominant node refers to a basic block that must be passed from the starting point of the control flow graph to a specific basic block. To reach node H, node A, node E, and node H itself must be passed. Therefore, node A, node E, and node H are all dominant nodes of node H. A strictly dominant node is a dominant node other than a specific basic block itself. Again, taking node H as an example, node A and node E are strictly dominant nodes of node H. A directly dominant node refers to a dominant node that is closest to a specific basic block, and node E is the direct dominant node of node H.

[0044] In the process of constructing the static single assignment form, we also need to consider the dominance frontier, which is where the dominance relationship of a node ends and where other control flows appear. The dominance frontier is intuitively understood as the boundary that a specific node can dominate (but not including this boundary). Figure 2 Taking the E node as an example, it strictly dominates the F node, G node, and H node. The dominating boundaries of the E node are the D node (the immediate successor node of the F node), the M node (the immediate successor node of the H node), and the L node (the immediate successor node of the node). As shown in the figure, the D node, the M node, and the L node have other branches leading to them, so they are not dominated by the E node.

[0045] One embodiment of the present disclosure is a method for calculating data dependencies in a program in a control flow graph. In an environment where tensor instructions are applicable, the program can be used to perform inference calculations or other operations on image, voice, and text data in a neural network, without specific limitation. For situations involving tensor instructions, a tensor memory interval may be set by multiple instructions. The method of the embodiment of the present application is used to analyze data dependencies between instructions based on memory descriptors. Figure 3 A flow chart of this embodiment is shown.

[0046] In step 301, the program is constructed into a control flow graph in a static single assignment form. There are many ways to convert a program into a static single assignment form. The simplest way is to replace each assigned variable with a new variable name, such as Figure 1A The variable y in the A basic block and the B basic block in the source program shown is changed to Figure 1B The variable y of the basic block A 1 With the variable y of the B basic block 2 .

[0047] However, in Figure 1AThe use of variable y in basic block C is indeterminate because the predecessor basic blocks (basic block A and basic block B) both assign values to variable y, and it is impossible to know at compile time which predecessor basic block the program will reach basic block C from. When the control flow graph encounters this situation, this step then adds a PHI function. As Figure 1B shown, a PHI function instruction is added at the beginning of basic block C, and a variable y is redefined based on variable y 3 , and the PHI function can select the corresponding version according to the program's execution path, that is, select to use variable y 1 or y 2 .

[0048] This embodiment accurately determines in which basic blocks the PHI function should be inserted through the dominance frontier. If a certain node assigns a value to a certain variable, then this variable will reach every node dominated by that node, and a PHI function needs to be added in the immediate successor basic block.

[0049] This embodiment implements the PHI function in the following way. Also taking Figure 1B as an example, assume that the y in basic block A 1 is allocated to register R 1 , and the y in basic block B 2 is allocated to register R 2 , then the PHI function y in basic block C 3 ←Ф(A:y 1 ,B:y 2 ) can generate the following instructions at the end of basic block A:

[0050] move R 3 ←R 1

[0051] That is, move the data in register R 1 to register R 3 . Similarly, the following instructions are generated at the end of basic block B:

[0052] move R 3 ←R 2

[0053] Move the data in register R 2 to register R 3 . In this way, no matter whether the program passes through basic block A or basic block B, register R 3 will be the correct assignment of variable y 3 .

[0054] In step 302, the directly controlling nodes of all nodes are identified. This step can use the classic Lengauer-Tarjan algorithm or other algorithms to identify the directly controlling nodes. Figure 2 Taking the control flow graph of as an example, this embodiment identifies that the directly controlling nodes are A node, B node, E node and I node.

[0055] In step 303, the initial information of all nodes is set, and the initial information is the fixed value information and kill set information of all memory descriptors of the corresponding directly controlled nodes. Since each variable in the directly controlled node will be directly used in the rear-drive basic block, this embodiment uses the fixed value and kill set of each variable in the directly controlled node as the initial information of the rear-drive basic block when setting the initial information. Furthermore, the variable is defined by the memory descriptor, so setting the initial information of all nodes is to set the initial information of each variable in the node, that is, to set the fixed value information and kill set information of the memory descriptor corresponding to the variable.

[0056] by Figure 2 For example, the C node is directly controlled by the B node. Therefore, the fixed value information and kill set information of the memory descriptor of the variable in the B node are used as the initial information of the fixed value information and kill set information of the memory descriptor of the variable in the C node. Figure 2 Taking the L node as an example, its directly controlled node is the A node. Therefore, the fixed value information and kill set information of the memory descriptor of the variable in the A node are used as the initial information of the fixed value information and kill set information of the memory descriptor of the variable in the L node.

[0057] In this embodiment, the kill set information is all in an ordered list, generally arranged from low to high addresses, to facilitate various intersection and union operations.

[0058] In step 304, iteration is performed based on the control flow graph. Each time the iteration is executed, all nodes are traversed, the fixed value information and kill set information of the memory descriptor of each node are calculated and updated, and the data dependency of the instruction is updated. Initially, the fixed value information and kill set information of the memory descriptor of each node are calculated based on the initial information obtained in step 303. After obtaining the new fixed value information and kill set information, the new fixed value information and kill set information are substituted for recalculation, and the iteration is repeated until the fixed value information and kill set information of the memory descriptor of the variable in each node no longer change.

[0059] In the iterative process, the order of the data stream can be pre-order, in-order, post-order or reverse post-order. Taking post-order as an example, the operation is to traverse the left subtree in reverse order, then traverse the right subtree in reverse order, and finally visit the root node. Figure 2For example, the result of post-order traversal is M→D→C→B→H→F→G→E→L→J→K→I→A. Taking the reverse post-order as an example, it is first traversed in post-order, and then the result is inverted, so Figure 2 The reverse post-order traversal result of the control flow graph is A→I→K→J→L→E→G→F→H→B→C→D→M, and the reverse post-order traversal can converge earlier. This embodiment does not limit the order of traversal, but preferably adopts the reverse post-order traversal.

[0060] When the fixed value information and kill set information of the memory descriptor of the variable in each node no longer change, the iteration can be ended, and the fixed value-use chain, use-fixed value chain and kill set information at this time are the final results. In detail, in the process of updating the fixed value information and kill set information of each memory descriptor, it is actually to update the data dependency between instructions. These data dependencies will be used as reference information for instruction compilation optimization. The optimized instructions can be compiled into machine code that can be executed by the computer, so that the computer can perform calculations such as image, voice, and text data according to the data dependencies of these instructions. Among them, instruction compilation optimization includes but is not limited to dead code deletion, common subexpression deletion, constant folding, etc.

[0061] This embodiment takes into account that the node may involve a PHI function, and in this step, the instructions of each basic block are further traversed to determine whether the successor basic block of each basic block is a PHI node. If it is a PHI node, the fixed value information of all direct predecessor nodes of the PHI node is set as the fixed value information of the memory descriptor of the PHI node to determine the fixed value information of the PHI node. Then, the kill set information of these immediate predecessor nodes is intersected to generate an intersection interval of the kill set information of the immediate predecessor node, and then the intersection interval is set as the kill set information of the memory descriptor of the PHI node to determine the kill set information of the PHI node.

[0062] Let's take an example to illustrate the PHI function's evaluation method. Assume that there are two branch inputs in the PHI node, and the two immediate predecessor nodes have instructions to evaluate the memory descriptor MD1, namely MD1V1 and MD1V2, and assume that the record information of MD1V1 and MD1V2 is as follows:

[0063] Fixed value information Kill set information MD1V1 IR1, IR2 {[1,127]} MD1V2 IR3, IR4 {[32,63]}

[0064] Set the value information of all immediate predecessors of the PHI node to the value information of the memory descriptor of the PHI node, namely IR1, IR2, IR3, and IR4. Then, take the intersection of the kill set information of these immediate predecessors to generate the intersection interval of the kill set information of the immediate predecessors. The intersection interval of [1, 127] and [32, 63] is [32, 63]. Therefore, the kill set information of the memory descriptor of the PHI node is [32, 63].

[0065]

[0066] In step 304 of the foregoing embodiment, generally, the uses of the instruction are identified first, and then the defs of the instruction are identified. More specifically, in the foregoing embodiment, it is first identified which instructions in each node are uses and which are defs, and then the value information and kill set information of the memory descriptors of the uses of those instructions are calculated and updated, and then the value information and kill set information of the memory descriptors of the defs of those instructions are calculated and updated.

[0067] For example, for the addition instruction: C[0, 127] = A[0, 127] + B[0, 127], this addition instruction defines MD1(var: C, offset: 0, size: 128), and this addition instruction uses MD2(var: A, offset: 0, size: 128) and MD3(var: B, offset: 0, size: 128). In the embodiments of the present disclosure, when calculating and updating the value information and kill set information of the memory descriptors in each node, the value information and kill set information of the uses (MD2 and MD3) of this addition instruction can be calculated and updated first, and then the value information and kill set information of the def MD1 of this addition instruction can be calculated and updated.

[0068] Another embodiment of the present disclosure is a method for calculating and updating the value information and kill set information of the memory descriptors of the uses of an instruction, Figure 4 showing its flowchart.

[0069] In step 401, it is determined whether there is a memory descriptor that must be used for the use of the instruction. If there is no memory descriptor that must be used, step 402 is executed to set the fixed value information of the memory descriptor that may be used as the fixed value information of the memory descriptor used by the instruction. Among them, the possible memory descriptor can be multiple memory descriptors corresponding to the same variable, or it can be a descriptor corresponding to multiple different variables. If there is a memory descriptor that must be used, step 403 is executed to determine whether there is a memory descriptor that must be used accurately, that is, whether the memory descriptor that must be used is accurate. If it is not accurate, step 404 is executed to set the fixed value information of the memory descriptor that must be used and the fixed value information of the memory descriptor that may be used as the fixed value information of the memory descriptor used by the instruction, that is, the fixed value information of the memory descriptor that must be used and the fixed value information of the memory descriptor that may be used are both used as the fixed value information of the memory descriptor used by the instruction. If it is accurate, step 405 is executed.

[0070] In step 405, it is determined whether the fixed value information of the memory descriptor that must be used accurately exists. If not, step 406 is executed to identify all possible memory descriptors that have fixed value information, and then step 413 is executed. If it exists, step 407 is executed to set the fixed value information of the memory descriptor that must be used accurately as the fixed value information used by the instruction, and then step 408 is executed.

[0071] In step 408, it is determined whether the kill set information of the memory descriptor that must be used accurately is empty, wherein the kill set can be determined by considering all possible memory descriptors that can be used for the same variable. If it is empty, it means that the fixed value information of the memory descriptor that must be used accurately has not been killed, then step 409 is executed, and there is no need to set the kill set information used by the instruction, that is, its kill set information is empty, and the whole process ends. If it is not empty, it means that part of the fixed value information of the memory descriptor that must be used accurately has been killed, then step 411 is executed.

[0072] In step 411, determine whether the fixed value information of the possible use of the memory descriptor that makes the kill set information not empty exists. If not, there is no need to consider the possible use of the memory descriptor, and the fixed value information based on the aforementioned memory descriptor that must be used can be used. At this time, execute step 409 to end the entire process. If it exists, execute step 413 to determine whether the intersection interval of the fixed value information of the memory descriptor that must be used and the fixed value information of the possible use of the memory descriptor has been killed. If it has not been killed, execute step 414 to set the fixed value information of the possible use of the memory descriptor and the fixed value information of the memory descriptor that must be used as the fixed value information used. If it has been killed, execute step 409 to end the entire process.

[0073] Another embodiment of the present disclosure is also a method for calculating and updating the value information and kill set information of the uses of an instruction. Figure 5 A flowchart showing this embodiment is different from Figure 4 the embodiment of

[0074] in two aspects. Figure 5 One aspect is that the embodiment of

[0075] does not include step 413. In other words, after step 406, without considering whether the intersection interval of the value information that must use a memory descriptor and the value information that may use a memory descriptor is killed, directly execute step 501 to set the value information that may use a memory descriptor as the value information of the uses of the instruction.

[0076] After calculating and updating the value information and kill set information of the uses of the memory descriptor of an instruction, step 304 then calculates and updates the value information and kill set information of the values of the instruction.

[0077] Another embodiment of the present disclosure is a method for calculating and updating the value information and kill set information of the values of an instruction. Figure 6 A flowchart showing it is as follows.

[0078] In step 601, it is judged whether there is a must-value memory descriptor for the value of the instruction. If not, execute step 602 to identify all possible value memory descriptors. Then execute step 603 to exclude the possible value memory descriptors covered by other possible value memory descriptors among all possible value memory descriptors. Then execute step 604 to exclude the possible value memory descriptors with existing value information among all possible value memory descriptors. Then execute step 605 to establish the value information of the possible value memory descriptors that are not excluded among all possible value memory descriptors. When it is judged in step 601 that there is a must-value memory descriptor for the value of the instruction, then execute step 606.

[0079] In step 606, it is determined whether the must-define memory descriptor is precise. If it is precise, then step 607 is executed to establish the definition information of the must-define memory descriptor in the definition of the instruction. Then step 608 is executed to identify the possible definition memory descriptors of the must-define memory descriptor in the definition of the instruction. Then step 609 is executed to place the definition information of the must-define memory descriptor in the definition of the instruction into the kill set information of the possible definition memory descriptor. When it is determined in step 606 that the must-define memory descriptor is not precise, then step 610 is executed.

[0080] In step 610, it is determined whether there is definition information for the possible definition memory descriptor. If there is definition information, then step 611 is executed to mark that the possible definition memory descriptor is killed. If there is no definition information, indicating that there is no information available for definition, then step 612 is executed to end the entire process.

[0081] In step 609, the way of placing can be further refined as shown in Figure 7 the following process. In step 701, it is determined whether the possible definition memory descriptor is completely killed. If it is completely killed, then step 702 is executed to delete the record of the possible definition memory descriptor. If it is not completely killed, then step 703 is executed to determine whether the kill set information of the possible definition memory descriptor is empty. If it is empty, then step 704 is executed to place all intervals of the definition information of the must-define memory descriptor in the definition of the instruction into the kill set information of the possible definition memory descriptor. If it is not empty, then step 705 is executed to establish the union interval of the kill set information of the possible definition memory descriptor and the definition information of the must-define memory descriptor. Then step 706 is executed to place the union interval into the kill set information of the possible definition memory descriptor.

[0082] In another scenario, when it is determined in step 601 whether there is a must-define memory descriptor in the definition of the instruction, some special possible definition memory descriptors as shown in step 603 or 604 are not excluded. Instead, after identifying all possible definition memory descriptors in step 602, the definition information of all possible definition memory descriptors is directly established.

[0083] In another scenario, when the foregoing must-define memory descriptor is predicated, it cannot be determined at compile time whether the predicate will be executed. Based on the predicate situation, this embodiment further executes as shown in Figure 8 the following process.

[0084] In step 801, it is determined whether the must-define memory descriptor in the definition of the instruction is predicated. If it is not predicated, then step 802 is executed to executeFigure 6 If it is a predicate, it is necessary to establish the fixed value information of the required fixed value memory descriptor of the instruction, then continue to execute step 803 to determine whether there is fixed value information for the required fixed value memory descriptor of the fixed value of the instruction. If there is fixed value information, execute step 804 to add the fixed value of the instruction to the fixed value information of the required fixed value memory descriptor of the fixed value of the instruction. If there is no fixed value information, it is necessary to establish the fixed value information of the required fixed value memory descriptor of the fixed value of the new instruction, then execute step 802, execute Figure 6 process.

[0085] At the same time, in the process of calculating and updating the fixed value information and kill set information of the memory descriptor of the instruction, step 304 can also simultaneously update the data dependency of the instruction, and the data dependency of the instruction can refer to the fixed value information corresponding to the use of each instruction, so that the fixed value-use chain and the use-fixed value chain can be determined. The data dependency can be recorded and stored in the form of an array.

[0086] In order to more clearly understand the technical solution of the present disclosure, the following examples are given to compare the above-mentioned processes.

[0087] In an example, a variable in a control flow graph involves multiple memory descriptors and their value information as follows: MD1[0,31], MD2[0,15], MD3[16,31], MD4[0,64], and based on the reverse data flow, there are 6 related instructions that set and use the variable as shown in the following table:

[0088]

[0089]

[0090] Each instruction is processed in sequence. First, instruction IR1 is processed, which must be set to MD1. Since it is the set value of the instruction, it is executed. Figure 6The process is as follows. In step 601, it is judged whether there is a must-define memory descriptor for IR1. Since MD1 is a must-define memory descriptor, step 606 is executed to judge whether the must-define memory descriptor is precise. The interval [0, 31] of MD1 is precise, and then step 607 is executed to establish the definition information of the must-define memory descriptor in IR1, that is, set MD1[0, 31] as the definition information of the variable. Then steps 608 and 609 are executed. Although MD2, MD3, and MD4 are may-define memory descriptors, by querying the initial information, it is determined that MD2, MD3, and MD4 do not appear in the instructions before IR1. Therefore, the may-define memory descriptors MD2, MD3, and MD4 cannot be considered in the definition of this instruction. Thus, in steps 608 and 609, there is no need to record the may-define memory descriptors nor update the kill set information. Therefore, the record information of the memory descriptor of this variable is as follows:

[0091] Fixed value information Kill set information MD1 IR1 {}

[0092] Among them, the kill set information is recorded as {} indicating that its kill set information is empty.

[0093] Next, process instruction IR2. It must use MD1. Since it is the use of an instruction, execute Figure 4 or Figure 5 the process. Here, take Figure 4 as an example to illustrate. In step 401, it is judged whether there is a must-use memory descriptor for the use of the instruction. Since there is MD1, step 403 is executed to judge whether there is a must-precisely-use memory descriptor. Since MD1 is precise, step 405 is executed to judge whether the definition information of the must-precisely-use memory descriptor exists. The definition information [0, 31] of MD1 exists. Then step 407 is executed to set the definition information of the must-precisely-use memory descriptor as the definition information of the use of the instruction. Therefore, the definition information of the use of instruction IR2 is set to IR1 (the definition instruction of MD1). Then step 408 is executed to judge whether the kill set information of the must-precisely-use memory descriptor is empty. Since no interval of MD1 has been killed yet, step 409 is executed and there is no need to consider the kill set information anymore, ending the entire process. In other words, the definition information of IR2 is IR1, and thus the data dependence relationship (i.e., the use_def chain) between instruction IR2 and IR1 can be determined, and the kill set information is empty.

[0094] Next, process instruction IR3. It must define MD2, so execute Figure 6The process. In step 601, it is judged whether there is a must-define memory descriptor for IR3. MD2 is a must-define memory descriptor, so step 606 is executed to judge whether the must-define memory descriptor is precise. The interval [0, 15] of MD2 is precise, and then step 607 is executed to establish the definition information of the must-define memory descriptor in IR3, that is, set MD2[0, 15] as the definition information of this variable. Then steps 608 and 609 are executed. Since MD1 is a possible definition memory descriptor of MD2, in step 609, the kill set information of MD1 is updated. Therefore, the updated record information of the memory descriptor of this variable is as follows:

[0095] Fixed value information Kill set information MD1 IR1 {[0,15]} MD2 IR3 {}

[0096] Next, process instruction IR4, which must use MD1. In step 401, it is judged whether there is a must-use memory descriptor for the use of the instruction. Since there is MD1, step 403 is executed to judge whether there is a must-precise use memory descriptor. Since MD1 is precise, step 405 is executed to judge whether the definition information of the must-precise use memory descriptor exists. The definition information of MD1 exists, and then step 407 is executed to set the definition information of the must-precise use memory descriptor as the definition information of the use of instruction IR4. Therefore, the definition information of the use of instruction IR4 is set to IR1. Then step 408 is executed to judge whether the kill set information of the must-precise use memory descriptor is empty. After processing IR3, the kill set information of MD1 is no longer empty, so step 411 is executed to judge whether the definition information of the possible use memory descriptor exists. MD2 has definition information, so step 413 is executed to judge whether the intersection interval [0, 15] of the definition information of MD1 and the definition information of MD2 is killed. Since the interval [0, 15] of MD2 is not killed, step 414 is executed to set the definition information of MD2 as the definition information of the use of this instruction. Therefore, the definition information of IR4 is: IR1 (the definition instruction of MD1) and IR3 (the definition instruction of MD2), so that the data dependence relationship (i.e., the use_def chain) between instructions IR4, IR2, and IR1 can be determined. In other words, IR4 uses MD1, and the interval of MD1 is defined by two instructions. Among them, IR1 defines [16, 31], and IR3 defines [0, 15].

[0097] Next, process instruction IR5, which must define MD3, so execute Figure 6The process. In step 601, it is judged whether there is a must-define memory descriptor for IR5. MD3 is a must-define memory descriptor, so step 606 is executed. It is judged whether the must-define memory descriptor is precise. MD3 is precise. Then step 607 is executed to establish the definition information of the must-define memory descriptor in IR5, that is, set MD3 as the definition information of the memory descriptor of this variable. Then steps 608 and 609 are executed. Since MD1 is a possible definition memory descriptor of MD3, in step 609, the kill set information of MD1 is updated. Since the original kill interval of MD1 is [0, 15] and the new kill interval is [16, 31], these two intervals are merged into a new interval [0, 31], and this interval happens to be the complete interval corresponding to MD1. In other words, all the definitions of MD1 have been killed. So the record of this variable is updated as follows:

[0098] Fixed value information Kill set information MD2 IR3 {} MD3 IR5 {}

[0099] Then process instruction IR6, which must use MD4. In step 401, it is judged whether there is a must-use memory descriptor for the use of the instruction. Since MD4 has not been defined in the previous instructions, there is no must-use memory descriptor. So step 402 is executed to set the definition information of the possible use memory descriptor as the definition information of the use of the instruction. When considering all possible use memory descriptors, only MD2 and MD3 exist in the record, and the valid intervals of these two memory descriptors have not been killed. So the definition information of these two memory descriptors (i.e., IR3 and IR5) is used as the definition information of IR6, so as to determine the data dependence relationship (i.e., use_def chain) between instructions IR6, IR3 and IR5.

[0100] In another example, assume there are four memory descriptors, namely: MD1[0, 31], MD2[0, X], MD3[0, 31], MD4[0, 63], where X represents the specific address of the corresponding memory interval that cannot be determined at compile time, and MD1 and MD2 describe the same variable, for example, variable A, and MD3 and MD4 describe the same variable, for example, variable B. The following are the instructions for these four memory descriptors:

[0101]

[0102] First, process instruction IR1, which must define MD1. Since it is the definition of the instruction, execute Figure 6Process. In step 601, it is judged whether there is a must-define memory descriptor in IR1. MD1 is a must-define memory descriptor, so step 606 is executed. It is judged whether the must-define memory descriptor is precise. MD1 is precise. Then step 607 is executed to establish the definition information of the must-define memory descriptor in IR1, that is, set MD1[0,31] as the definition information of variable A. Then steps 608 and 609 are executed. Although the definition of MD2 will affect the definition information of MD1, MD2 has not been defined by the previous instructions in IR1, so the possible definition memory descriptor MD2 cannot be considered in this instruction. Therefore, there is no need to record the possible definition memory descriptor and update the kill set information in steps 608 and 609. Therefore, the record information of the memory descriptor of variable A is established as follows:

[0103] Fixed value information Kill set information is_kill MD1 IR1 {} False

[0104] Among them, is_kill records whether the memory descriptor is killed. True means it is killed, and false means it is not killed.

[0105] Then instruction IR2 is processed, and it must define MD2. In step 601, it is judged whether there is a must-define memory descriptor in IR2. MD2 is a must-define memory descriptor, so step 606 is executed. It is judged whether the must-define memory descriptor is precise. MD2 is not precise, where X is undetermined. So in step 610, it is judged whether there is definition information for the possible definition memory descriptor. Since there is definition information for the possible definition memory descriptor MD1 of IR2, step 611 is executed to note that MD1 is killed, that is, the is_kill of MD1 is changed to true, indicating that a part of the interval of MD1 is killed. However, since the definition information of MD2 is not precise, the kill set information of MD1 cannot be determined. Therefore, the is_kill information is used to indicate that MD1 is killed. Therefore, the record of the memory descriptor of variable A is updated as follows:

[0106] Fixed value information Kill set information is_kill MD1 IR1 {} True MD2 IR2 {} False

[0107] Next, instruction IR3 is processed, which must use MD2. In step 401, it is determined whether the use of the instruction requires the use of a memory descriptor. MD2 is a memory descriptor that must be used, so step 403 is executed to determine whether a memory descriptor must be used accurately. Since MD2 is not accurate, step 404 is executed to set the fixed value information of the memory descriptor that must be used and the memory descriptor that may be used as the fixed value information of the memory descriptor used by the instruction, that is, the fixed value information of MD2 and the fixed value information of MD1 are both used as the fixed value information of IR3. The fixed value information used by IR3 for MD2 is IR1 and IR2, so that the data dependency relationship (i.e., use_def chain) between instructions IR3, IR2, and IR1 can be determined.

[0108] Next, instruction IR4 is processed, which is the fixed value of the instruction. In step 601, it is determined whether there is a required fixed value memory descriptor for the instruction. Since it does not exist, step 602 is executed to identify all possible fixed value memory descriptors. In this example, all possible fixed value memory descriptors are MD1, MD2, MD3, and MD4. Then step 603 is executed to exclude possible fixed value memory descriptors covered by other possible fixed value memory descriptors among all possible fixed value memory descriptors. Since MD3 is completely covered by MD4, MD3 is excluded. Then step 604 is executed to exclude possible fixed value memory descriptors that already have fixed value information among all possible fixed value memory descriptors. MD1 and MD2 already have fixed value information, so they are excluded, so only MD4 is left. Then step 605 is executed to establish the fixed value information of the possible fixed value memory descriptors that are not excluded among all possible fixed value memory descriptors, that is, the fixed value information of MD4 corresponding to the newly added variable B. The fixed value information of each memory descriptor after updating is as follows:

[0109] Fixed value information Kill set information is_kill MD1 IR1 {} True MD2 IR2 {} False MD4 IR4 {} False

[0110] Next, instruction IR5 is processed, which must evaluate to MD1. Since IR5 is predicated, the execution is as follows Figure 8 The process shown. In step 801, determine whether the required fixed value memory descriptor of the fixed value of the instruction is predicated. Since it is predicated, step 803 is executed to determine whether the required fixed value memory descriptor of the fixed value of the instruction has fixed value information. If MD1 has fixed value information, step 804 is executed to add the fixed value of the instruction to the fixed value information of the required fixed value memory descriptor of the fixed value of the instruction. Therefore, the fixed value record is updated as:

[0111] Fixed value information Kill set information is_kill MD1 IR1, IR5 {} True MD2 IR2 {} False MD4 IR4 {} False

[0112] Next, instruction IR6 is processed, which is the use of an instruction. In step 401, it is determined whether there is a memory descriptor that must be used for the use of the instruction. Since there is no memory descriptor that must be used, step 402 is executed to set the constant value information of the possible memory descriptor to the constant value information of the use of instruction IR6. The constant value information used in IR6 is: IR1, IR2, IR4, IR5, so that the data dependence relationship (i.e., the use_def chain) between instruction IR6 and IR2, IR1, IR4, and IR5 can be determined.

[0113] Another embodiment of the present disclosure is a computer-readable storage medium, on which computer program code for calculating data dependence relationships in a calculation program is stored. When the computer program code runs on a processor, various methods of the present disclosure are executed, such as Figures 3 to 8 the methods described above.

[0114] Through the above-described embodiments, the compiler analyzes the memory ranges and kill set information of each constant value and the use of instructions, calculates the data dependence relationships between instructions, and at the same time, for instructions with a constant value-use relationship, establishes technical means for a constant value-use chain and a use-constant value chain, to solve the technical problem of difficult analysis of data dependence relationships between memories, resulting in waste of computing resources, and achieve the technical effect of improving computing efficiency.

[0115] Based on the data dependence relationship, the compiler can perform compilation optimization, thereby effectively reducing unnecessary calculation programs and obtaining optimized code. The compiler can further convert the above optimized code into machine code, which can be executed by an artificial intelligence chip, enabling the artificial intelligence chip, especially neural network inference, to run at an accelerated speed.

[0116] Figure 9 FIG. is a structural diagram showing an integrated circuit device 900 to which embodiments of the present disclosure are applied. As Figure 9 shown, the integrated circuit device 900 includes a computing device 902, and the computing device 902 carries machine code compiled according to the embodiments of the present disclosure to implement neural network inference. In addition, the integrated circuit device 900 further includes a general-purpose interconnect interface 904 and other processing devices 906.

[0117] The other processing device 906 may be one or more types of processors such as a central processing unit, a graphics processing unit, and an artificial intelligence processor, and the number thereof is not limited but determined according to actual needs. The other processing device 906 serves as an interface for the computing device 902 to external data and control, and executes basic controls including but not limited to data transfer and starting and stopping the computing device 902. The other processing device 906 may also cooperate with the computing device 902 to jointly complete computing tasks.

[0118] The general interconnect interface 904 can be used to transfer data and control instructions between the computing device 902 and other processing devices 906. For example, the computing device 902 can obtain the required input data from other processing devices 906 via the general interconnect interface 904 and write it into the storage unit on the chip of the computing device 902. Further, the computing device 902 can obtain control instructions from other processing devices 906 via the general interconnect interface 904 and write them into the control cache on the chip of the computing device 902. Alternatively or optionally, the general interconnect interface 904 can also read the data in the storage module of the computing device 902 and transfer it to other processing devices 906.

[0119] The integrated circuit device 900 further includes a storage device 908, which can be connected to the computing device 902 and other processing devices 906 respectively. The storage device 908 is used to store the data of the computing device 902 and other processing devices 906, and is particularly suitable for the data that needs to be operated but cannot be fully stored in the internal storage of the computing device 902 or other processing devices 906.

[0120] According to different application scenarios, the integrated circuit device 900 can be used as a system-on-chip (SOC) for devices such as mobile phones, robots, drones, and video acquisition, thereby effectively reducing the core area of the control part, improving the processing speed, and reducing the overall power consumption. In this case, the general interconnect interface 904 of the integrated circuit device 900 is connected to some components of the device. Some of these components can be, for example, a camera, a display, a mouse, a keyboard, a network card, or a wifi interface.

[0121] The present disclosure also discloses a chip or an integrated circuit chip, which includes the integrated circuit device 900. The present disclosure also discloses a chip packaging structure, which includes the above chip.

[0122] Another embodiment of the present disclosure is a board card, which includes the above chip packaging structure. Refer to Figure 10 , in addition to including a plurality of the above chips 1002, the board card 1000 can also include other supporting components, and the supporting components include a storage device 1004, an interface device 1006, and a control device 1008.

[0123] The storage device 1004 is connected to the chip 1002 in the chip packaging structure through a bus 1014 and is used to store data. The storage device 1004 can include multiple groups of storage units 1010.

[0124] The interface device 1006 is electrically connected to the chip 1002 in the chip package structure. The interface device 1006 is used to realize data transmission between the chip 1002 and the external device 1012 (such as a server or a computer). In this embodiment, the interface device 1006 is a standard PCIe interface, and the data to be processed is transmitted from the server to the chip 1002 through the standard PCIe interface to realize data transfer. The calculation result of the chip 1002 is also transmitted back to the external device 1012 by the interface device 1006.

[0125] The control device 1008 is electrically connected to the chip 1002 so as to monitor the state of the chip 1002. Specifically, the chip 1002 and the control device 1008 may be electrically connected via an SPI interface. The control device 1008 may include a single chip microcomputer ("MCU", Micro Controller Unit).

[0126] Another embodiment of the present disclosure is an electronic device or apparatus, which includes the above-mentioned board 1000. According to different application scenarios, the electronic device or apparatus may include a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a means of transportation, a household appliance, and / or a medical device. The means of transportation include an airplane, a ship and / or a vehicle; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, an electric rice cooker, a humidifier, a washing machine, an electric lamp, a gas stove, and a range hood; the medical device includes an MRI, an ultrasound machine and / or an electrocardiograph.

[0127] The foregoing content can be better understood in accordance with the following terms:

[0128] Clause A1. A method for calculating data dependencies in a program, the method comprising: constructing the program into a control flow graph in a static single assignment form, the control flow graph comprising a plurality of nodes; setting initial information of the memory descriptors of the plurality of nodes, the initial information being the fixed value information and kill set information of all memory descriptors that directly control the nodes; and iterating based on the control flow graph, each iteration performing the following steps: traversing the plurality of nodes, calculating and updating the fixed value information and kill set information of the memory descriptor of each node, and updating the data dependencies of the instructions. The data dependencies of the instructions are used as reference information for instruction compilation optimization.

[0129] Item A2. The method according to Item A1, wherein the iteration step is performed in reverse order data flow.

[0130] Clause A3. The method according to Clause A1, wherein in the calculation step, the memory descriptor used by the instruction is calculated and updated first, and then the memory descriptor of the value of the instruction is calculated and updated.

[0131] Clause A4. The method according to Clause A3, wherein for the use of the instruction, the calculation step further includes: determining whether there is a memory descriptor that must be used precisely; if so, determining whether the value information of the memory descriptor that must be used precisely exists; if the value information exists, setting the value information of the memory descriptor that must be used precisely as the value information used.

[0132] Clause A5. The method according to Clause A4, wherein if the value information exists, the calculation step further includes: determining whether the kill set information of the memory descriptor that must be used precisely is empty; and if not, identifying the possible memory descriptors that make the kill set information not empty; determining whether the value information of the possible memory descriptors exists; if the value information of the possible memory descriptors exists, determining whether the intersection interval of the value information of the memory descriptor that must be used and the value information of the possible memory descriptors is killed; if not killed, setting the value information of the possible memory descriptors and the value information of the memory descriptor that must be used as the value information used by the instruction.

[0133] Clause A6. The method according to Clause A4, wherein if the value information exists, the calculation step further includes: determining whether the kill set information of the memory descriptor that must be used precisely is empty; and if not, determining whether the value information of the possible memory descriptors exists; if the value information of the possible memory descriptors exists, setting the value information of the possible memory descriptors and the value information of the memory descriptor that must be used as the value information used by the instruction.

[0134] Clause A7. The method according to Clause A4, wherein if the value information does not exist, the calculation step further includes: identifying all possible memory descriptors with value information; determining whether the intersection interval of the value information of the memory descriptor that must be used precisely and the value information of the possible memory descriptors is killed; and if not killed, setting the value information of the possible memory descriptors and the value information of the memory descriptor that must be used as the value information used by the instruction.

[0135] Item A8. A method according to Item A4, wherein if the constant value information does not exist, the calculation step further includes: identifying all possible memory descriptors that have constant value information; and setting the constant value information of the possible memory descriptors to be the constant value information used by the instruction.

[0136] Item A9. The method according to Item A4, wherein if there is no memory descriptor that must be used precisely, the calculation step further includes: setting the constant value information of the memory descriptor that must be used and the memory descriptor that may be used as the constant value information used by the instruction.

[0137] Item A10. A method according to Item A4, wherein the calculation step further includes: determining whether a memory descriptor must be used for the use of the instruction; and if a memory descriptor must not be used, setting the constant value information of the possible use of the memory descriptor as the constant value information for the use of the instruction.

[0138] Item A11. A method according to Item A3, wherein for the constant value of the instruction, the calculation step includes: establishing constant value information of a required constant value memory descriptor in the constant value of the instruction; identifying possible constant value memory descriptors of the required constant value memory descriptors in the constant value of the instruction; and placing the constant value information of the required constant value memory descriptor in the instruction into the kill set information of the possible constant value memory descriptors.

[0139] Clause A12. The method according to clause A11, wherein the placing step comprises: determining whether the possible constant value memory descriptor is completely killed; and if it is completely killed, deleting the record of the possible constant value memory descriptor.

[0140] Clause A13. The method according to clause A11, wherein the placing step includes: determining whether the kill set information of the possible fixed value memory descriptor is empty; if it is empty, placing all intervals of the fixed value information of the required fixed value memory descriptor in the fixed value of the instruction into the kill set information of the possible fixed value memory descriptor.

[0141] Clause A14. A method according to clause A13, wherein if the kill set information of the possible fixed value memory descriptor is not empty, the placing step includes: establishing a union interval of the kill set information of the possible fixed value memory descriptor and the fixed value information of the required fixed value memory descriptor; and placing the union interval into the kill set information of the possible fixed value memory descriptor.

[0142] Clause A15. The method according to clause A3, wherein for the fixed value of the instruction, the calculation step includes: determining whether the required fixed value memory descriptor in the fixed value of the instruction is accurate; if accurate: establishing the fixed value information of the required fixed value memory descriptor in the fixed value of the instruction; and identifying the possible fixed value memory descriptor of the required fixed value memory descriptor in the fixed value of the instruction; if inaccurate: determining whether there is fixed value information for the possible fixed value memory descriptor; and if there is fixed value information for the possible fixed value memory descriptor, noting that the possible fixed value memory descriptor has been killed.

[0143] Clause A16. A method according to clause A3, wherein for the fixed value of the instruction, the calculation step includes: determining whether there is a required fixed value memory descriptor for the fixed value of the instruction; if there is no required fixed value memory descriptor, performing the following steps: identifying all possible fixed value memory descriptors; excluding possible fixed value memory descriptors covered by other possible fixed value memory descriptors among all possible fixed value memory descriptors; excluding possible fixed value memory descriptors with existing fixed value information among all possible fixed value memory descriptors; and establishing fixed value information for possible fixed value memory descriptors that are not excluded among all possible fixed value memory descriptors.

[0144] Clause A17. A method according to clause A3, wherein for the constant value of the instruction, the calculation step includes: determining whether there is a required constant value memory descriptor for the constant value of the instruction; if there is no required constant value memory descriptor, establishing constant value information for all possible constant value memory descriptors.

[0145] Clause A18. A method according to clause A3, wherein for the constant value of the instruction, the calculation step includes: determining whether the required constant value memory descriptor of the constant value of the instruction is predicated; if so, establishing the constant value information of the required constant value memory descriptor of the constant value of the instruction.

[0146] Item A19. A method according to Item A18, wherein the step of establishing the fixed value information of the required fixed value memory descriptor of the fixed value of the instruction includes: determining whether there is fixed value information of the required fixed value memory descriptor of the fixed value of the instruction; if there is fixed value information, adding the fixed value of the instruction to the fixed value information of the required fixed value memory descriptor of the fixed value of the instruction; and if there is no fixed value information, establishing new fixed value information of the required fixed value memory descriptor of the fixed value of the instruction.

[0147] Clause A20. A method according to clause A1, wherein the calculation step comprises: traversing the instructions of each basic block to determine whether the successor basic block of each basic block is a PHI node; if it is a PHI node, executing the following steps: setting the constant value information of each basic block to the constant value information of the memory descriptor of the PHI node; establishing an intersection interval of the kill set information of all the basic blocks; and setting the intersection interval to the kill set information of the PHI node.

[0148] Clause A21. The method according to clause A1 further comprises: identifying the directly controlling node among the multiple nodes.

[0149] Clause A22. A method according to any one of clauses A1-21, wherein the kill set information is an ordered list.

[0150] Item A23. A computer-readable storage medium having stored thereon a computer program code for calculating data dependencies in a computing program, wherein when the computer program code is executed by a processor, the method described in any one of Items A1-22 is executed.

[0151] The embodiments of the present disclosure are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method of the present disclosure and its core idea. At the same time, for those skilled in the art, according to the ideas of the present disclosure, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. A method for calculating data dependencies in a program, the method include: constructing the program into a control flow graph in a static single assignment form, wherein the control flow graph includes a plurality of nodes; Setting initial information of the memory descriptors of the plurality of nodes, wherein the initial information is fixed value information and kill set information of all memory descriptors that directly control the nodes; as well as Iteration is performed based on the control flow graph, and each iteration performs the following steps: Traversing the multiple nodes, calculating and updating the fixed value information and kill set information of the memory descriptor of each node, and updating the data dependency relationship of the instruction; The kill set information is used to record the memory interval information killed by other instructions; The memory descriptor is used to describe a memory range; the data dependency of the instruction is used as reference information when the instruction is compiled and optimized.

2. The method according to claim 1, wherein the iterating step is performed in a reverse sequential data flow manner.

3. The method according to claim 1, wherein in the calculation step, the memory descriptor used by the instruction is calculated and updated first, and then the memory descriptor of the constant value of the instruction is calculated and updated.

4. The method according to claim 3, wherein for the use of the instruction, the calculation step further include: To determine whether a memory descriptor exists, it is necessary to use it precisely; If so, determining whether the fixed value information that requires accurate use of the memory descriptor exists; If the fixed value information exists, setting the fixed value information that must accurately use the memory descriptor as the used fixed value information; Among them, if the offset and size of a memory descriptor are both accurate values ​​or ranges, then the memory descriptor is accurate.

5. The method according to claim 4, wherein if the fixed value information exists, the calculating step further include: Determine whether the kill set information that must accurately use the memory descriptor is empty; as well as If it is not empty, determine whether the constant value information that may use the memory descriptor exists; If the fixed value information of the possible memory descriptor exists, determine whether the intersection interval of the fixed value information of the memory descriptor that must be used and the fixed value information of the possible memory descriptor is killed; If it is not killed, the fixed value information of the possible use of the memory descriptor and the fixed value information of the must-use memory descriptor are set as the fixed value information used by the instruction.

6. The method according to claim 4, wherein if the fixed value information exists, the calculating step further include: Determine whether the kill set information that must accurately use the memory descriptor is empty; as well as If it is not empty, determine whether the constant value information that may use the memory descriptor exists; If the fixed value information of the possible use memory descriptor exists, the fixed value information of the possible use memory descriptor and the fixed value information of the must-use memory descriptor are set as the fixed value information used by the instruction.

7. The method according to claim 4, wherein if the fixed value information does not exist, the calculating step further include: Identify all possible memory descriptors that have constant value information; Determine whether the intersection interval of the definite value information that must use the memory descriptor and the definite value information that may use the memory descriptor is killed; and If it is not killed, set the definite value information of the memory descriptor that may be used and the definite value information of the memory descriptor that must be used as the definite value information of the usage instruction.

8. The method according to claim 4, wherein if the definite value information does not exist, the calculation step further includes: Identify all possible memory descriptors with definite value information; and Set the definite value information of the possible memory descriptor as the definite value information of the usage of the instruction.

9. The method according to claim 4, wherein if there is no memory descriptor that must be used precisely, the calculation step further includes: Set the definite value information of the memory descriptor that must be used and the possible memory descriptor as the definite value information of the usage of the instruction.

10. The method according to claim 4, wherein the calculation step further includes: Determine whether there is a memory descriptor that must be used for the usage of the instruction; and If there is no memory descriptor that must be used, set the definite value information of the possible memory descriptor as the definite value information of the usage of the instruction.

11. The method according to claim 3, wherein for the definite value of the instruction, the calculation step includes: Establish the definite value information of the memory descriptor that must be definitely valued in the definite value of the instruction; Identify the possible memory descriptors that must be definitely valued in the definite value of the instruction; and Place the definite value information of the memory descriptor that must be definitely valued in the instruction into the kill set information of the possible memory descriptor.

12. The method according to claim 11, wherein the placement step includes: Determine whether the possible memory descriptor is completely killed; and If it is completely killed, delete the record of the possible memory descriptor.

13. The method according to claim 11, wherein the placement step includes: Determine whether the kill set information of the possible memory descriptor is empty; If it is empty, place all intervals of the definite value information of the memory descriptor that must be definitely valued in the definite value of the instruction into the kill set information of the possible memory descriptor.

14. The method according to claim 13, wherein if the kill set information of the possible memory descriptor is not empty, the placement step includes: Establish the union interval of the kill set information of the possible memory descriptor and the definite value information of the memory descriptor that must be definitely valued; and Place the union interval into the kill set information of the possible memory descriptor.

15. The method according to claim 3, wherein for the definite value of the instruction, the calculation step includes: Determine whether the memory descriptor that must be definitely valued in the definite value of the instruction is precise; If precise: Establish the definite value information of the memory descriptor that must be definitely valued in the definite value of the instruction; and Identify the possible memory descriptors that must be definitely valued in the definite value of the instruction; If not precise: Determine whether there is definite value information for the possible memory descriptor; and If the possible fixed value memory descriptor has fixed value information, it is noted that the possible fixed value memory descriptor has been killed.

16. The method according to claim 3, wherein for a given value of the instruction, the calculating step include: Determine whether a required fixed value memory descriptor exists for the fixed value of the instruction; If there is no required memory descriptor, perform the following steps: Identify all possible valued memory descriptors; Among all possible fixed-value memory descriptors, exclude possible fixed-value memory descriptors covered by other possible fixed-value memory descriptors; Among all possible fixed-value memory descriptors, exclude possible fixed-value memory descriptors that have already had fixed-value information; as well as Establish the fixed value information of the possible fixed value memory descriptors that are not excluded among all possible fixed value memory descriptors.

17. The method according to claim 3, wherein for the fixed value of the instruction, the calculation step include: Determine whether a required fixed value memory descriptor exists for the fixed value of the instruction; If there is no required constant value memory descriptor, establish the constant value information of all possible constant value memory descriptors.

18. The method according to claim 3, wherein for the fixed value of the instruction, the calculation step include: determining whether a required fixed-value memory descriptor of a fixed value of the instruction is predicated; If predicated, establish the value information of the required value memory descriptor for the value of the instruction.

19. The method according to claim 18, wherein the step of establishing the value information of the required value memory descriptor of the command value is include: Determine whether there is fixed value information in the required fixed value memory descriptor of the fixed value of the instruction; If fixed value information exists, adding the fixed value of the instruction to the fixed value information of the required fixed value memory descriptor of the fixed value of the instruction; as well as If the constant value information does not exist, then establish the constant value information of the required constant value memory descriptor of the new instruction.

20. The method according to claim 1, wherein the calculating step include: Traversing the instructions of each basic block, and determining whether a subsequent basic block of each basic block is a PHI node; If it is a PHI node, perform the following steps: Setting the fixed value information of each basic block to the fixed value information of the memory descriptor of the PHI node; Establishing an intersection interval of the kill set information of all the basic blocks; as well as The intersection interval is set to the kill set information of the PHI node.

21. The method according to claim 1, wherein include: The directly controlling node among the plurality of nodes is identified.

22. The method according to any one of claims 1-21, wherein the kill set information is an ordered list.

23. A computer-readable storage medium having stored thereon a computer program code for calculating data dependencies in a computing program, wherein when the computer program code is executed by a processor, the method according to any one of claims 1 to 22 is executed.

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