A transistor having a shield gate trench structure and a method of manufacturing the same

Abstract

The application discloses a transistor with a shielding gate trench structure and a manufacturing method thereof. In the manufacturing process, the oxide layer corresponding to the gate trench is selectively etched, and then the oxide is deposited again on the front surface. Therefore, the oxide layer between the gate trench and the source trench of the transistor is in a stepped shape, and the thickness of the oxide layer close to the source trench is greater than the thickness of the oxide layer close to the gate trench. In the manufacturing process, the source trench is shielded by a temporary protection material such as photoresist, so that the oxide layer filled in the source trench no longer has a pit, and the pit on the oxide layer in the source trench does not enter the gate polysilicon, thereby avoiding the risk of gate-source short circuit of the MOSFET with the SGT structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application belong to the field of semiconductor manufacturing, and particularly relate to a transistor with a shield gate trench structure and a manufacturing method thereof. BACKGROUND

[0002] Metal-oxide-semiconductor field-effect transistor (MOSFET) with a shield gate trench (SGT) structure is a current advanced MOSFET technology, which can well solve the contradiction between on-resistance and parasitic capacitance, and reduce the on-resistance and switching loss of the system, and improve the system efficiency.

[0003] In the manufacturing process of the existing MOSFET with SGT structure, the over-thick oxide layer is often etched first, and then the polysilicon is grown. However, when etching the oxide layer, pits may be generated on the sidewall of the source lead-out area trench, and the gate polysilicon will enter these pits when the gate polysilicon is grown. The subsequent process cannot completely remove the gate polysilicon in the pits, thereby causing the MOSFET with SGT structure to have the risk of gate-source short circuit. SUMMARY

[0004] The purpose of the present application is to provide a transistor with a shield gate trench structure and a manufacturing method thereof, which can improve the above problems.

[0005] In a first aspect, embodiments of the present application provide a transistor manufacturing method with a shield gate trench structure, comprising,

[0006] Growing an epitaxial layer on a substrate, etching a gate trench and a source trench on a front surface of the epitaxial layer away from the substrate, growing an oxide on the front surface to form a first oxide layer, so that the first oxide layer covers the trench bottom and the trench wall of the gate trench and the source trench;

[0007] Filling the gate trench and the source trench with gate polysilicon and source polysilicon, respectively;

[0008] Etching the gate polysilicon in the gate trench until the remaining gate polysilicon in the gate trench, and retaining all the source polysilicon in the source trench;

[0009] Etching the first oxide layer in the gate trench region;

[0010] Continuing to grow an oxide on the front surface to form a second oxide layer, so that the second oxide layer covers the gate polysilicon in the gate trench;

[0011] Continuing to fill the gate trench with gate polysilicon to a lip of the gate trench.

[0012] It can be understood that the embodiment of the present application discloses a transistor manufacturing method with a shielding gate trench structure. When etching the oxide layer, the oxide layer corresponding to the gate trench is selectively etched by photoresist shielding and other methods, so that the oxide layer on the gate trench wall is removed and the oxide layer on the source trench wall is retained. When filling the gate polysilicon, the source polysilicon lead-out area trench wall will not be left with gate polysilicon, thereby avoiding the risk of gate-source short circuit after subsequent growth of the gate polysilicon.

[0013] In an optional embodiment of the present application, after the gate trench and the source trench are respectively filled with gate polysilicon and source polysilicon, before the first oxide layer in the gate trench is etched, the method further comprises:

[0014] The first oxide layer on the front surface is etched and thinned to make the source polysilicon and the gate polysilicon higher than the surface of the first oxide layer after the thinning treatment.

[0015] It can be understood that before the oxide layer on the gate trench wall is etched, the oxide layer on the front surface also needs to be etched and thinned as a whole. Generally, after this step, the thickness of the oxide layer on the front surface is thinned to to , so that the source polysilicon is exposed to the oxide layer for subsequent manufacturing.

[0016] In an optional embodiment of the present application, before the gate polysilicon in the gate trench is etched until the remaining part of the gate polysilicon in the gate trench, it comprises:

[0017] Covering the source lead-out area polysilicon region with photoresist.

[0018] The etching of the first oxide layer in the gate trench region comprises etching the first oxide layer on the non-covered area of the photoresist on the front surface and the gate trench wall.

[0019] It can be understood that after the photoresist covers the source trench, the source polysilicon in the source trench can be shielded to achieve etching of the front surface only for the gate polysilicon in the gate trench.

[0020] In an optional embodiment of the present application, after etching the first oxide layer on the non-covered area of the photoresist on the front surface and the gate trench wall, it comprises,

[0021] continuing etching the last remaining first oxide layer of the gate trench sidewall until the first oxide layer thickness of the gate trench sidewall is zero;

[0022] removing the photoresist.

[0023] In an alternative embodiment of the present application, after the etching of the photoresist uncovered area of the front surface and the first oxide layer of the gate trench sidewall, the method comprises:

[0024] removing the photoresist;

[0025] etching the remaining first oxide layer of the gate trench sidewall, the first oxide layer between the source trench and the gate trench, and the first oxide layer of the source polysilicon lead-out area;

[0026] covering the source polysilicon lead-out area with photoresist again;

[0027] continuing etching the last remaining first oxide layer of the gate trench sidewall until the first oxide layer thickness of the gate trench sidewall is zero, and then removing the photoresist.

[0028] In an alternative embodiment of the present application, the distance between the source trench boundary and the adjacent gate boundary trench is L, and the distance between the photoresist boundary and the photoresist boundary adjacent to the adjacent gate trench boundary is between L / 3 and L / 2.

[0029] In an alternative embodiment of the present application, before the continued growth of the oxide on the front surface to form a second oxide layer so that the second oxide layer covers the gate polysilicon in the gate trench, the method comprises:

[0030] wet etching the surface of the sacrificial oxide after growing the sacrificial oxide on the front surface to remove the sacrificial oxide;

[0031] growing a gate oxide layer in the gate trench.

[0032] In an alternative embodiment of the present application, the method further comprises: sequentially fabricating a well layer, a source layer, and a dielectric layer; fabricating a first electrode, a second electrode, and a third electrode, the first electrode being in communication with the well layer through a conductive via, the second electrode being in communication with the gate polysilicon through a conductive via, and the third electrode being in communication with the source polysilicon through a conductive via; and growing a metal on the back surface of the substrate away from the epitaxial layer as a back gold layer.

[0033] In a second aspect, an embodiment of the present application provides a transistor with a shield gate trench structure, which is prepared by the transistor with a shield gate trench structure manufacturing method provided in the first aspect.

[0034] It can be understood that the application discloses a transistor with a shield gate trench structure, which is manufactured by any method of the first aspect. In the manufacturing process, the oxide layer corresponding to the gate trench is selectively etched, and then the oxide is deposited again on the front surface. Due to the temporary protection material such as photoresist for shielding the source trench in the manufacturing process, the oxide layer filled in the source trench no longer has a pit, avoiding the pit in the oxide layer in the source trench from entering the gate polysilicon, thereby avoiding the risk of gate-source short circuit of the MOSFET with the SGT structure. BRIEF DESCRIPTION OF DRAWINGS

[0035] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the principles of the application. Some specific embodiments of the application are described in detail below with reference to the accompanying drawings. The same reference numbers in the drawings indicate the same or similar components or parts throughout the several

[0036] Figure 1 is a structure schematic diagram of a transistor with a shield gate trench structure provided by an embodiment of the application;

[0037] Figure 2 is a flowchart of a manufacturing method of a transistor with a shield gate trench structure provided by the application;

[0038] Figures 3 to 12 is a stage structure schematic diagram of a transistor corresponding to the method shown in Figure 1

[0039] Figure 13 is a structure schematic diagram of a transistor with a shield gate trench structure provided by an embodiment 2 of the application;

[0040] Figures 14 to 16 is a stage structure schematic diagram of a transistor corresponding to the method shown in Figure 13 DETAILED DESCRIPTION

[0041] In order to enable persons skilled in the art to better understand the application scheme, the technical solutions in the embodiments of the application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the application. Obviously, the described embodiments are only a part of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by persons skilled in the art without creative labor should be within the protection scope of the application.

[0042] Embodiment 1 ​​

[0043] In the manufacturing process of the prior art MOSFET with SGT structure, the thick oxide layer 103 is usually etched first, and then the polysilicon 104, 105 and 106 is grown. However, when etching the oxide layer 103, pits may be generated on the sidewall of the source lead-out groove, and the gate polysilicon will enter the pits when the gate polysilicon is grown, forming residual gate polysilicon 109. As shown in Figure 1 , the subsequent process cannot completely remove the residual gate polysilicon 109 in the pits, thereby causing the transistor 100 with the shielding gate trench structure to have the risk of gate-source short circuit.

[0044] The first aspect, as shown in Figure 2 , the present application provides a transistor manufacturing method with a shielding gate trench structure, comprising,

[0045] Step 210, growing an epitaxial layer on a substrate, etching a gate trench and a source trench on the positive surface of the epitaxial layer away from the substrate, growing an oxide on the positive surface to form a first oxide layer, so that the first oxide layer covers the groove bottom and groove wall of the gate trench and the source trench;

[0046] Referring to Figure 2 and Figure 3 , step 210 is performed, an epitaxial layer 302 is grown on a substrate 301, a gate trench 303 and a source trench 304 are etched on the positive surface of the epitaxial layer 302 away from the substrate 301, and a first oxide layer 305 is grown on the positive surface, so that the first oxide layer 305 covers the groove bottom and groove wall of the gate trench 303 and the source trench 304. The method for growing the first oxide layer 305 is well known in the art and will not be described here. The first oxide layer 305 can play a blocking role.

[0047] Step 220, etching and thinning the first oxide layer 305 on the positive surface to make the source polysilicon 307 and the gate polysilicon 306 higher than the surface of the first oxide layer 305 after the thinning process away from the surface of the substrate 301. In the embodiment of the present application, the first oxide layer 305 on the positive surface is etched and thinned as a whole by a chemical mechanical polishing (CMP) process. After the thinning, the thickness of the first oxide layer 305 on the positive surface is thinned to to at this time, the source polysilicon 307 is higher than the first oxide layer 305 by to

[0048] Step 230, filling the gate polysilicon and the source polysilicon into the gate trench and the source trench, respectively;

[0049] Referring to Figure 2 and Figure 4 , step 230 is performed to fill the gate trench 303 and the source trench 304 with gate polysilicon 306 and source polysilicon 307, respectively;

[0050] Step 240 is performed to cover the source lead-out region polysilicon area with photoresist 500;

[0051] Referring to Figure 5 , step 240 is performed to cover the source lead-out region polysilicon area with photoresist 500; so that the uncovered area of the front surface and the first oxide layer 305 in the gate trench 303 are etched.

[0052] In this embodiment, the distance between the source trench 304 boundary and the adjacent gate trench 303 boundary is L, and the distance between the photoresist 500 boundary and the adjacent gate trench boundary is between L / 3 and L / 2, which facilitates subsequent etching of the gate polysilicon in the gate trench 303.

[0053] Step 250 is performed to etch the gate polysilicon 306 in the gate trench 303 until the remaining gate polysilicon 3061 in the gate trench 303, and all the source polysilicon 307 in the source trench 304 is retained.

[0054] Referring to Figure 6 , step 250 is performed to etch the gate polysilicon 306 in the gate trench 303 until the remaining gate polysilicon 3061 in the gate trench 303, and all the source polysilicon 307 in the source trench 304 is retained.

[0055] Step 260 is performed to etch the first oxide layer 305 in the area of the gate trench 303;

[0056] Referring to Figure 7 , step 260 is performed to etch the first oxide layer 305 in the area of the gate trench 303, which includes etching the uncovered area of the photoresist 500 on the front surface and the first oxide layer 305 on the sidewall of the gate trench 304.

[0057] Referring to Figure 8 , steps 270 and 280 are performed to continue etching the first oxide layer 305 until the remaining thickness of the first oxide layer 305 on the sidewall of the gate trench 303 is zero, and the photoresist 500 is removed.

[0058] Step 290 is performed to grow a sacrificial oxide on the front surface and wet etch the surface of the sacrificial oxide to remove the sacrificial oxide;

[0059] In the embodiment of the present application, the sacrificial oxide is grown on the front surface in an environment of 950-1100℃, so that the thickness of the sacrificial oxide reaches to range. After growing the sacrificial oxide on the front surface, the surface of the sacrificial oxide is wet-etched, so that the remaining thickness of the first oxide layer between the trenches on the front surface is in the range of to range.

[0060] Step 210, growing the oxide on the front surface to form a second oxide layer, so that the second oxide layer covers the gate polysilicon 306 in the gate trench;

[0061] Referring to Figure 9 , step 210 is performed, and finally, the second oxide layer 305 is grown in the gate trench 303 in an environment of 950-1100℃, so that the second oxide layer covers the gate polysilicon 306 in the gate trench;

[0062] Referring to Figure 10 , step 211, the gate polysilicon 3062 continues to fill the gate trench 303 to the mouth of the gate trench 303.

[0063] Referring to Figure 11 , step 212 is performed, and the well layer 308, the source layer 309, and the dielectric layer 310 are sequentially made; the first electrode 311, the second electrode 312, and the third electrode 313 are made, the first electrode 311 communicates with the well layer 308 through a conductive via, the second electrode 312 communicates with the gate polysilicon 306 through a conductive via, and the third electrode 313 communicates with the source polysilicon 307 through a conductive via; and a metal is grown on the back of the substrate 301 away from the epitaxial layer 302 as a back metal layer 314.

[0064] The present application discloses a transistor manufacturing method with a shielded gate trench structure. In the etching of the first oxide layer 305, the first oxide layer 305 corresponding to the gate trench 303 is selectively etched by methods such as photoresist 500 shielding, so that the first oxide layer 305 on the wall of the gate trench 303 is removed and the first oxide layer 305 on the wall of the source trench 304 is completely retained. Avoiding the appearance of pits in the manufacturing process, so as to avoid the risk of short circuit between the gate and the source caused by the residual gate polysilicon on the trench sidewall of the source lead-out area after growing the gate polysilicon.

[0065] In the optional embodiment of the present application, a transistor with a shielded gate trench structure is provided by the above process, which comprises a substrate 301, an epitaxial layer 302, an oxide layer 305, a first gate polysilicon 3061, a second gate polysilicon 3062, and a source polysilicon 307.

[0066] The transistor with the shield gate trench structure manufactured by the manufacturing process of embodiment 1 has the oxide layer 305 between the gate trench 303 and the source trench 304 in a stepped shape, and the thickness of the oxide layer 305 close to the source trench is greater than the thickness of the oxide layer 305 close to the gate trench 303, because the first oxide layer 305 corresponding to the gate trench 303 is etched selectively in the manufacturing process, and the oxide is deposited again on the front surface.

[0067] Embodiment 2

[0068] In this embodiment, the same parts as those in the same embodiment 1 will not be described again, and embodiment 2 only illustrates the differences.

[0069] As shown in Figure 12 , the transistor prepared by the manufacturing method of embodiment 2 is different from that of embodiment 1 in that the oxide layer between the gate deep trench 303 and the source deep trench 304 is flush and not in a stepped shape, and the thickness of the oxide layer close to the source deep trench 304 is equal to the thickness of the oxide layer close to the gate deep trench 303, and the rest of the transistor structure is the same as that obtained by the manufacturing method of embodiment 1.

[0070] Before step S260, it is the same as embodiment 1, and after step 260, step S370 is performed to remove the photoresist;

[0071] Referring to Figure 14 , step S313 is performed to etch the oxide layer in the relevant area, that is, to etch the first oxide layer remaining on the sidewall of the gate trench, the first oxide layer between the source trench and the gate trench, and the first oxide layer of the source poly silicon lead-out area;

[0072] Referring to Figure 15 , step S314 is performed to cover the source poly silicon lead-out area with photoresist again;

[0073] Referring to Figure 16 , then step S315 is performed to continue etching the last remaining first oxide layer on the sidewall of the gate trench until the thickness of the first oxide layer on the sidewall of the gate trench is zero, and then the photoresist is removed.

[0074] After the step S290 in the embodiment 1 is performed, the surface of the sacrificial oxide is wet etched to remove the sacrificial oxide after the growth of the sacrificial oxide on the front surface. After the step S290, the same as the embodiment 1, which is not repeated here.

[0075] As shown in FIG. 1, a transistor structure manufactured by the embodiment 1 of the present application is shown. Figure 12

[0076] The transistor with the shield gate trench structure manufactured by the manufacturing process of the embodiment 2 of the present application, because of the selective etching of the first oxide layer 305 corresponding to the gate trench 303 in the manufacturing process, and then the deposition of the oxide on the front surface, the oxide layer 305 between the gate trench 303 and the source trench 304 is flush, and the thickness of the oxide layer 305 near the source trench is equal to the thickness of the oxide layer 305 near the gate trench 303. Because of the shielding of the source trench 304 by the temporary protection material such as the photoresist 500 in the manufacturing process, the pits in the oxide layer 305 filled in the source trench 304 no longer exist, which avoids the risk of the gate-source short circuit of the MOSFET with the SGT structure caused by the entry of the gate polysilicon 306 into the pits on the oxide layer 305 in the source trench 304.

[0077] The embodiments in the present application are described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. Especially, the device, equipment and medium embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant part can be referred to the part of the method embodiment, which is not repeated here.

[0078] Thus far, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.

[0079] The expressions "first", "second", "the first" or "the second" used in various embodiments of the present disclosure can modify various components regardless of order and / or importance, but these expressions do not limit the corresponding components. The above expressions are configured only for the purpose of distinguishing the elements from other elements. For example, the first user equipment and the second user equipment represent different user equipment, although both are user equipment. For example, the first element can be called the second element, and similarly, the second element can be called the first element without departing from the scope of the present disclosure.​

[0080] When an element (e.g., a first element) is referred to as being “(operatively or communicatively) coupled with” or “(operatively or communicatively) coupled to” another element (e.g., a second element), or “connected to” another element (e.g., a second element), it should be understood that the one element is either directly connected to the other element or that one element is indirectly connected to the other element through yet another element (e.g., a third element). Conversely, it will be understood that when an element (e.g., a first element) is referred to as being “directly connected” or “directly coupled” to another element (a second element), then no element (e.g., a third element) intervenes between the two.

[0081] The above description is merely exemplary of the application and the application principles of the technology used. It should be understood that the scope of the application involved in this application is not limited to the technical solutions formed by the specific combinations of the above technical features, and should also cover other technical solutions formed by any combinations of the above technical features or their equivalent features without departing from the above inventive concept. For example, the above features can be replaced with the technical features disclosed in this application (but not limited to) having similar functions to form technical solutions.

[0082] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of fabricating a transistor having a shield gate trench structure, comprising: comprising, growing an epitaxial layer on a substrate, etching a gate trench and a source trench on a front surface of the epitaxial layer facing away from the substrate, growing an oxide on the front surface to form a first oxide layer such that the first oxide layer covers the bottom and the sidewall of the gate trench and the source trench; filling the gate trench and the source trench with gate polysilicon and source polysilicon respectively; etching the gate polysilicon in the gate trench until the remaining gate polysilicon in the gate trench, and keeping all the source polysilicon in the source trench; etching the first oxide layer in the gate trench region; continuing to grow the oxide on the front surface to form a second oxide layer such that the second oxide layer covers the gate polysilicon in the gate trench; continuing to fill the gate trench with gate polysilicon to the opening of the gate trench; after filling the gate trench and the source trench with gate polysilicon and source polysilicon respectively, and before etching the first oxide layer in the gate trench, the method further comprises: performing a thinning process on the first oxide layer on the front surface such that the surface of the source polysilicon and the gate polysilicon is higher than the surface of the thinned first oxide layer facing away from the substrate; wherein the first oxide layer on the front surface is thinned to a thickness of to the source poly is higher than the first oxide layer by to 2. The method of claim 1, wherein the method further comprises: forming a gate spacer on the gate electrode. before etching the gate polysilicon in the gate trench until the remaining gate polysilicon in the gate trench, the method further comprises, covering the source polysilicon region with photoresist.

3. The method of claim 2, wherein the method further comprises: forming a gate spacer on the gate electrode. etching the first oxide layer in the gate trench region comprises etching the first oxide layer on the photoresist non-covered region of the front surface and the sidewall of the gate trench.

4. A method for manufacturing a transistor with a shielded gate trench structure according to claim 3, characterized in that, after etching the first oxide layer on the photoresist non-covered region of the front surface and the sidewall of the gate trench, the method further comprises, continuing to etch the last remaining first oxide layer on the sidewall of the gate trench until the first oxide layer on the sidewall of the gate trench has a thickness of zero; removing the photoresist.

5. A method for manufacturing a transistor with a shielded gate trench structure according to claim 3, characterized in that, after etching the first oxide layer on the photoresist non-covered region of the front surface and the sidewall of the gate trench, the method further comprises, removing the photoresist; etching the remaining first oxide layer on the sidewall of the gate trench, the first oxide layer between the source trench and the gate trench, and the first oxide layer on the source polysilicon region; covering the source polysilicon region with photoresist again; continuing to etch the last remaining first oxide layer on the sidewall of the gate trench until the first oxide layer on the sidewall of the gate trench has a thickness of zero, and then removing the photoresist.

6. The method of claim 1 wherein the transistor is formed with a shield gate trench structure. before continuing to grow the oxide on the front surface to form a second oxide layer such that the second oxide layer covers the gate polysilicon in the gate trench, the method further comprises, performing a wet etching on the surface of the sacrificial oxide after growing the sacrificial oxide on the front surface to remove the sacrificial oxide.

7. The method of claim 1 wherein the transistor is formed with a shield gate trench structure. the method further comprises: sequentially fabricating a well layer, a source layer, and a dielectric layer; fabricating a first electrode, a second electrode, and a third electrode, the first electrode being in communication with the well layer through a conductive via, the second electrode being in communication with the gate polysilicon through a conductive via, and the third electrode being in communication with the source polysilicon through a conductive via; A metal is grown on the back surface of the substrate away from the epitaxial layer as a back metal layer.

8. The method of claim 7, further comprising: A well layer, a source layer and a dielectric layer are sequentially made. A first electrode, a second electrode and a third electrode are made, the first electrode is in communication with the well layer through a conductive via, the second electrode is in communication with the gate polysilicon through a conductive via, and the third electrode is in communication with the source polysilicon through a conductive via; a metal is grown on the back surface of the substrate away from the epitaxial layer as a back metal layer.

9. A transistor having a shielded gate trench structure, characterized by, A transistor with a shield gate trench structure is prepared by the transistor manufacturing method as claimed in any one of claims 1 to 8.

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