An integrated circuit, consumable chip and MCU chip

Abstract

This application provides an integrated circuit, a consumable chip, and an MCU chip, including a semiconductor substrate. The semiconductor substrate includes a first region, a second region, and a deep well. The deep well is disposed in the semiconductor substrate and extends to the surface of the semiconductor substrate, surrounding the first region. The first region includes a first doped region, and the second region includes a second doped region. The first doped region is electrically connected to one of a signal ground and a power ground, and the second doped region is electrically connected to the other of the signal ground and the power ground. In this application, the signal ground and the power ground are disposed in different regions of the semiconductor substrate isolated by the deep well, which not only isolates the potentials of the signal ground and the power ground but also avoids signal crosstalk between the signal ground and the power ground.

Description

[Technical Field]

[0001] This application relates to the field of electronic technology, and in particular to an integrated circuit, a consumable chip, and an MCU chip. [Background Technology]

[0002] In integrated circuits, the current flowing through the power ground is generally larger, while the current flowing through the signal ground is smaller. Connecting the ground points of different functions directly together with a ground wire can cause crosstalk between signals from different circuits, as the high-power circuit can affect the zero-potential reference point of the low-power circuit through the ground wire.

[0003] [Application Content]

[0004] In view of this, embodiments of this application provide an integrated circuit, a consumable chip, and an MCU chip to solve the above problems.

[0005] In a first aspect, embodiments of this application provide an integrated circuit including a semiconductor substrate. The semiconductor substrate includes a first region, a second region, and a deep well. The deep well is disposed in the semiconductor substrate and extends to the surface of the semiconductor substrate, surrounding the first region. The first region includes a first doped region, and the second region includes a second doped region. The first doped region is electrically connected to one of a signal ground and a power ground, and the second doped region is electrically connected to the other of the signal ground and the power ground.

[0006] In one implementation of the first aspect, the semiconductor substrate includes a first slit and a second slit, and an insulating structure is disposed within both the first slit and the second slit; the first slit is located between the deep well and the first doped region, and the second slit is located between the deep well and the second doped region.

[0007] In one implementation of the first aspect, the semiconductor substrate is a P-type substrate and the deep well is an N-well.

[0008] In one implementation of the first aspect, the semiconductor substrate is an N-type substrate and the deep well is a P-well.

[0009] In one implementation of the first aspect, the signal ground is at least one of analog ground and digital ground.

[0010] In one implementation of the first aspect, the integrated circuit further includes a common ground control circuit, which includes a first input terminal; wherein the first input terminal is electrically connected to the system ground, and the first doped region and the second doped region are electrically connected to the system ground through the common ground control circuit.

[0011] In one implementation of the first aspect, the common ground control circuit includes a first output terminal and a second output terminal. The first output terminal is electrically connected to the first doped region, and the second output terminal is electrically connected to the second doped region. When the first input terminal is electrically connected to the first output terminal and the second output terminal, the first doped region and the second doped region are electrically connected to the system ground.

[0012] In one implementation of the first aspect, the common-ground control circuit includes a first transistor and a second transistor, wherein the source of the first transistor is electrically connected to a first output terminal, and the source of the second transistor is electrically connected to a second output terminal; the drain of the first transistor is electrically connected to a first input terminal, and the drain of the second transistor is electrically connected to the first input terminal.

[0013] In one implementation of the first aspect, the common ground control circuit further includes a first resistor, one end of which is electrically connected to the analog signal power supply, and the other end of which is electrically connected to the gate of the first transistor and the gate of the second transistor; the first doped region is electrically connected to one of the analog ground and the power supply ground, and the second doped region is electrically connected to the other of the analog ground and the power supply ground; when the analog signal power supply outputs an analog signal, the first input terminal is electrically connected to the first output terminal and the second output terminal.

[0014] Secondly, embodiments of this application provide a consumable chip, including the integrated circuit provided in the first aspect.

[0015] Thirdly, embodiments of this application provide an MCU chip, including the integrated circuit provided in the first aspect.

[0016] In this application, the signal ground and power ground are located in different regions of the semiconductor substrate isolated by a deep well, and are electrically connected to the system ground (GND) via a common ground control circuit. When the integrated circuit or chip does not require a unified ground signal during operation, the common ground control circuit is turned off, and the signal ground and power ground are isolated by the deep well, which not only isolates the potentials of the signal ground and power ground but also avoids signal crosstalk between them. When the integrated circuit or chip requires a unified ground signal during operation, the common ground control circuit is turned on, and the signal ground, power ground, and system ground (GND) share a common ground, avoiding program execution errors caused by inconsistent ground signals during integrated circuit or chip operation. [Attached Image Description]

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1This is a schematic diagram of the semiconductor structure of an integrated circuit provided in an embodiment of this application;

[0019] Figure 2 A schematic diagram of the semiconductor structure of another integrated circuit provided in an embodiment of this application;

[0020] Figure 3 A flowchart illustrating the fabrication process of a deep trap, as provided in this application embodiment;

[0021] Figure 4 A schematic diagram of the semiconductor structure of another integrated circuit provided in an embodiment of this application;

[0022] Figure 5 A schematic diagram of the semiconductor structure of another integrated circuit provided in an embodiment of this application;

[0023] Figure 6 A schematic diagram of the semiconductor structure of another integrated circuit provided in an embodiment of this application;

[0024] Figure 7 A schematic diagram of a common ground control circuit provided in an embodiment of this application;

[0025] Figure 8 An equivalent circuit diagram of a common-ground control circuit provided in an embodiment of this application;

[0026] Figure 9 An equivalent circuit diagram of another common-ground control circuit provided in the embodiments of this application;

[0027] Figure 10 A schematic diagram of a consumable chip provided in an embodiment of this application;

[0028] Figure 11 A schematic diagram of an integrated circuit board in a consumable chip provided in this application embodiment.

[0029] Figure 12 This is a schematic diagram of an MCU chip provided in an embodiment of this application.

Detailed Implementation Methods

[0030] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0031] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0032] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0033] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0034] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0035] It should be understood that although terms such as "first," "second," etc., may be used to describe regions, doped regions, etc., in the embodiments of this application, these regions, doped regions, etc., should not be limited to these terms. These terms are only used to distinguish regions, doped regions, etc., from one another. For example, without departing from the scope of the embodiments of this application, a first region may also be referred to as a second region, and similarly, a second region may also be referred to as a first region.

[0036] Through meticulous and in-depth research, the applicant in this case has provided a solution to the problems existing in the prior art.

[0037] Figure 1 This is a schematic diagram of the semiconductor structure of an integrated circuit provided in an embodiment of this application. Figure 2 This is a schematic diagram of the semiconductor structure of another integrated circuit provided in an embodiment of this application.

[0038] like Figure 1 and Figure 2As shown, this application embodiment provides an integrated circuit 001, which includes a semiconductor substrate 01. The semiconductor substrate 01 includes a first region AA, a second region BB, and a deep well 10. The first region AA includes a first doped region 11, and the second region BB includes a second doped region 12. It should be noted that the first region AA and the second region BB include multiple doped regions formed by the same ion doping. The first doped region 11 specifically refers to one of the multiple doped regions in the first region AA, and the second doped region 12 specifically refers to one of the multiple doped regions in the second region BB. The deep well 10 is disposed in the semiconductor substrate 01 and extends to the surface of the semiconductor substrate 01. The deep well 10 surrounds the first region AA. It should be noted that the deep well 10 is located between the first region AA and the second region BB, surrounding both the first region AA and the second region BB.

[0039] The first doped region 11 is electrically connected to one of the signal ground SGND and the power ground PGND, and the second doped region 12 is electrically connected to the other of the signal ground SGND and the power ground PGND. That is, the signal ground SGND and the power ground PGND are located in different regions of the semiconductor substrate 01 and are isolated by the deep well 10.

[0040] It is understandable that, in addition to isolating the potential inside and outside the deep well 10, the deep well 10 can also prevent the internal module of the deep well 10 from affecting the electrical signals of the external module of the deep well 10, and at the same time prevent the external module of the deep well 10 from affecting the electrical signals of the internal module of the deep well 10.

[0041] Generally, the current flowing through the power ground is larger, while the current flowing through the signal ground is smaller. Directly connecting ground points of different functions together can cause high-power circuits to affect the zero-potential reference point of low-power circuits through the ground wire, leading to crosstalk between signals from different circuits. In this application, the signal ground SGND and the power ground PGND are located in different regions isolated by the deep well 10 on the semiconductor substrate 01. This not only isolates the potentials of the signal ground SGND and the power ground PGND but also avoids signal crosstalk between them, thus preventing crosstalk between signals from different circuits. Examples include interference from high-power circuits to the zero-potential reference point of low-power circuits through the ground wire, and signal crosstalk between high-frequency and low-frequency circuits. Furthermore, in semiconductor manufacturing processes, deep well processes are used to fabricate different doped regions. This application isolates the signal ground SGND and the power ground PGND through deep wells, eliminating the need for additional processes, simplifying the process, and saving costs.

[0042] In one implementation of the embodiments of this application, such as Figure 1As shown, the first doped region 11 is electrically connected to the signal ground SGND, and the second doped region 12 is electrically connected to the power ground PGND. That is, the signal ground SGND is located in the first region 11 of the semiconductor substrate 01, and the power ground PGND is located in the second region 12 of the semiconductor substrate 01. This isolates the potentials of the signal ground SGND and the power ground PGND, thus avoiding signal crosstalk between them.

[0043] In another implementation of the embodiments of this application, such as Figure 2 As shown, the first doped region 11 is electrically connected to the power ground PGND, and the second doped region 12 is electrically connected to the signal ground SGND. That is, the power ground PGND is located in the first region 11 of the semiconductor substrate 01, and the signal ground SGND is located in the second region 12 of the semiconductor substrate 01. It is understood that changes in the signal ground SGND potential can affect the operation of other modules in the second region 12 of the semiconductor substrate 01. This embodiment avoids the problem of the power ground PGND affecting the signal ground SGND potential, thereby preventing changes in the signal ground SGND potential from affecting the operation of other modules in the second region 12.

[0044] Figure 3 This is a flowchart illustrating the fabrication process of a deep trap, as provided in an embodiment of this application.

[0045] Please continue to refer to this. Figure 1 In one implementation of this application, the semiconductor substrate 01 is a P-type substrate, and the deep well 10 is a deep N-well. The fabrication process of the deep N-well is briefly described below:

[0046] like Figure 3 As shown, a silicon substrate 30 is provided, and a pad oxide layer 31 is formed on the surface of the silicon substrate 30 using a wet process. Then, using a deep N-well mask, photoresist 32 is used to expose the region where the deep N-well is located. High-energy, low-concentration N ions are then implanted into the exposed region, with P-type ions implanted as impurities, to form the deep N-well. The regions on both sides of the deep N-well are then exposed using photoresist 32, and high-energy, low-concentration N ions are implanted into the exposed region again, with P-type ions implanted as impurities, so that the deep N-well extends to the surface of the silicon substrate 30. It should be noted that after forming the deep N-well, further fabrication of other parts such as doped regions and shallow isolation layers is required, which will not be described in detail here.

[0047] Understandably, this application utilizes a deep N-well to isolate the P-type semiconductor substrate into a first region AA and a second region BB. The first doped region 11, electrically connected to either signal ground SGND or power ground PGND, is located in the first region AA, while the second doped region 12, electrically connected to the other of signal ground SGND and power ground PGND, is located in the second region BB. In other words, the deep N-well isolates signal ground SGND and power ground PGND, isolating their potentials while preventing signal crosstalk between them.

[0048] It should be noted that the semiconductor substrate 01 in this application can also be an N-type substrate, and the deep well is a deep P-well. That is, the deep P-well is used to isolate the N-type semiconductor substrate into the first region AA and the second region BB. This isolates the signal ground SGND and the power ground PGND, and while isolating the potentials of the signal ground SGND and the power ground PGND, it avoids signal crosstalk between the signal ground SGND and the power ground PGND.

[0049] Please continue to refer to this. Figure 1 The semiconductor substrate 01 also includes a first slit 13 and a second slit 14, both of which have insulating structures. Specifically, the insulating structures can be made of silicon oxide.

[0050] The first slit 13 is located between the deep well 10 and the first doped region 11, and the second slit 14 is located between the deep well 10 and the second doped region 12. That is, the deep well 10 is not electrically connected to the first doped region 11, nor is it electrically connected to the second doped region 12.

[0051] In this application, the first slit 13 is provided to prevent electrical continuity between the first doped region 11 and the deep well 10. The second slit 14 is provided to prevent electrical continuity between the second doped region 12 and the deep well 10. This avoids the problem of the first doped region 11 and the second doped region 12 being connected to the deep well 10, thus preventing the normal operation of the integrated circuit 001 from being affected.

[0052] Figure 4 This is a schematic diagram of the semiconductor structure of another integrated circuit provided in an embodiment of this application. Figure 5 This is a schematic diagram of the semiconductor structure of another integrated circuit provided in an embodiment of this application. Figure 6 This is a schematic diagram of the semiconductor structure of another integrated circuit provided in an embodiment of this application.

[0053] In one embodiment of this application, the signal ground SGND is at least one of analog ground AGND and digital ground DGND. That is, the signal ground SGND can be analog ground AGND, digital ground DGND, or it can include both analog ground AGND and digital ground DGND.

[0054] When the signal ground SGND is the analog ground AGND, it can be understood that the first doped region 11 is electrically connected to one of the analog ground AGND and the power ground PGND, and the second doped region 12 is electrically connected to the other of the analog ground AGND and the power ground PGND. It should be noted that a shallow isolation layer (STI) is also provided in the semiconductor substrate 01, and the shallow isolation layer (STI) is filled with insulating material. The shallow isolation layer (STI) is used to isolate the different doped regions.

[0055] Optionally, such as Figure 4 As shown, the first doped region 11 is electrically connected to the power ground PGND, and the second doped region 12 is electrically connected to the analog ground AGND. Since the first doped region 11 is located in the first region AA and the second doped region 12 is located in the second region BB, that is, the power ground PGND is located in the first region AA and the analog ground AGND is located in the second region BB, signal crosstalk between the power ground PGND and the analog ground AGND is avoided, thereby preventing the problem of the analog ground AGND potential changing and affecting the normal operation of other modules in integrated circuit 001.

[0056] Optionally, such as Figure 5 As shown, the first doped region 11 is electrically connected to the analog ground AGND, and the second doped region 12 is electrically connected to the power ground PGND. That is, the analog ground AGND is located in the first region AA, and the power ground PGND is located in the second region BB. The deep well 10 isolates the analog ground AGND and the power ground PGND to avoid signal crosstalk between the analog ground AGND and the power ground PGND.

[0057] When the signal ground SGND is the digital ground DGND, it can be understood that the first doped region 11 is electrically connected to one of the digital ground DGND and the power ground PGND, and the second doped region 12 is electrically connected to the other of the digital ground DGND and the power ground PGND.

[0058] Optionally, such as Figure 6As shown, the first doped region 11 is electrically connected to the power ground PGND, and the second doped region 12 is electrically connected to the digital ground DGND. Since the first doped region 11 is located in the first region AA and the second doped region 12 is located in the second region BB, the power ground PGND is located in the first region AA, and the digital ground DGND is located in the second region BB. It can be understood that by isolating the power ground PGND in the first region AA, signal crosstalk between the power ground PGND and the digital ground DGND is avoided, thus preventing the power ground PGND from affecting the zero-potential reference point of the digital ground DGND.

[0059] Figure 7 This is a schematic diagram of a common ground control circuit provided in an embodiment of this application.

[0060] In one embodiment of this application, please refer to Figure 4 — Figure 7 The integrated circuit 001 also includes a common ground control circuit 02, which includes a first input terminal IN1.

[0061] The first input terminal IN1 is electrically connected to system ground GND, and the first doped region 11 and the second doped region 12 can be electrically connected to system ground GND through the common ground control circuit 02. In other words, signal ground SGND and power ground PGND are electrically connected to system ground GND through the common ground control circuit 02. It can be understood that system ground GND is the unified grounding point of integrated circuit 001.

[0062] When the common ground control circuit 02 is turned off, the signal ground SGND and the power ground PGND are located in different regions of the semiconductor substrate 01 and are isolated by the deep well 10. The signal ground SGND and the power ground PGND are independent grounding points and do not interfere with each other.

[0063] When the common ground control circuit 02 is turned on, signal ground SGND and power ground PGND are both electrically connected to system ground GND. That is to say, signal ground SGND, power ground PGND, and system ground GND share a common ground.

[0064] Understandably, during the operation of integrated circuit 001, some tasks require a unified ground signal, and if the ground signal is not unified, it will cause program errors. When integrated circuit 001 requires a unified ground signal, the common ground control circuit 02 is turned on, making the signal ground SGND, power ground PGND, and system ground GND share a common ground, thereby avoiding program errors.

[0065] Please continue to combine Figure 4 — Figure 7In one embodiment of this application, the common ground control circuit 02 includes a first output terminal OUT1 and a second output terminal OUT2. The first output terminal OUT1 is electrically connected to the first doped region 11, and the second output terminal OUT2 is electrically connected to the second doped region 12. When the first input terminal IN1 is electrically connected to the first output terminal OUT1 and the second output terminal OUT2, the first doped region 11 and the second doped region 12 are electrically connected to the system ground GND.

[0066] It should be noted that while the first input terminal IN1 is conducting with the first output terminal OUT1, the first input terminal IN1 is also conducting with the second output terminal OUT2. Therefore, the first doped region 11 and the second doped region 12 are simultaneously electrically connected to the system ground GND. In other words, the signal ground SGND, power ground PGND, and system ground GND share a common ground. When a unified ground signal is required during the operation of integrated circuit 001, sharing a common ground among the signal ground SGND, power ground PGND, and system ground GND can prevent program errors.

[0067] Figure 8 This is an equivalent circuit diagram of a common-ground control circuit provided in an embodiment of this application.

[0068] like Figure 8 As shown, in one embodiment of this application, the common ground control circuit 02 includes a first transistor 21 and a second transistor 22. The source of the first transistor 21 is electrically connected to the first output terminal OUT1, the source of the second transistor 22 is electrically connected to the second output terminal OUT2, the drain of the first transistor 21 is electrically connected to the first input terminal IN1, and the drain of the second transistor 22 is electrically connected to the first input terminal IN1.

[0069] It is understood that the source of the first transistor 21 is electrically connected to the first doped region 11, the source of the second transistor 22 is electrically connected to the second doped region 12, the drain of the first transistor 21 is electrically connected to the system ground GND, and the drain of the second transistor 22 is electrically connected to the system ground GND. That is, the signal ground SGND and the power ground PGND are electrically connected to the system ground GND through the first transistor 21 and the second transistor 22. When the first transistor 21 is turned on, one of the signal ground SGND and the power ground PGND is connected to the system ground GND. When the second transistor 22 is turned on, the other of the signal ground SGND and the power ground PGND is connected to the system ground GND.

[0070] It should be noted that the first transistor 21 and the second transistor 22 are turned on and off simultaneously. When the first transistor 21 and the second transistor 22 are both turned on, the signal ground SGND, power ground PGND, and system ground GND share a common ground, thus ensuring that the integrated circuit 001 will not encounter program errors when a unified ground signal is required for operation. When the first transistor 21 and the second transistor 22 are both turned off, the signal ground SGND and the power ground PGND are located in different regions of the semiconductor substrate 01, and they are isolated by the deep well 10. The signal ground SGND and the power ground PGND are independent grounding points and do not interfere with each other.

[0071] Figure 9 This is an equivalent circuit diagram of another common-ground control circuit provided in the embodiments of this application.

[0072] In one embodiment of this application, please refer to Figure 4 , Figure 5 and Figure 9 The common-ground control circuit 02 also includes a first resistor 23. One end of the first resistor 23 is electrically connected to the analog signal power supply VCC, and the other end of the first resistor 23 is electrically connected to the gate of the first transistor 21 and the gate of the second transistor 22. That is, the gates of the first transistor 21 and the second transistor 22 are both electrically connected to the same end of the first resistor 23. It can be understood that the on / off control signals of the first transistor 21 and the second transistor 22 are the same, that is, the first transistor 21 and the second transistor 22 are simultaneously turned on and off.

[0073] The first doped region 11 is electrically connected to one of the analog ground AGND and the power ground PGND, and the second doped region 12 is electrically connected to the other of the analog ground AGND and the power ground PGND. It can be understood that since the first doped region 11 is located in the first region AA of the semiconductor substrate 01, and the second doped region 12 is located in the second region BB of the semiconductor substrate 01, and the first region AA is surrounded by the deep well 10, the analog ground AGND and the power ground PGND are located in different regions of the semiconductor substrate 01 and are isolated by the deep well 10.

[0074] In one implementation of this application, the first doped region 11 is electrically connected to the power ground PGND, and the second doped region 12 is electrically connected to the analog ground AGND. That is, the power ground PGND is located in the first region AA, and the analog ground AGND is located in the second region BB.

[0075] In another implementation of this application, the first doped region 11 is electrically connected to the analog ground AGND, and the second doped region 12 is electrically connected to the power ground PGND. That is, the analog ground AGND is located in the first region AA, and the power ground PGND is located in the second region BB.

[0076] When the analog signal power supply VCC outputs an analog signal, the first input terminal IN1 is electrically connected to the first output terminal OUT1 and the second output terminal OUT2. It can be understood that the analog signal output by the analog signal power supply is the control signal for the first transistor 21 and the second transistor 22. Since the first output terminal IN1 is electrically connected to system ground GND, the first output terminal OUT1 is electrically connected to the first doped region 11, and the second output terminal OUT2 is electrically connected to the second doped region 12, when the analog signal power supply outputs an analog signal, the first doped region 11 and the second doped region 12 are electrically connected to system ground GND. That is, analog ground AGND, power ground PGND, and system ground GND share a common ground.

[0077] In this embodiment, when the analog signal power supply VCC outputs an analog signal, the gate of the first transistor 21 and the gate of the second transistor 22 receive the analog signal through the first resistor 23, meaning that the first transistor 21 and the second transistor 22 receive a control signal. Then, the source and drain of the first transistor 21 are connected, and the source and drain of the second transistor 22 are connected. Since the source of the first transistor 21 is electrically connected to the first doped region 11, and the drain of the first transistor 21 is electrically connected to the system ground GND; and the source of the second transistor 22 is electrically connected to the second doped region 12, and the drain of the second transistor 22 is electrically connected to the system ground GND, both the first doped region 11 and the second doped region 12 are electrically connected to the system ground GND. Furthermore, since the first doped region 11 is electrically connected to either the analog ground AGND or the power ground PGND, and the second doped region 12 is electrically connected to the other of the analog ground AGND or the power ground PGND, the analog ground AGND, the power ground PGND, and the system ground GND share a common ground. In other words, when the analog signal power supply outputs an analog signal, the analog ground AGND, power ground PGND, and system ground GND share a common ground, thereby avoiding program execution errors when the integrated circuit 001 needs a unified ground signal to operate.

[0078] It should be noted that, please refer to Figure 6 and Figure 8 When the signal module circuit is a digital circuit, one end of the first resistor 23 is electrically connected to the digital signal power supply VSS, and the other end of the first resistor 23 is electrically connected to the gate of the first transistor 21 and the gate of the second transistor 22. The first doped region 11 is electrically connected to one of the digital ground DGND and the power ground PGND, and the second doped region 12 is electrically connected to the other of the digital ground AGND and the power ground PGND. When the digital signal power supply VSS outputs a digital signal, the first input terminal IN1 is electrically connected to the first output terminal OUT1 and the second output terminal OUT2.

[0079] In the integrated circuit 001 provided in this application, signal ground SGND and power ground PGND are located in different regions of the semiconductor substrate 01 isolated by a deep well 10, and are electrically connected to system ground GND through a common ground control circuit 02. When the integrated circuit 001 does not require a unified ground signal, the common ground control circuit 02 is turned off, and the signal ground SGND and power ground PGND are isolated by the deep well 10. This not only isolates the potentials of the signal ground SGND and power ground PGND, but also avoids signal crosstalk between them. When the integrated circuit 001 requires a unified ground signal, the common ground control circuit 02 is turned on, and the signal ground SGND, power ground PGND, and system ground GND share a common ground, avoiding program errors caused by inconsistent ground signals during the operation of the integrated circuit 001.

[0080] Figure 10 This is a schematic diagram of a consumable chip provided in an embodiment of this application. Figure 11 This is a schematic diagram of an integrated circuit board in a consumable chip provided in an embodiment of this application.

[0081] This application provides a consumable chip 002, such as... Figure 10 As shown, it includes an integrated circuit 001 as provided in any of the above embodiments. The consumable chip 002 includes a printer consumable chip.

[0082] In one embodiment of this application, such as Figure 11 As shown, the consumable chip 002 includes an integrated circuit board 2A. The integrated circuit board 2A includes a first interface C1, a second interface C2, a third interface C3, a fourth interface C4, and a fifth interface C5 for communicating with the host, and the first interface C1, the second interface C2, the third interface C3, the fourth interface C4, and the fifth interface C5 are electrically connected to each other.

[0083] Specifically, the first interface C1 provides a ground signal for the consumable chip 002; it can be understood that the first interface C1 is the system ground GND of the consumable chip 002. The second interface C2 provides a power supply voltage signal VDD for the consumable chip 002; the third interface C3 provides a chip select signal CS for the consumable chip 002; the fourth interface C4 provides a control signal SCL for the consumable chip 002; and the fifth interface C5 provides a data signal SDA for the consumable chip 002. It should be noted that the integrated circuit board 2A may also include a first sensor contact point H1, a second sensor contact point H2, a first short-circuit detection pin S1, and a second short-circuit detection pin S2.

[0084] It is understandable that consumable chip 002 includes digital signals, power signals, and analog signals. If the digital ground DGND, power ground PGND, and analog ground AGND are all directly connected to the first interface C1, crosstalk between different signals will occur, affecting the accuracy of the analog circuit and increasing the difficulty of EMC experiments.

[0085] In the consumable chip 002 provided in this application, the signal ground SGND and the power ground PGND are located in different regions of the semiconductor substrate 01 isolated by the deep well 10, and can be electrically connected to the system ground GND through the common ground control circuit 02. When the consumable chip 002 does not require a unified ground signal during operation, the common ground control circuit 02 is turned off, and the signal ground SGND and the power ground PGND are isolated by the deep well 10, which not only isolates the potentials of the signal ground SGND and the power ground PGND, but also avoids signal crosstalk between the signal ground SGND and the power ground PGND. When the consumable chip 002 requires a unified ground signal during operation, the common ground control circuit 02 is turned on, and the signal ground SGND, the power ground PGND, and the system ground GND share a common ground, avoiding program execution errors caused by inconsistent ground signals during the operation of the consumable chip 002. The signal ground SGND includes at least one of digital ground DGND and analog ground AGND.

[0086] Figure 12 This is a schematic diagram of an MCU chip provided in an embodiment of this application.

[0087] This application provides a microcontroller unit (MCU) chip 003, such as... Figure 12 As shown, it includes the integrated circuit 001 provided in any of the above embodiments. The MCU chip includes at least one of a remote control controller, a motor controller, a tape recorder mechanism controller, and a robotic arm controller.

[0088] In the MCU chip 003 provided in this application, signal ground SGND and power ground PGND are located in different regions of the semiconductor substrate 01 isolated by a deep well 10, and are electrically connected to system ground GND through a common ground control circuit 02. When the MCU chip 003 does not require a unified ground signal during operation, the common ground control circuit 02 is turned off, and the signal ground SGND and power ground PGND are isolated by the deep well 10. This not only isolates the potentials of the signal ground SGND and power ground PGND, but also avoids signal crosstalk between them. When the MCU chip 003 requires a unified ground signal during operation, the common ground control circuit 02 is turned on, and the signal ground SGND, power ground PGND, and system ground GND share a common ground, preventing program errors caused by inconsistent ground signals during the operation of the MCU chip 003.

[0089] It is understood that when a measuring device needs to output multiple measured values ​​via current signals, the measuring device includes a multi-channel current signal output circuit, and the multi-channel current signal output circuits share a common ground. In one embodiment of this application, the MCU chip 003 is applied to a measuring device including a multi-channel current signal output circuit.

[0090] The MCU chip 003 includes a sampling module, a control module, and a pulse width modulation (PWM) module.

[0091] The sampling module is used to filter the input voltage signal and then transmit it to the control module; the input voltage signal can be a signal received from the analog signal power supply VCC.

[0092] The control module calculates and obtains control values ​​from the input signals transmitted from the sampling module; it also converts the received measured values ​​into control values ​​for the PWM module. The control module can change the PWM duty cycle.

[0093] The PWM module is used to generate a PWM voltage signal corresponding to the control value of MCU chip 003, and then convert the voltage signal into a current signal output.

[0094] In this embodiment, the MCU chip can output N current signals, and the output principles of the first current signal output to the Nth current signal output are the same. N can be any value greater than or equal to 2, such as N=2 or N=6.

[0095] The PWM module includes a PWM generator. In this embodiment, a timer_B can be used as the PWM generator. It is understood that one pin of the microcontroller can output one PWM signal. In this embodiment, one pin of the microcontroller outputs the first PWM signal PWM1, and another pin outputs the second PWM signal PWM2. The output principles of the first PWM signal PWM1 and the second PWM signal PWM2 are the same. Taking the first PWM signal PWM1 as an example, PWM1 is filtered by a two-stage capacitor-resistor circuit (RC circuit). After filtering, PWM1 becomes a DC voltage signal, which is then converted into a current signal for output.

[0096] In this application, the power ground port of the MCU chip 003 is power ground PGND, and the ground port of the PWM module is analog ground AGND. Analog ground AGND and power ground PGND are located in different regions of the semiconductor substrate 01 isolated by a deep well 10, and are electrically connected through a common ground control circuit 02. When the MCU chip 003 does not require a unified ground signal, the common ground control circuit 02 is turned off, and the analog ground AGND and power ground PGND are isolated by the deep well 10. This not only isolates the potentials of the analog ground AGND and power ground PGND, but also avoids signal crosstalk between them. When the MCU chip 003 requires a unified ground signal, the common ground control circuit 02 is turned on, and the analog ground AGND and power ground PGND share a common ground, preventing program errors caused by inconsistent ground signals during MCU chip 003 operation.

[0097] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An integrated circuit, characterized in that, Includes a semiconductor substrate, which includes: The first region includes a first doped region; The second region includes the second doped region; A deep well is disposed in a semiconductor substrate and extends to the surface of the semiconductor substrate; the deep well surrounds a first region; The first doped region is electrically connected to one of the signal ground and the power ground, and the second doped region is electrically connected to the other of the signal ground and the power ground. The signal ground is at least one of the analog ground and the digital ground. The integrated circuit also includes a common ground control circuit, which includes a first input terminal; wherein the first input terminal is electrically connected to the system ground, and the first doped region and the second doped region are electrically connected to the system ground through the common ground control circuit; when the common ground control circuit is turned off, the signal ground is isolated from the power supply ground; when the common ground control circuit is turned on, the signal ground, the power supply ground and the system ground are electrically connected. The common ground control circuit includes a first output terminal and a second output terminal, the first output terminal being electrically connected to the first doped region and the second output terminal being electrically connected to the second doped region; The common-ground control circuit includes a first transistor, a second transistor, and a first resistor. The source of the first transistor is electrically connected to the first output terminal, and the source of the second transistor is electrically connected to the second output terminal. The drain of the first transistor is electrically connected to the first input terminal, and the drain of the second transistor is electrically connected to the first input terminal. One end of the first resistor is electrically connected to the signal module circuit, and the other end of the first resistor is electrically connected to the gate of the first transistor and the gate of the second transistor. When the signal module circuit outputs an analog signal or a digital signal, the first input terminal is electrically connected to the first output terminal and the second output terminal. When the first transistor is turned on, one of the signal ground and the power ground is connected to the system ground; when the second transistor is turned on, the other of the signal ground and the power ground is connected to the system ground. The first transistor and the second transistor are turned on or off simultaneously. If the first transistor and the second transistor are turned on simultaneously, the signal ground, power ground, and system ground are common ground, thus ensuring that the integrated circuit will not encounter program errors when it needs a unified ground signal to operate. If the first transistor and the second transistor are turned off simultaneously, the signal ground and the power ground are located in different regions of the semiconductor substrate and are isolated by a deep well. The signal ground and the power ground are independent grounding points and do not interfere with each other.

2. The integrated circuit according to claim 1, characterized in that, The semiconductor substrate includes a first slit and a second slit, and an insulating structure is provided in both the first slit and the second slit. The first slit is located between the deep well and the first doped region, and the second slit is located between the deep well and the second doped region.

3. The integrated circuit according to claim 1, characterized in that, The semiconductor substrate is a P-type substrate, and the deep well is an N-well.

4. The integrated circuit according to claim 1, characterized in that, The semiconductor substrate is an N-type substrate, and the deep well is a P-well.

5. A consumable chip, characterized in that, Including the integrated circuit as described in any one of claims 1-4.

6. An MCU chip, characterized in that, Including the integrated circuit as described in any one of claims 1-4.

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