Semiconductor structure, semiconductor device and method for forming the same

Abstract

Embodiments of the present disclosure provide embodiments of semiconductor devices. In one embodiment, the semiconductor device includes a gate structure, a source / drain component adjacent to the gate structure, a first dielectric layer located above the source / drain component, an etch stop layer located above the gate structure and the first dielectric layer, a second dielectric layer located above the etch stop layer, a source / drain contact including a first portion extending through the first dielectric layer and a second portion extending through the etch stop layer and the second dielectric layer, a metal silicide layer disposed between the second portion and the etch stop layer, and a metal nitride layer disposed between the first portion and the first dielectric layer. Embodiments of the present application provide semiconductor structures, semiconductor devices, and methods for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures, semiconductor devices, and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. During the evolution of ICs, as the geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases, the functional density (i.e., the number of interconnected devices per unit chip area) is generally increasing. This scale reduction process generally provides many benefits by increasing production efficiency and reducing associated costs. This scaling down process also increases the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology moves toward smaller technology nodes, it becomes more difficult to control source / drain series resistance within tolerable limits. Specifically, copper plug technology has difficulty keeping up with aggressive device performance. Therefore, although existing contact plug structures are generally satisfactory for their intended purpose, they are not satisfactory in all aspects. Summary of the invention

[0004] An embodiment of the present application provides a semiconductor device, comprising: a gate structure; a source / drain component adjacent to the gate structure; a first dielectric layer located above the source / drain component; an etch stop layer located above the gate structure and the first dielectric layer; a second dielectric layer located above the etch stop layer; a source / drain contact comprising: a first portion extending through the first dielectric layer, and a second portion extending through the etch stop layer and the second dielectric layer; a metal silicide layer disposed between the second portion and the etch stop layer; and a metal nitride layer disposed between the first portion and the first dielectric layer.

[0005] An embodiment of the present application provides a semiconductor structure, comprising: a source / drain component; a first dielectric layer located above the source / drain component; a second dielectric layer located above the first dielectric layer; a source / drain contact, comprising: a first portion extending through the first dielectric layer, and a second portion extending through the second dielectric layer; a conductive barrier layer disposed between the first portion and the first dielectric layer; a dielectric barrier layer disposed between the conductive barrier layer and the first dielectric layer; and a metal silicide layer disposed between and in contact with the second dielectric layer and the second portion.

[0006] An embodiment of the present application also provides a method, comprising: receiving a workpiece, the workpiece comprising: a gate structure, a source / drain component adjacent to the gate structure, a bottom etch stop layer located above the source / drain component, a first dielectric layer located above the bottom etch stop layer, and a second dielectric layer located above the first dielectric layer; forming a source / drain contact opening through the bottom etch stop layer, the first dielectric layer and the second dielectric layer to expose the source / drain component, conformally depositing a dielectric barrier layer above the workpiece; grooved the dielectric barrier layer to expose a top-facing surface of the workpiece; after grooved the dielectric barrier layer, conformally deposited a metal layer above the workpiece; after conformally depositing the metal layer, annealing the workpiece to form a metal nitride layer; etch back the metal nitride layer; and after the etch back, forming a contact plug above the metal nitride layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the accompanying drawings illustrate only typical embodiments of the present invention and, therefore, should not be viewed as limiting the scope of the present invention, as the present invention may be equally well applied to other embodiments.

[0008] Figure 1 is a flow chart illustrating a method of manufacturing a semiconductor device according to one or more aspects of the present disclosure.

[0009] Figure 2-Figure 12 According to one or more aspects of the present disclosure, Figure 1 Partial cross-sectional views of a workpiece at various manufacturing stages in the method. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component formed between the first component and the second component does not directly contact the first component and the second component. Moreover, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, but does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0011] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0012] In addition, when "about," "approximately," or the like is used to describe a value or range of values, the term is intended to encompass numbers within a reasonable range, taking into account variations that inherently occur during manufacturing as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing components having values ​​associated with the values, a value or range of values ​​encompasses a reasonable range including the value, such as within + / -10% of the value. For example, a material layer having a thickness of "about 5 nm" may encompass a size range of 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is known to those of ordinary skill in the art to be + / -15%. In addition, the present invention may repeat reference numerals and / or letters in various instances. Such repetition is intended solely for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0013] The present disclosure relates generally to contact structures for semiconductor devices, and more particularly to source / drain contact structures.

[0014] As IC devices move to smaller technology nodes, it becomes more difficult to control source / drain series resistance within tolerable limits. The need for low resistance poses a significant challenge as current density increases with decreasing size. It is estimated that in current technology, series resistance can reduce saturation current by 40% or more. On top of that, the increase in interconnect resistance due to scaling is expected to require lower resistance values ​​for device contacts. To maximize the advantage of high mobility channels in drain current, it becomes important to reduce contact resistance. Copper used as contact material is unlikely to meet demanding contact resistance device performance requirements.

[0015] The present disclosure provides a method for forming a contact structure to improve the contact resistance (Rcsd) at the source / drain region. In an exemplary embodiment, a workpiece is received. The workpiece includes a gate structure, a source / drain component adjacent to the gate structure, a first dielectric layer located above the source / drain component, an etch stop layer located above the first dielectric layer, and a second dielectric layer located above the etch stop layer. A source / drain contact opening is formed through the second dielectric layer, the etch stop layer, and the first dielectric layer to expose the source / drain component. A dielectric barrier layer is deposited above the workpiece, and the dielectric barrier layer is grooved to expose the source / drain component. A metal layer is then deposited above the workpiece, including on the exposed source / drain component. After the workpiece is annealed to form a metal nitride layer from the metal layer and the dielectric barrier layer, the metal nitride layer is etched back until the metal nitride layer and the top surface of the gate structure are coplanar. The etch back process includes using photon assisted implantation to implant germanium and form a silicide layer on the second dielectric layer. A source / drain contact plug that may include cobalt is then formed in the source / drain contact opening. The source / drain contact plug includes a first portion extending through the first dielectric layer and a second portion extending through the etch stop layer and the second dielectric layer. Due to the etch back of the metal nitride layer, the second portion is wider than the first portion, which improves the metal filling window and relaxes the coverage requirement when forming a contact feature over the source / drain contact plug.

[0016] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 1 is a flow chart illustrating a method 100 of forming a semiconductor device according to one or more aspects of the present disclosure. The method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Figure 2-Figure 12 The method 100 is described, which is a partial cross-sectional view of a workpiece 200 at different stages of fabrication according to an embodiment of the method 100. Because the workpiece 200 is fabricated into a semiconductor device 200 after completing the fabrication process, the workpiece 200 may be referred to herein as a semiconductor device 200. Throughout this disclosure, the same reference numerals refer to the same components unless otherwise specified.

[0017] First reference Figure 1 and Figure 2 The method 100 includes a block 102 of receiving a workpiece 200. Figure 2As shown, the workpiece 200 includes a substrate 202 and a fin structure 204 rising from the substrate 202. The workpiece 200 also includes an active region (whose view is blocked) isolated from adjacent active regions by an isolation structure 204. The active region extends longitudinally along the X direction and is divided into a source / drain region 202SD and a channel region 202C. Figure 2 2 shows a source / drain region 202SD and two channel regions 202C. A first gate structure 208-1 and a second gate structure 208-2 are formed over the channel regions 202C of the active region and the isolation member 204. Figure 2 As shown, a source / drain feature 206 is formed over the source / drain region 202SD of the active region, and at least a portion of the source / drain feature 206 extends into the isolation feature 204. A gate spacer 210 is disposed along the sidewalls of the first gate structure 208-1 and the second gate structure 208-2. The workpiece 200 also includes a bottom contact etch stop layer (BCESL) 212 disposed over the source / drain feature 206 and the sidewalls of the first gate structure 208-1 and the second gate structure 208-2. A first interlayer dielectric (ILD) layer 214 is disposed over the BCESL 212. Figure 2 In the illustrated embodiment, the workpiece 200 further includes an etch stop layer (ESL) 218 ​​located above the first ILD layer 214, the first gate structure 208-1, and the second gate structure 208-2. A dielectric layer 220 is disposed above the ESL 218. In some cases, the workpiece 200 may further include a dielectric cut feature 216 that separates an active region from an adjacent active region aligned along the X direction.

[0018] Substrate 202 may be a silicon (Si) substrate. Alternatively or additionally, substrate 202 may include other elemental semiconductor materials such as germanium (Ge). In some embodiments, substrate 202 is made of a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, substrate 202 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, substrate 202 includes one or more epitaxial layers. For example, substrate 202 may have an epitaxial layer located above a bulk semiconductor. In some embodiments, substrate 202 may include a buried insulator layer, such as a buried silicon oxide layer, and may be a silicon on insulator (SOI) substrate.

[0019] The active region where the first gate structure 208-1, the second gate structure 208-2 and the source / drain component 206 are located may include a vertical stack of one or more fin elements or channel components. When the active region includes one or more fin structures, the first gate structure 208-1 and the second gate structure 208-2 are gate structures for fin field effect transistors (FinFETs). When the active region includes a vertical stack of channel components, the first gate structure 208-1 and the second gate structure 208-2 are gate structures for multi-bridge channel (MBC) transistors. FinFET and MBC transistors are examples of multi-gate devices that have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current and reducing short channel effect (SCE). With regard to MBC transistors, because their gate structure surrounds the channel region, MBC transistors may also be referred to as surround gate transistors (SGTs) or full ring gate (GAA) transistors. The channel components of MBC transistors may be in the shape of nanowires, nanosheets, or other nanostructures. The shape of the channel member also provides alternative names for MBC transistors, such as nanosheet transistors or nanowire transistors. The active region can be patterned from substrate 202, but the epitaxial layers are deposited on substrate 20. The active region can include silicon (Si), silicon germanium (SiGe), germanium (Ge), or III-V semiconductor materials such as gallium arsenide, indium arsenide, or indium phosphide.

[0020] The isolation feature 204 may also be referred to as a shallow trench isolation (STI) feature 204. In some embodiments, the isolation feature 204 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. Depending on the conductivity type of the semiconductor device 200, the source / drain feature 206 may be n-type or p-type. When the source / drain feature 206 is n-type, it may include silicon doped with phosphorus (Si:P), silicon doped with arsenic (Si:As), or silicon doped with antimony (Si:Sb). When the source / drain feature 206 is p-type, it may include silicon germanium doped with boron (SiGe:B) or silicon germanium doped with gallium (SiGe:Ga). The source / drain feature 206 may be formed using vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE) and may be referred to as an epitaxial feature. In some embodiments, the source / drain feature 206 may include more than one layer. For example, as Figure 2 As shown, the source / drain features 206 may include an outer epitaxial layer and an inner epitaxial layer, and the inner epitaxial layer is more heavily doped than the outer epitaxial layer to reduce resistance.

[0021] Although not explicitly shown, each of the first gate structure 208-1 and the second gate structure 208-2 may include a gate dielectric layer and a gate electrode. The gate dielectric layer may include an interface layer disposed on the active region and a high-k dielectric layer disposed above the interface layer. Here, the high-k dielectric material refers to a dielectric material having a dielectric constant greater than the dielectric constant of silicon dioxide (approximately 3.9). In some embodiments, the interface layer includes silicon oxide and silicon halide. The high-k dielectric layer may include hafnium oxide (HfO 2 Alternatively, the high-k dielectric layer may include other high-k dielectrics, such as titanium oxide (TiO 2 ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2 O 5 ), Hafnium Silicon Oxide (HfSiO 4 )、ZrO 2 ), zirconium oxide silicon (ZrSiO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 )、ZrO、Yttrium oxide (Y 2 O 3 )、SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, Hafnium Lanthanum Oxide (HfLaO), Lanthanum Silicon Oxide (LaSiO), Aluminum Silicon Oxide (AlSiO), Hafnium Tantalum Oxide (HfTaO), Hafnium Titanium Oxide (HfTiO), (Ba, Sr)TiO 3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof or other suitable materials. The gate electrode layer may include a single layer or an alternative multilayer structure, such as a metal layer (work function metal layer) having a selected work function that enhances device performance, a liner, a wetting layer, an adhesion layer, various combinations of metal alloys or metal silicides. For example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof.

[0022] The gate spacer 210 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbon, silicon oxynitride, and / or combinations thereof. The BCESL 212 and the ESL 218 may include silicon nitride. The first ILD layer 214 may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (such as borophosphosilicate glass (BPSG), fused quartz glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG)), and / or other suitable dielectric materials. The dielectric cutting member 216 may be formed of silicon nitride or a metal oxide material. Exemplary metal oxide materials may include aluminum oxide, zirconium oxide, or hafnium oxide. The dielectric layer 220 may include silicon oxide. In one embodiment, the dielectric layer 220 may be formed of silicon oxide using plasma enhanced chemical vapor deposition (PECVD), and such silicon oxide may be referred to as plasma enhanced oxide (PEOX). In some embodiments, the thickness of BCESL 212 along the Z direction is between about 2 nm and about 4 nm; the thickness of ESL 218 along the Z direction is between about 2 nm and about 4 nm; and the thickness of first ILD layer 214 along the Z direction is between about 8 nm and about 10 nm.

[0023] refer to Figure 1 and Figure 3 , the method 100 includes a frame 104, forming a source / drain contact opening 222. The source / drain contact opening 222 can be formed using a combination of photolithography and etching processes. In an exemplary process, a hard mask is deposited over the workpiece 200. A photoresist layer is then deposited over the hard mask layer. The photoresist layer is exposed to radiation reflected from or transmitted through the photomask, a post-exposure bake process is performed, and the photoresist layer is developed to form a masking element including the photoresist layer. The masking element can then be used as an etching mask to pattern the hard mask, and the patterned hard mask is used as an etching mask to etch the dielectric layer 220, the ESL 218, the first ILD layer 214, and the BCESL 212 to form the source / drain contact opening 222 to expose the source / drain feature 206. In some embodiments, the etching process to form the source / drain contact opening 222 can be a dry etching process or a reactive ion etching (RIE). Exemplary dry etching processes may include oxygen-containing gases, hydrogen gases, fluorine-containing gases (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , CH 3 F.C 4 H 8 , C 4 F 6 and / or C 2 F 6), carbon-containing gases (e.g., CO, CH 4 and / or C 3 H 8 ), chlorine-containing gases (e.g., Cl 2 , CHCl 3 , CCl 4 and / or BCl 3 ), bromine-containing gases (e.g., HBr and / or CHBr 3 ), iodine-containing gas, other suitable gas and / or plasma and / or a combination thereof. Figure 3 In some of the embodiments shown, the source / drain contact openings 222 may partially extend into the source / drain features 206 .

[0024] refer to Figure 1 and Figure 4 , the method 100 includes a block 106 of depositing a dielectric barrier layer 224 over the workpiece 200. In some embodiments, the dielectric barrier layer 224 may include silicon nitride. In some embodiments, the dielectric barrier layer 224 may be deposited using CVD, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), sub-atmospheric pressure CVD (SACVD), or atomic layer deposition (ALD). In some embodiments, the dielectric barrier layer 224 may be conformally deposited in the source / drain contact openings 222 such that it extends along the sidewalls of the source / drain contact openings 222. Figure 4 As shown, the dielectric barrier layer 224 may be deposited over the top surface of the dielectric layer 220, the sidewalls of the dielectric layer 220, the sidewalls of the ESL 218, the sidewalls of the first ILD layer 214, and the sidewalls of the BCESL 212. Figure 4 In the embodiment of the present invention, dielectric barrier layer 224 is deposited over and covers source / drain features 206. In some cases, dielectric barrier layer 224 can be deposited to a thickness between about 3 nm and about 4 nm.

[0025] refer to Figure 1 and Figure 5 , the method 100 includes a block 108 of recessing the dielectric barrier layer 224 to expose the source / drain features 206. In some embodiments, an anisotropic etching process 300 is performed on the workpiece 200 at block 108 to remove the dielectric barrier layer 224 deposited on the source / drain features 206. Figure 5 As shown, at the end of the operation at block 108, at least a portion of the source / drain feature 206 is exposed in the source / drain contact opening 222. In some embodiments, the anisotropic etching process 300 may include a reactive ion etching (RIE) process using hydrogen, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH2 F 2 , CHF 3 and / or C 2 F 6 ), chlorine-containing gases (e.g., Cl 2 , CHCl 3 , CCl 4 and / or BCl 3 ), bromine-containing gases (e.g., HBr and / or CHBR 3 ), iodine-containing gas, other suitable gas and / or plasma, and / or a combination thereof. After the trenching at block 108, the dielectric barrier layer 224 may remain disposed along the sidewalls of the dielectric layer 220, the sidewalls of the ESL 218, the sidewalls of the first ILD layer 214, and the sidewalls of the BCESL 212. Figure 5 In some embodiments shown, a bottom corner portion 2240 of the dielectric barrier layer 224 can be subjected to the anisotropic etching process 300. The bottom corner portion 2240 can cover a portion of the source / drain feature 206.

[0026] Still refer to Figure 1 and Figure 5 , the method 100 includes a block 110 of implanting dopants into the exposed source / drain features 206. In some embodiments, an implantation process 300 may be performed at block 110 to implant germanium (Ge) into the exposed source / drain features 206. In some implementations where the source / drain features 206 are p-type, the source / drain features 206 may have an uneven distribution of germanium due to germanium aggregation, which may result in unsatisfactory silicide formation thereon in subsequent processes. The germanium (Ge) implantation at block 110 may help provide a uniform distribution of germanium on the exposed surface of the p-type source / drain features 206, which helps in satisfactory silicide formation. In some embodiments, the implantation process 300 may be a photon assisted implantation (PAI). In order to ensure that the germanium is directed downward from the source / drain contact opening 222 to the source / drain features 206, the implantation process 300 may have a small (i.e., steep) implantation angle. The germanium implantation process 300 may also be referred to as a pre-silicide implantation process.

[0027] refer to Figure 1 and Figure 6, the method 100 includes a block 112 of depositing a first metal liner 226 over the workpiece 200. The first metal liner 226 may include titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), or tungsten (W). In one embodiment, the first metal liner 226 includes titanium (Ti). Because the first metal liner 226 will react with other layers to form a silicide layer or a metal nitride layer, the first metal liner 226 may also be referred to as a metal precursor layer. In some embodiments, the first metal liner 226 may be deposited using physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), or metal organic chemical vapor deposition (MOCVD).

[0028] refer to Figure 1 and Figure 7 , the method 100 includes a block 114, performing an annealing process 400 to form the second metal liner 228 and the silicide feature 230. In some embodiments, the annealing process 400 at block 112 may be a rapid thermal annealing (RTA) process, a laser annealing process, a spike annealing process, or a millisecond annealing (MSA) process. In some cases, the annealing process 400 may include an annealing temperature or a peak annealing temperature between about 200° C. and about 500° C. The annealing process 400 may induce or accelerate a reaction between the first metal liner 226 and the dielectric barrier layer 224 and between the first metal liner 226 and the exposed source / drain feature 206. As Figure 7As shown, through the annealing process 400, the first metal liner 226 and the dielectric barrier layer 224 can react to form the second metal liner 228. The second metal liner 228 can include the metal in the first metal liner 226 and the nitrogen atoms from the dielectric barrier layer 224. For example, when the first metal liner 226 includes titanium and the dielectric barrier layer 224 includes silicon nitride, the titanium in the first metal liner 226 can be at least partially nitrided to form titanium nitride (TiN). Because nitridation can be completed, the second metal liner 228 can include both the metal of the first metal liner 226 and the metal nitride form from nitridation. That is, in this example, the second metal liner 228 can include both titanium (Ti) and titanium nitride (TiN). At the same time, the first metal liner 226 in contact with the source / drain feature 206 can undergo a silicidation reaction caused or accelerated by the annealing process 400. For example, when the first metal liner 226 includes titanium and the source / drain feature 206 includes silicon, the titanium in the first metal liner 226 can undergo a silicidation reaction to form a silicide feature 230 at the interface between the first metal liner 226 and the source / drain feature 206. In this example, the silicide feature 230 can include titanium silicide. Depending on the composition of the first metal liner 226, the second metal liner 228 can also include a mixture of tantalum (Ta) and tantalum nitride (TaN), a mixture of cobalt (Co) and cobalt nitride (CoN), a mixture of nickel (Ni) and nickel nitride (NiN), or a mixture of tungsten (W) and tungsten nitride (WN). The silicide feature 230 can also include tantalum silicide, cobalt silicide, nickel silicide, or tungsten silicide. Although in Figure 7 1 , but the annealing process 400 may also react the metal in the second metal liner 228 with the silicon in the dielectric layer 220 to form a metal silicide that may be precipitated near the boundary between the dielectric barrier layer 224 and the dielectric layer 220. This precipitation of the metal silicide may be exposed as the third metal liner 232 during block 116.

[0029] refer to Figure 1 , Figure 8 and Fig. 9 The method 100 includes a block 116 of etching back the second metal liner 228. In some embodiments, an etch back process is used to etch back the second metal liner 228 and the dielectric barrier layer 224. In some embodiments, the etch back process can be anisotropic and can include a reactive ion etching (RIE) process using hydrogen, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 and / or C 2 F 6 ), chlorine-containing gases (e.g., Cl 2, CHCl 3 , CCl 4 and / or BCl 3 ), bromine-containing gases (e.g., HBr and / or CHBR 3 ), iodine-containing gas, other suitable gas and / or plasma and / or a combination thereof. Figure 8 In some embodiments shown, the etch back process etches the second metal liner 228 and the dielectric barrier layer 224 until the top surface of the second metal liner 228 is substantially coplanar with the top surfaces of the first gate structure 208-1, the second gate structure 208-2, and the first ILD layer 214. Figure 8 As shown, since the etch-back process can substantially remove the first metal liner 228 and the dielectric barrier layer 224 from the surface of the dielectric layer 220 and the ESL 218, the third metal liner 232 deposited and formed at the frame 114 can be exposed. The third metal liner 232 may include a metal silicide and may have a composition similar to the silicide component 230. In one embodiment, the third metal liner 232 may include titanium silicide. In some other embodiments, the third metal liner 232 may include tantalum silicide, cobalt silicide, nickel silicide, or tungsten silicide.

[0030] Figure 8 The dashed area in the figure is enlarged and Fig. 9 As shown in FIG. 5 . Since the etch-back process 500 removes the second metal liner 228 and the dielectric barrier layer 224 from the sidewalls of the dielectric layer 220 and the ESL 218, Fig. 9 The source / drain contact opening 222 in the embodiment includes a step change in the width direction at the interface level between the first ILD layer 214 and the ESL 218. That is, the width of the source / drain contact opening 222 may experience an abrupt change near or around the interface level between the first ILD layer 214 and the ESL 218. Additionally, due to the presence of the bottom corner portion 2240 and the second metal liner 228 disposed above the bottom corner portion 2240, the source / drain contact opening 222 also includes a step change in the width direction adjacent to the bottom corner portion 2240.

[0031] refer to Figure 1 and Fig.10 The method 100 includes a block 118 of depositing a first metal layer 234 in the source / drain contact opening 222. The first metal layer 234 forms a contact plug 240 ( Fig.11The first metal layer 234 is formed at a periphery of the contact plug 240 and at interfaces with the first dielectric layer 220, the ESL 218, the second metal layer 228, and the dielectric barrier layer 224. In some embodiments, the first metal layer 234 may include cobalt (Co) and may be deposited using atomic layer deposition (ALD) or plasma enhanced ALD (PEALD). An exemplary precursor for cobalt (Co) deposition at box 116 may include bis(ethylcyclopentadienyl)cobalt (i.e., cobaltocene). Although ALD or PEALD deposition allows the first metal layer 234 to be conformal, it is slow and may increase process time and cost. Therefore, in some embodiments, the first metal layer 234 is only formed to a thickness between about 1 nm and about 2 nm, and a deposition method with a greater deposition rate is used to deposit the remainder of the contact plug 240. In some alternative embodiments, the first metal layer 234 may include other metals, such as ruthenium (Ru), nickel (Ni), molybdenum (Mo), or tungsten (W). As Fig.10 As shown, since the first metal layer 234 lines the periphery of the contact plug, it may be referred to as a halo metal layer or halo layer.

[0032] refer to Figure 1 and Fig.11 , method 100 includes box 120, depositing a second metal layer 236 over the first metal layer 234. The second metal layer 236 constitutes a metal filling layer for the contact plug 240. In some embodiments, the second metal layer 236 may include cobalt (Co) and may be deposited using CVD, plasma enhanced CVD (PECVD), or metal organic CVD (MOCVD). In these embodiments, the composition of the first metal layer 234 and the composition of the second metal layer 236 may be substantially the same. In alternative embodiments, the second metal layer 236 may include other metals, such as copper (Cu), ruthenium (Ru), nickel (Ni), molybdenum (Mo), or tungsten (W). The second metal layer is separated from the first dielectric layer 220, the ESL 218, the second metal liner 228, and the dielectric barrier layer 224 by the first metal layer 234. After depositing the second metal layer 236, a planarization process such as a chemical mechanical polishing (CMP) process is performed to remove excess material, such as excess first metal layer 234 or excess second metal layer 236. Fig.11 As shown, the planarization process removes the material above the dielectric layer 220 and even the surface portion of the dielectric layer 220, so that the second metal layer 236 and the top surface of the dielectric layer 220 are coplanar. At this time, the contact plug 240 is basically formed in the source / drain contact opening 222 ( Fig.10 shown).

[0033] because Fig. 9 The source / drain contact openings 222 in the embodiment include a step-wise width variation, so Fig.11 The contact plug in the also includes a step width variation. Fig.11 , the contact plug 240 includes a bottom portion 240B, a lower portion 240L located above the bottom portion 240B, and an upper portion 240U located above the lower portion 240L. The bottom portion 240B refers to a portion of the contact plug 240 below the top surface of the corner portion 2240. The lower portion 240L refers to a portion of the contact plug 240 between the top surface of the corner portion 2240 and the top surface of the first ILD layer 214. The upper portion 240U refers to a portion of the contact plug above the top surface of the first ILD layer 214. The bottom portion 240B has a first width (W1) along the X direction, the lower portion 240L has a second width (W2) along the X direction, the bottom surface of the upper portion 240U has a third width (W3) along the X direction, and the top surface of the upper portion 240U has a fourth width (W4) along the X direction. The fourth width (W4) is greater than the third width (W3), the third width (W3) is greater than the second width (W2), and the second width (W2) is greater than the first width (W1). In some cases, the first width (W1) can be between about 12nm and about 14nm, the second width (W2) is between about 13nm and about 15nm, the third width (W3) is between about 14nm and about 16nm, and the fourth width (W4) is between about 15nm and about 17nm. A step-like width change can be observed at the junction between the lower portion 240L and the upper portion 240U. Although the lower portion 240L and the upper portion 240U are continuous, the change from the second width W2 to the third width W3 is discontinuous and abrupt. This is due to the etching back of the dielectric barrier layer 224 and the second metal liner 228 at the frame 114. The bottom of the second metal liner 228 extends downward through the dielectric barrier layer 224, and the bottom 240B of the contact plug 240 extends to the bottom of the second metal liner 228. Along the Z direction, the thickness of the silicide feature 230 is between about 4 nm and about 5 nm.

[0034] refer to Figure 1 and Fig.12, the method 100 includes a block 122, performing further processing. Such additional processes may include the formation of a top silicide layer 246, the deposition of an intermediate contact etch stop layer (MCESL) 242, the deposition of a second ILD layer 244, the formation of source / drain contact vias 250, and the formation of a gate contact via 260. The MCESL 242 may include silicon nitride, silicon carbonitride, or silicon oxycarbide, and may be deposited using CVD, PECVD, or ALD. In one embodiment, the MCESL 242 includes silicon nitride. The silicon precursor of the MCESL 242 deposition process may react with the contact plug 240 and form a top silicide layer 246 on the top surface of the contact plug 240. In one embodiment, the top silicide layer 246 may include cobalt silicide. The composition and deposition of the second ILD layer 244 may be similar to the first ILD layer 214. In some embodiments, the second ILD layer 244 may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG)), and / or other suitable dielectric materials. In some embodiments, the second ILD layer 244 may be deposited using spin coating, CVD, flowable CVD (FCVD), PECVD, or a suitable deposition method. Then, source / drain contact via openings are formed through the second ILD layer 244 and the MCESL 242 to expose the top silicide layer 246 or the contact plug 240. In the same process or a separate process, a gate contact via opening is formed through the second ILD layer 244, the MCESL 242, and the dielectric layer 220 to expose the second gate structure 208-2. In some embodiments, reactive ion etching (RIE) may be used to form the source / drain contact via openings and the gate contact via opening. Such RIE processes may include a plasma having an oxygen-containing gas, a hydrogen gas, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , CH 3 F.C 4 H 8 , C 4 F 6 and / or C 2 F 6 ), carbon-containing gases (e.g., CO, CH 4 and / or C 3 H 8 ), chlorine-containing gases (e.g., Cl 2 , CHCl 3 , CCl 4 and / or BCl 3), bromine-containing gases (e.g., HBr and / or CHBr 3 ), iodine-containing gas, other suitable gas and / or plasma and / or combination thereof. After the pre-cleaning process removes debris and contaminants above the contact plug 240 and the second gate structure 208-2, source / drain contact vias 250 and gate contact vias 260 are then formed in the source / drain contact via openings and the gate contact via openings, respectively. In some embodiments, the source / drain contact vias 250 and the gate contact vias 260 may include tungsten and may be deposited using PVD or electroless plating.

[0035] Given that Fig.12 , some benefits of the embodiments of the present disclosure are apparent. Due to the etch-back process at frame 116, the upper portion 240U ( Fig.11 The width of the source / drain contact via 250 is wider than that of the contact plug 240 without the second metal liner 228, which is less conductive than the contact plug 240. Therefore, the method and structure of the present disclosure reduces the contact resistance and improves the process tolerance. Even when the cover layer is not ideal (as shown by the arrow along the X direction), the possibility of the source / drain contact via 250 completely missing the contact plug 240 or falling on the second metal liner 228 (or the dielectric barrier layer 224) is reduced.

[0036] One aspect of the present invention relates to a semiconductor device. The semiconductor device includes a gate structure, a source / drain feature adjacent to the gate structure, a first dielectric layer located above the source / drain feature, an etch stop layer located above the gate structure and the first dielectric layer, a second dielectric layer located above the etch stop layer, a source / drain contact including a first portion extending through the first dielectric layer and a second portion extending through the etch stop layer and the second dielectric layer, a metal silicide layer disposed between the second portion and the etch stop layer, and a metal nitride layer disposed between the first portion and the first dielectric layer.

[0037] In some embodiments, the metal nitride layer comprises titanium nitride. In some cases, the metal silicide layer comprises titanium silicide. In some embodiments, the source / drain contact comprises cobalt. In some embodiments, the source / drain contact consists essentially of cobalt. In some embodiments, the semiconductor device may further include a dielectric barrier layer sandwiched between the metal nitride layer and the first dielectric layer. In some embodiments, the dielectric barrier layer comprises silicon nitride. In some embodiments, the metal silicide layer is in direct contact with a second portion of the source / drain contact. In some embodiments, the first portion comprises a top width, the second portion comprises a bottom width, and the bottom width of the second portion is greater than the top width of the first portion.

[0038] Another aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a source / drain component, a first dielectric layer located above the source / drain component, a second dielectric layer located above the first dielectric layer, a source / drain contact including a first portion extending through the first dielectric layer and a second portion extending through the second dielectric layer, a conductive barrier layer disposed between the first portion and the first dielectric layer, a dielectric barrier layer disposed between the conductive barrier layer and the first dielectric layer, and a metal silicide layer disposed between the second dielectric layer and the second portion and in contact therewith. In some embodiments, the source / drain contact includes a step width variation between the first portion and the second portion. In some cases, the semiconductor structure may also include a silicide component disposed between the source / drain contact and the source / drain component. In some embodiments, an end of the conductive barrier layer extends through the dielectric barrier layer and into the silicide component. In some embodiments, the source / drain contact also includes a bottom portion disposed below the first portion, and the bottom of the source / drain contact extends into the end of the conductive barrier layer. In some cases, the first dielectric layer and the second dielectric layer include silicon oxide, wherein the metal silicide layer includes titanium silicide, the dielectric barrier layer includes silicon nitride, the conductive barrier layer includes titanium nitride, and the source / drain contacts include cobalt. In some embodiments, the semiconductor structure may further include an etch stop layer disposed between the first dielectric layer and the second dielectric layer.

[0039] Another aspect of the present disclosure relates to a method. The method includes: receiving a workpiece, which includes a gate structure, a source / drain component adjacent to the gate structure, a bottom etch stop layer located above the source / drain component, a first dielectric layer located above the bottom etch stop layer, and a second dielectric layer located above the first dielectric layer. The method may also include: forming a source / drain contact opening through the bottom etch stop layer, the first dielectric layer, and the second dielectric layer to expose the source / drain component; conformally depositing a dielectric barrier layer above the workpiece; groove the dielectric barrier layer to expose the top-facing surface of the workpiece; after groove the dielectric barrier layer, conformally depositing a metal layer above the workpiece; after conformally depositing the metal layer, performing an annealing process on the workpiece to form a metal nitride layer; etching back the metal nitride layer; and after etching back, forming a contact plug above the metal nitride layer.

[0040] In some embodiments, the method may further include: implanting germanium into the workpiece after the dielectric barrier layer is grooved. In some embodiments, the implanting includes a photon-assisted implantation process. In some embodiments, etching back the metal nitride layer includes: etching the metal nitride layer until a top surface of the metal nitride layer is substantially coplanar with a top surface of the gate structure. In some cases, etching back the metal nitride layer includes: forming a metal silicide layer above a surface of the second dielectric layer.

[0041] An embodiment of the present application provides a semiconductor device, comprising: a gate structure; a source / drain component adjacent to the gate structure; a first dielectric layer located above the source / drain component; an etch stop layer located above the gate structure and the first dielectric layer; a second dielectric layer located above the etch stop layer; a source / drain contact, comprising: a first portion extending through the first dielectric layer, and a second portion extending through the etch stop layer and the second dielectric layer; a metal silicide layer disposed between the second portion and the etch stop layer; and a metal nitride layer disposed between the first portion and the first dielectric layer. In some embodiments, the metal nitride layer comprises titanium nitride. In some embodiments, the metal silicide layer comprises titanium silicide. In some embodiments, the source / drain contact comprises cobalt. In some embodiments, the source / drain contact consists essentially of cobalt. In some embodiments, further comprising: a dielectric barrier layer sandwiched between the metal nitride layer and the first dielectric layer. In some embodiments, the dielectric barrier layer comprises silicon nitride. In some embodiments, the metal silicide layer is in direct contact with the second portion of the source / drain contact. In some embodiments, the first portion includes a top width, wherein the second portion includes a bottom width, wherein the bottom width of the second portion is greater than the top width of the first portion.

[0042] An embodiment of the present application provides a semiconductor structure, comprising: a source / drain component; a first dielectric layer located above the source / drain component; a second dielectric layer located above the first dielectric layer; a source / drain contact, comprising: a first portion extending through the first dielectric layer, and a second portion extending through the second dielectric layer; a conductive barrier layer disposed between the first portion and the first dielectric layer; a dielectric barrier layer disposed between the conductive barrier layer and the first dielectric layer; and a metal silicide layer disposed between and in contact with the second dielectric layer and the second portion. In some embodiments, the source / drain contact comprises a step width variation between the first portion and the second portion. In some embodiments, it further comprises: a silicide component disposed between the source / drain contact and the source / drain component, wherein an end of the conductive barrier layer extends through the dielectric barrier layer and into the silicide component. In some embodiments, the source / drain contact further comprises a bottom portion disposed below the first portion, wherein the bottom portion of the source / drain contact extends into an end of the conductive barrier layer. In some embodiments, the first dielectric layer and the second dielectric layer include silicon oxide, wherein the metal silicide layer includes titanium silicide, wherein the dielectric barrier layer includes silicon nitride, wherein the conductive barrier layer includes titanium nitride, wherein the source / drain contact includes cobalt. In some embodiments, an etch stop layer is further included, disposed between the first dielectric layer and the second dielectric layer.

[0043] The embodiment of the present application also provides a method, comprising: receiving a workpiece, the workpiece comprising: a gate structure, a source / drain component adjacent to the gate structure, a bottom etch stop layer located above the source / drain component, a first dielectric layer located above the bottom etch stop layer, and a second dielectric layer located above the first dielectric layer; forming a source / drain contact opening through the bottom etch stop layer, the first dielectric layer and the second dielectric layer to expose the source / drain component, conformally depositing a dielectric barrier layer above the workpiece; groove the dielectric barrier layer to expose the top-facing surface of the workpiece; after groove the dielectric barrier layer, conformally depositing a metal layer above the workpiece; after conformally depositing the metal layer, performing an annealing process on the workpiece to form a metal nitride layer; etching back the metal nitride layer; and after the etching back, forming a contact plug above the metal nitride layer. In some embodiments, it also includes: after groove the dielectric barrier layer, implanting germanium into the workpiece. In some embodiments, the implantation includes a photon-assisted implantation process. In some embodiments, etching back the metal nitride layer comprises: etching the metal nitride layer until a top surface of the metal nitride layer is substantially coplanar with a top surface of the gate structure. In some embodiments, etching back the metal nitride layer comprises: forming a metal silicide layer over a surface of the second dielectric layer.

[0044] The above content summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that the present invention can be easily used as a basis to design or modify other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced in the present invention. Those skilled in the art should also be aware that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention. For example, by implementing different thicknesses for the bit line conductor and the word line conductor, different resistances of the conductor can be achieved. However, other techniques for changing the resistance of the metal conductor may also be used.

Claims

1. A semiconductor device, comprising: Gate structure; a source / drain component adjacent to the gate structure; a first dielectric layer located above the source / drain features; an etch stop layer, located above the gate structure and the first dielectric layer; a second dielectric layer located above the etch stop layer; Source / drain contacts, including: a first portion extending through the first dielectric layer, and a second portion extending through the etch stop layer and the second dielectric layer; a metal silicide layer disposed between the second portion and the etch stop layer; a metal nitride layer disposed between the first portion and the first dielectric layer; and a silicide component disposed between the source / drain component and the metal nitride layer, a dielectric barrier layer extending between the metal nitride layer and the first dielectric layer and between the metal nitride layer and the silicide feature, Wherein, a first bottom portion of the metal nitride layer is separated from the silicide component by a dielectric barrier layer, and a second bottom portion of the metal nitride layer is in direct contact with the silicide component.

2. The semiconductor device according to claim 1, wherein The metal nitride layer includes titanium nitride.

3. The semiconductor device according to claim 1, wherein The metal silicide layer includes titanium silicide.

4. The semiconductor device according to claim 1, wherein: The source / drain contacts include cobalt.

5. The semiconductor device according to claim 1, wherein The source / drain contacts consist essentially of cobalt.

6. The semiconductor device according to claim 1, wherein A top surface of the silicide feature is lower than a top surface of the source / drain feature.

7. The semiconductor device according to claim 6, wherein: The dielectric barrier layer includes silicon nitride.

8. The semiconductor device according to claim 6, wherein: The metal silicide layer is in direct contact with the second portion of the source / drain contact.

9. The semiconductor device according to claim 1, in, The first portion includes a top width, wherein the second portion includes a bottom width, Wherein, the bottom width of the second portion is greater than the top width of the first portion.

10. A semiconductor structure comprising: Source / drain components; a first dielectric layer located above the source / drain features; a second dielectric layer, located above the first dielectric layer; Source / drain contacts, including: a first portion extending through the first dielectric layer, and a second portion extending through the second dielectric layer; a conductive barrier layer disposed between the first portion and the first dielectric layer; a silicide component disposed between the source / drain component and the conductive barrier layer; a dielectric barrier layer disposed between the conductive barrier layer and the first dielectric layer and between the conductive barrier layer and the silicide feature; and a metal silicide layer disposed between and in contact with the second dielectric layer and the second portion, The first bottom portion of the conductive barrier layer is separated from the silicide component by a dielectric barrier layer, and the second bottom portion of the conductive barrier layer is in direct contact with the silicide component.

11. The semiconductor structure according to claim 10, wherein: The source / drain contact includes a step width variation between the first portion and the second portion.

12. The semiconductor structure according to claim 10, in, An end of the conductive barrier layer extends through the dielectric barrier layer and into the silicide feature.

13. The semiconductor structure according to claim 12, in, The source / drain contact also includes a bottom portion disposed below the first portion, The bottom of the source / drain contact extends into the end of the conductive barrier layer.

14. The semiconductor structure according to claim 10, in, The first dielectric layer and the second dielectric layer include silicon oxide, Wherein, the metal silicide layer comprises titanium silicide, Wherein, the dielectric barrier layer comprises silicon nitride, Wherein, the conductive barrier layer comprises titanium nitride, Wherein, the source / drain contacts include cobalt.

15. The semiconductor structure of claim 10, further comprising: An etch stop layer is disposed between the first dielectric layer and the second dielectric layer.

16. A method of forming a semiconductor device, comprising: A workpiece is received, the workpiece comprising: Gate structure, a source / drain component adjacent to the gate structure, a bottom etch stop layer, located above the source / drain features, a first dielectric layer disposed above the bottom etch stop layer, and a second dielectric layer, located above the first dielectric layer; forming a source / drain contact opening through the bottom etch stop layer, the first dielectric layer, and the second dielectric layer to expose the source / drain feature, conformally depositing a dielectric barrier layer over the workpiece; groove the dielectric barrier layer to expose a top-facing surface of the workpiece; after trenching the dielectric barrier layer, conformally depositing a metal layer over the workpiece; After conformally depositing the metal layer, performing an annealing process on the workpiece to form a metal nitride layer; etching back the metal nitride layer; and After the etch-back, a contact plug is formed over the metal nitride layer.

17. The method for forming a semiconductor device according to claim 16, further comprising: After the dielectric barrier layer is trenched, germanium is implanted into the workpiece.

18. The method for forming a semiconductor device according to claim 17, wherein: The implantation includes a photon assisted implantation process.

19. The method for forming a semiconductor device according to claim 16, wherein: Etching back the metal nitride layer includes etching the metal nitride layer until a top surface of the metal nitride layer is substantially coplanar with a top surface of the gate structure.

20. The method for forming a semiconductor device according to claim 16, wherein: Etching back the metal nitride layer includes forming a metal silicide layer over a surface of the second dielectric layer.

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