Adaptive Gate Regulation for Synchronous Rectifier Flyback Converters

Abstract

The present invention is entitled "Adaptive Gate Regulation for Synchronous Rectifier Flyback Converter". The present invention provides a flyback converter that dynamically adjusts the drain threshold voltage of a synchronous rectifier switching transistor for a current cycle based on operating conditions in a previous cycle of the synchronous rectifier switching transistor. A differential amplifier drives the gate voltage of the synchronous rectifier switching transistor during the on-time of the current cycle so that the drain voltage of the synchronous rectifier switching transistor is equal to the drain threshold voltage during the regulated portion of the current cycle.

Description

Technical Field

[0001] The present application relates to switching power converters, and more particularly, to adaptive gate regulation of a synchronous rectifier switching transistor in a flyback converter. Background Art

[0002] As is known in the flyback art, the secondary winding current in the transformer of a flyback converter is rectified so as not to conduct when the primary winding current is conducting. This rectification can be performed by an output diode or a synchronous rectifier switching transistor. Although the output diode is passive and therefore does not require synchronous rectifier control, the use of an output diode reduces efficiency compared to a flyback converter with synchronous rectification. Therefore, synchronous rectification is widely used to improve efficiency.

[0003] The synchronous rectifier switching transistor is typically a metal oxide semiconductor field effect transistor (MOSFET). To control the switching of the synchronous rectifier (SR) switching MOSFET, the SR controller monitors the drain-to-source voltage on the SR MOSFET. Based on the drain-to-source voltage, the SR controller detects whether the power switch transistor has been disconnected so that the SR switch transistor can be turned on. For example, if the SR switch transistor is an n-type metal oxide semiconductor (NMOS) transistor, the SR controller turns on the SR switch transistor by increasing the gate-to-source voltage of the SR switch transistor above its threshold voltage.

[0004] Operation of the flyback converter in the continuous conduction mode (CCM) of operation complicates synchronous rectifier control. In CCM, the power switch transistor is turned on before the secondary winding current ramps down to zero. In contrast, during the discontinuous conduction mode (DCM) of operation, the secondary winding current has already ramped down to zero before the power switch transistor is turned on. During DCM operation, the SR controller can turn on the SR switch transistor when the drain-to-source voltage of the SR MOSFET is less than the turn-on threshold voltage (e.g., -120mV). The SR controller can then turn off the SR switch transistor when the drain-to-source voltage approaches the turn-off threshold voltage (such as -3mV). Then because the SR switch transistor is turned off, the power switch transistor can be turned on without any risk of "breakdown", which is an undesirable co-conduction condition in which the primary winding current and the secondary winding current are simultaneously conducted.

[0005] However, in CCM operation, the power switch transistor is turned on while the SR switch transistor is still conducting. The drain-to-source voltage of the SR switch transistor rises rapidly due to the power switch transistor being turned on, causing the drain-to-source voltage to rise to the disconnection threshold voltage, and then the SR controller turns off the SR switch transistor. However, there is a common conduction condition from when the power switch transistor is turned on to when the SR switch transistor is turned off. Since the common conduction problem during CCM operation puts pressure on the power converter, a pre-drop technique is conventionally applied to the gate voltage of the SR switch transistor to reduce the common conduction time. In the pre-drop technique, the gate voltage of the SR switch transistor is pulled down to approximately the threshold voltage of the SR switch transistor. Since the gate-to-source voltage of the SR switch transistor hardly meets the threshold voltage, the SR controller can turn off the SR switch transistor faster in response to the drain-to-source voltage rising to the disconnection threshold voltage.

[0006] But how and when to pre-drop the gate voltage of the SR switch transistor remains a problem. If the gate voltage drops too fast and has an undershoot below the threshold voltage, the on-resistance of the SR switch transistor will suddenly become larger. As a result, the drain voltage of the SR switch transistor drops, resulting in increased power loss. In order to reduce power loss, it is known to control the gate voltage of the SR switch transistor to adjust its drain voltage to a fixed preset value. This regulation works well during DCM operation and critical DCM operation. But during CCM voltage, the drain voltage may not reach the expected preset value. In order to achieve regulation during CCM operation, the expected preset value can be reduced, but the resulting threshold for controlling the gate voltage sacrifices efficiency during CCM and DCM operation.

[0007] Therefore, there is a need in the art for a flyback converter with improved gate voltage control to increase power efficiency in both DCM and CCM operations. Summary of the invention

[0008] According to a first aspect of the present disclosure, a synchronous rectifier controller for a flyback converter is provided, the synchronous rectifier controller comprising: a differential amplifier, the differential amplifier being configured to drive a gate voltage of the synchronous rectifier switching transistor during a regulated portion of a current cycle of the synchronous rectifier switching transistor, the differential amplifier being responsive to a difference between a drain voltage of the synchronous rectifier switching transistor and a dynamic drain threshold voltage; and a sample-and-hold circuit, the sample-and-hold circuit being configured to sample and hold the drain voltage during the current cycle of the synchronous rectifier switching transistor to provide the dynamic drain threshold voltage, the sample-and-hold circuit being further configured to sample the drain voltage at a sampling time, the sampling time being a function of a previous cycle of the synchronous rectifier switching transistor.

[0009] According to a second aspect of the present disclosure, a synchronous rectifier controller is provided, comprising: a differential amplifier configured to drive a gate voltage of a synchronous rectifier switching transistor during an regulated portion of a current cycle of the synchronous rectifier switching transistor, the differential amplifier responding to a difference between a drain voltage of the synchronous rectifier switching transistor and a dynamic drain threshold voltage; and a timing analysis circuit configured to adjust the dynamic drain threshold voltage based on a comparison of a duration of an regulated portion of a previous cycle of the synchronous rectifier switching transistor with a threshold delay.

[0010] According to a third aspect of the present disclosure, a method for controlling the gate voltage of a synchronous rectifier switching transistor is provided, the method comprising: adapting a dynamic drain threshold voltage in response to a previous cycle of the synchronous rectifier switching transistor; and during the on-time in a current cycle of the synchronous rectifier switching transistor, responding to the drain voltage of the synchronous rectifier switching transistor rising to equal the dynamic drain voltage by controlling the gate voltage of the synchronous rectifier switching transistor to maintain the drain voltage of the synchronous rectifier switching transistor equal to the dynamic drain threshold voltage.

[0011] By reading the following specific embodiments, these and other aspects of the present invention will be more fully understood. When reading the following description of specific exemplary embodiments in conjunction with the accompanying drawings, other aspects, features and embodiments will become apparent to those of ordinary skill in the art. Although features can be discussed relative to certain embodiments and the following drawings, all embodiments may include one or more of the advantageous features discussed herein. In other words, although one or more embodiments may be discussed as having certain advantageous features, one or more of such features may also be used according to the various embodiments discussed herein. In a similar manner, although exemplary embodiments may be discussed as equipment, system or method embodiments below, it should be understood that such exemplary embodiments may be implemented in various equipment, systems and methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A flyback converter including a secondary side controller configured to regulate a drain voltage of a synchronous rectifier switching transistor equal to a dynamic drain threshold voltage during a regulated portion of an on-time of the synchronous rectifier switching transistor is shown according to one aspect of the present disclosure.

[0013] Figure 2An SR controller according to one aspect of the present disclosure is shown that samples the drain voltage as a percentage of the on-time of the previous cycle of the SR switch transistor to provide a dynamic drain threshold voltage.

[0014] Figure 3 Shows Figure 2 Some operating waveforms of the SR controller during normal operation (no sudden load transients).

[0015] Figure 4 Shows Figure 2 Some operating waveforms of SR controllers respond to sudden load transients.

[0016] Figure 5 An SR controller according to one aspect of the present disclosure is shown that compares a regulated portion of a previous cycle of an SR switch transistor to a threshold delay to adjust a dynamic drain threshold voltage in a current cycle of the SR switch transistor.

[0017] Figure 6 An SR controller according to one aspect of the present disclosure is shown that samples the drain voltage at a sampling time during a current cycle to provide a dynamic drain threshold voltage based on a comparison of the gate voltage during a previous cycle with a threshold gate voltage.

[0018] Figure 7 Shows Figure 6 Some exemplary waveforms of an SR controller.

[0019] Embodiments of the present disclosure and their advantages are best understood by referring to the following detailed description.It should be appreciated that like reference numerals are used to identify like elements shown in one or more of the figures of the drawings. DETAILED DESCRIPTION

[0020] The present invention provides a flyback converter in which a secondary side SR controller uses feedback to control the gate voltage of the SR switching transistor in order to regulate its drain voltage. Figure 11 shows an exemplary flyback converter 100 with a gate voltage regulating secondary side SR controller (U2) 105. The flyback converter 100 is powered by a rectified input voltage Vin, such as generated by a diode bridge (not shown) that rectifies an AC voltage from an AC mains. The primary side controller U1 controls the cycle of the power switch transistor S1 to regulate the output voltage V_OUT supplied to the load. When the primary side controller U1 turns on the power switch transistor S1, the primary winding current is conducted through the primary winding T1 of the transformer T. When the sense resistor voltage across the sense resistor (not shown) at the drain of the power switch transistor S1 reaches a desired peak value (Vipk), the primary side controller U1 turns off the power switch transistor S1.

[0021] The SR controller 105 detects whether the power switch transistor SW is turned on or off by monitoring the drain-to-source voltage Vds on the SR switch transistor. To perform this monitoring, the SR controller 105 has a drain monitoring terminal SR_D and a source monitoring terminal SR_S. In addition, the SR controller 105 includes a gate terminal SR_G, which is connected to the gate of the SR switch transistor to control whether the SR switch transistor is turned on or off. In response to detecting that the power switch transistor S1 is turned on, the SR controller 105 maintains the SR switch transistor off to prevent the secondary winding current from flowing in the secondary winding T2 of the transformer T. In response to detecting that the power switch transistor S1 is turned off, the SR controller 105 turns on the SR switch transistor to allow the secondary winding current to flow and charges the output capacitor Cout with the output voltage. In an alternative embodiment, instead of monitoring the drain-to-source voltage of the SR switch transistor to determine the switching state of the power switch transistor, the SR controller 105 can instead receive the on or off state of the power switch transistor S1 through an isolation channel (such as an optocoupler).

[0022] The voltage pre-drop problem for CCM and DCM operation is solved by adaptively adjusting the drain voltage. With respect to this adjustment, it should be noted that there are two conflicting issues that should be resolved. For example, with respect to reducing the conduction losses (Rds on-resistance) in the SR switch transistor, it is best not to adjust the drain voltage but to drive the gate voltage of the SR switch transistor so that it is in saturation throughout the SR switch transistor on-time (transformer reset time Trst). However, in the case where the gate voltage is relatively high, common conduction losses (switching losses) will occur during CCM operation because it will take longer to turn off the SR switch transistor in response to the turning on of the power switch transistor. In contrast, if the drain voltage of the SR switch transistor is adjusted by a feedback-controlled reduction of the gate voltage of the SR switch transistor, the common conduction losses are reduced. It is therefore advantageous to leave the drain voltage unregulated during the initial portion of the SR switch transistor on-time and then to regulate the drain voltage during the final portion of the SR switch transistor on-time. The regulated portion should not be too short, or the gate voltage is not sufficiently reduced at the end of the SR switch on-time, resulting in unacceptable common conduction losses. Conversely, if the conditioned portion is too long, the conduction losses may be unacceptable.Therefore, there is an optimal duration for the conditioned portion that achieves the desired goal of reducing common conduction losses without causing unacceptable conduction losses.

[0023] However, the prior art does not achieve a "just right" duration for the final regulated portion. For example, a fixed drain threshold voltage is conventionally used to determine when the drain voltage regulation begins. But the drain voltage behavior during the unregulated portion depends on the load. At relatively high loads (such as for supporting a fast charging mode), the flyback converter is operated in CCM, so that the drain voltage is more negative during the unregulated portion. In contrast, the flyback converter is operated in DCM during the period of lower load, so that the drain voltage is less negative during the unregulated portion. Since the drain voltage is less negative during DCM operation, the negative value of the drain threshold voltage should also be less, otherwise the regulated portion becomes too long. But this relatively large value of the drain threshold voltage is not suitable for CCM operation, because the drain voltage may never rise to the drain threshold voltage that triggers the drain voltage regulation. In this case, the gate voltage will be too high at the end of the SR switch transistor on time, causing common conduction losses to occur. The solution would be to reduce the drain threshold voltage, but the regulation time becomes too long during DCM operation, causing conduction losses to occur.

[0024] To address these issues, a dynamic drain threshold voltage is utilized that is adjusted in response to drain voltage adjustments in previous SR switch transistor cycles. As time continues, each current SR switch transistor cycle becomes a previous SR switch transistor cycle for a subsequent SR switch transistor cycle. The following discussion will assume that the dynamic drain threshold voltage is adjusted for the current SR switch transistor cycle based on adjustments in the immediately preceding SR switch transistor cycle, but it should be understood that historical SR switch transistor behavior can be averaged over several SR switch transistor cycles.

[0025] With respect to the drain voltage adjustment in the previous SR switch transistor on-time, several factors can be used to adjust the dynamic drain threshold voltage in the current SR switch transistor on-time. For example, the dynamic drain threshold voltage can be adjusted in response to the duration of the previous SR switch transistor on-time. If the current cycle is represented by an integer n, the on-time of the previous cycle can be represented by a variable Trst(n-1), where Trst(i) is the SR switch transistor on-time in its i-th cycle. Based on the duration, the drain voltage is then sampled during the on-time of the current cycle to form the dynamic drain threshold voltage of the current cycle. The sampling may be performed as a percentage of the SR switch on-time in the previous SR switch transistor cycle, which percentage represents the desired division between the initial unregulated portion and the final regulated portion of the SR switch transistor on-time. Note that the division should be such that the final regulated portion is neither too large nor too small. In one embodiment, the percentage of the SR switch transistor on-time occupied by the initial unregulated portion will be assumed to be greater than 50% (such as 67.5%). Then, a sampling time of the drain voltage in the current cycle will occur after a delay of 67.5% of Trst(n-1) after the turn-on of the SR switching transistor in the current cycle has expired. However, such a percentage is somewhat arbitrary and may be increased or decreased in alternative embodiments. For example, in alternative embodiments, the percentage of the initial unregulated portion of the SR switching transistor turn-on time may be adjusted based on operating conditions (such as switching frequency). Alternatively, the sampling time may be a constant time c that is shorter than the previous turn-on time, so that the sampling time will occur after a delay of Trst(n-1)-c after the turn-on of the SR switching transistor in the current (nth) cycle has expired.

[0026] exist Figure 2, which adjusts the dynamic drain threshold voltage based on the SR switch transistor on-time Trst(n-1) in the previous cycle of the SR switch transistor. The timer 215 times the desired delay as a function of Trst(n-1). In this embodiment, the desired delay is 67.5% of Trst(n-1), but other functions may be used, such as Trst(n-1)-c discussed previously. The sample-and-hold (S / H) circuit 210 samples the drain voltage at the expiration of the delay timed by the timer 215 to form the dynamic drain threshold voltage (Vds_ref) for the current switching cycle. When the drain voltage rises to equal the dynamic drain threshold voltage (Vds_ref) during the SR switch transistor on-time, the differential amplifier 205 begins to regulate the gate voltage Vg of the SR switch transistor in its current cycle. Prior to this time, the differential amplifier 205 acts as a gate driver, causing the SR switch transistor to be in saturation during the initial unregulated portion of the SR switch transistor on-time. But when the drain voltage rises to equal the dynamic drain threshold voltage, the differential amplifier 205 is used to control the gate voltage so that during the final regulated portion of the SR switch transistor on time, the drain voltage is regulated to equal the dynamic drain threshold voltage.

[0027] exist Figure 3, some operating waveforms of an SR controller 200 in one embodiment are shown, which adjusts the dynamic drain threshold voltage based on the SR switch transistor on time Trst(n-1) in the previous cycle of the SR switch transistor. The SR switch on time in the current switching cycle starts at time t1. Then, a delay of 67.5% of Trst(n-1) expires at time t2, so that the drain voltage VDS is sampled by the S / H pulse in the sample-and-hold circuit. Therefore, the initial unregulated portion of the current SR switch transistor on time extends from time t1 to time t2. When the SR switch transistor is turned off, the final regulated portion extends from time t2 to time t3. The dynamic drain threshold voltage is equal to the value of the drain voltage at sampling time t2. During the final regulated portion, the drain voltage is regulated to be equal to the dynamic drain threshold voltage. Therefore, when the gate driver drives the SR switch transistor into a saturated state during this time, the resulting gate voltage is relatively high during the initial unregulated portion. But during the final regulated portion, the gate voltage continues to decrease due to the drain voltage regulation. Thus, the final regulated portion will be equal to (100–67.5)% or 32.5% of the SR switch transistor on time. This is very advantageous in ensuring that the duration of the final regulated portion is neither too long nor too short. In an alternative embodiment in which the sampling time is a fixed offset or constant value c relative to Trst(n-1), the final regulated portion will have a constant duration c, which is also advantageous in ensuring that the duration of the final regulated portion is neither too long nor too short. In order to overcome any differential amplifier offset and sample-and-hold offset, a fine-tunable offset can be added (or subtracted) from the sampled drain voltage to form a dynamic drain threshold voltage. For example, the dynamic drain threshold voltage (Vds_ref) can be equal to the sampled drain voltage minus the fine-tunable offset. The fine-tunable offset can be set during a test mode of operation, such as by burning a fuse in a one-time programmable memory.

[0028] In the event of sudden load changes or input voltage changes, the SR switch transistor on-time may vary significantly from one cycle to another. It is therefore possible that if the current switching cycle is significantly shorter than the previous switching cycle, basing the drain voltage regulation on the on-time of the previous cycle may cause the final regulated portion to become unacceptably short or may not even occur. For example, if the SR switch transistor on-time of the current cycle is less than the function of Trst(n-1) used to form the sampling time, the drain voltage regulation will not be triggered in the current switching cycle. Undesirable common conduction losses and / or damage to the flyback converter may then occur. To avoid these problems, the SR controller 200 can respond to transient occurrences by using a minimum sampling time. Figure 4Some exemplary operating waveforms of this occurrence are shown in FIG. The SR switch transistor on-time begins at time t1. At time t2, the minimum sampling time (Min ton) expires and the S / H pulse is triggered to sample the drain voltage at time t2. The drain voltage is then regulated to be equal to the sampled drain voltage during the final regulated portion of the off-time from time t2 to time t3. Therefore, despite the application of a transient load, the gate voltage is sufficiently reduced at time t3, but there is no danger of excessive breakdown.

[0029] Rather than using a function of the SR switch transistor on-time, the final regulated portion of the previous SR switch cycle can be measured and used to adjust the dynamic drain threshold voltage in the current switch cycle. Figure 5 , where a timing circuit (conceptually shown as a comparator) 505 compares the final regulated portion of the previous switching cycle to a threshold delay. If the final regulated portion is longer than the threshold delay, a timing analysis circuit 520 increases the digital value converted by a digital-to-analog converter (DAC) 515 to a dynamic drain threshold voltage Vds_ref. The differential amplifier 205 functions as discussed with respect to the SR controller 200 to regulate the drain voltage to be equal to the dynamic drain threshold voltage during the final regulated portion of the current switching cycle. Referring again to Figure 3 , it will be appreciated that increasing the dynamic drain threshold voltage shortens the final regulated portion of the current switching cycle. Conversely, if the final regulated portion of the previous cycle was too short, the timing analysis circuit 520 decreases the digital value and thereby decreases the dynamic drain threshold voltage. This decrease in the dynamic drain threshold voltage increases the duration of the final regulated portion of the current switching cycle. Therefore, feedback through the differential amplifier 205 in the SR controller 500 is used to adjust the final regulated portion to be equal to the threshold delay. This is very advantageous in ensuring that the final regulated portion is neither too long nor too short to provide the desired reduction in both common conduction losses and conduction losses.

[0030] In another embodiment, for Figure 6As shown in the SR controller 600 in FIG. 1 , the gate voltage during each SR switch transistor on time is compared to a threshold gate voltage value. The threshold is selected so that the resulting final regulated portion will have an appropriate duration. The following discussion will assume that the threshold gate voltage is 3V, but it should be understood that in alternative embodiments, it can be higher or lower than this exemplary threshold. Comparator 610 compares the gate voltage to the threshold gate voltage during each SR switch transistor on time. The sampling time of the drain voltage is a dynamic value (Tsamp) adjusted by the dynamic timer 605 based on the comparison in the comparator 610. If the comparison indicates that the gate voltage is reduced to below the threshold gate voltage during the final regulated portion of the previous switching cycle, the previous switch is considered to be a successful switch, so that the dynamic timer 605 reduces the sampling time. The sample and hold circuit 210 functions as discussed with respect to the SR controller 200 to sample the drain voltage at the adjusted sampling time to obtain a dynamic drain threshold voltage. Similarly, the differential amplifier 205 also functions as discussed with respect to the SR controller 200 to regulate the drain voltage to be equal to the dynamic drain threshold voltage during the final regulated portion of the current SR switch transistor on-time. If the comparison made by the comparator 610 indicates that the gate voltage did not decrease below the gate threshold voltage during the SR switch transistor on-time of the previous switching cycle, the dynamic timer 605 reduces the sampling time to provide a longer final regulated portion of the current SR switch transistor on-time. Referring again to Figure 1 It should be understood that SR controller 105 is a general representation of SR controllers 200 , 500 , and 600 .

[0031] exist Figure 7 Some exemplary operating waveforms of the SR controller 600 are shown in FIG. 1 . The first switching cycle begins by turning on the SR switching transistor at time t1. The initial unregulated portion ends at time t2 with a sampling S / H pulse for sampling the drain voltage. The drain voltage is then regulated at the sampling level for the final regulated portion extending from time t2 to time t3, when the SR switching transistor on time ends. From time t2 to time t3, the gate voltage remains above the desired level, so the sampling time is reduced for the subsequent switching cycle starting at time t4. The initial regulated portion of this second switching cycle extends from time t4 to time t5. The final regulated portion extends from time t5 to time t6. Comparing the first switching cycle and the second switching cycle, it can be seen that the delay between time t5 and t6 is reduced compared to the delay between time t2 and t3. This is beneficial because the final regulated portion of the first switching cycle was once undesirably long, which can result in conduction losses. These losses are reduced in the second switching cycle.

[0032] The third switching cycle begins at time t7 and has an initial unregulated portion from time t7 to time t8. The final regulated portion of the third switching cycle extends from time t8 to time t9. However, since the gate voltage has not decreased below the gate threshold voltage, the sampling time is reduced for the fourth switching cycle that begins at time t10. The initial unregulated portion of the fourth switching cycle extends from time t10 to time t11. The final regulated portion of the fourth switching cycle extends from time t11 to time t12. Comparing the third switching cycle and the fourth switching cycle, it can be seen that the final regulated portion of the fourth switching cycle increases compared to the final regulated portion in the third switching cycle. This is advantageous because the gate voltage is not sufficiently reduced during the final regulated portion of the third switching cycle, which can result in common conduction losses. However, the gate voltage is reduced to a greater extent in the final regulated portion of the fourth switching cycle, thereby reducing the possibility of any common conduction losses.

[0033] Those skilled in the art will now appreciate that, without departing from the scope of the present disclosure, various modifications, substitutions and changes may be made to the materials, devices, configurations and methods of use of the apparatus of the present invention. In view of this, the scope of the present disclosure should not be limited to the scope of the specific embodiments shown and described herein, as they are only some examples thereof, but should be fully commensurate with the scope of the claims appended hereto and their functional equivalents.

Claims

1. A synchronous rectifier controller for a flyback converter, the synchronous rectifier controller comprising: a differential amplifier configured to drive a gate voltage of a synchronous rectifier switching transistor during a regulated portion of a current cycle of the synchronous rectifier switching transistor, the differential amplifier being responsive to a difference between a drain voltage of the synchronous rectifier switching transistor and a dynamic drain threshold voltage; as well as a sample-and-hold circuit configured to sample and hold the drain voltage during the current cycle of the synchronous rectifier switching transistor to provide the dynamic drain threshold voltage, the sample-and-hold circuit further configured to sample the drain voltage at a sampling time that is a function of a previous cycle of the synchronous rectifier switching transistor.

2. The synchronous rectifier controller according to claim 1 , further comprising: A timer configured to time an on-time of the synchronous rectifier switching transistor in the previous cycle, wherein the function of the previous cycle is a percentage of the on-time.

3. The synchronous rectifier controller according to claim 1 , further comprising: A timer is configured to time an on-time of the synchronous rectifier switching transistor in the previous cycle, wherein the function of the previous cycle is a difference between the on-time and a constant value. The synchronous rectifier controller of claim 2 , wherein the percentage is greater than 50%.

5. The synchronous rectifier controller according to claim 1 , further comprising: a dynamic timer configured to adjust the sampling time in response to whether the gate voltage of the synchronous rectifier switching transistor during the previous cycle was less than a threshold gate voltage, wherein the function of the previous cycle was a comparison that the gate voltage of the synchronous rectifier switching transistor was less than the threshold gate voltage.

6. The synchronous rectifier controller according to claim 5, further comprising: A comparator is configured to compare the gate voltage of the synchronous rectifier switching transistor with the threshold gate voltage, wherein the dynamic timer is configured to increase the sampling time when the output signal of the comparator indicates that the gate voltage of the synchronous rectifier switching transistor is less than the threshold gate voltage. 7 . The synchronous rectifier controller of claim 6 , wherein the dynamic timer is further configured to reduce the sampling time when the output signal of the comparator indicates that the gate voltage of the synchronous rectifier switching transistor is not less than the threshold gate voltage.

8. The synchronous rectifier controller of claim 7, wherein the threshold gate voltage is 3V.

9. A synchronous rectifier controller, comprising: a differential amplifier configured to drive a gate voltage of a synchronous rectifier switching transistor during a regulated portion of a current cycle of the synchronous rectifier switching transistor, the differential amplifier being responsive to a difference between a drain voltage of the synchronous rectifier switching transistor and a dynamic drain threshold voltage; as well as A timing analysis circuit is configured to adjust the dynamic drain threshold voltage based on a comparison of a duration of an adjusted portion of a previous cycle of the synchronous rectifier switching transistor to a threshold delay.

10. The synchronous rectifier controller according to claim 9, further comprising: A digital-to-analog converter is used to convert the digital value from the timing analysis circuit into the dynamic drain threshold voltage.

11. The synchronous rectifier controller of claim 9, wherein the timing analysis circuit is further configured to increase the dynamic drain threshold voltage in response to a duration of the regulated portion of the previous cycle of the synchronous rectifier switching transistor being greater than the threshold delay.

12. The synchronous rectifier controller of claim 11, wherein the timing analysis circuit is further configured to reduce the dynamic drain threshold voltage in response to a duration of the regulated portion of the previous cycle of the synchronous rectifier switching transistor being less than the threshold delay.

13. The synchronous rectifier controller of claim 12, wherein the threshold delay is a constant.

14. The synchronous rectifier controller of claim 12 wherein the threshold delay is a variable delay.

15. A method for controlling a gate voltage of a synchronous rectifier switching transistor, the method comprising: adapting a dynamic drain threshold voltage in response to a comparison of a duration of an adjusted portion of a previous cycle of the synchronous rectifier switching transistor and a threshold delay; as well as During the on-time in the current cycle of the synchronous rectifier switching transistor, the drain voltage of the synchronous rectifier switching transistor is maintained equal to the dynamic drain threshold voltage by controlling the gate voltage of the synchronous rectifier switching transistor in response to the drain voltage of the synchronous rectifier switching transistor rising to be equal to the dynamic drain threshold voltage.

16. The method according to claim 15, further comprising: measuring an on-time of the synchronous rectifier switching transistor during the previous cycle of the synchronous rectifier switching transistor to provide a measured on-time; as well as During the on-time in the current cycle of the synchronous rectifier switching transistor, the drain voltage of the synchronous rectifier switching transistor is sampled at a measured percentage of the on-time to provide the dynamic drain threshold voltage.

17. The method according to claim 15, further comprising: measuring an on-time of the synchronous rectifier switching transistor during the previous cycle of the synchronous rectifier switching transistor to provide a measured on-time; as well as During the on-time in the current cycle of the synchronous rectifier switching transistor, the drain voltage of the synchronous rectifier switching transistor is sampled at a sampling time equal to a difference between the measured on-time and a constant value to provide the dynamic drain threshold voltage.

18. The method according to claim 15, further comprising: timing an adjusted portion of an on-time of the synchronous rectifier switching transistor during the previous cycle of the synchronous rectifier switching transistor to provide a measured adjusted portion; adjusting the sampling time based on a measured difference between the adjusted portion and the threshold delay to provide an adjusted sampling time; as well as During the on-time in the current cycle of the synchronous rectifier switching transistor, the drain voltage of the synchronous rectifier switching transistor is sampled at the adjusted sampling time to provide the dynamic drain threshold voltage.

19. The method according to claim 15, further comprising: adjusting a sampling time based on a comparison of the gate voltage of the synchronous rectifier switching transistor during an on-time of the synchronous rectifier switching transistor during the previous cycle of the synchronous rectifier switching transistor and a threshold gate voltage to provide an adjusted sampling time; as well as During the on-time in the current cycle of the synchronous rectifier switching transistor, the drain voltage of the synchronous rectifier switching transistor is sampled at the adjusted sampling time to provide the dynamic drain threshold voltage.

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