Method and apparatus for timing signal calibration of a memory device

Abstract

This application relates to timing signal calibration for memory devices. In some memory devices, operations for accessing memory cells may be performed at a timing that is asynchronous with an input signal. To support asynchronous timing, a timing signal generation component of the memory device may include a delay component that supports generating a timing signal having an aspect of being delayed relative to the input signal. The delay component may have characteristics that are sensitive to manufacturing or operational variability, such that the timing signal may also be affected by this variability. According to an example as disclosed herein, a memory device may include a delay component associated with access operation timing signal generation, the delay component being configured to be selectively enabled or disabled based on a calibration operation of the memory device, which may improve the memory device's ability to account for various sources of timing signal variability.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 891,601, titled "Timing Signal Calibration for Memory Devices," filed by Kim on June 3, 2020, which is assigned to the assignee hereof and is hereby incorporated by reference in its entirety.

[0003] The technical field relates to timing signal calibration for memory devices. BACKGROUND OF THE INVENTION

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, often represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states, and any one of the two states can be stored. To access the stored information, a component can read or sense at least one of the stored states in the memory device. To store information, a component can write or program a state in the memory device.

[0005] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), spin-transfer torque memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. A non-volatile memory such as FeRAM can maintain its stored logical state for a long time even in the absence of an external power supply. A volatile memory device such as DRAM may lose its stored state when disconnected from an external power supply. SUMMARY OF THE INVENTION

[0006] A method is described. The method can include: sequentially processing a first timing signal through each of a first plurality of delay components of a memory device to generate a plurality of delayed timing signals, each delayed timing signal corresponding to an output of a respective one of the first plurality of delay components; comparing a second timing signal with each of a plurality of reference signals, each reference signal of the plurality of reference signals being at least partially based on a respective one of the plurality of delayed timing signals; and selectively enabling or disabling a second plurality of delay components configured to generate an access operation timing signal of the memory device at least partially based on the comparison.

[0007] Describe a device. The device may include: an array of memory cells; a timing calibration component including a first plurality of delay components configured to generate a plurality of delayed timing signals, each delayed timing signal corresponding to an output of a respective delay component among the first plurality of delay components, and a comparison component configured to generate a plurality of delay configuration signals, each delay configuration signal being generated at least in part based on comparing a second timing signal with a respective one of a plurality of reference signals, each reference signal among the plurality of reference signals being at least in part based on a respective one of the plurality of delayed timing signals; and an access timing component coupled to the memory cell array and the timing calibration component, the access timing component may include a second plurality of delay components configured to generate an access operation timing signal to access the memory cell array, wherein each delay component among the second plurality of delay components is configured to be selectively enabled or disabled at least in part based on the plurality of delay configuration signals.

[0008] Describe another device. The device may include: an array of memory cells; a column decoder coupled to the memory cell array and configured to activate columns of the memory cell array at least in part based on a column select signal; a read latch coupled to the memory cell array and configured to latch a result of accessing memory cells of the activated columns at least in part based on a read trigger signal; and a signal generator coupled to the column decoder and the read latch, the signal generator being configured to generate a read trigger signal having a timing relative to the column select signal, the timing being at least in part based on selectively enabling or disabling a plurality of delay components according to a delay value. Brief Description of the Drawings

[0009] Figure 1 Illustrate an example of a system that supports calibration of timing signals for a memory device according to an example disclosed herein.

[0010] Figure 2 Illustrate an example of a memory die that supports calibration of timing signals for a memory device according to an example disclosed herein.

[0011] Figure 3 Illustrate a block diagram of a timing circuit that supports calibration of timing signals for a memory device according to an example disclosed herein.

[0012] Figure 4A And 4B Illustrate examples of a calibration input signal generator and a calibration signal generator that respectively support calibration of timing signals for a memory device according to an example disclosed herein.

[0013] Figure 5A And 5BDescribe examples of timing diagrams that support timing signal calibration for a memory device according to examples disclosed herein.

[0014] Figure 6 Describe examples of access operation timing signal generators that support timing signal calibration for a memory device according to examples disclosed herein.

[0015] Figure 7 Show a block diagram of a memory device that supports timing signal calibration for a memory device according to aspects of the present disclosure.

[0016] Figure 8 Show a flowchart of one or more methods that support timing signal calibration for a memory device according to examples disclosed herein. Detailed Description

[0017] In some memory devices, accessing a memory cell may involve multiple operations controlled by multiple signals. Multiple operations may be performed at a timing generated from input signals. Thus, at least some internal operations may occur at a different time than a rising edge transition or a falling edge transition of an input signal such as a clock signal or a command signal. Such operations may be triggered or otherwise supported by a core timing signal of the memory device, which may be generated by a timing signal generation component of the memory device. To support the timing of multiple signals, the timing signal generation component of the memory device may include a delay component that supports generating a timing signal having aspects of delay or timing relative to an input signal, which may be received from a host device or otherwise related to signaling from a host device. Such a timing signal generated by a delay element may be referred to as an asynchronous timing signal. In one example, the delay component may support generating a read strobe signal that may trigger or initiate latching information detected by a sense amplifier or transferring information to an input / output component of the memory device, among other purposes. The read strobe signal may have a transition (e.g., a rising edge, a falling edge) that is delayed relative to a transition of an input signal (e.g., a column select signal, a column activation signal), or may have a pulse width (e.g., a duration between a rising edge and a falling edge) that is at least partially based on the delay element.

[0018] A delay component may include various circuit elements that impose a delay between a transition of an input signal and a corresponding transition of an output signal. For example, a delay component may include one or more gate delays or gate delay components, which may be associated with a duration between an input signal of a component crossing a threshold voltage and an output signal of the component crossing the threshold voltage. The gate delay components may be linked together in series, and this configuration of components may be referred to as a delay chain. In some instances (e.g., to support a delay between a rising edge of an input signal and a rising edge of an output signal), the delay chain may include an even number of inverters connected in series. However, other configurations may be used to support timing signal generation. In some instances, the delay component may have timing characteristics that are sensitive to manufacturing variability (e.g., process variability) or operating condition variability (e.g., voltage variability, temperature variability), such that asynchronous timing signals may also be affected by this variability. The variability of the asynchronous timing signals may be associated with adverse performance of a memory device, including reduced read margins, increased read or write errors, extended latencies to support timing or signaling uncertainties, etc.

[0019] According to an example as disclosed herein, a memory device may include a delay component associated with access operation timing signal generation, the delay component being configured to be selectively enabled or disabled (e.g., bypassed) based on a calibration operation of the memory device. In some instances, the calibration operation may include sequentially processing a first timing signal (e.g., a calibration timing signal) through each of a first set of delay components to generate a set of delayed timing signals. Different delays associated with respective ones of the set of delayed timing signals may support identification of which or how many of a second set of delay components should be enabled to support access operation timing signals of the memory device. Such selective enabling or disabling of the delay components may improve the ability of the memory device to account for manufacturing variability, operating condition variability, or other phenomena including aspects related to asynchronous timing signal generation.

[0020] The features of the present disclosure were initially described in the context of a memory system and die, as referenced Figure 1 and 2 described. The features of the present disclosure are described in the context of timing signal calibration circuitry and operations, and timing signal generation utilizing such calibration circuitry and operations, as referenced Figure 3 through 5 described. These and other features of the present disclosure are further illustrated by and described with reference to device schematics and flowcharts related to timing signal calibration for a memory device as referenced Figure 6 and 7 described.

[0021] Figure 1Describe an example of a system 100 that supports timing signal calibration for a memory device according to an example disclosed herein. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 that couple the host device 105 to the memory device 110. The system 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0022] The system 100 may include portions of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, and the like. The memory device 110 may be a component of a system that is operable to store data for one or more other components of the system 100.

[0023] At least a portion of the system 100 may be an example of the host device 105. The host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or some other fixed or portable electronic device, among other examples. In some examples, the host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functions of an external memory controller 120. In some examples, the external memory controller 120 may be referred to as the host or host device 105.

[0024] The memory device 110 may be an independent device or component operable to provide a physical memory address / space that can be used or referenced by the system 100. In some examples, the memory device 110 may be configured to work with one or more different types of host devices. Signaling between the host device 105 and the memory device 110 may be operable to support one or more of the following: a modulation scheme for modulating signals, various pin configurations for transmitting signals, various form factors for the physical packages of the host device 105 and the memory device 110, clock signaling and synchronization between the host device 105 and the memory device 110, timing conventions, or other factors.

[0025] The memory device 110 is operable to store data for components of the host device 105. In some instances, the memory device 110 can act as a slave device of the host device 105 (e.g., respond to and execute commands provided by the host device 105 via the external memory controller 120). Such commands can include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0026] The host device 105 can include one or more of the external memory controller 120, the processor 125, the basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of the host device can be coupled to each other using the bus 135.

[0027] The processor 125 is operable to provide control or other functionality for at least part of the system 100 or at least part of the host device 105. The processor 125 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or a combination of these components. In such instances, the processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a system-on-chip (SoC), among other examples. In some instances, the external memory controller 120 can be implemented by or as part of the processor 125.

[0028] The memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N), and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 can be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sections), where each memory cell is operable to store at least one bit of data. A memory device 110 that includes two or more memory dies can be referred to as a multi-die memory or a multi-die package, or a multi-chip memory or a multi-chip package.

[0029] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be operable to receive, transfer, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be operable to communicate with the external memory controller 120, one or more memory dies 160, or one or more of the processors 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0030] The local memory controller 165 (e.g., local to the memory die 160) may be operable to control the operation of the memory die 160. In some instances, the local memory controller 165 may be operable to communicate with the device memory controller 155 (e.g., receive or transfer data or commands or both). In some instances, the memory device 110 may not include the device memory controller 155, and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125 or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165 or both may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transferring signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transferred, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165 or both.

[0031] The external memory controller 120 is operable to enable the communication of one or more of information, data, or commands between components of the system 100 or the host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may transform or translate the communications exchanged between the components of the host device 105 and the memory device 110. In some instances, the external memory controller 120 or other components of the system 100 or the host device 105, or its functionality described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, software, or some combination thereof implemented by the processor 125, or other components of the system 100 or the host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some instances, the external memory controller 120 or its functionality described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0032] Components of the host device 105 may exchange information with the memory device 110 using one or more channels 115. The channels 115 are operable to support the communication between the external memory controller 120 and the memory device 110. Each channel 115 may be an example of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. The signal path may be an example of a conductive path operable to carry signals. For example, the channel 115 may include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. The pins may be examples of conductive input or output points of devices of the system 100, and the pins may be operable to act as part of the channel.

[0033] The channels 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, the channels 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some instances, single data rate (SDR) signaling or double data rate (DDR) signaling may be used to transmit signaling over the channels 115. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock period (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock period (e.g., on the rising and falling edges of the clock signal).

[0034] In some instances, operations for accessing memory array 170 may be triggered or otherwise supported by core timing signals of memory device 110, which may be generated by timing signal generation components of memory device 110 (e.g., device memory controller 155, local memory controller 165). To support non-simultaneous timing, the timing signal generation components of memory device 110 may include delay components that support generating timing signals having aspects of delay or timing relative to an input signal, which may be received from host device 105 or otherwise related to signaling from host device 105 (e.g., command signals received on CA channel 186). In one instance, the timing signal generation component may generate a read strobe signal that may trigger or initiate latching information detected by a sense amplifier or read latch, or passing the information to an input / output component of the memory device (e.g., latching the information for output on DQ channel 190 or a related signal path of memory device 110).

[0035] In some instances, the delay components may have characteristics that are sensitive to manufacturing variability (e.g., process variability) or operating condition variability (e.g., voltage variability, temperature variability), such that the core timing signals may also be affected by such variability. The variability of the core timing signals may be associated with adverse performance of memory device 110 or the overall system 100, including reduced read margins, increased read or write errors, extended latencies to support timing or signaling uncertainties, etc. According to an example as disclosed herein, memory device 110 may include delay components associated with access operation timing signal generation that are configured to be selectively enabled or disabled (e.g., bypassed) based on a calibration operation of memory device 110. The selective enabling or disabling of such delay components may improve the ability of memory device 110 to account for manufacturing variability, operating condition variability, or other phenomena.

[0036] Figure 2 An example of memory die 200 supporting timing signal calibration for a memory device according to an example as disclosed herein is illustrated. Memory die 200 may be a reference Figure 1An example of the described memory die 160. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmable to store different logical states (e.g., programmed to one of a set of two or more possible states). For example, the memory cell 205 may be operable to store one bit of information (e.g., a logic 0 or a logic 1) at a time. In some examples, the memory cell 205 (e.g., a multi-level memory cell) may be operable to store more than one bit of information (e.g., logic 00, logic 01, logic 10, logic 11) at a time. In some examples, the memory cells 205 may be arranged in an array, such as the memory array 170 described with reference to Figure 1 the described memory array 170.

[0037] The memory cell 205 may store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor that includes a dielectric material to store charge representing a programmable state. In other memory architectures, other storage devices and components are possible. For example, non-linear dielectric materials may be used. The memory cell 205 may include logic storage components, such as a capacitor 230 and a switching component 235. The capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. The node of the capacitor 230 may be coupled to a voltage source 240, which may be a cell plate reference voltage, such as Vpl, or may be ground, such as Vss.

[0038] The memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digit lines 215), which are arranged in a pattern, such as a grid pattern. The access lines may be conductive lines coupled to the memory cells 205 and may be used to perform access operations on the memory cells 205. In some examples, the word lines 210 may be referred to as row lines. In some examples, the digit lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines or the like may be interchanged without affecting understanding or operation. The memory cells 205 may be located at the intersections of the word lines 210 and the digit lines 215.

[0039] Operations such as reading and writing may be performed on the memory cells 205 by activating or selecting access lines, such as one or more of the word lines 210 or the digit lines 215. By biasing the word lines 210 and the digit lines 215 (e.g., applying a voltage to the word lines 210 or the digit lines 215), a single memory cell 205 may be accessed at their intersection. The intersection of the word lines 210 and the digit lines 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of the memory cell 205.

[0040] Access to the memory cells 205 can be controlled by the row decoder 220 or the column decoder 225. For example, the row decoder 220 can receive a row address from the local memory controller 260 and activate the word line 210 based on the received row address. The column decoder 225 can receive a column address from the local memory controller 260 and can activate the digit line 215 based on the received column address.

[0041] Selecting or deselecting the memory cells 205 can be achieved by activating or deactivating the switch component 235 using the word line 210. The capacitor 230 can be coupled to the digit line 215 using the switch component 235. For example, when the switch component 235 is deactivated, the capacitor 230 can be isolated from the digit line 215, and when the switch component 235 is activated, the capacitor 230 can be coupled to the digit line 215.

[0042] The word line 210 can be a wire that is in electronic communication with the memory cells 205 for performing access operations on the memory cells 205. In some architectures, the word line 210 can be coupled to the gate of the switch component 235 of the memory cells 205 and can be operative to control the switch component 235 of the memory cells. In some architectures, the word line 210 can be coupled to the node of the capacitor of the memory cells 205, and the memory cells 205 may not include a switch component.

[0043] The digit line 215 can be a wire that connects the memory cells 205 and the sense component 245. In some architectures, the memory cells 205 can be selectively coupled to the digit line 215 during a portion of an access operation. For example, the word line 210 and the switch component 235 of the memory cells 205 can be operative to couple and / or isolate the capacitor 230 of the memory cells 205 and the digit line 215. In some architectures, the memory cells 205 can be coupled to the digit line 215.

[0044] The sense component 245 can be operative to detect a state (e.g., charge) stored on the capacitor 230 of the memory cells 205 and determine the logic state of the memory cells 205 based on the stored state. The sense component 245 can include one or more sense amplifiers to amplify or otherwise transform a signal generated due to accessing the memory cells 205. The sense component 245 can compare the signal detected from the memory cells 205 with a reference 250 (e.g., a reference voltage). The detected logic state of the memory cells 205 can be provided as an output of the sense component 245 (e.g., to the input / output component 255) and can indicate the detected logic state to another component of the memory device that includes the memory die 200.

[0045] The local memory controller 260 may control access to the memory cells 205 through various components (e.g., row decoder 220, column decoder 225, sense component 245). The local memory controller 260 may be an example of the local memory controller 165 described in reference Figure 1 In some instances, one or more of the row decoder 220, column decoder 225, and sense component 245 may be in the same location as the local memory controller 260. The local memory controller 260 may operate to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information usable by the memory die 200, perform one or more operations on the memory die 200, and transfer data from the memory die 200 to the host device 105 based on the performance of the one or more operations. The local memory controller 260 may generate row signals and column address signals to activate the target word line 210 and the target digit line 215. The local memory controller 260 may also generate and control various voltages or currents used during the operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may be different for the various operations discussed in operating the memory die 200.

[0046] The local memory controller 260 may operate to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, the access operations may be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 may operate to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0047] The local memory controller 260 is operable to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During the write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logical state. The local memory controller 260 can identify the target memory cell 205 on which the write operation is to be performed. The local memory controller 260 can identify the target word line 210 and the target digit line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The local memory controller 260 can apply a specific signal (e.g., a write pulse) to the digit line 215 during the write operation to store a specific state (e.g., a charge) in the capacitor 230 of the memory cell 205. The pulse used as part of the write operation can include one or more voltage levels over a period of time.

[0048] The local memory controller 260 is operable to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cells 205 of the memory die 200 can be determined. The local memory controller 260 can identify the target memory cell 205 on which the read operation is to be performed. The local memory controller 260 can identify the target word line 210 and the target digit line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 can transfer a signal to the sensing component 245 in response to a biased access line. The sensing component 245 can amplify the signal. The local memory controller 260 can activate the sensing component 245 (e.g., latch the sensing component), and thus compare the signal received from the memory cell 205 with the reference 250. Based on the comparison, the sensing component 245 can determine the logical state stored on the memory cell 205.

[0049] The access operation of the memory die 200 may be triggered or otherwise supported by a core timing signal of the memory die 200 or the memory device 110 that includes the memory die 200, and the core timing signal may be generated by a timing signal generation component of the memory die 200 or the associated memory device 110. In one example, the local memory controller 260 may include a timing signal generation component 265, but the timing signal generation component 265 may be included in other parts of the memory device 110, or distributed among multiple components of the memory device. In one example, the timing signal generation component 265 may generate a read strobe signal, which may be an example of an asynchronous timing signal for supporting (e.g., triggering, initiating) latching information detected by the sensing component 245 (e.g., the sense amplifier output of the sensing component 245), transferring the information to the input / output component 255, or latching the information of the input / output component 255 to a channel (e.g., DQ channel) shared with the host device 105, and other purposes. The timing signal generation component 265 may generate a read strobe signal that has a transition (e.g., rising edge, falling edge) with a transition delay relative to a second signal, such as a column select signal associated with the column decoder 225 selecting or activating a digit line 215. In some examples, the timing signal generation component 265 may generate a read pulse signal that has a pulse width (e.g., the duration between the rising edge and the falling edge) at least partially based on a delay element of the timing signal generation component 265.

[0050] The timing signal generation component 265 may have operating characteristics that are sensitive to manufacturing variability (e.g., process variability) or operating condition variability (e.g., voltage variability, temperature variability), such that the timing signals of the memory die 200 may also be affected by this variability. The variability of the timing signals may be associated with adverse performance of the memory die 200, or the memory device 110 or system that includes the memory die 200, including reducing read margins, increasing read or write errors, extending latencies that support timing or signaling uncertainties, etc. According to examples disclosed herein, the timing signal generation component 265 may include a delay component associated with access operation timing signal generation, and the delay component is configured to be selectively enabled or disabled (e.g., bypassed) based on a calibration operation. The selective enabling or disabling of such delay components may improve the ability of access operations performed on the memory die to be less dependent on manufacturing variability, operating condition variability, or other phenomena.

[0051] Figure 3Describe an example of a timing circuit 300 that supports timing signal calibration for a memory device according to an example disclosed herein. The timing circuit 300 may refer to the circuitry of the memory device 110 and may be a component of the device memory controller 155, the local memory controller 165, or the local memory controller 260, or other parts of the memory device 110 or the memory die 200. The timing circuit 300 includes a timing signal generation component 310 (e.g., an access timing component) configured to generate an access operation timing signal 330 at least in part based on one or more input signals 320. The timing signal generation component 310 may be an example of the timing signal generation component 265 described in reference Figure 2 above.

[0052] The access operation timing signal 330 may be used to trigger or initiate various access operations (e.g., asynchronous operations) of the memory device 110 or the memory die 200 that includes the timing circuit 300. In one example, the access operation timing signal 330 may be a read strobe signal that may be used to support (e.g., initiate, trigger) latching read data for output by the sense component 245 or the input / output component 255 or other read latches. However, in other examples of the described technology, the access operation timing signal 330 may refer to other types of timing or logic signals, including asynchronous timing or logic signals (e.g., asynchronous with respect to a clock signal, asynchronous with respect to a command signal), such as a read trigger signal, a signal for supporting operations such as: the row decoder 220 opening a row of memory cells 205, the column decoder 225 activating one or more columns of the memory cells 205, the sense component 245 generating or latching a sense signal, or the input / output component 255 latching or receiving an information exchange, and other operations.

[0053] The access operation timing signal 330 may be generated with various delays or durations relative to the one or more input signals 320, where the input signals 320 may include signals such as a clock signal, a command signal, or some other synchronization or sequencing signal output by the memory device 110. In some examples, the input signals 320 may be received directly or indirectly from the host device 105 (e.g., via the CK channel, via the CA channel, via the device memory controller 155). In some examples, the input signals 320 may be generated or forwarded by components of the memory device 110, which may or may not be based on another signal received from the host device 105.

[0054] The delay or duration of the access operation timing signal 330 relative to the input signal 320 can be generated by one or more delay components 315 of the timing signal generation component 310. In some instances, the duration of the delay (e.g., asynchronous delay) between the input signal 320 and the access operation timing signal 330 (e.g., between the rising or falling edge of the input signal 320 and the rising or falling edge of the access operation timing signal 330) can be at least partially based on one or more of the delay components 315. In some instances, the pulse width of the access operation timing signal 330 (e.g., the duration between the rising and falling edges of the access operation timing signal 330, the duration between the falling and rising edges of the access operation timing signal 330) can be at least partially based on one or more of the delay components 315. The delay components 315 can include components or circuitry, such as transistors, inverters, capacitors, resistors, gate delay components, or other components associated with the timing or duration of transitions or levels of input and output signals. In some cases, the delay components 315 can be configured in a delay chain (e.g., in series with each other). In some cases, each of the delay components 315 can have the same or similar delay (e.g., the same number of delay gates). Alternatively, the delay components 315 can be in parallel with each other (e.g., can have different delays), and the access operation timing signal 330 can be selected from the output of one of the delay components 315.

[0055] The operating characteristics of the delay components 315 or other components of the memory device 110 (e.g., other components of the timing signal generation component 310, other components of the memory die 200 configured to support access operations) can be affected by variability, such as variability due to manufacturing (e.g., process variability, manufacturing variability) or operating conditions (e.g., voltage variability, temperature variability, frequency variability), such that the access operation timing signal 330 can also be affected by this variability. For example, due to process or operating condition variability, the access operation timing signal 330 can have a longer or shorter delay relative to the input signal 320, or can have a longer or shorter pulse width, among other variabilities.

[0056] To reduce the sensitivity of the timing signal generation component 310 or other components or operations of the memory device 110 to processing or operational variability, the timing circuit 300 may include a calibration component 340 configured to selectively enable or disable one or more of the delay components 315 of the timing signal generation component 310. For example, the calibration component 340 may provide a calibration signal 360 (e.g., a delay configuration signal) to the delay component 315 or other support circuitry (e.g., a signal path selection component or circuitry) of the timing signal generation component 310 to enable (e.g., included in an access operation timing signal delay chain) or disable (e.g., bypassed from an access operation timing signal delay chain) the corresponding delay component 315. In various instances, the calibration component 340 may be co-located with the timing signal generation component 310 (e.g., in the memory die 200), or the calibration component 340 may be located in a different part of the memory device 110 (e.g., in the device memory controller 155).

[0057] In some instances, the calibration component 340 may be configured to sequentially process a calibration input signal 350 (e.g., an input signal, a timing signal) through a set of delay components (e.g., a set of delay components of the calibration component 340, which may be different from the delay component 315) to generate a set of delayed timing signals. Each of the delayed timing signals may have a different delay duration, and the corresponding timing signal may be compared directly or indirectly (e.g., at least partially based on an intermediate signal using the delayed timing signal) to another signal to evaluate a target delay duration or whether an existing delay duration should be extended (e.g., by enabling one or more disabled delay components 315) or shortened (e.g., by disabling one or more enabled delay components 315). In other words, the different delays associated with the corresponding delayed timing signals of the set of delayed timing signals of the calibration component 340 may support the identification or inference of which delay components 315 or how many delay components 315 in the timing signal generation component 310 should be enabled to support the timing signal generation component 310 in generating the access operation timing signal 330.

[0058] Selective enabling or disabling of the delay component 315 can improve the ability of the memory device to account for manufacturing variability, operating condition variability, or other phenomena. For example, when the access operation timing signal 330 refers to a read strobe signal, the pulse width or timing of the read strobe signal can be sensitive to manufacturing or operating variability of the memory device 110. If the pulse width of the read strobe signal is too short, or the read strobe signal otherwise transitions too quickly after the column select or activation signal with a duration, a read signal based on accessing the memory cell 205 may not be developed, which can be referred to as a setup margin failure or otherwise associated with a setup margin failure. If the pulse width of the read strobe signal is too long, or the read strobe signal otherwise transitions without meeting a hold margin relative to the first column select or activation signal, a second column select or activation signal may be issued before latching the signaling or information based on accessing the first memory cell 205 associated with the first column select or activation signal. In some such cases, the logical value associated with accessing the first memory cell 205 may be lost, or a different memory cell 205 may have been accessed (e.g., as associated with the second column select or activation signal), which can be referred to as a hold margin failure or otherwise associated with a hold margin failure. Thus, to support proper access of the memory cell 205 for a read operation, aspects of the read strobe signal can be adjusted to account for manufacturing or operating variations and other reasons.

[0059] In some instances of generating the read strobe signal, the calibration component 340 can be configured to calibrate the timing signal generation component 310 (e.g., by selectively enabling or disabling the delay component 315) to generate a read strobe signal having a pulse that is equal to or otherwise at least partially based on the pulse width, or cycle time (e.g., periodicity) of a clock signal or other reference signal. The clock signal for this calibration can be sampled or otherwise received at an instance that is independent of a particular access command, such that the access operation signal 33 itself is not generated based on the clock signal. Instead, the calibration component 340 can determine a calibration result from the received clock signal, where this result is stored or otherwise applied to multiple subsequent access operations to generate subsequent access operation timing signals 330.

[0060] In some instances, the calibration timing signal generation component 310 may be selectively enabled or disabled based on the delay component 315 to time the access operation timing signal 330 relative to the column select or activation signal generation. In some instances, a clock signal or other reference signal may be provided as the calibration input signal 350 to the calibration component 340 such that the calibration component 340 generates a calibration signal 360 based on which delay components 315 or a quantity of delay components 315 should be enabled or disabled to generate a read strobe signal (e.g., the access operation timing signal 330) having a desired pulse width or duration. This timing calibration may be at least partially based on performing a calibration operation that uses delay components of the same (e.g., having the same number or type of delay components) or different calibration components 340 as the delay component 315.

[0061] Thus, according to these and other instances, the timing signal generation component 310 may be configured to generate an access operation timing signal 330 having timing characteristics that are at least partially based on the selective enabling or disabling of the delay component 315, where this selective enabling or disabling is at least partially based on the calibration signal 360. In some instances, the timing signal generation component 310 may support generating the pulse width of the access operation timing signal 330 based at least partially on the selective enabling or disabling of a second plurality of delay components 315. Additionally or alternatively, the timing signal generation component 310 may support generating the timing or delay of the access operation timing signal 330 (e.g., the timing of the rising or falling edge relative to an input signal 320 such as a column select signal) based at least partially on the selective enabling or disabling of a second plurality of delay components 315.

[0062] The calibration operation using the calibration component 340 may be triggered or initiated based on various operations of the memory device 110 or the memory die 200. In some instances, the execution of the calibration operation may be initiated based at least partially on identifying an initial configuration operation (e.g., an initial mode register write operation performed after powering on the memory device 110) after powering on the memory device 110. In some instances, the execution of the calibration operation may be initiated based at least partially on identifying a change in the frequency set point of the memory device 110, which may be initiated by signaling received from the host device 105. Additionally or alternatively, the calibration operation of the calibration component 340 may be initiated based on other operating modes or detections, such as the detection of an assembly or facility operation, an identified change in operating conditions, an identified change in operating mode, an identified anomaly in access timing (e.g., the identification of a setup margin fault or a hold margin fault), or an identified error detection or error correction adjustment, and other conditions that may support dynamically adjusting the timing characteristics of the access operation timing signal 330 in response to various sources of variability or to otherwise account for various sources of variability.

[0063] Figure 4A and 4B illustrate examples of a calibration input signal generator 400 and a calibration signal generator 450 that respectively support timing signal calibration for a memory device according to examples disclosed herein. The calibration input signal generator 400 and the calibration signal generator 450 may be included in the calibration component 340 described in the reference Figure 3 The calibration signal generator 450 may support generating the signal CAL<0:2> as a single calibration signal 360-a or a set of calibration signals 360-a. The calibration input signal generator 400 may support generating the signals EN1 and EN2, which may be provided to the calibration signal generator 450 to generate one or more signals CAL<0:2>. Generating the signals EN1 and EN2 may be at least partially based on the signal CLK, which may be an example of a calibration input signal 350-a.

[0064] The calibration input signal generator 400 may be configured to support the calibration signal generator 450 in performing a calibration operation based on an initial configuration operation after powering on the memory device 110. For example, the signal PWRUP may be enabled when powering on the memory device 110, and the signal MRW may be enabled during a mode register write operation of the memory device 110. Thus, during an initial mode register write operation (e.g., an initial enabling of the signal MRW after enabling the signal PWRUP), the calibration input signal generator 400 may continue to generate the signals EN1 and EN2 (e.g., at least partially based on the switching signal EN). The calibration input signal generator 400 may also be configured to support the calibration signal generator 450 in performing a calibration operation based on a change in the frequency set point of the memory device 110. For example, the signal MDFSP may be enabled when the memory device 110 has been commanded with a frequency set point change or when the memory device 110 is otherwise performing a frequency set point change. Thus, during a frequency set point operation, the calibration input signal generator 400 may continue to generate the signals EN1 and EN2 (e.g., at least partially based on the switching signal EN).

[0065] Generating the signal EN1 may be at least partially based on providing the signal EN to a first D flip-flop (DFF) that is also fed by the clock signal CLK. The first DFF may introduce a delay relative to the signal EN when a state transition of the output of the first DFF is triggered by a transition of the clock signal CLK. The output of the first DFF may be fed through two inverters (e.g., delay inverters, gate delay components), which may introduce additional delay to generate the signal EN1 (e.g., the rising edge of the signal EN1).

[0066] The generated signal EN2 can be at least partially based on providing the output of the first DFF to two other DFFs that are also fed by the clock signal CLK. When the state transitions of the corresponding outputs of the other DFFs are triggered by transitions of the clock signal CLK, the other DFFs can introduce additional delays relative to the signal EN. The outputs of these DFFs can be fed, as shown, through a NOR gate and an inverter to generate the signal EN2 (e.g., the rising edge of the signal EN2), which can be delayed relative to the signal EN1. The signal EN2 can be fed back through the calibration input signal generator 400 to generate the falling edges of both the signal EN1 and the signal EN2.

[0067] The signals EN1 and EN2 can be provided to the calibration signal generator 450 to support the generation of the signal CAL<0:2>. For example, the duration between the rising edge of EN1 and the rising edge of EN2 can be approximately equal to the duration of one clock cycle (e.g., of the clock signal CLK), which may be insensitive or relatively insensitive to variations in the manufacturing or operating conditions of the calibration input signal generator 400. This duration between the rising edges of EN1 and EN2 can be related to the target duration or pulse width of the read strobe signal, and the calibration signal generator 450 can thus enable or disable each of the signals CAL<0:2> to support the timing signal generation assembly 310 in generating a read strobe signal having this duration or pulse width, or otherwise reduce variations in this target attributable to manufacturing or operating variability.

[0068] The calibration signal generator 450 can receive the signal EN1 (e.g., the timing signal, the calibration input signal 350), and process the signal EN1 through each of four delay components 455 (e.g., calibration delay components) as shown. Although four delay components 455 are shown in the calibration signal generator 450, the calibration signal generator of the calibration assembly 340 can include any number of delay components 455. In some instances, at least some of a quantity of delay components 455 can be associated with or correspond to a quantity of delay components 315 of the timing signal generation assembly 310 that are configured to be selectively enabled or disabled.

[0069] Each of the delay components 455 may be associated with a corresponding number of gate delays, such as a certain amount of inverters (e.g., delay inverters, gate delay components) or other delay components (e.g., 8-gate delay). A signal (e.g., default) through the first delay component 455-a may have a default delay, a signal (e.g., D0) through the second delay component 455-b may have the cumulative delay of two delay components (e.g., delay components 455-a and 455-b), a signal (e.g., D1) through the third delay component 455-c may have the cumulative delay of three delay components (e.g., delay components 455-a, 455-b, and 455-c), and a signal through the fourth delay (e.g., D2) may have the cumulative delay of all four delay components (e.g., delay components 455-a, 455-b, 455-c, and 455-d). The signals D0, D1, and D2 may be instances of delay timing signals respectively corresponding to the outputs of the respective delay components.

[0070] The signals D0, D1, and D2 may be provided to corresponding NAND gates, and each NAND gate is also provided with the inversion of the signal EN2 to generate the respective signals N0, N1, and N2. The signals N0, N1, and N2 may be processed by a glitch elimination circuit 460, which may include respective glitch elimination circuit paths through skewed delay components, inverters, and gates as shown, to generate the respective signals ND0, ND1, and ND2. However, in some instances, the glitch elimination circuit 460 may be omitted. The calibration signal generator 450 may also process the signal EN2 through skewed delay components and inverters as shown to generate the signal CONTROL. The skewed delay components and inverters for processing EN2 may introduce delays similar to those introduced by the respective processing paths of the glitch elimination circuit 460, which may help maintain similar processing delays between the signal EN2 and the signals N0, N1, and N2.

[0071] Each of the signals ND0, ND1, and ND2 may be provided to a corresponding DFF 465 that may be triggered by the signal CONTROL. Thus, each of the DFFs 465 may support comparing a second timing signal (e.g., CONTROL) with each of a set of reference signals (e.g., ND0, ND1, and ND2), where each reference signal in the set of reference signals is at least partially based on a corresponding one of a set of delayed timing signals (e.g., D0, D1, D2). In another instance, each of the DFFs 465 may support latching, storing, or outputting the state of each of a set of reference signals at least partially based on the second timing signal (e.g., triggered by the second timing signal). Thus, the DFFs 465 may be regarded as comparison components, latching components, or storage components that support evaluation signals with different timings or delays, where this evaluation is at least partially based on the target delay or pulse width used to generate the access operation timing signal 330.

[0072] The result of this comparison or latching can be fed through other inverters and NAND gates as shown to generate the signal CAL<0:2> (e.g., calibration signal 360-a), which can be provided to the timing signal generation component 310 to selectively enable one or more delay components 315. For example, the signal CAL<0> can support selectively including or bypassing the first delay component 315 in the delay chain of the timing signal generation component 310, the signal CAL<1> can support selectively including or bypassing the second delay component 315 in the delay chain, and the signal CAL<2> can support selectively including or bypassing the third delay component 315 in the delay chain. In some instances, the second delay component 455-b for processing the signal EN1 can have a delay equal to, equivalent to, or otherwise representative of the delay of the first delay component 315 (e.g., corresponding to the signal CAL<0>), the third delay component 455-c for processing the signal EN1 can have a delay equal to, equivalent to, or otherwise representative of the delay of the second delay component 315 (e.g., corresponding to the signal CAL<1>), and the fourth delay component 455-d for processing the signal EN1 can have a delay equal to, equivalent to, or otherwise representative of the delay of the third delay component 315 (e.g., corresponding to the signal CAL<2>). Although described with reference to three selectable delay components 315, the calibration signal generator 450 can be extended to support generating signals CAL<0:N-1> for any number N of selectable delay components.

[0073] According to these and other instances, the delay components 455 of the calibration signal generator 450 (e.g., components of the calibration component 340) can be substitutes for or otherwise correspond to the respective delay components 315 of the timing signal generation component 310. The operational variability of the delay components 455 can be used to infer the operational variability of the delay components 315, and the comparison or evaluation of the calibration operation can be used to reduce the impact that such variability of the delay components 315 would have on the access operation timing signal 330 by selectively enabling or disabling the delay components 315.

[0074] Figure 5A and 5B illustrate examples of timing diagrams 500 and 550 that respectively support timing signal calibration for a memory device according to the examples disclosed herein. Refer to Figure 4A and 4B as described, the timing diagram 500 can illustrate an example of signaling of the calibration input signal generator 400, and the timing diagram 550 can illustrate an example of signaling of the calibration signal generator 450.

[0075] Timing diagram 500 illustrates an example for generating signals EN1 and EN2. In the example of timing diagram 500, signal MRW can transition to a high state, which can correspond to a first mode register write after powering on memory device 110 or memory die 200 that includes a calibration input signal generator. Thus, timing diagram 500 illustrates an example of generating a calibration signal or otherwise initiating a calibration operation at least partially based on a configuration operation of memory device 110, which can be an initial configuration operation after powering on memory device 110. Signals EN1 and EN2 can be at least partially based on clock signal CLK (e.g., calibration input signal 350-b), for example having a timing or pulse width that is at least partially based on clock signal CLK (e.g., the cycle time or time period t CLK ) of clock signal CLK.

[0076] Timing diagram 550 illustrates an example for generating signal CAL<0:2> (e.g., calibration signal 360-b) at least partially based on signals EN1 and EN2. In the example of timing diagram 550, signal EN2f can illustrate the signal after a first inverter having signal EN2 and can represent the inversion of EN2. The duration between the rising edge of EN1 and the falling edge of EN2f can be approximately equal to the clock cycle duration t CLK (e.g., as described with reference to timing diagram 500), and can be used as a calibration duration for determining which signals CAL<0:2> should be enabled or activated.

[0077] Timing diagram 550 illustrates signals D0, D1, and D2, which can be examples of timing signals for a set of delays corresponding to respective delay components 455 of calibration signal generator 450. Signals D0, D1, and D2 can have a pulse width similar to that of signal EN1, but each of D0, D1, and D3 can have a respective delay that is different in time, as shown. Signals ND0, ND1, and ND2 can refer to processed signals output by glitch elimination circuit 460 of calibration signal generator 450. Signals ND0, ND1, and ND2 can be compared, latched, or stored by respective DFFs 465, such as triggered by the rising edge of signal CONTROL (e.g., at time 555). The resulting outputs of DFFs 465 can be further processed and used to evaluate whether to enable the corresponding signals among signals CAL<0:2>. In the example of timing diagram 550, signals ND0 and ND1 are in a low signal state during the rising edge of CONTROL, and thus signals CAL<0> and CAL<1> can transition to a high signal state. Signal ND2 is in a high signal state during the rising edge of CONTROL, and thus signal CAL<2> can remain in a low signal state.

[0078] Timing diagram 550 illustration example, where at calibration signal generator 450, the default delay (e.g., according to a single delay component) is insufficient to meet the target timing (e.g., the duration of one clock cycle). Instead, calibration signal generator 450 determines that at least two additional delay components (e.g., delay component 315) should be enabled (e.g., corresponding to the generation of signals D0 and D1). Calibration signal generator 450 also determines that the delay of a third additional delay (e.g., corresponding to the generation of signal D2) component will be excessive relative to the target. This determination may consider manufacturing or operational variations of calibration signal generator 450 (e.g., delay components for generating signals ND0, ND1, ND2, including delay components, inverters, and gates), which may correspond to similar operational variations that may be experienced at timing signal generation component 310. By activating signals CAL<0> and CAL<1> and deactivating signal CAL<2>, (e.g., calibration signal 360-b) calibration signal generator 450 can provide an indication to timing signal generation component 310 to enable or disable corresponding delay components 315, respectively.

[0079] In another example not shown, the signal processing of calibration signal generator 450 can operate more quickly (e.g., due to processing or operational variations), such that signal ND2 is also in a low state during the rising edge of CONTROL. In such a case, signal CAL<2> can also be activated, thereby activating or enabling an additional delay component 315 of timing signal generation component 310 (e.g., to extend the read strobe pulse duration that is otherwise too short due to processing or operational variations). In yet another example not shown, the signal processing of calibration signal generator 450 can operate more slowly (e.g., due to processing or operational variations), such that neither signal ND1 nor signal ND2 is in a low state during the rising edge of CONTROL. In such a case, signals CAL<1> and CAL<2> can be deactivated, such that one delay component 315 of timing signal generation component 310 is selectively enabled or activated (e.g., bypassing some delay components 315 to shorten the read strobe pulse duration that is otherwise too long due to processing or operational variations).

[0080] Figure 6 Illustrates an example of a delay circuit system 600 that supports calibration of memory device timing signals according to an example as disclosed herein. In an example of delay circuit system 600, signal AF may represent a column select or activation signal (e.g., signal 320-c), and signal YF may represent a read strobe signal (e.g., access operation timing signal 330-c) generated at least in part based on signal AF and a set of delay components 605.

[0081] The delay components 605 may each represent a corresponding set of one or more gate delay components and may thus each correspond to a corresponding delay duration. The delay component 605-a may generate a delay between a signal AF, which is an input to the delay circuitry 600, and an output signal YF, e.g., a delay between a rising edge of AF and a rising edge of YF. A further delay between the rising edge of AF and the rising edge of YF may be introduced by an inverter or a gate, as shown. For example, a rising edge of the signal YF may be fed back through a feedback loop to generate a falling edge, and a duration between the rising edge of YF and the falling edge of YF may correspond to a pulse width of the signal YF.

[0082] The feedback loop may include delay components 605-b and 605-c, which may facilitate a default delay of the feedback loop. The feedback loop may also include delay components 605-d, 605-e, and 605-f, which may be examples of the delay components 315 described for reference Figure 3 above. Each of the delay components 605-d, 605-e, and 605-f may illustrate an example of a delay component of the delay circuitry 600 that is configured to be selectively enabled (e.g., included in the feedback loop) or disabled (e.g., bypassed in the feedback loop). For example, the selective enabling or disabling of the delay components 605-d, 605-e, and 605-f may be supported by a signal tm<0:2>, which may correspond to an inverted state of a signal CAL<0:2>, as described for reference Figure 5B above.

[0083] For example, the delay component 605-d can be selectively enabled or disabled by the signal tm<0>, which can be described as a disable or bypass signal associated with the delay component 605-d. When the signal tm<0> is in the high state, the output of the NAND gate 610-a can be effectively disabled because the high state of the signal tm<0> can cause the output of the NAND gate 610-a to remain in the low state regardless of the state at node 615. Thus, any rising or falling edge of the signaling at node 615 can alternatively pass through the NAND gate 610-b as fed by the inverted state of tm<0> (e.g., inverted to the low state), effectively bypassing the delay component 605-d. When the signal tm<0> is in the low state, the output of the NAND gate 610-b can be effectively disabled because the inverted low state of the signal tm<0> (e.g., high state) can cause the output of the NAND gate 610-b to remain in the low state regardless of the state at node 615. Thus, any rising or falling edge of the signaling at node 615 can alternatively pass through the NAND gate 610-a as fed by the low state of tm<0>, and any rising or falling edge at node 615 can be delayed by passing through the delay component 605-d. Similarly, the delay component 605-e can be selectively enabled or disabled by the signal tm<1>, which can be described as a disable or bypass signal associated with the delay component 605-e, and the delay component 605-f can be selectively enabled or disabled by the signal tm<2>, which can be described as a disable or bypass signal associated with the delay component 605-f.

[0084] Thus, the delay circuit system 600 can be included in a timing signal generator, such as the timing signal generation component 310 described in reference Figure 3 where the delay components 605-d, 605-e, and 605-f can be instances of the delay components 315 configured to be selectively enabled or disabled. The delay components 605-a, 605-b, and 605-c can be instances of other delay components of the timing signal generator that are not configured to be selectively enabled or disabled (e.g., included in a delay chain regardless of the calibration signal 360). By including the delay components 605-d, 605-e, and 605-f, the delay circuit system 600 can support dynamic calibration of read strobe timing, such as dynamic calibration of the pulse width of the read strobe signal. This calibration can support a hold margin or setup margin that tracks process or operation variability, which can improve the operation of the memory device 110 or system 100 that includes the delay circuit system 600 compared to the operation of the memory device 110 or system 100 that does not include the delay circuit system 600 or other configurable timing signal generation components 310.

[0085] Figure 7FIG. 700 shows a block diagram of a memory device 705 that supports timing signal calibration for a memory device as disclosed herein. The memory device 705 can be an example of aspects of a memory device as described with reference to Figure 1 through 5. The memory device 705 can include a calibration delay chain component 710, a calibration signal comparison component 715, an access operation delay chain component 720, an access operation timing signal generation component 725, a memory device initialization component 730, a calibration initiation component 735, a memory device frequency configuration component 740, a comparison signal generation component 745, and a glitch elimination component 750. Each of these modules can communicate directly or indirectly with each other (e.g., via one or more buses).

[0086] The calibration delay chain component 710 can sequentially process a first timing signal through each of a first set of delay components of the memory device to generate a set of delayed timing signals, each delayed timing signal corresponding to an output of a respective delay component in the first set of delay components.

[0087] The calibration signal comparison component 715 can compare a second timing signal with each of a set of reference signals, each reference signal in the set of reference signals being based on a respective one of the set of delayed timing signals.

[0088] The access operation delay chain component 720 can selectively enable or disable a second set of delay components configured to generate an access operation timing signal for the memory device based on the comparison. In some instances, the second set of delay components can be different from the first set of delay components.

[0089] In some instances, the access operation timing signal generation component 725 can generate an access operation timing signal for latching data to be output by the memory device based on selectively enabling or disabling the second set of delay components.

[0090] In some instances, to generate an access operation timing signal, the access operation timing signal generation component 725 can generate a pulse width of the access operation timing signal based on selectively enabling or disabling the second set of delay components.

[0091] In some instances, to generate an access operation timing signal, the access operation timing signal generation component 725 can generate a timing of the access operation timing signal relative to column selection of the memory device based on selectively enabling or disabling the second set of delay components.

[0092] In some instances, the memory device initialization component 730 can identify an initial configuration operation after powering on the memory device.

[0093] In some instances, the calibration initiation component 735 can generate a first timing signal based on identifying the initial configuration operation.

[0094] In some examples, the memory device frequency configuration component 740 may identify a change in the frequency set point of the memory device.

[0095] In some examples, the calibration initiation component 735 may generate a first timing signal based on identifying the change in the frequency set point.

[0096] In some examples, the comparison signal generation component 745 may generate a second timing signal based on the pulse width of a clock signal received at the memory device.

[0097] In some examples, the glitch elimination component 750 may generate each of the set of reference signals based on processing a respective one of the set of delayed timing signals through the respective glitch elimination component.

[0098] Figure 8 FIG. shows a flowchart illustrating one or more methods 800 in support of timing signal calibration for a memory device in accordance with aspects of the present disclosure. The operations of method 800 may be implemented by a memory device or components thereof as described herein. For example, the operations of method 800 may be performed by a memory device as described with reference to Figure 7 described. In some examples, the memory device may execute an instruction set to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0099] At 805, the memory device may sequentially process a first timing signal through each of a first set of delay components of the memory device to generate a set of delayed timing signals, each delayed timing signal corresponding to an output of a respective delay component of the first set of delay components. The operation of 805 may be performed according to the methods described herein. In some examples, aspects of the operation of 805 may be performed by a calibration delay chain component as described with reference to Figure 7 described.

[0100] At 810, the memory device may compare the second timing signal with each of a set of reference signals, each reference signal of the set of reference signals being based on a respective one of the set of delayed timing signals. The operation of 810 may be performed according to the methods described herein. In some examples, aspects of the operation of 810 may be performed by a calibration signal comparison component as described with reference to Figure 7 described.

[0101] At 815, the memory device may selectively enable or disable a second set of delay components configured to generate access operation timing signals for the memory device based on the comparison. The operation of 815 may be performed according to the methods described herein. In some examples, aspects of the operation of 815 may be performed by a component as described with reference to Figure 7Aspects of the access operation latency chain component performing the operation 815 are described.

[0102] In some instances, a device as described herein may execute one or more methods such as method 800. The device may include features, circuitry, devices, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: sequentially processing a first timing signal through each of a first set of delay components of a memory device to generate a set of delayed timing signals, each delayed timing signal corresponding to an output of a respective delay component in the first set of delay components; comparing a second timing signal with each of a set of reference signals, each reference signal in the set of reference signals being based on a respective one of the set of delayed timing signals; and selectively enabling or disabling a second set of delay components configured to generate an access operation timing signal for the memory device based on the comparison.

[0103] Some instances of method 800 and the device described herein may further include operations, features, circuitry, devices, or instructions for generating an access operation timing signal for latching data to be output by the memory device based on selectively enabling or disabling the second set of delay components.

[0104] In some instances of method 800 and the device described herein, generating the access operation timing signal may include operations, features, circuitry, devices, or instructions for generating a pulse width of the access operation timing signal based on selectively enabling or disabling the second set of delay components.

[0105] In some instances of method 800 and the device described herein, generating the access operation timing signal may include operations, features, circuitry, devices, or instructions for generating a timing of the access operation timing signal relative to a column selection of the memory device based on selectively enabling or disabling the second set of delay components.

[0106] Some instances of method 800 and the device described herein may further include operations, features, circuitry, devices, or instructions for identifying an initial configuration operation after powering on the memory device, and generating a first timing signal based on identifying the initial configuration operation.

[0107] Some instances of method 800 and the device described herein may further include operations, features, circuitry, devices, or instructions for identifying a change in a frequency set point of the memory device, and generating a first timing signal based on identifying the change in the frequency set point.

[0108] Some examples of the method 800 and apparatus described herein may further include operations, features, circuitry, apparatus, or instructions for generating a second timing signal based on the pulse width of a clock signal received at a memory device.

[0109] Some examples of the method 800 and apparatus described herein may further include operations, features, circuitry, apparatus, or instructions for generating each of the set of reference signals based on processing a respective one of the set of delayed timing signals by a respective error cancellation component.

[0110] In some examples of the method 800 and apparatus described herein, the second set of delay components may be different from the first set of delay components.

[0111] Note that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0112] A device is described. The device may include: an array of memory cells; a timing calibration component including: a first set of delay components configured to generate a set of delayed timing signals, each delayed timing signal corresponding to an output of a respective delay component in the first set of delay components; and a comparison component configured to generate a set of delay configuration signals, each delay configuration signal being generated based on comparing a second timing signal with a respective one of a set of reference signals, each reference signal in the set of reference signals being based on a respective one of the set of delayed timing signals. The device may further include an access timing component coupled to the memory cell array and the timing calibration component, the access timing component including a second set of delay components configured to generate an access operation timing signal to access the memory cell array, wherein each delay component in the second set of delay components may be configured to be selectively enabled or disabled based on the set of delay configuration signals.

[0113] In some examples, the access timing component may be configured to generate an access operation timing signal for latching data for output by the device based on selectively enabling or disabling the second set of delay components.

[0114] In some examples, the access timing component may be configured to generate an access operation timing signal having a certain pulse width, the pulse width being based on selectively enabling or disabling the second set of delay components.

[0115] In some examples, the access timing component may be configured to generate an access operation timing signal having a timing relative to column selection of the memory cell array, the timing being based on selectively enabling or disabling the second set of delay components.

[0116] In some instances, the timing calibration component may be configured to generate the set of delay configuration signals based on identifying an initial configuration operation after powering on the device.

[0117] In some instances, the timing calibration component may be configured to generate the set of delay configuration signals based on identifying a change in the frequency set point of the device.

[0118] Some instances of the device may include a second signal generator configured to generate a second timing signal based on the pulse width of a clock signal.

[0119] In some instances, the timing calibration component may include a set of glitch elimination circuits, and the timing calibration component may be configured to generate each of the set of reference signals based on a respective one of the set of glitch elimination circuits.

[0120] In some instances, each delay component in the first set of delay components includes a respective set of transistor gate delay components.

[0121] In some instances, each delay component in the second set of delay components includes a respective second set of transistor gate delay components, which is different from the respective set of transistor gate delay components in the first set of delay components.

[0122] Describe another device. The device may include: an array of memory cells; a column decoder coupled to the memory cell array and configured to activate columns of the memory cell array based on column select signals; a read latch coupled to the memory cell array and configured to latch the result of accessing the memory cells of the activated columns based on a read trigger signal; and a signal generator coupled to the column decoder and the read latch, the signal generator being configured to generate a read trigger signal having a timing relative to the column select signal, the timing being based on selectively enabling or disabling a set of delay components according to a delay value.

[0123] Some instances of the device may include a delay calibration circuitry configured to: process a first timing signal sequentially through each of a second plurality of delay components to generate a plurality of delayed timing signals, each of the plurality of delayed timing signals corresponding to an output of a respective delay component in the second plurality of delay components; compare the second timing signal with each of a plurality of reference signals, each of the plurality of reference signals being at least partially based on a respective one of the plurality of delayed timing signals; and generate a delay value associated with selectively enabling or disabling the plurality of delay components of the signal generator.

[0124] In some instances of the device, the delay calibration circuitry may be configured to generate the second timing signal based on the pulse width of a clock signal received at the device.

[0125] In some examples of the device, the delay calibration circuitry may be configured to generate each of the set of reference signals based on processing, by a respective glitch elimination component, a respective one of the set of delayed timing signals.

[0126] In some examples of the device, the delay calibration circuitry may be configured to identify an initial configuration operation after powering on the device, and generate a set of delay configuration signals associated with selectively enabling or disabling the set of delay components of the signal generator based on identifying the initial configuration operation.

[0127] In some examples of the device, the delay calibration circuitry may be configured to identify a change in the frequency set point of the device, and generate a set of delay configuration signals associated with selectively enabling or disabling the set of delay components of the signal generator based on identifying the change in the frequency set point.

[0128] In some examples, the signal generator may be configured to generate a read trigger signal having a certain pulse width, which may be based on selective enabling or disabling.

[0129] Any of a variety of different techniques and arts may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0130] The terms "electronically communicate", "conductive contact", "connected", and "coupled" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be electronically communicating (or in conductive contact, or connected, or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device that includes the connected components, the conductive path between components that are electronically communicating (or in conductive contact or connected or coupled) with each other may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time using, for example, one or more intermediate components such as switches or transistors.

[0131] The term "coupling" refers to the condition of moving from an open-circuit relationship between components to a closed-circuit relationship, where in the open-circuit relationship, signals cannot currently be conveyed between components through a conductive path, and in the closed-circuit relationship, signals can be conveyed between components through a conductive path. When a component such as a controller couples other components together, the components initiate a change that allows signals to flow between the other components via a conductive path that previously did not permit signal flow.

[0132] The term "isolation" refers to the relationship between components where signals cannot currently flow between the components. If there is an open circuit between the components, the components are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, the controller effects the following change: preventing signals from flowing between the components using a conductive path that previously permitted signal flow.

[0133] The devices (including memory arrays) discussed herein may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemicals including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation or by any other doping method during the initial formation or growth of the substrate.

[0134] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals may be connected to other electronic components by a conductive material such as metal. The source and the drain may be conductive and may include heavy doping such as degenerate semiconductor regions. The source and the drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The conductivity of the channel may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0135] The description set forth herein in conjunction with the accompanying drawings describes exemplary configurations and does not represent all examples that are implementable or within the scope of the claims. The term “exemplary” as used herein means “serving as an example, instance, or illustration” and is not preferred or advantageous over other examples. The detailed description includes specific details to provide an understanding of the described technology. However, the technology may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0136] In the figures, like components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that differentiates among the like components. If only the first reference label is used in the specification, the description applies to any one of the like components having the same first reference label, regardless of the second reference label.

[0137] Any of a variety of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0138] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or executed using a general purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0139] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. The features implementing the functions can also be physically located in various places, including being distributed such that portions of the functions are implemented at different physical locations. Also, as used herein, including in the claims, the "or" used in a list of items (e.g., a list of items that begins with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" can be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0140] The description provided herein enables those skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method, comprising: sequentially processing a first timing signal through each of a first plurality of delay components of a memory device to generate a plurality of delayed timing signals, each delayed timing signal corresponding to an output of a respective one of the first plurality of delay components; comparing a second timing signal with each of a plurality of reference signals, each of the plurality of reference signals being at least partially based on a respective one of the plurality of delayed timing signals; selectively enabling or disabling a second plurality of delay components configured to generate an access operation timing signal for the memory device, at least partially based on the comparison; and generating the access operation timing signal for latching data output by the memory device, at least partially based on the selectively enabling or disabling of the second plurality of delay components, wherein generating the access operation timing signal includes: generating a pulse width of the access operation timing signal, at least partially based on the selectively enabling or disabling of the second plurality of delay components.

2. The method of claim 1, wherein generating the access operation timing signal includes: generating a timing of the access operation timing signal relative to a column selection of the memory device, at least partially based on the selectively enabling or disabling of the second plurality of delay components.

3. The method of claim 1, further comprising: identifying an initial configuration operation after powering on the memory device; and generating the first timing signal, at least partially based on identifying the initial configuration operation.

4. The method of claim 1, further comprising: generating the second timing signal, at least partially based on a pulse width of a clock signal received at the memory device.

5. The method of claim 1, further comprising: generating each of the plurality of reference signals, at least partially based on processing a respective one of the plurality of delayed timing signals through a respective glitch elimination component.

6. The method of claim 1, wherein the second plurality of delay components is different from the first plurality of delay components.

7. A method, comprising: identifying a change in a frequency set point of a memory device; generating a first timing signal, at least partially based on identifying the change in the frequency set point; sequentially processing the first timing signal through each of a first plurality of delay components of the memory device to generate a plurality of delayed timing signals, each delayed timing signal corresponding to an output of a respective one of the first plurality of delay components; comparing a second timing signal with each of a plurality of reference signals, each of the plurality of reference signals being at least partially based on a respective one of the plurality of delayed timing signals; and selectively enabling or disabling a second plurality of delay components configured to generate an access operation timing signal for the memory device, at least partially based on the comparison.

8. The method of claim 7, further comprising: Generating the access operation timing signal for latching data output by the memory device is at least partially based on selectively enabling or disabling the second plurality of delay components.

9. The method according to claim 8, wherein generating the access operation timing signal comprises: Generating a pulse width of the access operation timing signal at least partially based on selectively enabling or disabling the second plurality of delay components.

10. The method according to claim 7, wherein generating the access operation timing signal comprises: Generating a timing of the access operation timing signal relative to column selection of the memory device at least partially based on selectively enabling or disabling the second plurality of delay components.

11. The method according to claim 7, further comprising: Identifying an initial configuration operation after powering on the memory device; and Generating the first timing signal at least partially based on identifying the initial configuration operation.

12. An apparatus, comprising: An array of memory cells; A timing calibration component, comprising: A first plurality of delay components configured to generate a plurality of delayed timing signals, each delayed timing signal corresponding to an output of a respective delay component among the first plurality of delay components; A comparison component configured to generate a plurality of delay configuration signals at least partially based on identifying a change in a frequency set point of the apparatus, each delay configuration signal being generated at least partially based on comparing a second timing signal with a respective one of a plurality of reference signals, each reference signal among the plurality of reference signals being at least partially based on a respective one of the plurality of delayed timing signals; and An access timing component coupled to the array of memory cells and the timing calibration component, the access timing component comprising a second plurality of delay components configured to generate an access operation timing signal for accessing the array of memory cells, wherein each delay component among the second plurality of delay components is configured to be selectively enabled or disabled at least partially based on the plurality of delay configuration signals.

13. The apparatus according to claim 12, wherein the access timing component is configured to generate the access operation timing signal for latching data output by the apparatus at least partially based on selectively enabling or disabling the second plurality of delay components.

14. The apparatus according to claim 12, wherein the access timing component is configured to generate the access operation timing signal having a certain pulse width, the pulse width being at least partially based on selectively enabling or disabling the second plurality of delay components.

15. The apparatus according to claim 12, wherein the access timing component is configured to generate the access operation timing signal having a timing relative to column selection of the array of memory cells, the timing being at least partially based on selectively enabling or disabling the second plurality of delay components.

16. The apparatus according to claim 12, wherein the timing calibration component is configured to generate the plurality of delay configuration signals at least partially based on identifying an initial configuration operation after powering on the apparatus.

17. The apparatus according to claim 12, further comprising: A second signal generator configured to generate the second timing signal based at least in part on a pulse width of a clock signal.

18. The apparatus according to claim 12, wherein the timing calibration component includes a plurality of glitch elimination circuits, and wherein the timing calibration component is configured to generate each of the plurality of reference signals based at least in part on a respective one of the plurality of glitch elimination circuits.

19. The apparatus according to claim 12, wherein each delay component of the first plurality of delay components includes a respective plurality of transistor gate delay components.

20. The apparatus according to claim 19, wherein each delay component of the second plurality of delay components includes a respective second plurality of transistor gate delay components different from the respective plurality of transistor gate delay components of the first plurality of delay components.

21. An apparatus comprising: An array of memory cells; A column decoder coupled to the array of memory cells and configured to activate columns of the array of memory cells based at least in part on column select signals; A read latch coupled to the array of memory cells and configured to latch results of accessing memory cells of the columns of the array of memory cells based at least in part on a read trigger signal; And A signal generator coupled to the column decoder and the read latch, the signal generator being configured to generate the read trigger signal having a timing and a pulse width relative to the column select signal, the timing being based at least in part on selectively enabling or disabling a plurality of delay components according to a delay value, the pulse width being based at least in part on the selectively enabling or disabling.

22. The apparatus according to claim 21, further comprising: A delay calibration circuitry configured to: Process a first timing signal sequentially through each of a second plurality of delay components to generate a plurality of delayed timing signals, each of the plurality of delayed timing signals corresponding to an output of a respective delay component of the second plurality of delay components; Compare a second timing signal with each of a plurality of reference signals, each of the plurality of reference signals being based at least in part on a respective one of the plurality of delayed timing signals; And Generate the delay value associated with the selectively enabling or disabling the plurality of delay components of the signal generator.

23. The apparatus according to claim 22, wherein the delay calibration circuitry is configured to: Generate the second timing signal based at least in part on a pulse width of a clock signal received at the apparatus.

24. The apparatus according to claim 22, wherein the delay calibration circuitry is configured to: Generate each of the plurality of reference signals based at least in part on processing a respective one of the plurality of delayed timing signals through a respective glitch elimination component.

25. The apparatus according to claim 22, wherein the delay calibration circuitry is configured to: Identify an initial configuration operation after powering the device; and Generate a plurality of delay configuration signals associated with the plurality of delay components that selectively enable or disable the signal generator, at least in part based on identifying the initial configuration operation.

26. The apparatus of claim 22, wherein the delay calibration circuitry is configured to:[[]] Identify a change in a frequency set point of the device; and Generate a plurality of delay configuration signals associated with the plurality of delay components that selectively enable or disable the signal generator, at least in part based on identifying the change in the frequency set point.

27. A method, comprising:[[]] Sequentially process a first timing signal through each of a first plurality of delay components of a memory device to generate a plurality of delayed timing signals, each delayed timing signal corresponding to an output of a respective delay component of the first plurality of delay components; Generate each of a plurality of reference signals, at least in part based on processing a respective one of the plurality of delayed timing signals through a respective glitch elimination component; Compare a second timing signal with each of the plurality of reference signals, each reference signal of the plurality of reference signals being at least in part based on a respective one of the plurality of delayed timing signals; and And Selectively enable or disable a second plurality of delay components configured to generate an access operation timing signal for the memory device, at least in part based on the comparison.

28. An apparatus, comprising:[[]] A memory cell array; A timing calibration component, comprising:[[]] A first plurality of delay components configured to generate a plurality of delayed timing signals, each delayed timing signal corresponding to an output of a respective delay component of the first plurality of delay components; A comparison component configured to generate a plurality of delay configuration signals, each delay configuration signal being generated at least in part based on comparing a second timing signal with a respective one of a plurality of reference signals, each reference signal of the plurality of reference signals being at least in part based on a respective one of the plurality of delayed timing signals; and An access timing component coupled to the memory cell array and the timing calibration component, the access timing component including a second plurality of delay components configured to generate an access operation timing signal to access the memory cell array, wherein each delay component of the second plurality of delay components is configured to be selectively enabled or disabled at least in part based on the plurality of delay configuration signals, wherein the access timing component is configured to generate the access operation timing signal having a certain pulse width, the pulse width being at least in part based on selectively enabling or disabling the second plurality of delay components.

29. An apparatus, comprising:[[]] A memory cell array; A timing calibration component, comprising:[[]] A first plurality of delay components configured to generate a plurality of delayed timing signals, each delayed timing signal corresponding to an output of a respective delay component of the first plurality of delay components; A plurality of glitch elimination circuits, wherein the timing calibration component is configured to generate each of a plurality of reference signals at least in part based on a respective one of the plurality of glitch elimination circuits; A comparison component configured to generate a plurality of delay configuration signals, each delay configuration signal being generated at least in part based on comparing a second timing signal with a respective one of the plurality of reference signals, each of the plurality of reference signals being at least in part based on a respective one of the plurality of delayed timing signals; and An access timing component coupled to the memory cell array and the timing calibration component, the access timing component including a second plurality of delay components configured to generate an access operation timing signal to access the memory cell array, wherein each of the second plurality of delay components is configured to be selectively enabled or disabled at least in part based on the plurality of delay configuration signals.

30. An apparatus comprising: A memory cell array; A column decoder coupled to the memory cell array and configured to activate columns of the memory cell array at least in part based on a column select signal; A read latch coupled to the memory cell array and configured to latch a result of accessing memory cells of the column of the memory cell array at least in part based on a read trigger signal; A signal generator coupled to the column decoder and the read latch, the signal generator being configured to generate the read trigger signal having a timing relative to the column select signal, the timing being at least in part based on selectively enabling or disabling a plurality of delay components according to a delay value; And A delay calibration circuitry configured to: Process a first timing signal sequentially through each of a second plurality of delay components to generate a plurality of delayed timing signals, each of the plurality of delayed timing signals corresponding to an output of a respective one of the second plurality of delay components; Generate each of a plurality of reference signals at least in part based on processing a respective one of the plurality of delayed timing signals through a respective glitch elimination component; Compare the second timing signal with each of the plurality of reference signals, each of the plurality of reference signals being at least in part based on a respective one of the plurality of delayed timing signals; And Generate the delay value associated with selectively enabling or disabling the plurality of delay components of the signal generator.

31. An apparatus comprising: A memory cell array; A column decoder coupled to the memory cell array and configured to activate columns of the memory cell array at least in part based on a column select signal; A read latch coupled to the memory cell array and configured to latch a result of accessing memory cells of the column of the memory cell array at least in part based on a read trigger signal; A signal generator, which is coupled to the column decoder and the read latch, the signal generator being configured to generate the read trigger signal having a timing relative to the column select signal, the timing being at least partially based on selectively enabling or disabling a plurality of delay components according to a delay value; and A delay calibration circuit system, which is configured to: Identify a change in the frequency set point of the device; Generate a plurality of delay configuration signals associated with selectively enabling or disabling the plurality of delay components of the signal generator at least partially based on identifying the change in the frequency set point; Process a first timing signal sequentially through each of a second plurality of delay components to generate a plurality of delayed timing signals, each of the plurality of delayed timing signals corresponding to an output of a respective delay component of the second plurality of delay components; Compare a second timing signal with each of a plurality of reference signals, each of the plurality of reference signals being at least partially based on a respective one of the plurality of delayed timing signals; and Generate the delay value associated with selectively enabling or disabling the plurality of delay components of the signal generator.

Images