Dry etching method for manufacturing trench structure of semiconductor device

Abstract

The present invention relates to a dry etching method for manufacturing a groove structure of a semiconductor device. The dry etching method comprises the following steps: Step 1: providing a semiconductor substrate. A patterned photoresist layer is arranged on the semiconductor substrate and placed in a reaction chamber. Step 2: introducing a first etching gas into the reaction chamber to perform a first etching method to form a groove. The first etching gas comprises sulfur hexafluoride, oxygen, helium, nitrogen trifluoride and a first organic silicon compound. Step 3: introducing a second etching gas into the reaction chamber to perform a second etching method to etch the groove downward. The second etching gas comprises sulfur hexafluoride, oxygen, helium and a second organic silicon compound. Step 4: introducing a third etching gas into the reaction chamber to perform a third etching method. The third etching gas comprises hydrobromic acid, oxygen and helium.

Description

Technical Field

[0001] The invention relates to an etching method, and in particular to a dry etching method for manufacturing a trench structure of a semiconductor device. Background Art

[0002] The semiconductor industry is booming. Technological advances in semiconductor design and materials have enabled semiconductor devices to have smaller and more complex circuits. The functional density of semiconductor devices is generally increased while the size is reduced, which can improve production efficiency and reduce costs.

[0003] The functions of semiconductor devices are limited by the area of ​​semiconductor chips. With the development of semiconductor technology, more and more devices use three-dimensional stacking technology to increase the density of components. However, three-dimensional stacking technology increases the complexity of semiconductor device manufacturing processes, makes it more difficult to maintain the process quality and stability of semiconductor devices, and affects production. For semiconductor chips of three-dimensional integrated circuits, a higher trench aspect ratio is required. In traditional technology, the deep reactive-ion etching (DRIE) process developed by Bosch is usually used to make trenches. However, the existing DRIE process still has the problem of high trench sidewall roughness, which affects the electrical and mechanical properties of semiconductor chips. Therefore, corresponding development in the process of semiconductor devices to improve process quality and stability is an urgent problem to be solved.

[0004] The "Prior Art" section is only used to help understand the content of the present invention. Therefore, the content disclosed in the "Prior Art" section may contain some common technologies that are not known to those with ordinary knowledge in the relevant technical field. The content disclosed in the "Prior Art" section does not mean that the content or the problems to be solved by one or more embodiments of the present invention have been known or recognized by those with ordinary knowledge in the relevant technical field before the application of the present invention. Summary of the invention

[0005] The invention provides a dry etching method for manufacturing a groove structure of a semiconductor device, which can improve the quality and stability of the semiconductor device and increase the yield.

[0006] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0007] The dry etching method for manufacturing a trench structure of a semiconductor device of the present invention comprises the following steps:

[0008] Step 1: Provide a semiconductor substrate, on which a patterned photoresist layer is disposed and placed in a reaction chamber, wherein the semiconductor substrate has a reserved area shielded by the photoresist layer and an exposed area to be etched, and the reaction chamber includes an upper electrode and a lower electrode. Step 2: Introduce a first etching gas into the reaction chamber to perform a first etching method, and remove part of the area to be etched to form a groove, wherein the groove has a first depth, and the first etching gas includes sulfur hexafluoride, oxygen, helium, nitrogen trifluoride and a first organic silicon compound. Step 3: Introduce a second etching gas into the reaction chamber to perform a second etching method, and etch the groove from the first depth to a second depth, and the second etching gas includes sulfur hexafluoride, oxygen, helium and a second organic silicon compound, wherein the pressure of the reaction chamber in the second etching method is greater than the pressure of the reaction chamber in the first etching method. Step 4: Introduce a third etching gas into the reaction chamber to perform a third etching method, wherein the third etching gas includes hydrobromic acid, oxygen and helium, wherein the temperature change per second in the reaction chamber does not exceed + / -1%, the pressure change per second in the reaction chamber does not exceed + / -5%, and the power change per second of the upper electrode or the lower electrode does not exceed + / -1%.

[0009] In one embodiment of the present invention, in the above-mentioned first etching method, the flow rate of sulfur hexafluoride is between 10 sccm and 2000 sccm, the flow rate of oxygen is between 10 sccm and 500 sccm, the flow rate of helium is between 10 sccm and 500 sccm, the flow rate of nitrogen trifluoride is between 10 sccm and 300 sccm, and the flow rate of the first organic silicon compound is between 50 sccm and 200 sccm.

[0010] In one embodiment of the present invention, in the above-mentioned first etching method, the volume percentage of sulfur hexafluoride relative to the first etching gas is 30%, the volume percentage of oxygen relative to the first etching gas is 20%, the volume percentage of helium relative to the first etching gas is 20%, the volume percentage of nitrogen trifluoride relative to the first etching gas is 10%, and the volume percentage of the first organic silicon compound relative to the first etching gas is 20%.

[0011] In one embodiment of the present invention, in the above-mentioned first etching method, the power of the upper electrode is 3000W, and the power of the lower electrode is 500W.

[0012] In one embodiment of the present invention, in the above-mentioned second etching method, the flow rate of sulfur hexafluoride is between 10 sccm and 2000 sccm, the flow rate of oxygen is between 10 sccm and 500 sccm, the flow rate of helium is between 10 sccm and 500 sccm, and the flow rate of the second organic silicon compound is between 50 sccm and 200 sccm.

[0013] In one embodiment of the present invention, in the above-mentioned second etching method, the volume percentage of sulfur hexafluoride relative to the second etching gas is 20%, the volume percentage of oxygen relative to the second etching gas is 20%, the volume percentage of helium relative to the second etching gas is 40%, and the volume percentage of the second organic silicon compound relative to the second etching gas is 20%.

[0014] In one embodiment of the present invention, in the above-mentioned second etching method, the power of the upper electrode is 7000W, and the power of the lower electrode is 2000W.

[0015] In one embodiment of the present invention, in the third etching method, the flow rate of hydrobromic acid is between 10 sccm and 2000 sccm, the flow rate of oxygen is between 10 sccm and 500 sccm, and the flow rate of helium is between 10 sccm and 500 sccm.

[0016] In one embodiment of the present invention, in the third etching method, the volume percentage of hydrobromic acid relative to the third etching gas is 60%, the volume percentage of oxygen relative to the third etching gas is 10%, and the volume percentage of helium relative to the third etching gas is 30%.

[0017] In one embodiment of the present invention, in the third etching method, the power of the upper electrode is 1000W, and the power of the lower electrode is 100W.

[0018] Based on the above, the dry etching method for manufacturing the groove structure of a semiconductor device provided by the present invention uses the first etching method, the second etching method, and the third etching method to respectively perform the first etching gas, the second etching gas, and the third etching gas to manufacture a semiconductor structure with a deep groove, which can improve the process quality and stability, and can also increase the yield.

[0019] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 FIG. 1 is a schematic diagram of a dry etching device for manufacturing a trench structure of a semiconductor device according to an embodiment of the present invention.

[0021] Figure 2A , Figure 2B , Figure 2C , Figure 2D is a cross-sectional view illustrating an intermediate stage of a dry etching method for fabricating a trench structure of a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0022] The above-mentioned other technical contents, features and effects of the present invention will be clearly presented in the detailed description of one of the preferred embodiments with reference to the drawings below. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention. Herein, the terms "about" and "approximately" usually mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantity given here is an approximate quantity, that is, in the absence of a specific description of "about" or "approximately", the meaning of "about" or "approximately" can still be implied.

[0023] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a dry etching device 17 for fabricating a trench structure of a semiconductor device 10 according to an embodiment of the present invention.

[0024] Please also refer to Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2A , Figure 2B , Figure 2C , Figure 2D is a cross-sectional view of an intermediate stage of a dry etching method for manufacturing a trench structure of a semiconductor device 10 according to some embodiments. Figure 2A The dry etching method for manufacturing the trench structure of the semiconductor device 10 of this embodiment includes the following steps:

[0025] Step 1: Provide a semiconductor substrate 11. The semiconductor substrate 11 is provided with a patterned photoresist layer 13 and is placed in a reaction chamber 171 (eg Figure 1 The semiconductor substrate 11 has a reserved area 111 shielded by the photoresist layer 13 and an exposed area to be etched 113. The reaction chamber 171 includes an upper electrode 173 and a lower electrode 175. The material of the semiconductor substrate 11 includes silicon, for example. The reaction chamber 171 is disposed inside the dry etching device 17 (as shown in FIG. 1 ). Figure 1 shown).

[0026] In addition, the semiconductor device 10 may include an oxide layer 15 . The oxide layer 15 is disposed below the semiconductor substrate 11 .

[0027] For the sake of convenience, Figure 2A , Figure 2B , Figure 2C , Figure 2D The dry etching device 17 is not shown. Figure 2B .

[0028] Step 2: Introduce a first etching gas g1 into the reaction chamber 171 to perform a first etching method E1, and remove a portion of the to-be-etched area 113 to form a trench 19a. The trench 19a has a first depth d1. In this embodiment, the first etching gas g1 includes sulfur hexafluoride (SF6), oxygen (O2), helium (He), nitrogen trifluoride (NF3) and a first organic silicon compound.

[0029] Step 3: If Figure 2C As shown, a second etching gas g2 is introduced into the reaction chamber 171 to perform a second etching method E2, and the trench 19a is etched downward from the first depth d1 to a second depth d2. The second etching method E2 also etches away the oxide at the bottom of the trench 19a to form a trench 19b. The trench 19b is partially covered with the protective layer 18a. In this embodiment, the second etching gas g2 includes sulfur hexafluoride (SF6), oxygen (O2), helium (He) and a second organic silicon compound.

[0030] Step 4: Figure 2D As shown, a third etching gas g3 is introduced into the reaction chamber 171 to perform a third etching method E3. The third etching gas includes hydrobromic acid (HBr), oxygen (O2) and helium (He). In the third etching method E3, the trench 19b is etched from the second depth d2 down to the oxide layer 15 to form a trench 19c. The third etching gas g3 does not etch the oxide layer 15.

[0031] In this embodiment, the temperature variation within the reaction chamber 171 does not exceed + / -1% per second.

[0032] In this embodiment, the pressure variation of the reaction chamber 171 per second does not exceed + / -5%.

[0033] In this embodiment, the power variation of the upper electrode 173 or the lower electrode 175 per second does not exceed + / -1%.

[0034] like Figure 1As shown, specifically, the dry etching device 17 may include a plurality of tanks t1, t2, t3, t4 and a pipeline p. The tanks t1, t2, t3, t4 are used to store the gases required for each etching method, and the pipeline p is used to transmit the gases required for each etching method to the reaction chamber 171. The present invention does not limit the number of tanks and the storage location and storage method of the etching gas. The upper electrode 173 and the lower electrode 175 are used to react with each etching gas to perform etching, and the details are not repeated. In some embodiments, the first organosilicon compound and / or the second organosilicon compound can be replaced by dichlorosilane (H2SiCl2).

[0035] Specifically, in step 1, the exposed area 113 of the semiconductor substrate 11 to be etched generates oxide (native oxide) (not shown). In the first etching method E1 of step 2, the first etching gas g1 must be used for etching to decompose the oxide in order to continue etching. Sulfur hexafluoride ions and free radicals can etch the silicon of the semiconductor substrate 11. Figure 2B In the protective layer 18 shown, the first organic silicon compound reacts with oxygen to form silicon oxide (SiO2) to protect the top and side walls of the photoresist layer 13. Oxygen reacts with silicon and fluorine to form silicon oxide (SiOxFy) polymer to protect the side walls of the groove 19a from being corroded by sulfur hexafluoride ions and free radicals. Nitrogen trifluoride is used to etch the oxide polymer on the photoresist layer 13 and the silicon oxide polymer on the side walls of the groove 19a to control the profile of the groove 19a.

[0036] exist Figure 2A In the embodiment, the thickness of the semiconductor substrate 11 is, for example, about 600 μm, and the thickness of the photoresist layer 13 is, for example, about 20 μm. Figure 2B In the embodiment, the width of the trench 19 a is, for example, about 5 μm, and the thickness of the protection layer 18 is, for example, about 30 nm.

[0037] In this embodiment, the pressure of the reaction chamber 171 in the second etching method E2 (step 3) is greater than the pressure of the reaction chamber 171 in the first etching method E1 (step 2).

[0038] In this embodiment, in the first etching method E1 (step 2), the flow rate of sulfur hexafluoride is between 10 sccm and 2000 sccm, the flow rate of oxygen is between 10 sccm and 500 sccm, the flow rate of helium is between 10 sccm and 500 sccm, the flow rate of nitrogen trifluoride is between 10 sccm and 300 sccm, and the flow rate of the first organic silicon compound is between 50 sccm and 200 sccm.

[0039] In this embodiment, in the first etching method E1 (step 2), the volume percentage of sulfur hexafluoride relative to the first etching gas g1 is 30%, the volume percentage of oxygen relative to the first etching gas g1 is 20%, the volume percentage of helium relative to the first etching gas g1 is 20%, the volume percentage of nitrogen trifluoride relative to the first etching gas g1 is 10%, and the volume percentage of the first organosilicon compound relative to the first etching gas g1 is 20%.

[0040] In this embodiment, in the first etching method E1 (step 2), the power of the upper electrode 173 is about 3000W, and the power of the lower electrode 175 is about 500W.

[0041] In addition, in the first etching method E1, in order to increase the etching depth, the pressure of the reaction chamber 171 must be as low as less than 100 mT (milli-Torr). In the first etching method E1, the etching time of the first etching method E1 must be greater than 30 seconds to reduce the instability of the gas flow in the Bosch deep reactive ion etching and reduce the unexpected etching stop phenomenon in the etching method.

[0042] In this embodiment, after the first etching method E1, the thickness of the photoresist layer 13 can still retain 2 / 3 to 1 / 2 of the thickness before etching. As mentioned above, a polymer can be deposited to protect the photoresist layer 13 and the sidewalls of the groove 19a. The pressure of the reaction chamber 171 must be greater than 150mT. The power of the upper electrode 173 is less than 7000w, and the power of the lower electrode 175 is less than 50w. At this time, the proportion of the gas includes about 40vol.% oxygen and 60vol.% Si organic compound.

[0043] In detail, in the second etching method E2 of step 3, helium can reduce the density of sulfur hexafluoride, reduce the etching rate, and reduce the polymer growth at the bottom of the trench.

[0044] In this embodiment, in the second etching method E2 (step 3), the flow rate of sulfur hexafluoride is between 10 sccm and 2000 sccm, the flow rate of oxygen is between 10 sccm and 500 sccm, the flow rate of helium is between 10 sccm and 500 sccm, and the flow rate of the second organic silicon compound is between 50 sccm and 200 sccm.

[0045] In this embodiment, in the second etching method E2 (step 3), the volume percentage of sulfur hexafluoride relative to the second etching gas g2 is 20%, the volume percentage of oxygen relative to the second etching gas g2 is 20%, the volume percentage of helium relative to the second etching gas g2 is 40%, and the volume percentage of the second organosilicon compound relative to the second etching gas g2 is 20%.

[0046] In this embodiment, in the second etching method E2 (step 3), the power of the upper electrode 173 is approximately 7000W, and the power of the lower electrode 175 is approximately 2000W.

[0047] In this embodiment, since the second etching gas g2 will etch the material of the oxide layer 15 , the third etching method E3 must be performed. The third etching gas g3 will not etch the material of the oxide layer 15 .

[0048] In detail, the third etching method E3 of step 4 is an over-etch method. The third etching method E3 uses hydrobromic acid, oxygen and helium to deposit a polymer (not shown) to protect the photoresist layer 13 and the trench 19c. Hydrobromic acid is used to etch silicon, and can also produce hydrogen (H2) and silicon bromide (SiOxBry). Silicon bromide can be deposited to protect the oxide layer 15 and the photoresist layer 13 below. Oxygen, silicon and hydrogen can form SiOH polymer (not shown) to protect the sidewalls of the trench 19c.

[0049] In this embodiment, in the third etching method E3 (step 4), the flow rate of hydrobromic acid is between 10 sccm and 2000 sccm, the flow rate of oxygen is between 10 sccm and 500 sccm, and the flow rate of helium is between 10 sccm and 500 sccm.

[0050] In this embodiment, in the third etching method E3 (step 4), the volume percentage of hydrobromic acid relative to the third etching gas g3 is 60%, the volume percentage of oxygen relative to the third etching gas g3 is 10%, and the volume percentage of helium relative to the third etching gas g3 is 30%.

[0051] In this embodiment, in the third etching method E3 (step 4), the power of the upper electrode 173 is approximately 1000W, and the power of the lower electrode 175 is approximately 100W.

[0052] The dry etching method for manufacturing the groove structure of the semiconductor device 10 of this embodiment manufactures a semiconductor structure with a deep groove (groove 19c) by adjusting temperature and / or power parameters, applying specific etching gas, and adjusting etching parameters. As a result, micro grooves are not easily generated on the bottom oxide layer 15, and no bending (necking / bowing) occurs on the groove 19c. The roughness of the side wall of the groove 19c can be improved, the formation of micro grooves in the oxide layer 15 can be avoided, and the yield of the semiconductor device 10 can be increased.

[0053] In the dry etching method for manufacturing the trench structure of the semiconductor device 10 of this embodiment, the first etching method E1, the second etching method E2, and the third etching method E3 have sufficient reaction time, and through strict temperature, pressure, and power control, the roughness of the sidewall of the trench 19c and the profile of the trench 19c can be greatly improved. The sidewall roughness of the trench 19c of this embodiment can be less than 10nm, the aspect ratio can be greater than 100, and the bottom profile angle of the trench 19c can be between 89.7 degrees and 90.3 degrees. The sidewall roughness of the trench (not shown) produced by the current prior art is usually greater than 100nm, the aspect ratio is usually between 30-60, and the bottom profile angle of the trench is usually between 88 degrees and 92 degrees.

[0054] The semiconductor device 10 having the trench 19 c with a high aspect ratio in this embodiment can be applied to microelectromechanical systems (MEMS), for example.

[0055] In summary, the dry etching method for manufacturing the groove structure of the semiconductor device according to the embodiment of the present invention uses the first etching gas, the second etching gas, and the third etching gas to respectively perform the first etching method, the second etching method, and the third etching method to manufacture a semiconductor structure with a deep groove, which can improve the process quality and stability, and can also increase the yield.

Claims

1. A dry etching method for manufacturing a trench structure of a semiconductor device, characterized in that: The following steps are involved: Step 1: providing a semiconductor substrate, on which a patterned photoresist layer is disposed and placed in a reaction chamber, wherein the semiconductor substrate has a reserved area shielded by the photoresist layer and an exposed area to be etched, and the reaction chamber includes an upper electrode and a lower electrode; Step 2: introducing a first etching gas into the reaction chamber to perform a first etching method, thereby removing a portion of the area to be etched to form a groove, wherein the groove has a first depth, the first etching gas comprises sulfur hexafluoride, oxygen, helium, nitrogen trifluoride and a first organic silicon compound, wherein in the first etching method, the power of the upper electrode is 3000 W, and the power of the lower electrode is 500 W; Step 3: introducing a second etching gas into the reaction chamber to perform a second etching method, thereby etching the trench downward from the first depth to a second depth, the second etching gas comprising sulfur hexafluoride, oxygen, helium and a second organic silicon compound, wherein the pressure of the reaction chamber in the second etching method is greater than the pressure of the reaction chamber in the first etching method, wherein in the second etching method, the power of the upper electrode is 7000W, and the power of the lower electrode is 2000W; as well as Step 4: introducing a third etching gas into the reaction chamber to perform a third etching method, wherein the third etching gas includes hydrobromic acid, oxygen and helium, wherein in the third etching method, the power of the upper electrode is 1000 W, and the power of the lower electrode is 100 W; The temperature variation per second in the reaction chamber does not exceed + / -1%, the pressure variation per second in the reaction chamber does not exceed + / -5%, and the power variation per second of the upper electrode or the lower electrode does not exceed + / -1%.

2. A dry etching method for manufacturing a trench structure of a semiconductor device, characterized in that: The following steps are involved: Step 1: providing a semiconductor substrate, on which a patterned photoresist layer is disposed and placed in a reaction chamber, wherein the semiconductor substrate has a reserved area shielded by the photoresist layer and an exposed area to be etched, and the reaction chamber includes an upper electrode and a lower electrode; Step 2: introducing a first etching gas into the reaction chamber to perform a first etching method, thereby removing a portion of the area to be etched to form a groove, wherein the groove has a first depth, the first etching gas comprises sulfur hexafluoride, oxygen, helium, nitrogen trifluoride and dichlorosilane, wherein in the first etching method, the power of the upper electrode is 3000 W, and the power of the lower electrode is 500 W; Step 3: introducing a second etching gas into the reaction chamber to perform a second etching method, thereby etching the trench from the first depth to a second depth, the second etching gas comprising sulfur hexafluoride, oxygen, helium and dichlorosilane, wherein the pressure of the reaction chamber in the second etching method is greater than the pressure of the reaction chamber in the first etching method, wherein in the second etching method, the power of the upper electrode is 7000W, and the power of the lower electrode is 2000W; as well as Step 4: introducing a third etching gas into the reaction chamber to perform a third etching method, wherein the third etching gas includes hydrobromic acid, oxygen and helium, wherein in the third etching method, the power of the upper electrode is 1000 W, and the power of the lower electrode is 100 W; The temperature variation per second in the reaction chamber does not exceed + / -1%, the pressure variation per second in the reaction chamber does not exceed + / -5%, and the power variation per second of the upper electrode or the lower electrode does not exceed + / -1%.

3. The dry etching method according to claim 1 or claim 2, characterized in that: In the first etching method, the flow rate of sulfur hexafluoride is between 10 sccm and 2000 sccm, the flow rate of oxygen is between 10 sccm and 500 sccm, the flow rate of helium is between 10 sccm and 500 sccm, the flow rate of nitrogen trifluoride is between 10 sccm and 300 sccm, and the flow rate of the first organic silicon compound or dichlorosilane is between 50 sccm and 200 sccm.

4. The dry etching method according to claim 1 or claim 2, characterized in that: In the first etching method, the volume percentage of sulfur hexafluoride relative to the first etching gas is 30%, the volume percentage of oxygen relative to the first etching gas is 20%, the volume percentage of helium relative to the first etching gas is 20%, the volume percentage of nitrogen trifluoride relative to the first etching gas is 10%, and the volume percentage of the first organic silicon compound or dichlorosilane relative to the first etching gas is 20%.

5. The dry etching method according to claim 1 or claim 2, characterized in that: In the second etching method, the flow rate of sulfur hexafluoride is between 10 sccm and 2000 sccm, the flow rate of oxygen is between 10 sccm and 500 sccm, the flow rate of helium is between 10 sccm and 500 sccm, and the flow rate of the second organic silicon compound or dichlorosilane is between 50 sccm and 200 sccm.

6. The dry etching method according to claim 1 or claim 2, characterized in that: In the second etching method, the volume percentage of sulfur hexafluoride relative to the second etching gas is 20%, the volume percentage of oxygen relative to the second etching gas is 20%, the volume percentage of helium relative to the second etching gas is 40%, and the volume percentage of the second organic silicon compound or dichlorosilane relative to the second etching gas is 20%.

7. The dry etching method according to claim 1 or claim 2, characterized in that: In the third etching method, the flow rate of hydrobromic acid is between 10 sccm and 2000 sccm, the flow rate of oxygen is between 10 sccm and 500 sccm, and the flow rate of helium is between 10 sccm and 500 sccm.

8. The dry etching method according to claim 1 or claim 2, characterized in that: In the third etching method, the volume percentage of hydrobromic acid relative to the third etching gas is 60%, the volume percentage of oxygen relative to the third etching gas is 10%, and the volume percentage of helium relative to the third etching gas is 30%.

Images