Method of manufacturing a semiconductor element

Abstract

A method of fabricating a semiconductor device, embodiments of the present disclosure provide methods for forming conductive lines having dielectric cut features. In particular, embodiments of the present disclosure provide a method for forming a conductive line pattern using two patterning processes. In a first patterning process, a line pattern is formed. In a second patterning process, a line pattern is formed over a cut pattern. The cut pattern is formed by forming cut openings having a width less than a line width of the line pattern, and then filling the cut openings with a masking material.

Description

TECHNICAL FIELD

[0001] Some embodiments of the present disclosure relate to a method of fabricating a semiconductor device, and more particularly to a method of reducing line end spacing. BACKGROUND

[0002] The semiconductor industry has experienced continuous rapid growth as the integration density of various electronic components continues to improve. In most cases, this has been driven by the continual reduction in the minimum feature size, which allows more components to be integrated into a given chip area. As the minimum feature size is reduced, the manufacturing of these devices has approached and even exceeded the theoretical limits of optical lithography equipment. As semiconductor devices continue to shrink, the desired spacing between components of the device (i.e., pitch) is less than can be manufactured using conventional optical masks and optical lithography equipment. SUMMARY

[0003] Some embodiments of the present disclosure provide a method of fabricating a semiconductor device. The method includes depositing a first hardmask layer over a dielectric layer, forming a plurality of hardmask strips in the first hardmask layer, wherein the plurality of hardmask strips are separated by a plurality of openings, filling the plurality of openings between the plurality of hardmask strips with a first material, forming a cut opening through the first material, filling the cut opening with a second material, removing the first material to expose the second material and the plurality of hardmask strips, and patterning the dielectric layer using the plurality of hardmask strips and the second material.

[0004] Some embodiments of the present disclosure provide a method of fabricating a semiconductor device. The method includes depositing a first hardmask layer, depositing a second hardmask layer over the first hardmask layer, patterning the second hardmask layer to form a plurality of hardmask strips over the first hardmask layer, wherein the plurality of hardmask strips extend along a first direction, depositing a mask layer over the plurality of hardmask strips and the first hardmask layer, depositing a photoresist layer over the mask layer, patterning the photoresist to form a cut opening to expose at least one of the plurality of hardmask strips, forming a cut mask in the cut opening, wherein the cut mask extends along a second direction substantially perpendicular to the first direction, patterning the first hardmask layer using the plurality of hardmask strips and the cut mask as etch masks.

[0005] Some embodiments of the present disclosure include a method of manufacturing a semiconductor device. The method includes depositing a dielectric layer, patterning the dielectric layer using an extreme ultraviolet patterning technique to form a first opening and a second opening in the dielectric layer, filling the first opening and the second opening in the dielectric layer to form a first conductive line and a second conductive line in the dielectric layer, wherein the first conductive line and the second conductive line extend along a same direction, an end portion of the first conductive line faces an end portion of the second conductive line, an end-to-end spacing between the end portions of the first conductive line and the second conductive line is less than a line width of the first conductive line, and the line width is less than about 25 nanometers. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the present disclosure can be best understood with reference to the following embodiments. It should be noted that various features will not be discussed in scale according to standard practice in the industry. In fact, the size of various features can be arbitrarily increased or decreased for the sake of clarity of discussion.

[0007] Figure 1 A flowchart of a method for manufacturing a semiconductor device according to embodiments of the present disclosure;

[0008] Figures 2 to 6 、 Figures 7A to 7C To Figures 12A to 12C 、 Figures 13 to 14 And Figures 15A to 15C Schematically illustrates a semiconductor device at various manufacturing stages according to the present disclosure;

[0009] Figure 16A A schematic plan view of an intermetal dielectric layer according to embodiments of the present disclosure;

[0010] Figure 16B A partial enlarged view of the intermetal dielectric layer of Figure 16A

[0011]

Symbolic Description

[0012] B-B: Line

[0013] C-C: Line

[0014] L1: Length

[0015] L2: Length

[0016] L3: Length

[0017] L4: Length

[0018] R1: Radius

[0019] W1: Width

[0020] W2: Width ​

[0021] W3: width

[0022] W4: width

[0023] X: axis

[0024] Y: axis

[0025] Z: axis

[0026] 100: method

[0027] 102: operation

[0028] 104: operation

[0029] 106: operation

[0030] 108: operation

[0031] 110: operation

[0032] 112: operation

[0033] 114: operation

[0034] 116: operation

[0035] 118: operation

[0036] 120: operation

[0037] 122: operation

[0038] 124: operation

[0039] 126: operation

[0040] 128: operation

[0041] 130: operation

[0042] 200: semiconductor element

[0043] 202: substrate

[0044] 204: etch stop layer

[0045] 206: dielectric layer

[0046] 206c: cut feature

[0047] 206v: via opening

[0048] 208: first hard mask layer

[0049] 210: second hard mask layer

[0050] 212: third hard mask layer

[0051] 212o: opening

[0052] 212s: mask strip

[0053] 214: protective mask layer

[0054] 216: photoresist structure

[0055] 218: anti-reflective coating layer

[0056] 220: backside anti-reflective coating layer

[0057] 222: photoresist layer

[0058] 222o: opening

[0059] 222s: photoresist strip

[0060] 224: second protective mask layer

[0061] 226: photoresist structure

[0062] 228: anti-reflective coating layer

[0063] 230: backside anti-reflective coating layer

[0064] 232: photoresist layer

[0065] 232ol: cut opening

[0066] 232os: cut opening

[0067] 234: cut mask

[0068] 236a: corner

[0069] 236e: end

[0070] 236f: flat portion

[0071] 236l: conductive line

[0072] 236v: conductive via

[0073] 236ld: segment

[0074] 236lu: segment DETAILED DESCRIPTION

[0075] The detailed description set forth below provides a description of various different embodiments or examples of the provided subject matter. The detailed description includes specific examples of assemblies and arrangements described herein. These are intended as examples only, and are not intended to limit the scope in any way. For example, in the description that follows, the formation of a first feature over or on a second feature can include embodiments in which the first and second features are formed in direct contact with each other, and can also include embodiments in which additional features can be formed between the first and second features, such that the first and second features can not be in direct contact. In addition, in various examples, the present disclosure can repeat use of certain elements or names thereof in the description and / or the drawings so as not to obscure the concepts further detailed below. Repeated use of certain elements' names in the description does not necessarily

[0076] Further, spatial or directional terms, such as "under", "below", "lower", "over", "upper", and the like, can be used in this specification to describe the relative position of one element to another element as illustrated in the figures. The spatial or directional terms are used for purposes of clarity and convenience in understanding the descriptions of the figures and are likewise intended to be non-limiting terms of orientation. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial or directional descriptions used herein can likewise be interpreted in a corresponding manner.

[0077] Embodiments of the present disclosure provide methods for forming conductive lines having dielectric cut features. In particular, embodiments of the present disclosure provide methods for forming conductive line patterns by first forming a line pattern, and then forming a cut pattern over the line pattern. The cut pattern can be formed by forming cut openings having a width less than the width of the lines in the line pattern, and then filling the cut openings with a masking material.

[0078] Figure 1 A flowchart of a method 100 for fabricating a semiconductor element in accordance with embodiments of the present disclosure. In particular, the method 100 is directed to a process of forming conductive lines in a semiconductor element. Figures 2 to 6 、 Figures 7A to 7C To Figures 12A to 12C 、 Figures 13 to 14 And Figures 15A to 15C A semiconductor element 200 is schematically illustrated at various stages of fabrication in accordance with the method 100. Figures 2 to 6 、 Figures 7A to 12A 、 Figures 13 to 14 、 Figure 15A Schematic perspective views of the semiconductor element 200 at various intermediate stages of forming the conductive lines. Figures 7B to 12B And Figure 15C are cross-sectional views of the semiconductor element 200 along the line B-B illustrated in Figure 6 Figures 7C to 12C And​Figure 15C semiconductor element 200 along the line C-C illustrated in Figure 6

[0079] Method 100 involves patterning and forming conductive lines in a layer of dielectric material. In some embodiments, the conductive lines can be part of a metallization structure or an interconnect structure of a semiconductor element. The conductive lines can be formed from an electrically conductive material such as a metal. For example, the conductive lines formed using the techniques described herein can be used to form conductive interconnect structures as part of a back end of line (BEOL) process or a front end of line (FEOL) process.

[0080] In some embodiments, semiconductor element 200 is processed as part of a larger wafer. A singulation process can be applied to the scribe line regions of the wafer to separate individual semiconductor dies from the wafer.

[0081] As illustrated in Figure 2 semiconductor element 200 includes a substrate 202. In some embodiments, substrate 202 includes various features formed thereon. For example, substrate 202 can include active elements, interconnect structures, and the like.

[0082] Substrate 202 can include a semiconductor material such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Substrate 202 can include other semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or combinations thereof. Other substrates can also be used such as a multilayer or graded substrate. Elements (not shown) such as transistors, for example, planar transistors, field effect transistors (FETs), fin field effect transistors (Fin-FETs), horizontal gate all around (HGAA) fin field effect transistors, vertical gate all around (VGAA) fin field effect transistors, diodes, capacitors, resistors, semiconductor elements, or other suitable elements can be formed in and / or on an active surface of the semiconductor material in substrate 202. Interconnect structures such as interlayer dielectric layers, etch stop layers, intermetal dielectric layers can also be included in substrate 202.​

[0083] The semiconductor element 200 can include a dielectric layer 206 formed over the substrate 202. According to the method 100 described herein, a conductive line is formed in the dielectric layer 206.

[0084] In some embodiments, the dielectric layer 206 is an IMD layer. In some embodiments, the dielectric layer 206 can be formed over an inter-layer dielectric (ILD) layer on the substrate 202. In other embodiments, the dielectric layer 206 can be an inter-layer dielectric layer formed over a dielectric layer in a source / drain region or a gate of a transistor (e.g., a fin field effect transistor), an interconnect structure, or an inter-layer dielectric layer used in other types of metallization structures. For example, the dielectric layer 206 can be formed over a fin structure, a metal gate, or a source / drain region in one or more fin field effect transistors formed in the substrate 202.

[0085] In some embodiments, the dielectric layer 206 includes one or more layers of dielectric material, such as a nitride material, such as silicon nitride (SiN), an oxide material, such as silicon oxide (SiO), TEOS, BPTEOS, or the like. The dielectric layer 206 can also be a low-k dielectric material, a polymer material, other dielectric material, the like, or a combination thereof. The dielectric layer 206 can be formed by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), plasma vapor deposition (PVD), or the like.

[0086] In some embodiments, the dielectric layer 206 can be in physical contact with the substrate 202. In other embodiments, any number of intermediate layers can be disposed between the dielectric layer 206 and the substrate 202. These intermediate layers can include an inter-metal dielectric layer or a dielectric layer, and can have contact plugs, conductive lines, and / or via features formed therein, or can include one or more intermediate layers, such as etch stop layers, adhesion layers, and the like, combinations thereof, and the like.

[0087] In Figure 2In one example, an alternative etch stop layer 204 may be provided directly beneath the dielectric layer 206. The etch stop layer 204 may, for example, serve as a stop layer for subsequent etch processes performed on the dielectric layer 206. The materials and processes used to form the etch stop layer 204 may depend on the material of the dielectric layer 206. In some embodiments, the etch stop layer 204 may be formed from silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCON), silicon carbide (SiC), silicon carbonitride (SiOC), silicon carbonitride (SiCN), silicon oxide (SiO), other dielectrics, the like, or combinations thereof. The etch stop layer 204 may be formed by plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, plasma vapor deposition, or the like. Other materials and processes may be used to form the etch stop layer 204.

[0088] Method 100 can be used to pattern the dielectric layer 206 to form conductive lines with diced openings. Figures 2 to 15C In the example illustrated, two patterning processes are used to form a conductive line pattern in dielectric layer 206. A first patterning process is performed to form a mask strip. A second patterning process is then performed to form dicing features between the mask strips. The mask strips and dicing features are then transferred to dielectric layer 206 to form line openings with end spacing corresponding to the dicing features.

[0089] In operation 102 of method 100, a first hard masking layer 208 is deposited on dielectric layer 206, such as Figure 2 As illustrated in the figure. In subsequent processing steps, a pattern is formed on the first hard mask layer 208 using the patterning techniques described herein. The patterned first hard mask layer 208 is then used as an etch mask for patterning the dielectric layer 206. In some embodiments, the material composition of the first hard mask layer 208 may be selected to provide high etch selectivity relative to a mask layer subsequently formed over the first hard mask layer 208. The first hard mask layer 208 may comprise more than one layer and contain more than one material.

[0090] The first hard masking layer 208 may be formed from an oxide material such as titanium oxide, silicon oxide, or the like; a nitride material such as silicon nitride, boron nitride, titanium nitride, tantalum nitride; a carbide material such as tungsten carbide, silicon carbide; a semiconductor material such as silicon; a metal such as titanium, tantalum; or a combination thereof. In some embodiments, when the dielectric layer 206 contains a low dielectric constant material, the first hard masking layer 208 may be formed from an oxide material or silicon nitride.

[0091] The first hardmask layer 208 can be formed using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. In some embodiments, the first hardmask layer 208 has a thickness between about 100 Angstroms and about 200 Angstroms. In other embodiments, the first hardmask layer 208 can have another thickness that is suitable for the critical dimensions of features to be patterned in the dielectric layer 206 and the first hardmask layer 208.

[0092] In operation 104 of the method 100, a second hardmask layer 210 is formed over the first hardmask layer 208, as illustrated in FIG. 2B. In subsequent processing steps, a pattern is formed on the second hardmask layer 210 using the patterning techniques described herein. The second hardmask layer 210 can be formed from a material including an oxide material such as titanium oxide, silicon oxide, or the like; a nitride material such as silicon nitride, boron nitride, titanium nitride, tantalum nitride; a carbide material such as tungsten carbide, silicon carbide; a semiconductor material such as silicon; a metal such as titanium, tantalum; or a combination thereof. Figure 2

[0093] As discussed later, the second hardmask layer 210 is used as an etch mask for etching the first hardmask layer 208 and transferring the pattern of the second hardmask layer 210 to the first hardmask layer 208. The second hardmask layer 210 can be formed from a different material than the first hardmask layer 208. Alternatively, the first hardmask layer 208 can include more than one layer and include more than one material and can include a different material than the second hardmask layer 210. In some embodiments, when the first hardmask layer 208 includes an oxide material or silicon nitride, the second hardmask layer 210 can be formed from titanium nitride, tungsten, silicon, titanium oxide, or a metal oxide.

[0094] The second hardmask layer 210 can be formed by processes such as chemical vapor deposition, atomic layer deposition, or the like. Other processes and materials can be used to form the second hardmask layer 210. In some embodiments, the second hardmask layer 210 has a thickness between about 100 Angstroms and about 300 Angstroms. In other embodiments, the second hardmask layer 210 can have another thickness that is suitable for the critical dimensions of features to be patterned in the dielectric layer 206, the first hardmask layer 208, or the second hardmask layer 210.

[0095] In operation 106 of the method 100, a third hardmask layer 212 is formed over the second hardmask layer 210, as illustrated in FIG. 2C. In subsequent processing steps, a pattern is formed on the third hardmask layer 212 using the patterning techniques described herein. The third hardmask layer 212 can be formed from a material including an oxide material such as titanium oxide, silicon oxide, or the like; a nitride material such as silicon nitride, boron nitride, titanium nitride, tantalum nitride; a carbide material such as tungsten carbide, silicon carbide; a semiconductor material such as silicon; a metal such as titanium, tantalum; or a combination thereof. Figure 2 ​The third hard mask layer 212 is formed over the second hard mask layer 210, as illustrated in

[0096] The third hard mask layer 212 can be formed from a material including an oxide material such as titanium oxide, silicon oxide, or the like; a nitride material such as silicon nitride, boron nitride, titanium nitride, tantalum nitride; a carbide material such as tungsten carbide, silicon carbide; a semiconductor material such as silicon; a metal such as titanium, tantalum; or a combination thereof. The third hard mask layer 212 can include more than one layer and more than one material, and can include a different material than the second hard mask layer 210. In some embodiments, the third hard mask layer 212 can be formed from an oxide material or silicon nitride when the second hard mask layer 210 includes titanium nitride, tungsten, silicon, titanium oxide, or a metal oxide.

[0097] The third hard mask layer 212 can be formed using a process such as chemical vapor deposition, atomic layer deposition, or the like. In some embodiments, the material composition of the third hard mask layer 212 can be determined to provide a high etch selectivity with respect to other layers such as the first hard mask layer 208, the second hard mask layer 210, the protective mask layer 214 described below, or other layers.

[0098] In some embodiments, the third hard mask layer 212 has a thickness between about 100 Angstroms and about 300 Angstroms. In other embodiments, the third hard mask layer 212 can have another thickness suitable for the critical dimensions of features to be patterned in the dielectric layer 206, the first hard mask layer 208, the second hard mask layer 210, or the third hard mask layer 212.

[0099] In operation 108 of the method 100, a protective mask layer 214 is formed over the third hard mask layer 212, as illustrated in Figure 2 In subsequent processing steps, a pattern is formed on the protective mask layer 214 using the patterning techniques described herein. The patterned protective mask layer 214 is then used as an etch mask for patterning the third hard mask layer 212.

[0100] The protective mask layer 214 can be formed from a suitable dielectric material. In some embodiments, the protective mask layer 214 is a carbon material such as a carbon-containing polymer material, for example, a spin-on-carbon (SOC) material or the like, a carbon layer deposited using a chemical vapor deposition process, or another type of carbon material. The protective mask layer 214 can include more than one layer and more than one material.

[0101] The protective mask layer 214 can be formed by a suitable process, such as chemical vapor deposition, atomic layer deposition, Plasma-Enhanced Atomic Layer Deposition (PEALD), spin coating, or the like. In some embodiments, the protective mask layer 214 has a thickness between about 200 Angstroms and about 500 Angstroms. In other embodiments, the protective mask layer 214 can have another thickness suitable for the critical dimensions of the features to be patterned in the dielectric layer 206, the first hard mask layer 208, the second hard mask layer 210, the third hard mask layer 212, or in the protective mask layer 214.

[0102] In operation 110 of the method 100, a photoresist structure 216 is formed over the protective mask layer 214, as illustrated in FIG. 1B. In one embodiment, the photoresist structure 216 can be selected to be suitable for extreme ultraviolet (EUV) photolithography. Figure 2 The photoresist structure 216 illustrated in FIG. 1B includes an anti-reflection coating (ARC) layer 218 formed over the protective mask layer 214, a backside anti-reflection coating (BARC) layer 220 formed over the anti-reflection coating layer 218, and a photoresist layer 222 formed over the backside anti-reflection coating layer 220. The photoresist structure 216 can be referred to as a three-layer photoresist structure. In other embodiments, one or both of the anti-reflection coating layer 218 and the backside anti-reflection coating layer 220 can be omitted to form a two-layer photoresist structure or a single-layer photoresist structure. Figure 2 The anti-reflection coating layer 218 can be a material such as silicon oxycarbide (SiOC), silicon, silicon oxynitride, titanium oxide, silicon oxide, silicon nitride, a polymer, or a combination thereof. The anti-reflection coating layer 218 contains a material that is patternable and / or has a composition that is tuned to provide anti-reflective properties. The anti-reflection coating layer 218 can be formed by a spin coating process. In other embodiments, the anti-reflection coating layer 218 can be formed by another suitable deposition process. The anti-reflection coating layer 218 can have a thickness between about 50 Angstroms and 300 Angstroms.

[0103]

[0104] ​The backside anti-reflective coating layer 220 can have a composition that provides anti-reflective properties and / or hard mask properties for the photolithography process. In one embodiment, the backside anti-reflective coating layer 220 includes a silicon-containing layer, such as a silicon hard mask material. The backside anti-reflective coating layer 220 can include a silicon-containing inorganic polymer. In other embodiments, the backside anti-reflective coating layer 220 includes a siloxane polymer, such as a polymer having a backbone of O-Si-O-Si. The silicon ratio of the backside anti-reflective coating layer 220 can be selected to control the etch rate. In other embodiments, the backside anti-reflective coating layer 220 can include silicon oxide, for example, spin-on glass (SOG), silicon nitride, silicon oxynitride, polysilicon, metal-containing organic polymer materials containing metals such as titanium, titanium nitride, aluminum, and / or tantalum; and / or other suitable materials. The backside anti-reflective coating layer 220 can be omitted when there is good adhesion between the anti-reflective coating layer 218 and the photoresist layer 222. The backside anti-reflective coating layer 220 can have a thickness between about 50 Angstroms and 300 Angstroms.

[0105] The photoresist layer 222 can be a positive photoresist layer or a negative photoresist layer. In some embodiments, the photoresist layer 222 is made of polymethyl methacrylate (PMMA), polymethyl glutarimide (PMGI), phenol formaldehyde resin (DNQ / Novolac), or SU-8. In one embodiment, the photoresist layer 222 can have a thickness between about 200 Angstroms and 500 Angstroms.

[0106] In operation 114 of the method 100, the photoresist layer 222 is patterned using a photolithography process, as illustrated in FIG. 2B. In some embodiments, the photoresist layer 222 can be patterned using an extreme ultraviolet photolithography process, which uses extreme ultraviolet lasers or soft X-rays, i.e., radiation with a wavelength shorter than 130 nanometers. Figure 3

[0107] As illustrated in FIG. 2B, the patterned photoresist layer 222 forms a plurality of photoresist strips 222s separated by a plurality of openings 222o. The plurality of openings 222o exposes the backside anti-reflective coating layer 220 (if present), or the anti-reflective coating layer 218 if the backside anti-reflective coating layer 220 is not present. Figure 3

[0108] The openings 222o can be parallel to each other. Adjacent openings 222o can be separated by a photoresist strip 222s. In some embodiments, the openings 222o and the photoresist strips 222s can extend along the Y-axis length direction. Perpendicular to the length direction, i.e., along the X-axis, each opening 222o can have a width Wl. Each of the plurality of photoresist strips 222s can have a width W2 along the X-axis.

[0109] ​​In some embodiments, the openings 222o correspond to openings for conductive lines to be formed in the dielectric layer 206. The width Wl of the openings 222o corresponds to a minimum line width of the semiconductor elements to be formed, i.e., a critical dimension of the line width. In some embodiments, the width Wl is between about 15 nanometers and about 25 nanometers. The width W2 of the photoresist strips 222s corresponds to a minimum line-to-line spacing of the semiconductor elements to be formed, i.e., a critical dimension of the line-to-line spacing. In some embodiments, the width W2 is between about 15 nanometers and about 25 nanometers.

[0110] Even though a single photo-lithographic patterning process is described in operation 112, two or more photo-lithographic patterning processes, i.e., multiple patterning, can be used to allow for smaller pitches of the patterned features. Other photo-lithographic techniques, including additional or different steps, are within the scope of the present disclosure.

[0111] In operation 114 of the method 100, the pattern of the photoresist layer 222 is transferred to the third hard mask layer 212, as illustrated in FIG. 2B. In some embodiments, one or more anisotropic etching processes are used to transfer the pattern of the photoresist layer 222 onto the third hard mask layer 212 to sequentially etch through the backside anti-reflective coating layer 220, the anti-reflective coating layer 218, the protective mask layer 214, and the third hard mask layer 212. Figure 4

[0112] In some embodiments, the patterned photoresist layer 222 is used as a mask to pattern the backside anti-reflective coating layer 220. Accordingly, the pattern of the photoresist layer 222 is transferred to the backside anti-reflective coating layer 220 and a patterned backside anti-reflective coating layer 220 is formed. After the backside anti-reflective coating layer 220 is patterned, the patterned backside anti-reflective coating layer 220 is used to pattern the anti-reflective coating layer 218. The backside anti-reflective coating layer 220 and the anti-reflective coating layer 218 can be patterned using a plasma process, for example, by patterning the backside anti-reflective coating layer 220 and the anti-reflective coating layer 218 with one or more process gases such as tetrafluoromethane (CF4), difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), chlorine (CI2), argon (Ar), oxygen (O2), nitrogen (N2), ammonia (NH3), hydrogen (H2), another type of gas, or a combination thereof. The etching process can be anisotropic so that the openings 222o in the photoresist layer 222 extend through the anti-reflective coating layer 218 and the openings 222o have about the same size in the anti-reflective coating layer 218 as in the photoresist layer 222.

[0113] ​The pattern of the anti-reflective coating layer 218 is then transferred to the protective mask layer 214 in an etching process. The etching process can be anisotropic so that the openings in the anti-reflective coating layer 218 extend through the protective mask layer 214 and the openings have about the same size in the protective mask layer 214 as in the anti-reflective coating layer 218. The etching process to etch the protective mask layer 214 can include a wet etching process, a dry etching process, or a combination thereof. A plasma etching process can include one or more process gases such as tetrafluoromethane, difluoromethane, fluoromethane, trifluoromethane, chlorine, argon, oxygen, another type of suitable process gas, or a combination thereof. For example, in some embodiments, process gases including fluorine such as tetrafluoromethane, difluoromethane, fluoromethane, or trifluoromethane can be used to etch layers formed of some dielectric materials, while process gases including chlorine such as chlorine can be used to etch layers formed of materials such as silicon or titanium nitride. Other etching techniques can be used in other embodiments. During etching of the protective mask layer 214, the patterned anti-reflective coating layer 218 can be consumed and the third hard mask layer 212 can be at least partially consumed.

[0114] The pattern of the protective mask layer 214 is transferred to the third hard mask layer 212 in an etching process. The etching process can be anisotropic so that the openings in the protective mask layer 214 extend through the third hard mask layer 212 and the openings have about the same size in the third hard mask layer 212 as in the protective mask layer 214. As Figure 4 As illustrated in FIG. 1 IB, after operation 114, a plurality of mask strips 212s are formed in the third hard mask layer 212. Adjacent mask strips 212s are separated by openings 212o formed through the third hard mask layer 212. The openings 212o have about the same size as the openings 222o. The mask strips 212s have about the same size as the photoresist strips 222s.

[0115] The etching process to etch the third hard mask layer 212 can include a wet etching process, a dry etching process, or a combination thereof. A plasma etching process can include one or more process gases such as tetrafluoromethane, fluoromethane, perfluorobutadiene (C4F6), octafluorocyclobutane (C4F8), another type of suitable gas, or a combination thereof. Other etching techniques can be used in other embodiments.

[0116] After etching the third hard mask layer 212, portions of the protective mask layer 214 can remain. In some embodiments, the remaining portions of the protective mask layer 214 can be removed using, for example, a wet etching process. In other embodiments, the remaining portions of the protective mask layer 214 are left over the patterned third hard mask layer 212, for example, to be used as a protective layer.

[0117] In operation 116 of the method 100, a second protective mask layer 224 is deposited over the patterned third hard mask layer 212, as illustrated in Figure 5 The material of the second protective mask layer 224 fills the openings 212o in the third hard mask layer 212 formed in operation 114.

[0118] The second protective mask layer 224 can be similar to the protective mask layer 214. The second protective mask layer 224 is a carbon material layer, such as, for example, a spin-on carbon material or a similar carbon-containing polymer material, a carbon layer deposited using a chemical vapor deposition process, or another type of carbon material. The second protective mask layer 224 can be formed by, for example, chemical vapor deposition, atomic layer deposition, plasma-enhanced atomic layer deposition, spin coating, or a similar suitable process. In some embodiments, the second protective mask layer 224 has a thickness between about 200 Angstroms and about 500 Angstroms. In some embodiments, the thickness of the second protective mask layer 224 is measured from the top surface of the third hard mask layer 212. In other embodiments, the second protective mask layer 224 can have another thickness suitable for the critical dimensions of the features to be patterned in the dielectric layer 206, the first hard mask layer 208, the second hard mask layer 210, the third hard mask layer 212, or the second protective mask layer 224.

[0119] In operation 118 of the method 100, a second photoresist structure 226 is formed over the second protective mask layer 224, as illustrated in Figure 6 The photoresist structure 226 can be similar to the photoresist structure 216. In one embodiment, the photoresist structure 226 is a three-layer photoresist including an anti-reflective coating layer 228, a backside anti-reflective coating layer 230, and a photoresist layer 232.

[0120] The anti-reflective coating layer 228 can be a material such as silicon oxycarbide, silicon, silicon oxynitride, titanium oxide, silicon oxide, silicon nitride, a polymer, or a combination thereof. The anti-reflective coating layer 228 can have a thickness between about 50 Angstroms and 300 Angstroms.

[0121] The backside anti-reflective coating layer 230 can have a composition that provides anti-reflective properties and / or hard mask properties for a photolithography process. In one embodiment, the backside anti-reflective coating layer 230 includes a silicon-containing layer, such as a silicon hard mask material. The backside anti-reflective coating layer 230 can have a thickness between about 50 Angstroms and 300 Angstroms.

[0122] The photoresist layer 232 can be a positive photoresist layer or a negative photoresist layer. In some embodiments, the photoresist layer 232 is made of polymethyl methacrylate, polymethyl glutarimide, phenol formaldehyde resin (DNQ / Novolac), or SU-8. In one embodiment, the photoresist layer 232 can have a thickness between about 200 Angstroms and 500 Angstroms.

[0123] In operation 120 of the method 100, the photoresist layer 232 is patterned using a photolithography process to form one or more cut openings, as Figures 7A to 7C illustrated. In some embodiments, the photoresist layer 232 can be patterned using an extreme ultraviolet photolithography process.

[0124] As Figure 7A illustrated, the photoresist layer 232 is patterned to form one or more cut openings 232ol, 232os. The cut openings 232ol, 232os expose the backside anti-reflective coating layer 230 if present, or the anti-reflective coating layer 228 if the backside anti-reflective coating layer 230 is not present.

[0125] In some embodiments, the cut openings 232ol, 232os can extend in length along the X-axis. The cut openings 232ol, 232os can have lengths LI, L2 that vary along the X-axis, respectively. The cut openings 232ol, 232os can have substantially the same width W3, which is perpendicular to the length direction, e.g., along the Y-axis.

[0126] The cut openings 232ol, 232os in the photoresist layer 232 are intended to facilitate cut features between the mask strips 212s in the third hard mask layer 212. Accordingly, the cut openings 232ol, 232os are formed at locations corresponding to line end spacing between adjacent conductive lines to be formed in the dielectric layer 206. Each cut opening 232ol, 232os can extend in length along the X-axis, across one or more openings 212o, forming one or more openings 212o in the third hard mask layer 212 and filled with the material of the second protective mask layer 224. In some embodiments, each cut opening 232ol, 232os will also intersect the mask strips 212s on both sides of the openings 212o. As Figure 7B illustrated, the cut opening 232ol extends along the X-axis, covering two openings 212o and intersecting three mask strips 212s. The cut opening 232os intersecting one opening 212o will facilitate the formation of a cut feature for a single conductive line. The cut opening 232ol intersecting two openings 212o will facilitate the formation of cut features in two adjacent conductive lines. Cut openings of longer lengths can be formed according to the circuit layout and intersect more openings 212o.

[0127] In some embodiments, the width W3 of the cut openings 232ol, 232os is formed wider than the intended width of the cut opening features to be formed in the dielectric layer 206. In some embodiments, the width W3 can be similar to the critical dimension of the line width of the conductive lines to be formed or the line width W1 of the openings 212o. As discussed later, during subsequent pattern transfer, the width of the cut openings is reduced from the width of the cut openings in the photoresist layer 232 to a narrower width in the third hardmask layer 212 and the second protective mask layer 224 as needed, thereby reducing the line end spacing between the conductive lines to be formed. As Figure 7C illustrated in FIG. 2B, the width of the cut openings to be formed in the third hardmask layer 212 and the second protective mask layer 224 has a width W4, which is narrower than the width W3 of the cut openings 232ol, 232os. In some embodiments, the width W4 is in the range of less than about 50% of the width W1 of the openings 212o.

[0128] In some embodiments, the length of the cut openings in the photoresist layer 232 can also be longer than the intended length of the cut openings to be formed in the third hardmask layer 212 and the second protective mask layer 224. As illustrated in FIG. 2B, the length L2 of the cut openings 232ol is longer than the intended length L3 of the cut openings to be formed in the third hardmask layer 212 and the second protective mask layer 224. The increased length in the cut openings 232ol, 232os provides a tolerance for size reduction in subsequent pattern transfer operations. Figure 7B

[0129] In operation 122 of the method 100, the pattern of the photoresist layer 232 is transferred to the third hardmask layer 212, as illustrated in FIG. 2C. In some embodiments, the pattern of the photoresist layer 232 is then transferred to the third hardmask layer 212 using one or more etching processes to sequentially etch through the backside anti-reflective coating layer 230, the anti-reflective coating layer 228, the second protective mask layer 224, and the third hardmask layer 212. Figures 8A to 8C

[0130] In some embodiments, the width of the cut openings is reduced from the width W3 of the cut openings 232ol, 232os to the width W4 during one or more steps of the pattern transfer from the photoresist layer 232 to the second protective mask layer 224. In some embodiments, the length of the cut openings is correspondingly reduced during one or more steps of the pattern transfer from the photoresist layer 232 to the second protective mask layer 224.

[0131] In Figures 8A to 8C ​​In the embodiment illustrated in FIG. 2, the width of the cut opening is reduced from the width W3 of the cut opening 232ol, 232os to the width W4 of the cut opening 228ol during the pattern transfer from the photoresist layer 232 to the anti-reflective coating layer 228. Alternatively, the pattern transfer from the photoresist layer 232 to the anti-reflective coating layer 228 can be a non-isotropic etch for direct pattern transfer, while the width of the cut opening is reduced during the pattern transfer from the anti-reflective coating layer 228 to the second protective mask layer 224. In another embodiment, the pattern transfer from the photoresist layer 232 to the anti-reflective coating layer 228 and the pattern transfer from the anti-reflective coating layer 228 to the second protective mask layer 224 both reduce the width of the cut opening.

[0132] In some embodiments, the backside anti-reflective coating layer 230, if present, is patterned using the patterned photoresist layer 232 as a mask. Accordingly, the pattern of the photoresist layer 232 is transferred to the backside anti-reflective coating layer 230 and a patterned backside anti-reflective coating layer 230 is formed. The backside anti-reflective coating layer 230 can be patterned using a plasma process, for example, by patterning the backside anti-reflective coating layer 230 with one or more process gases such as tetrafluoromethane, difluoromethane, fluoromethane, trifluoromethane, chlorine, argon, oxygen, nitrogen, ammonia, hydrogen, another type of gas, or a combination thereof.

[0133] The anti-reflective coating layer 228 is patterned using the patterned photoresist layer 232 or the patterned backside anti-reflective coating layer 230, if present. In some embodiments, the anti-reflective coating layer 228 can be patterned using a plasma process, for example, by patterning the anti-reflective coating layer 228 with one or more process gases such as tetrafluoromethane, difluoromethane, fluoromethane, trifluoromethane, chlorine, argon, oxygen, nitrogen, ammonia, hydrogen, another type of gas, or a combination thereof.

[0134] In some embodiments, the etching gas can include two or more etchants having different etching properties to control the size of the openings formed in the anti-reflective coating layer 228 relative to the size of the openings in the etching mask, such as the patterned photoresist layer 232 and / or the patterned backside anti-reflective coating layer 230. In some embodiments, the etching gas includes a direct etchant and a size-reducing etchant. The direct etchant, when used alone, transfers the pattern directly from the mask to the layer being etched. The size-reducing etchant, when used alone, forms openings having a reduced size compared to the features in the mask. The ratio of the direct etchant and the size-reducing etchant can be adjusted to achieve a target size reduction. In some embodiments, the direct etchant includes tetrafluoromethane and the size-reducing etchant includes trifluoromethane. The ratio of tetrafluoromethane and trifluoromethane in the etching gas is selected to achieve a desired ratio of opening width reduction.

[0135] As Figures 8A to 8CAs illustrated in the middle, the cut openings 228ol, 228os are formed through the anti-reflective coating layer 228. The width W4 of the cut openings 228ol, 228os is less than the width W3 of the cut openings 232ol, 232os. In some embodiments, the ratio of the width W4 to the width W3 is in a range between 80% to 40%. In some embodiments, the length L3, L4 of the cut openings 228os, 228ol are also reduced in similar dimensions. For example, if the width W4 of the cut openings 228os, 228ol is 12 nanometers narrower than the width W3 of the cut openings 232ol, 232os, then the length L3, L4 of the cut openings 228os, 228ol are about 12 nanometers shorter than the length LI, L2 of the cut openings 232ol, 232os, respectively. The etching gas can include tetrafluoromethane and trifluoromethane. The ratio of the tetrafluoromethane and trifluoromethane is selected to achieve a desired width reduction. In some embodiments, the ratio of the tetrafluoromethane and trifluoromethane is in a range between about 1:0.2 to about 0.8:1. A higher ratio of the tetrafluoromethane and trifluoromethane corresponds to a higher ratio of the width W4 to the width W3. For example, when the ratio of the tetrafluoromethane and trifluoromethane is about 1:0, the ratio of the width W4 to the width W3 is about 100%. When the ratio of the tetrafluoromethane and trifluoromethane is about 1:1, the ratio of the width W4 to the width W3 is about 50%.

[0136] The pattern of the anti-reflective coating layer 228 is then transferred to the second protective mask layer 224 by an etching process. The etching process can be anisotropic so that the cut openings 228ol, 228os in the anti-reflective coating layer 228 extend through the second protective mask layer 224 to form cut openings 224ol, 224os. The cut openings 224ol, 224os expose portions of the mask strips 212s and the second hard mask layer 210 in the areas corresponding to the openings 212o. The etching process to etch the second protective mask layer 224 can include a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the dry etching process can be a plasma etching process using one or more process gases such as tetrafluoromethane, difluoromethane, fluoromethane, trifluoromethane, chlorine, argon, oxygen, another type of process gas, or a combination thereof.

[0137] In some embodiments, the exposed portions of the mask strips 212s can be removed during the etching process of the anti-reflective coating layer 228. In other embodiments, the etching process to remove the exposed portions of the mask strips 212s can be omitted and the exposed portions of the mask strips 212s are left as part of the mask to be formed in subsequent operations.

[0138] In operation 124, a cut mask 234 is formed within the cut openings 228ol, 228os in the anti-reflective coating layer 228 and the cut openings 224ol, 224os in the second protective mask layer 224, as illustrated in FIG. 2C. Figures 9A to 9C and Figures 11A to 11C .

[0139] A mask material can be used to fill the cut openings 228ol, 228os in the anti-reflective coating layer 228 and the cut openings 224ol, 224os in the second protective mask layer 224, as illustrated in FIG. 2C. Figures 9A to 9C The mask material can have properties similar to those of the material of the third hard mask layer 212, so that the cut mask 234 and the mask strips 212s together are used as an etch mask for patterning the second hard mask layer 210.

[0140] The cut mask 234 can be formed from a material including an oxide material such as titanium oxide, silicon oxide, or similar oxide materials; a nitride material such as silicon nitride, boron nitride, titanium nitride, tantalum nitride; a carbide material such as tungsten carbide, silicon carbide; a semiconductor material such as silicon; a metal such as titanium, tantalum; or a combination thereof. In some embodiments, when the second hard mask layer 210 includes titanium nitride, tungsten, silicon, titanium oxide, or metal oxide, the cut mask 234 can be formed from an oxide material or silicon nitride.

[0141] The cut mask 234 can be formed using a process such as chemical vapor deposition, atomic layer deposition, or similar processes. In some embodiments, the cut mask 234 is formed by filling the cut openings 228ol, 228os in the anti-reflective coating layer 228 and the cut openings 224ol, 224os in the second protective mask layer 224 by an atomic layer deposition process.

[0142] After filling the cut openings 228ol, 228os in the anti-reflective coating layer 228 and the cut openings 224ol, 224os in the second protective mask layer 224, a planarization process such as chemical mechanical polishing (CMP) is used to expose the anti-reflective coating layer 228, as illustrated in FIG. 2D. Figures 10A to 10C

[0143] The anti-reflective coating layer 228 and the second protective mask layer 224 are then removed to expose the cut mask 234, as illustrated in FIG. 2E. In addition to the portions occupied by the cut mask 234, the openings 212o formed in the third hard mask layer 212 in operation 122 are reestablished. The cut mask 234 and the mask strips 212s in the third hard mask layer 212 are then used together to pattern the second hard mask layer 210. Figures 11A to 11C

[0144] ​​In operation 126 of the method 100, the pattern defined by the mask strips 212s and the cut mask 234 in the third hardmask layer 212 is transferred to the second hardmask layer 210 in an etch process, as illustrated in FIGS. 10D-10F. Figures 12A to 12C

[0145] The etch process can be anisotropic so that the openings 212o in the third hardmask layer 212 extend through the second hardmask layer 210 and have about the same size in the second hardmask layer 210 as in the third hardmask layer 212. The resulting structure is illustrated in FIGS. 10A-10C. A pattern including mask strips 210s and mask cut features 210c is formed in the second hardmask layer 210. The mask strips 210s and mask cut features 210c define a plurality of line openings 210o. The line openings 210o are primarily elongated openings that are segmented by the mask cut features 210c.

[0146] The etch process to etch the second hardmask layer 210 can include a wet etch process, a dry etch process, or a combination thereof. In some embodiments, the dry etch process can be a plasma etch using one or more process gases such as Cl2, CH4, N2, HBr, another type of process gas, or a combination thereof. Other etch techniques can be used in other embodiments. In some embodiments, portions of the third hardmask layer 212 and the cut mask 234 can be preserved during etching of the second hardmask layer 210.

[0147] In operation 128 of the method 100, the mask strips 212s and the cut mask 234 in the second hardmask layer 210 are used as an etch mask to extend the openings 212o through the first hardmask layer 208 into the dielectric layer 206, thus forming openings 208o in the first hardmask layer 208 and openings 206o in the dielectric layer 206, as illustrated in FIGS. 10D-10F. Figure 13 Figure 14 In some embodiments, the openings 206o through the dielectric layer 206 can be formed as part of a conductive line patterning process such as a damascene patterning process.

[0148] Etching the dielectric layer 206 can include an anisotropic dry etch process and / or a wet etch process that etches through the first hardmask layer 208 into the dielectric layer 206. In some embodiments, the first hardmask layer 208 is etched in an etch step that is separate from the etch process to form the openings 206o in the dielectric layer 206. As illustrated in FIGS. 10D-10F, the openings 208o in the first hardmask layer 208 and the openings 206o in the dielectric layer 206 are aligned with each other. Figure 13 ​​As illustrated in FIG. 2, the pattern in the second hardmask layer 210 is transferred to the first hardmask layer 208. The unetched portions of the first hardmask layer 208 include mask strips 208s and mask cut features 208c. The unetched portions of the dielectric layer 206 can have the same pattern as the first hardmask layer 208. The unetched portions of the dielectric layer 206 include strips 206s and cut features 206c. The strips 206s and cut features 206c define openings 206o where conductive lines are to be formed. Since the pattern is transferred directly from the first hardmask layer 208 to the dielectric layer 206, the width of the openings 206o along the X-axis is substantially the same as the width Wl, and the width of the cut features 206c along the Y-axis is substantially the same as the width W4.

[0149] After the patterned openings 206o, a wet clean process can be performed to remove any remaining portions of the first hardmask layer 208. In some embodiments, an additional patterning process can be performed to form via openings 206v through the dielectric layer 206 and the etch stop layer 204, as illustrated in FIG. 2. The via openings 206v can expose contacts, metal lines, or other conductive features underneath the dielectric layer 206, such as conductive features in another layer underneath the substrate 202 or the dielectric layer 206. Figure 14

[0150] In operation 130 of the specification, as shown in FIG. 2, conductive lines 236l are formed in the patterned openings 206o in the dielectric layer 206, and conductive vias 236v can be formed in the via openings 206v. Figures 15A to 15C

[0151] As illustrated in FIG. 2, the width of the conductive lines 236l along the X-axis is substantially the same as the width Wl. Two conductive lines 236l can extend along the same line parallel to the Y-axis, separated by one cut feature 206c at the ends of the two conductive lines. As discussed previously, the width of the cut features 206c along the Y-axis is substantially the same as the width W4. Figure 15A Figure 15C

[0152] ​​​​In some embodiments, the width W1 of the conductive lines 2361 corresponds to a line width critical dimension in the semiconductor element 200, and the width W4 corresponds to a line end critical dimension in the semiconductor element 200. As discussed previously, the width W4 is reduced to a range between about 80% to about 40% of the width W1 during the formation of the cut mask 234. Thus, the line end critical dimension is smaller than the line width critical dimension that satisfies the design rules of the circuit design. The width W4 or the line end critical dimension is in a range between about 80% to about 40% of the width W1 or the line width critical dimension. If the line end critical dimension is greater than 80% of the line width critical dimension, the design rules of the circuit layout can not be well satisfied. If the line end critical dimension is less than 40% of the line width critical dimension, the cut features 206c can not provide sufficient isolation function between the conductive lines 2361. In some embodiments, the width W1 or the line end critical dimension of the semiconductor element 200 is between about 15 nanometers to about 25 nanometers, and the width W4 is less than about 12 nanometers, for example, in a range between about 12 nanometers and about 6 nanometers.

[0153] The conductive lines 2361 and the conductive via features 236v can be formed by filling the openings 206o and the via feature openings 206v with a conductive material. The conductive material can include cobalt (Co), copper (Cu), silver (Ag), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), nickel (Ni), tungsten (W), zinc (Zn), calcium (Ca), gold (Au), magnesium (Mg), molybdenum (Mo), chromium (Cr), or the like. The conductive material can be formed by chemical vapor deposition, plasma vapor deposition, plating, atomic layer deposition, or other suitable techniques. In some embodiments, one or more liners (not shown) can be formed along the sidewalls and bottom surfaces of the openings 206o and the via feature openings 206v prior to filling with the conductive material, and the conductive lines 2361 and the conductive via features 236v include the one or more liners and the conductive fill material. The liners can include titanium oxide (TiO), titanium nitride (TiN), tantalum oxide (TaO), tantalum nitride (TaN), or the like, and can provide a diffusion barrier, adhesion, and / or seed layer for the conductive lines.

[0154] Subsequently, a chemical mechanical polishing process is performed to remove excess conductive material and expose the dielectric layer 206. After operation 130, interconnect structures or adhesion pad layers can be formed on the dielectric layer 206 according to the circuit design.

[0155] The semiconductor element according to the present disclosure not only has an improved line end critical dimension, but also has an improved line end profile. Figure 16AA schematic plan view of an example of a dielectric layer 206 having conductive lines 236l, according to an embodiment of the present disclosure. Figure 16B for Figure 16A A partially enlarged view.

[0156] like Figure 16A As illustrated, multiple conductive lines 236l are formed in the dielectric layer 206. The conductive lines 236l are parallel to each other, and adjacent conductive lines 236l are separated by dielectric strips 206l. Each conductive line 236l is divided into segments 236lu and 236ld by dielectric cutting features 206c.

[0157] like Figure 16B As illustrated in the enlarged view, segments 236lu and 236ld have a line width W1. The line end spacing is W4, and the line spacing is W2. According to an embodiment of this disclosure, the line width W1 is less than about 25 nanometers, for example, in the range of about 15 nanometers to about 25 nanometers. The line end spacing W4 is in the range of about 80% to about 40% of W1. The line spacing W2 is substantially equal to the line width W1, or in the range of about 15 nanometers to about 25 nanometers.

[0158] Each segment 236ld, 236lu of the conductive line 236l has an end portion 236e facing the cut feature 206c. Compared to line ends formed by the present technology, the end portion 236e has a relatively flat profile. Specifically, the end portion 236e has a profile including two corners 236a connected by a flat segment 236f. ​​The corners 236a may have a radius R1. In some embodiments, the radius R1 may be less than about 20% of the line width W1, and the flat segment 236f may be greater than about 60% of the line width W1. The relatively flat end portion 236e and the segments 236ld, 236lu of the conductive line 236l improve the performance of the semiconductor device.

[0159] Compared to existing technologies, the various embodiments or examples described herein offer several advantages. Embodiments of this disclosure reduce line end spacing to better meet circuit layout design rules. Conductive lines according to this disclosure also provide a flatter line end profile for conductive lines near cut features, thereby improving component performance.

[0160] It will be understood that this document does not need to discuss all advantages, all embodiments or examples do not require specific advantages, and other embodiments or examples may provide different advantages.

[0161] Some embodiments of the present disclosure provide a method of fabricating a semiconductor device. The method includes depositing a first hardmask layer over a dielectric layer, forming a plurality of mask strips in the first hardmask layer, wherein the plurality of mask strips are separated by a plurality of openings, filling the plurality of openings between the plurality of mask strips with a first material, forming a cut opening through the first material, filling the cut opening with a second material, removing the first material to expose the second material and the plurality of mask strips, and patterning the dielectric layer using the plurality of mask strips and the second material. In some embodiments, the method further includes filling a conductive material in the dielectric layer after patterning the dielectric layer. In some embodiments, the mask strips extend in a lengthwise direction along a first direction, the cut opening extends in a lengthwise direction along a second direction perpendicular to the first direction, and the cut opening intersects two or more mask strips. In some embodiments, forming the cut opening in the first material includes forming a first opening having a first width in a photoresist layer, and performing an etching process using a size-reducing etchant to transfer the first opening in the photoresist layer to the first material to form the cut opening, wherein the cut opening has a second width, and the second width is smaller than the first width. In some embodiments, the method further includes depositing a backside anti-reflective coating layer over the first material before forming the first opening in the photoresist layer. The backside anti-reflective coating layer is etched using the size-reducing etchant to form a second opening having the second width. The first material is patterned using the backside anti-reflective coating layer. In some embodiments, the step of filling the first material in the openings includes forming a protective mask layer using the first material over the mask strips. In some embodiments, the method further includes depositing a second hardmask layer over the dielectric layer before forming the first hardmask layer. Depositing a third hardmask layer over the second hardmask layer, wherein the first hardmask layer is formed over the third hardmask layer. In some embodiments, patterning the dielectric layer includes patterning the third hardmask layer using the mask strips and the second material. Patterning the second hardmask layer using the third hardmask layer. Patterning the dielectric layer using the second hardmask layer.

[0162] Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The method includes depositing a first hardmask layer, depositing a second hardmask layer on the first hardmask layer, patterning the second hardmask layer to form a plurality of hardmask strips over the first hardmask layer, wherein the plurality of hardmask strips extend along a first direction, depositing a mask layer over the plurality of hardmask strips and the first hardmask layer, depositing a photoresist layer over the mask layer, patterning the photoresist layer to form a cut opening to expose at least one of the plurality of hardmask strips, forming a cut mask in the cut opening, wherein the cut mask extends along a second direction substantially perpendicular to the first direction, removing the mask layer and the photoresist layer, and patterning the first hardmask layer using the plurality of hardmask strips and the cut mask as etch masks. In some embodiments, forming the cut mask includes filling the cut opening with a mask material. In some embodiments, patterning the photoresist layer to form the cut opening includes forming a first opening in the photoresist layer, wherein a width of the first opening is substantially equal to a width of the hardmask strips. Forming the cut opening in the mask layer using the photoresist layer as an etch mask for a size-reduction etchant such that the cut opening is narrower than the first opening. In some embodiments, the method further includes forming the first opening in the photoresist layer. Forming a second opening in a backside anti-reflective coating layer formed on the mask layer using the photoresist layer as an etch mask, wherein the second opening is narrower than the first opening. Forming the cut opening in the mask layer using the backside anti-reflective coating layer as an etch mask. In some embodiments, the cut opening is narrower than the second opening. In some embodiments, the width of the first opening is substantially equal to the width of the hardmask strips, and the width of the cut opening is in a range between about 80% and about 40% of the width of the first opening.

[0163] Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a dielectric layer, a first conductive line formed in the dielectric layer, and a second conductive line formed in the dielectric layer, wherein the first conductive line and the second conductive line extend along a same direction, an end portion of the first conductive line faces an end portion of the second conductive line, an end-to-end spacing between the end portions of the first conductive line and the second conductive line is less than a line width of the first conductive line, and the line width is less than about 25 nanometers.

[0164] Some embodiments of the present disclosure include a method of fabricating a semiconductor device. The method includes depositing a dielectric layer, patterning the dielectric layer using an extreme ultraviolet patterning technique to form a first opening and a second opening in the dielectric layer, filling the first opening and the second opening in the dielectric layer to form a first conductive line and a second conductive line in the dielectric layer, wherein the first conductive line and the second conductive line extend along a same direction, an end portion of the first conductive line faces an end portion of the second conductive line, an end-to-end spacing between the end portions of the first conductive line and the second conductive line is less than a line width of the first conductive line, and the line width is less than about 25 nanometers. In some embodiments, the end-to-end spacing is in a range between about 80% to about 40% of the line width. In some embodiments, the end-to-end spacing is less than 50% of the line width. In some embodiments, patterning the dielectric layer further includes forming a third opening in the dielectric layer, and filling the third opening to form a third conductive line parallel to the first conductive line, a line-to-line spacing between the first conductive line and the third conductive line is substantially equal to the line width. In some embodiments, the end portion of the first conductive line includes a profile, the profile includes a first corner, a second corner, and a flat portion connecting the first corner and the second corner, wherein a length of the flat portion is between about 60% to about 80% of the line width. In some embodiments, a radius of the first corner is less than about 20% of the line width.

[0165] The foregoing summary of the embodiments is presented to provide a basic understanding of the aspects of the present disclosure. Those skilled in the art will appreciate that the foregoing summary is not an exhaustive list of the aspects of the present disclosure, and that the aspects of the present disclosure can be practiced in other ways not expressly described or contemplated herein.

Claims

1. A method of manufacturing a semiconductor element, characterized by, Comprising: depositing a first hardmask layer on a dielectric layer; forming a plurality of mask strips in the first hardmask layer, wherein the mask strips are separated by a plurality of openings; filling a first material in the openings between the mask strips; forming a cut opening through the first material, wherein the mask strips extend in a lengthwise direction along a first direction, the cut opening extends in a lengthwise direction along a second direction perpendicular to the first direction, and the cut opening intersects two or more mask strips; filling the cut opening with a second material; removing the first material to expose the second material and the mask strips; patterning the dielectric layer using the mask strips and the second material.

2. The method of claim 1, wherein, Further comprising: filling a conductive material in the dielectric layer after patterning the dielectric layer.

3. The method of claim 1, wherein, depositing a second hardmask layer on the dielectric layer prior to depositing the first hardmask layer, such that after depositing the first hardmask layer, the second hardmask layer is between the first hardmask layer and the dielectric layer, and after forming the cut opening, the cut opening exposes the second hardmask layer.

4. The method of claim 1, wherein, Forming the cut opening in the first material comprises: forming a first opening having a first width in a photoresist layer; and performing an etch process using a size-reducing etchant to transfer the first opening in the photoresist layer to the first material to form the cut opening, wherein the cut opening has a second width, and the second width is smaller than the first width.

5. The method of claim 4, wherein, Further comprising: depositing a backside anti-reflective coating layer on the first material prior to forming the first opening in the photoresist layer; etching the backside anti-reflective coating layer using the size-reducing etchant to form a second opening having the second width; and patterning the first material using the backside anti-reflective coating layer.

6. The method of claim 1, wherein, The step of filling the first material in the openings comprises forming a protective mask layer using the first material on the mask strips.

7. The method of claim 1, wherein, Further comprising: depositing a second hardmask layer on the dielectric layer prior to forming the first hardmask layer; and depositing a third hardmask layer on the second hardmask layer, wherein the first hardmask layer is formed on the third hardmask layer.

8. The method of claim 7, wherein, Patterning the dielectric layer comprises: patterning the third hardmask layer using the mask strips and the second material; patterning the second hardmask layer using the third hardmask layer; and patterning the dielectric layer using the second hardmask layer.

9. A method of manufacturing a semiconductor element, characterized by, Comprising: depositing a first hardmask layer on a dielectric layer; depositing a second hardmask layer on the first hardmask layer; patterning the second hardmask layer to form a plurality of mask strips on the first hardmask layer, wherein the mask strips extend in a first direction, wherein the mask strips are separated by a plurality of openings; depositing a mask layer on the mask strips and the first hardmask layer, the mask layer further filling the openings; depositing a photoresist layer on the mask layer; patterning the photoresist layer to form a cut opening to expose at least one of the mask strips, wherein the cut opening extends in a lengthwise direction along a second direction perpendicular to the first direction, and the cut opening intersects two or more mask strips; forming a cut mask to fill the cut opening, wherein the cut mask extends in a lengthwise direction along the second direction substantially perpendicular to the first direction, and a bottom surface of the cut mask contacts the first hardmask layer; removing the mask layer to expose the cut mask and the mask strips; and using the mask strips and the cut mask as etch masks, patterning the first hardmask layer and the dielectric layer.

10. The method of claim 9, wherein, patterning the photoresist layer to form the cut opening includes: forming a first opening in the photoresist layer, wherein a width of the first opening is substantially equal to a width of the mask strips; and using the photoresist layer as an etch mask for a size-reduction etchant, forming the cut opening in the mask layer such that the cut opening is narrower than the first opening.

11. The method of claim 9, wherein, further includes: forming a first opening in the photoresist layer; using the photoresist layer as an etch mask, forming a second opening in a backside anti-reflective coating layer on the mask layer, wherein the second opening is narrower than the first opening; and using the backside anti-reflective coating layer as an etch mask, forming the cut opening in the mask layer.

12. The method of claim 11, wherein, the cut opening is narrower than the second opening.

13. The method of claim 11, wherein, a width of the first opening is equal to a width of the mask strips, and a width of the cut opening is between 80% and 40% of a width of the first opening.

14. A method of manufacturing a semiconductor element, characterized by, includes: depositing a dielectric layer; patterning the dielectric layer using extreme ultraviolet lithography to form a first opening and a second opening in the dielectric layer, wherein patterning the dielectric layer to form the first opening and the second opening in the dielectric layer includes: depositing a first hardmask layer on a dielectric layer; forming mask strips in the first hardmask layer, wherein the mask strips are separated by third openings; filling the third openings between the mask strips with a first material; forming a cut opening through the first material, wherein the mask strips extend in a lengthwise direction along a first direction, the cut opening extends in a lengthwise direction along a second direction perpendicular to the first direction, and the cut opening intersects two or more mask strips; filling the cut opening with a second material; removing the first material to expose the second material and the mask strips; using the mask strips and the second material to pattern the dielectric layer to form the first opening and the second opening in the dielectric layer; and filling the first opening and the second opening in the dielectric layer to form a first conductive line and a second conductive line in the dielectric layer, wherein the first conductive line and the second conductive line extend along the same direction, an end portion of the first conductive line faces an end portion of the second conductive line, an end-to-end spacing between the end portions of the first conductive line and the second conductive line is less than a line width of the first conductive line, and the line width is less than 25 nanometers, wherein the end portion of the first conductive line includes a profile, the profile includes: a first corner; a second corner; and a flat portion connecting the first corner and the second corner, wherein a length of the flat portion is between 60% and 80% of the line width.

15. The method of claim 14, wherein, The end-to-end spacing is between 80% and 40% of the line width.

16. The method of claim 14, wherein, The end-to-end spacing is less than 50% of the line width.

17. The method of claim 15, wherein, The patterning the dielectric layer further includes forming a third opening in the dielectric layer and filling the third opening to form a third conductive line parallel to the first conductive line, a line spacing between the first conductive line and the third conductive line is substantially equal to the line width.

18. The method of claim 14, wherein, The end-to-end spacing is between 6 nanometers and 12 nanometers.

19. The method of claim 18, wherein, A radius of the first corner is less than 20% of the line width. The end-to-end spacing is less than 50% of the line width. The patterning the dielectric layer further includes forming a third opening in the dielectric layer and filling the third opening to form a third conductive line parallel to the first conductive line, a line spacing between the first conductive line and the third conductive line is substantially equal to the line width. The end-to-end spacing is between 6 nanometers and 12 nanometers. A radius of the first corner is less than 20% of the line width.

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