Method of manufacturing transistor

Abstract

A method for manufacturing a transistor includes forming a semiconductor layer above a substrate; etching a portion of the semiconductor layer to form a first groove and a second groove; forming a first mask layer above the semiconductor layer; performing a first heat treatment on the first mask layer, the first heat treatment densifying the first mask layer; etching the first mask layer to expose the first groove; forming a first semiconductor material in the first groove; and removing the first mask layer.

Description

Technical Field

[0001] The present disclosure relates to a method of manufacturing a transistor. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and using lithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size to allow more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be addressed. Summary of the invention

[0004] In one embodiment, the method includes forming a semiconductor layer above a substrate; etching a portion of the semiconductor layer to form a first groove and a second groove; forming a first mask layer above the semiconductor layer; performing a first heat treatment on the first mask layer, the first heat treatment densifying the first mask layer; etching the first mask layer so as to expose the first groove; forming a first semiconductor material in the first groove; and removing the first mask layer.

[0005] In one embodiment, the method includes forming a semiconductor layer above a first substrate; etching the semiconductor layer to form a first groove in a first region and a second groove in a second region; depositing a first mask layer above the first region and the second region; roughening the first mask layer; removing the first mask layer from the second region; forming a first epitaxial source / drain region in the second groove; removing the remaining portion of the first mask layer; depositing a second mask layer above the first region and the second region; roughening the second mask layer; removing the second mask layer from the first region; forming a second epitaxial source / drain region in the first groove; removing the remaining portion of the second mask layer; and forming a gate structure above the semiconductor layer.

[0006] In one embodiment, the method includes depositing a mask layer over a substrate, the substrate including a first groove and a second groove; performing post-deposition processing on the mask layer; anisotropically etching the mask layer to expose the second groove; epitaxially growing a first portion of semiconductor material over the mask layer and a second portion of the semiconductor material in the second groove, the first portion including a discontinuous nodule; and isotropically etching to remove the mask layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of this disclosure are as follows: Figure 1The following embodiments are best understood by reading together. It should be noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 An example of a nanostructure field-effect transistor (Nano-FET) is shown in a three-dimensional view according to some embodiments;

[0009] Figure 2 , 3 ,4,5,6A,6B,7A,7B,8A,8B,9A,9B,10A,10B,11A,11B,12A,12B,13A,13B,13C, 14A, 14B, 15A, 15B, 15C, 16A, 16B, 16C, 17A, 17B, 17C, 17D, 18A, 18B, 18C, 19A, 19 B, 19C, 20A, 20B, 20C, 20D, 21A, 21B, 21C, 22A, 22B, 23A, 23B, 24A, 24B, 25A, 25B, 26A, 26B, 26C, 27A, 27B, 27C, 28A, 28B, and 28C are cross-sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments.

[0010]

Explanation of symbols

[0011] 20: Divider

[0012] 50:Substrate

[0013] 50N: n-type region

[0014] 50P: p-type region

[0015] 51: first semiconductor layer

[0016] 51A-C: first semiconductor layer

[0017] 52: The First Nanostructure

[0018] 52A-C: First Nanostructure

[0019] 53: Second semiconductor layer

[0020] 53A-C: Second semiconductor layer

[0021] 54: Second Nanostructure

[0022] 54A-C: Second Nanostructure

[0023] 55: Nanostructure

[0024] 60: Virtual dielectric layer

[0025] 64: Multi-layer stacking

[0026] 66: Fin

[0027] 68: Shallow trench isolation area

[0028] 70: Virtual dielectric layer

[0029] 71: Dummy gate dielectric

[0030] 72: Virtual gate layer

[0031] 74: Mask layer

[0032] 76: dummy gate

[0033] 78: Mask

[0034] 80: First separation layer

[0035] 81: First separator

[0036] 82: Second separation layer

[0037] 83: Second separator

[0038] 86: First groove

[0039] 88: Sidewall groove

[0040] 90: First internal partition

[0041] 92: epitaxial source / drain region

[0042] 92A: first semiconductor material layer

[0043] 92B: Second semiconductor material layer

[0044] 92C: third semiconductor material layer

[0045] 92N: Nodule

[0046] 93:p-mask layer

[0047] 93A: Amorphous layer

[0048] 93B: Rough exposed surface

[0049] 93C: Crystalline layer

[0050] 93S: Smooth exposed surface

[0051] 93R: Rough surface

[0052] 94:n-mask layer

[0053] 94A: Amorphous layer

[0054] 94B: Rough surface

[0055] 94C: Crystalline layer

[0056] 94S: Smooth exposed surface

[0057] 94R: Rough surface

[0058] 95: contact etching stop layer

[0059] 96: First interlayer dielectric

[0060] 98: Second groove

[0061] 100: Gate dielectric layer

[0062] 102: Gate electrode

[0063] 104: Gate mask

[0064] 108: The third groove

[0065] 110: Silicide region

[0066] 112:Contact

[0067] 114: Gate contact

[0068] 118: Conductive material

[0069] 200: Post-deposition processing

[0070] 201: Area

[0071] 300: Post-deposition processing

[0072] 301: Area

[0073] A-A': Cross section

[0074] B-B': Cross section

[0075] C-C': Cross section

[0076] T 93C :thickness

[0077] T 93A :thickness

[0078] T 94C :thickness

[0079] T 94A :thickness DETAILED DESCRIPTION

[0080] The following disclosure provides many different embodiments or examples of different features of an embodiment of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0081] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "below," "above," "over," and the like, may be used herein to describe the relationship of one element or feature to another element or features as illustrated in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0082] Various embodiments provide methods for forming a grain containing a nano-FET. The method includes forming a stack of semiconductor layers and etching the stack to form an epitaxial source / drain region. While forming or processing features in a grain region dedicated to an n-type transistor, a grain region dedicated to a p-type transistor can be shielded. Similarly, while forming or processing features in a grain region dedicated to a p-type transistor, a grain region dedicated to an n-type transistor can be shielded. Each mask layer can be formed and processed in a manner that improves the efficiency of those other processes while also making each mask layer easier to remove later. Then, a gate structure can be formed on the stack of semiconductor layers to form a transistor structure. In addition, a front interconnect structure can be formed on a first side of the transistor structure, and a back interconnect structure can be formed on an opposite side of the transistor structure. However, various embodiments can be applied to grains containing other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, or the like) instead of or in combination with nano-FETs.

[0083] Figure 1An example of a nano-FET (e.g., a nanowire FET, a nanosheet FET, or the like) in a three-dimensional view according to some embodiments is shown. The nano-FET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, or the like) above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 acts as a channel region of the nano-FET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. A shallow trench isolation (STI) region 68 is disposed between adjacent fins 66, which may protrude above and between adjacent STI regions 68. Although the STI region 68 is described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may refer to a semiconductor substrate alone or a combination of a semiconductor substrate and an isolation region. In addition, although the bottom portion of the fin 66 is shown as a single continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this case, the fin 66 refers to the portion extending between adjacent STI regions 68.

[0084] A gate dielectric layer 100 is over the top surface of the fin 66 and along the top surface, sidewalls, and bottom surface of the nanostructure 55. A gate electrode 102 is over the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0085] Figure 1 Reference cross sections for use in later figures are further illustrated. Cross section AA' is along the longitudinal axis of gate electrode 102 and in a direction perpendicular to the direction of current flow, e.g., between epitaxial source / drain regions 92 of the nano-FET. Cross section BB' is perpendicular to cross section AA' and parallel to the longitudinal axis of fin 66 of the nano-FET and in the direction of current flow, e.g., between epitaxial source / drain regions 92 of the nano-FET. Cross section CC' is parallel to cross section AA' and runs through the epitaxial source / drain regions of the nano-FET. For clarity purposes, subsequent figures refer to these reference cross sections.

[0086] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments encompass aspects used in planar devices such as planar FETs or fin field-effect transistors (FinFETs).

[0087] Figures 2 to 28C is a cross-sectional view of an intermediate stage in the fabrication of a nano-FET according to some embodiments. Figures 2 to 5, 6A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, and 28A are shown in Figure 1 Reference cross section AA' is shown in . Figure 6B , 7B , 8B, 9B, 10B, 11B, 12B, 13B, 13C, 14B, 15B, 16B, 17B, 17D, 18B, 19B, 20B, 20D, 21B, 22B, 23B, 24B, 25B, 26B, 27B, and 28B are shown in Figure 1 Reference cross section BB' is shown in FIG. Fig. 7A , 8A , 9A, 10A, 11A, 12A, 13A, 14A, 15A, 15C, 16A, 16C, 17A, 17C, 18A, 18C, 19A, 19C, 20A, 20C, 21C, 26C, 27C, and 28C are shown in Figure 1 Reference cross section CC' shown in .

[0088] exist Figure 2 In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. In general, the SOI substrate layer is a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide indium phosphide; or a combination thereof.

[0089] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nano-FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nano-FET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0090] In addition Figure 2 In the embodiment of the present invention, a multilayer stack 64 is formed on a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustration purposes and as discussed in more detail below, the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form a channel region of a nano-FET in the p-type region 50P. Again, the first semiconductor layer 51 is removed and the second semiconductor layer 53 is patterned to form a channel region of a nano-FET in the n-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nano-FET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nano-FET in the p-type region 50P. In other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nano-FET in both the n-type region 50N and the p-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nano-FET in both the n-type region 50N and the p-type region 50P.

[0091] For exemplary purposes, the multilayer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of the first semiconductor layer 51 and the second semiconductor layer 53. The layers of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nano-FET, such as silicon germanium or the like, and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nano-FET, such as silicon, silicon carbon, or the like. For exemplary purposes, the multilayer stack 64 is shown as having a lowest semiconductor layer suitable for a p-type nano-FET. In some embodiments, the multilayer stack 64 may be formed so that the lowest layer is a semiconductor layer suitable for an n-type nano-FET.

[0092] The first semiconductor material and the second semiconductor material may be materials having high etching selectivity to each other. Therefore, the first semiconductor layer 51 of the first semiconductor material may be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material in the n-type region 50N, thereby patterning the second semiconductor layer 53 to form the channel region of the n-type NSFETS. Similarly, the second semiconductor layer 53 of the second semiconductor material may be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material in the p-type region 50P, thereby patterning the first semiconductor layer 51 to form the channel region of the p-type NSFETS.

[0093] View now Figure 3According to some embodiments, fins 66 are formed in substrate 50 and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 may be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. Etching may be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 may further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from first semiconductor layer 51 and second nanostructures 54A-C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 may further be collectively referred to as nanostructures 55.

[0094] The fins 66 and nanostructures 55 can be patterned by any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more lithography processes, including double patterning or multiple patterning processes. In general, the double patterning or multiple patterning processes combine lithography with a self-aligned process, allowing the generation of patterns with, for example, spacings that are smaller than would otherwise be obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Using a self-aligned process, spacers are formed next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0095] For illustrative purposes, Figure 3 The fins 66 in the n-type region 50N and the p-type region 50P are shown as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater or thinner than the fins 66 in the p-type region 50P. In addition, while the fins 66 and each of the nanostructures 55 are shown as having a uniform width throughout, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls so that the width of each of the fins 66 and / or nanostructures 55 increases continuously in a direction toward the substrate 50. In these embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0096] exist Figure 4In the embodiment shown, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material on the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitride, the like, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed so that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can first be formed along the surface of the substrate 50, the fin 66, and the nanostructure 55. Thereafter, a fill material, such as those discussed above, may be formed over the liner.

[0097] Then, a removal process is applied to the insulating material to remove excess insulating material on the nanostructures 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like may be utilized. The planarization process exposes the nanostructures 55 so that after the planarization process is completed, the top surfaces of the nanostructures 55 and the insulating material are flush.

[0098] Then, the insulating material is recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 in regions 50N and 50P protrude between adjacent STI regions 68. In addition, the top surface of the STI regions 68 may have a flat surface as shown, a convex surface, a concave surface (such as a dished shape), or a combination thereof. The top surface of the STI regions 68 may be formed flat, convex, and / or concave by suitable etching. The STI regions 68 may be recessed using an acceptable etching process, such as a process that is selective to the material of the insulating material (e.g., etches the material of the insulating material at a faster rate than the material of the fins 66 and the nanostructures 55). For example, oxide removal using, for example, dilute hydrofluoric (dHF) may be used.

[0099] As above relative to Figures 2 to 4The process described is only one example of how the fin 66 and nanostructure 55 may be formed. In some embodiments, the fin 66 and / or nanostructure 55 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed on the top surface of the substrate 50, and a trench may be etched through the dielectric layer so as to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 66 and / or nanostructure 55. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, thereby eliminating previous and / or subsequent implants, but in situ and implant doping may be used together.

[0100] In addition, for exemplary purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as including the same material in the p-type region 50P and the n-type region 50N. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials or formed in a different order in the p-type region 50P and the n-type region 50N.

[0101] In addition Figure 4 In the embodiment of the present invention, suitable holes (not shown separately) may be formed in the fins 66, nanostructures 55, and / or STI regions 68. In embodiments with different hole types, different implantation steps for the n-type region 50N and the p-type region 50P may be achieved using a photoresist or other mask (not shown separately). For example, a photoresist may be formed on the fins 66 and STI regions 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned so as to expose the p-type region 50P. The photoresist may be formed using one or more spin coating or deposition techniques and may be patterned using acceptable lithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted in the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, or the like, which is present at a rate of about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 After implantation, the photoresist is removed, such as by an acceptable ashing process.

[0102] After or before implanting the p-type region 50P, a photoresist or other mask (not separately shown) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned so as to expose the n-type region 50N. The photoresist may be formed using one or more spin coating or deposition techniques and may be patterned using acceptable lithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region 50N, and the photoresist may act as a mask so as to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity may be boron, boron fluoride, indium, or the like, which is present at about 10 13 atoms / cm 3 to about 10 14 atoms / cm 3 After implantation, the photoresist may be removed, such as by an acceptable ashing process.

[0103] After implanting n-type region 50N and p-type region 50P, annealing may be performed to repair implant damage and activate implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, thereby eliminating implantation, but in-situ and implantation doping may be used together.

[0104] exist Figure 5In the embodiment of the present invention, a dummy dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 may be deposited on the dummy dielectric layer 70 and then planarized, such as by CMP. The mask layer 74 may be deposited on the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials having a higher etch selectivity than the etch isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that for exemplary purposes only, the dummy dielectric layer 70 is shown as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited so that the dummy dielectric layer 70 covers the STI region 68 so that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0105] 6A to 20D Various additional steps in fabricating an embodiment device are shown. Fig. 6A , 7A , 8A, 9A, 10A, 11A, 12A, 13A, 13C, 14A, 15A, 15C, 16A, 16C, 17A, 17C, 17D, 18A, 18C, 19A, 19C, 20A, and 20C show features in the n-type region 50N or the p-type region 50P. Fig. 6A and Figure 6B In the embodiment, the mask layer 74 (see Figure 5 ) can be patterned using acceptable lithography and etching techniques to form a mask 78. The pattern of mask 78 can then be transferred to dummy gate layer 72 and dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectrics 71, respectively. Dummy gates 76 cover corresponding channel regions of fins 66. The pattern of mask 78 can be used to physically separate each of the dummy gates 76 from adjacent dummy gates 76. Dummy gates 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of corresponding fins 66.

[0106] exist Fig. 7A and Figure 7B In the embodiment, the first separation layer 80 and the second separation layer 82 are respectively Fig. 6A and Figure 6B The first spacer layer 80 and the second spacer layer 82 are then patterned to act as spacers for forming self-aligned source / drain regions. Fig. 7A and Figure 7B , a first spacer layer 80 is formed on the top surface of the STI region 68; the top surface and sidewalls of the fin 66, the nanostructure 55, and the mask 78; and the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. A second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like using a technique such as thermal oxidation, or deposited by CVD, ALD, or the like. The second spacer layer 82 can be formed of a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and can be deposited by CVD, ALD, or the like.

[0107] After the first spacer layer 80 is formed and before the second spacer layer 82 is formed, an implant (not separately shown) of a lightly doped source / drain (LDD) region may be performed. In embodiments with different device types, similar to the above, Figure 4 , a mask such as a photoresist may be formed in the n-type region 50N while the p-type region 50P is exposed, and an appropriate type (e.g., p-type) impurity may be implanted in the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed in the p-type region 50P while the n-type region 50N is exposed, and an appropriate type impurity (e.g., n-type) may be implanted in the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a doping density of approximately 1×10 15 atoms / cm 3 About 1x10 19 Atom / cm 3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0108] exist Fig. 8A and Figure 8B, the first spacer layer 80 and the second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83. As discussed in more detail below, the first spacer 81 and the second spacer 83 are used to self-align the subsequently formed source and drain regions, and to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, so that when the second spacer layer 82 is patterned, the first spacer layer 80 can act as an etching stop layer, and so that when the first spacer layer 80 is patterned, the second spacer layer 82 can act as a mask. For example, the second spacer layer 82 can be etched using an anisotropic etching process, wherein the first spacer layer 80 acts as an etching stop layer, and wherein the remaining portion of the second spacer layer 82 forms the second spacer 83, such as Fig. 8A Thereafter, when etching the exposed portion of the first spacer layer 80, the second spacer 83 acts as a mask, thereby forming the first spacer 81, as shown in FIG. Fig. 8A Although not shown in Figure 8B As specifically shown in FIG. 1 , according to some embodiments, an etching process (eg, an anisotropic etching process) may additionally remove the first spacer layer 80 and the second spacer layer 82 from the top of the mask 78 , and remove the second spacer layer 82 from the sides of the dummy gate 76 and the mask 78 .

[0109] like Fig. 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8B As shown, portions of first spacer 81 and second spacer 83 may remain adjacent to and over mask 78, dummy gate 76, and dummy gate dielectric 71. In other embodiments not specifically shown, second spacer layer 82 may be removed from over first spacer layer 80, and first spacer layer 80 may be removed from the top of mask 78, adjacent to and over top mask 78, dummy gate 76, and dummy gate dielectric 71.

[0110] It should be noted that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be patterned before depositing the second spacer layer 82), additional spacers may be formed and removed, and / or the like. Furthermore, n-type and p-type devices may be formed using different structures and steps.

[0111] exist Fig.9A and Fig. 9BIn some embodiments, a first recess 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region is then formed in the first recess 86. The first recess 86 may penetrate the first nanostructure 52 and the second nanostructure 54 and enter the substrate 50. Fig.9A 66. In various embodiments, the fin 66 may be etched so that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68; or the like. The first recess 86 may be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process such as RIE, NBE, or the like. During the etching process for forming the first recess 86, the first spacer 81, the second spacer 83, and the mask 78 shield portions of the fin 66, the nanostructure 55, and the substrate 50. A single etching process or multiple etching processes may be used to etch the various layers of the nanostructure 55 and / or the fin 66. A timed etching process may be used so that the etching of the first recess 86 is terminated after the first recess 86 reaches a desired depth.

[0112] exist Fig. 10A and Fig. 10B In the embodiment, the portion of the sidewall of the layer of the multilayer stack 64 formed of the first semiconductor material (e.g., the first nanostructure 52) exposed by the first groove 86 is etched to form the sidewall groove 88 in the n-type region 50N, and the portion of the sidewall of the layer of the multilayer stack 64 formed of the second semiconductor material (e.g., the second nanostructure 54) exposed by the first groove 86 is etched to form the sidewall groove 88 in the p-type region 50P. Fig. 10B, the sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall recess 88 are shown as straight, but the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process, such as a wet etch or similar process. While the first nanostructure 52 is etched using an etchant selective to the first semiconductor material, the p-type region 50P may be protected using a mask (not shown) so that the second nanostructure 54 and the substrate 50 remain relatively unetched as compared to the first nanostructure 52 in the n-type region 50N. Similarly, while the second nanostructure 54 is etched using an etchant selective to the second semiconductor material, the n-type region 50N may be protected using a mask (not shown) so that the first nanostructure 52 and the substrate 50 remain relatively unetched as compared to the second nanostructure 54 in the p-type region 50P. In an embodiment where the first nanostructure 52 includes, for example, SiGe, and the second nanostructure 54 includes, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch the sidewalls of the first nanostructure 52 in the n-type region 50N, and a dry etching process using hydrogen fluoride, another fluorine-based etchant, or the like may be used to etch the sidewalls of the second nanostructure 54 in the p-type region 50P.

[0113] exist Figure 11A-11B In the embodiment, the first internal partition 90 is formed in the side wall groove 88. The first internal partition 90 can be formed by Fig. 10A and Fig. 10B 8. The first inner spacer 90 is formed by depositing an inner spacer layer (not shown separately) over the structure shown in FIG. The first inner spacer 90 acts as an isolation feature between the subsequently formed source / drain regions and the gate structure. As discussed in more detail below, the source / drain regions are formed in the first recess 86 while the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are replaced with corresponding gate structures.

[0114] The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, or the like. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, but any suitable material may be utilized, such as a low-dielectric constant (low-k) material having a k-value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form a first inner spacer 90. The first inner spacer 90 may be used to prevent subsequent etching processes, such as etching processes used to form gate structures, from damaging subsequently formed source / drain regions (such as epitaxial source / drain regions 92, discussed below). Although the outer sidewall first inner spacer 90 is shown as being flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and flush with the sidewalls of the first nanostructure 52 in the p-type region 50P, the outer sidewalls of the first inner spacer 90 may extend beyond or be recessed from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0115] exist Figures 12A-19C , the epitaxial source / drain region 92 is formed in the first groove 86. Specifically, Figures 12A-15C The epitaxial source / drain regions 92 are shown formed in the n-type region 50N, and Figures 16A-19C Epitaxial source / drain regions 92 are shown formed in p-type region 50P. In some embodiments, epitaxial source / drain regions 92 can stress second nanostructures 54 in n-type region 50N and first nanostructures 52 in p-type region 50P, thereby improving performance. As shown, epitaxial source / drain regions 92 are formed in first recesses 86 so that each dummy gate 76 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate epitaxial source / drain regions 92 from dummy gates 76 and first internal spacers 90 are used to separate epitaxial source / drain regions 92 from nanostructures 55 by a suitable lateral distance so that epitaxial source / drain regions 92 do not short circuit with subsequently formed gates of the resulting nano-FET.

[0116] refer to Figure 12A-12B, a p-mask layer 93 is formed over the structures (e.g., n-type region 50N and p-type region 50P). The p-mask layer 93 protects the p-type region 50P during the formation of the n-type epitaxial source / drain region 92 in the first recess 86 of the n-type region 50N (e.g., NMOS region). The p-mask layer 93 may be deposited by a conformal deposition process such as ALD, CVD, or the like. The p-mask layer 93 may include materials such as metal oxides, including aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, zinc oxide, or the like. Using a metal oxide as the p-mask layer 93 allows for a thin p-mask layer 93, thereby advantageously protecting the substrate by providing complete coverage even when features such as the first recess 86 have very small critical dimensions. After deposition, the p-mask layer 93 may have a substantially smooth exposed surface 93S and be substantially or completely amorphous. For example, in some embodiments, the p-mask layer 93 may be deposited to a thickness between about 1 nm and about 10 nm, about 2.6 g / cm 3 About 4.0g / cm 3 and a density between about 0.1 nm and about 0.8 nm.

[0117] refer to Figure 13A-13C After deposition, a post-deposition treatment 200 (or roughening treatment 200) may be performed on the p-mask layer 93. The post-deposition treatment 200 stabilizes the p-mask layer 93 to form a denser layer. As a result, the p-mask layer 93 may have a more wavy, or rougher, exposed surface 93R than the previously smooth exposed surface 93S. The more wavy (or rougher) shape of the exposed surface 93R improves subsequent steps (see Figure 15A-Figure 15C ) because the epitaxial growth grows less easily and in smaller nodules on the rougher surface 93R of the p-mask layer 93. Less growth of epitaxial growth over the p-mask layer 93 also allows for more efficient removal of the p-mask layer 93 after the epitaxial source / drain regions 92 are formed in the n-type region 50N (see Figure 16A-16C ).

[0118] The post-deposition treatment 200 may include a thermal treatment, a plasma treatment, a UV treatment, a microwave treatment, a plasma bombardment, an implantation, a reticle absorption treatment, an electron anneal, a radiation anneal, the like, or any combination thereof. According to some embodiments, the post-deposition treatment 200 may include a thermal treatment including annealing at a temperature greater than about 650° C., including a temperature between about 650° C. and about 900° C., for a duration between about 30 minutes and about 8 hours. The thermal treatment may be performed in an environment of nitrogen, argon, helium, hydrogen, or the like. When some or all of the p-mask layer 93 crystallizes and / or densifies during the post-deposition treatment 200, the p-mask layer 93 may become thinner. After the post-deposition treatment 200, the p-mask layer 93 may have a thickness between about 0.5 nm and about 6 nm, a thickness of about 2.8 g / cm 3 About 4.2g / cm 3 and a density between about 2 nm and about 5 nm.

[0119] Reference shows Fig. 13B An enlarged view of area 201 Fig. 13C , the post-deposition treatment 200 may partially or completely convert the amorphous p-mask layer 93 to a crystalline form. Note that region 201 is shown depicting a portion of the p-mask layer 93, which represents any or all other portions of the p-mask layer 93 disposed above the structure. For example, an upper portion of the p-mask layer 93 may include a crystalline layer 93C, while a lower portion of the p-mask layer 93 may remain a substantially amorphous layer 93A. The crystalline layer 93C may have a thickness T between about 2 nm and about 5 nm. 93C , and the amorphous layer 93A may have a thickness T between about 2 nm and about 5 nm. 93A .

[0120] Additionally or alternatively, post-deposition treatment 200 may include plasma treatment. During the plasma treatment, surface 93S of p-mask layer 93 is exposed to a plasma of nitrogen, argon, ammonia, oxygen, helium, the like, or a combination thereof, so as to change the material properties of p-mask layer 93 and / or etch portions. The plasma treatment may be performed at a temperature between about 50° C. and about 500° C. and at a pressure between about 0.5 Torr and about 10 Torr for a duration between about 10 seconds and about 10 minutes.

[0121] The post-deposition treatment 200 may further include a UV radiation treatment. During the UV radiation treatment, the surface 93S of the p-mask layer 93 is exposed to UV radiation in an environment of nitrogen, argon, ammonia, oxygen, helium, the like, or any combination thereof, so as to change the material properties and / or etch portions of the p-mask layer 93. The UV radiation treatment may be performed at an energy between about 50 watts and about 1000 watts for a duration between about 30 seconds and about 10 minutes.

[0122] Additionally or alternatively, post-deposition treatment 200 may include microwave radiation treatment. During microwave radiation treatment, surface 93S of p-mask layer 93 is exposed to microwave radiation in an environment of nitrogen, argon, ammonia, oxygen, helium, the like, or any combination thereof, so as to change the material properties of p-mask layer 93 and / or etch portions. Microwave radiation treatment may be performed at an energy between about 500 watts and about 3000 watts for a duration between about 30 seconds and about 10 minutes.

[0123] According to some embodiments, the post-deposition treatment 200 may include a combination of one or more of the above-mentioned treatment processes. For example, the post-deposition treatment 200 may include a thermal treatment and a plasma treatment, whether or not performed simultaneously or in succession. In other embodiments, the post-deposition treatment 200 may include a thermal treatment, a plasma treatment, and a UV radiation treatment, whether or not two or all are performed simultaneously or all three are performed in succession.

[0124] refer to Figure 14A-14B , after the post-deposition treatment 200, the p-mask layer 93 is removed from the n-type region 50N. A photoresist (not specifically shown), such as a hard mask, may be formed over the p-mask layer 93 and patterned so as to expose the p-mask layer 93 in the n-type region 50N. The p-mask layer 93 may then be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. The photoresist may then be removed by a suitable process, such as an isotropic etching process or an anisotropic etching process. In other embodiments, the p-mask layer 93 is removed in the n-type region 50N by one of the above processes without first forming a photoresist over the p-mask layer 93.

[0125] refer to Figure 15A-Figure 15C , epitaxial source / drain region 92 is epitaxially grown in first recess 86 in n-type region 50N, and nodules 92N of epitaxial material may be formed above p-mask layer 93. Epitaxial source / drain region 92 may include any acceptable material suitable for n-type nano-FET. For example, if second nanostructure 54 is silicon, epitaxial source / drain region 92 may include a material that applies tensile strain to second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. Epitaxial source / drain region 92 may have a surface elevated from a corresponding upper surface of nanostructure 55 and may have an end face.

[0126] As described above, nodules 92N (e.g., a small amount of epitaxy) may grow over p-mask layer 93. However, rough surface 93R of p-mask layer 93 reduces the number and size of nodules 92N that may otherwise form, thereby allowing for greater control over the formation of epitaxial source / drain regions 92 and improved removal of p-mask layer 93 (and nodules 92N) in subsequent steps discussed in more detail below. As shown, each of epitaxial source / drain regions 92 is formed as a unitary continuous material, while nodules 92N are formed as discontinuous clusters or nodules.

[0127] Similar to the process discussed previously for forming lightly doped source / drain regions, the epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form the source / drain regions, followed by annealing. The source / drain regions may have a dopant density of approximately 1×10 19 atoms / cm 3 With about 1x10 21 atoms / cm 3 The n-type impurities in the source / drain regions may be any of the impurities discussed previously. While the p-mask layer 93 still protects the p-type region 50P, the n-type impurities may be implanted. In some embodiments, the epitaxial source / drain regions 92 may be doped in situ during growth.

[0128] Due to the epitaxial process used to form epitaxial source / drain regions 92, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of nanostructures 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same NSFET to merge, such as Fig.15A In other embodiments, after the epitaxy process is completed, adjacent epitaxy source / drain regions 92 remain separated, such as Fig. 15C Shown. Fig.15A and Fig. 15C In the illustrated embodiment, the first spacer 81 may be formed on the top surface of the STI region 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewall of the nanostructure 55, thereby further blocking epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 may be adjusted to remove the spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 68.

[0129] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of a different semiconductor material and may be doped to a different dopant concentration. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited above the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited above the second semiconductor material layer 92B.

[0130] exist Figures 16A-19C , the p-mask layer 93 and the nodules 92N may be removed from the p-type region 50P, and the epitaxial source / drain regions 92 in the p-type region 50P (eg, a PMOS region) may be formed in a manner similar to that described above with respect to the epitaxial source / drain regions 92 in the n-type region 50N.

[0131] refer to Figure 16A-16C, the p-mask layer 93 and the nodules 92N may be removed from the p-type region 50P. For example, the p-mask layer 93 and the nodules 92N may be removed using a wet or dry etch with an etchant such as sulfuric acid (H2SO4), hydrogen fluoride (HF), hydrogen chloride (HCl), ammonia (NH3+H2O), the like, any combination thereof, or any suitable etchant. The reduced size and number of nodules 92N (due to the rough surface 93R of the p-mask layer 93) improves the efficiency of removing the p-mask layer 93 and the nodules 92N by the above process. Then, the n-mask layer 94 may be formed over the structure (e.g., the n-type region 50N and the p-type region 50P). The n-mask layer 94 protects the n-type region 50N during the formation of the p-type epitaxial source / drain region 92 in the first recess 86 of the p-type region 50P (e.g., the PMOS region). The n-mask layer 94 may be deposited by a conformal deposition process such as ALD, CVD, or the like. The n-mask layer 94 may include materials such as metal oxides, including aluminum oxide, hafnium oxide (HfO2), zirconium oxide (ZrO2), or the like. The n-mask layer 94 may be the same or different from the p-mask layer 93 and may be formed by similar or different processes. Using a metal oxide as the n-mask layer 93 allows for a thin n-mask layer 94, thereby advantageously protecting the substrate by providing complete coverage even when features such as the first recess 86 have very small critical dimensions. After deposition, the n-mask layer 94 may have a substantially smooth exposed surface 94S and be substantially or completely amorphous. The n-mask layer 94 may be thinner and have a thickness between about 1 nm and about 10 nm, about 2.6 g / cm 3 About 4.0g / cm 3 and a density between about 0.1 nm and about 0.8 nm.

[0132] refer to Figures 17A-17D After deposition, post-deposition treatment 300 (or roughening treatment 300) may be performed on n-mask layer 94. As with p-mask layer 93, post-deposition treatment 300 stabilizes n-mask layer 94 to form a denser layer. As a result, n-mask layer 94 may have a more wavy, or rougher, exposed surface 94B than the previously smooth exposed surface 94S. As with the rougher exposed surface 93R of p-mask layer 93, the rougher exposed surface 94R of n-mask layer 94 improves subsequent steps (see Figure 19A-Figure 19C) because the epitaxial growth grows less easily and in smaller nodules on the rougher surface 94R of the n-mask layer 94. Less epitaxial growth over the n-mask layer 94 also allows for more efficient removal of the n-mask layer 94 after the epitaxial source / drain regions 92 are formed in the p-type region 50P (see Figures 20A-20D ).

[0133] Any post-deposition treatment 200 described with respect to p-mask layer 93 may be used for post-deposition treatment 300 of n-mask layer 94 (e.g., thermal treatment, plasma treatment, UV treatment, microwave treatment, plasma bombardment, implantation, reticle absorption treatment, electron annealing, radiation annealing, the like, or any combination thereof). Post-deposition treatment 300 of n-mask layer 94 may be the same or similar process as post-deposition treatment 200 for p-mask layer 93, or the processes may be different. According to some embodiments, post-deposition treatment 300 may include a thermal treatment including annealing at a temperature greater than about 650° C., including between about 650° C. and about 900° C., for a duration between about 30 minutes and about 8 hours. The thermal treatment may be performed in an environment of nitrogen, argon, helium, hydrogen, or the like. When some or all of n-mask layer 94 crystallizes and / or densifies during post-deposition treatment 300, n-mask layer 94 may become thinner. After post-deposition treatment 300, n-mask layer 94 may have a thickness between about 0.5 nm and about 6 nm, a thickness of about 2.8 g / cm 3 About 4.2g / cm 3 and a density between about 2 nm and about 5 nm.

[0134] For example, in some embodiments, both post-deposition treatments 200 and 300 may include a thermal treatment and / or a plasma treatment. In other embodiments, one of the post-deposition treatments 200 or 300 may include one type of treatment (e.g., a thermal treatment) while the other post-deposition treatment 200 or 300 includes a different type of treatment (e.g., a plasma treatment). In other embodiments, one of the post-deposition treatments 200 or 300 may include a combination of treatments (e.g., a thermal treatment and a plasma treatment) while the other post-deposition treatment 200 or 300 includes a single treatment or a different combination of treatments (e.g., a thermal treatment and a UV radiation treatment).

[0135] Reference shows Fig. 17B An enlarged view of area 301 Fig.17D, post-deposition treatment 300 may partially or completely convert amorphous n-mask layer 94 to a crystalline form. Note that region 301 is shown depicting a portion of n-mask layer 94, which represents any or all other portions of n-mask layer 94 disposed above the structure. For example, an upper portion of n-mask layer 94 may include crystalline layer 94C, while a lower portion of n-mask layer 94 may remain substantially amorphous layer 94A. Crystalline layer 94C may have a thickness T between about 2 nm and about 5 nm. 94C , and the amorphous layer 94A may have a thickness T between about 2 nm and about 5 nm. 94A As some or all of p-mask layer 93 crystallizes and / or densifies during post-deposition processing 300, n-mask layer 93 may become thinner.

[0136] refer to Figures 18A-18C , after the post-deposition process 300, the n-mask layer 94 is removed from the p-type region 50P. A photoresist (not specifically shown), such as a hard mask, may be formed over the n-mask layer 94 and patterned so as to expose the n-mask layer 94 in the p-type region 50P. The n-mask layer 94 may then be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. The photoresist may then be removed by a suitable process, such as an isotropic etching process or an anisotropic etching process. In other embodiments, the n-mask layer 94 is removed in the p-type region 50P by one of the above processes without first forming a photoresist over the n-mask layer 94.

[0137] refer to Figure 19A-Figure 19C , epitaxial source / drain regions 92 are epitaxially grown in first recesses 86 in p-type region 50P, and nodules 92N of epitaxial material may be formed above n-mask layer 94. Epitaxial source / drain regions 92 may include any acceptable material suitable for p-type nano-FETs. For example, if first nanostructure 52 is silicon germanium, epitaxial source / drain regions 92 may include a material that applies compressive strain to first nanostructure 52, such as silicon-germanium, germanium, germanium tin, or the like. Epitaxial source / drain regions 92 may have surfaces elevated from corresponding surfaces of multilayer stack 64 and may have end faces.

[0138] As described above, nodules 92N (e.g., a small amount of epitaxy) may grow over n-mask layer 94. However, rough surface 94B of n-mask layer 94 reduces the number and size of nodules 92N that may otherwise form, thereby allowing for greater control over the formation of epitaxial source / drain regions 92 and improved removal of n-mask layer 94 (and nodules 92N) in subsequent steps discussed in more detail below. As shown, each of epitaxial source / drain regions 92 is formed as a unitary continuous material, while nodules 92N are formed as discontinuous clusters or nodules.

[0139] Similar to the process discussed previously for forming lightly doped source / drain regions, the epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form the source / drain regions, followed by annealing. The source / drain regions may have a dopant density of approximately 1×10 19 atoms / cm 3 With about 1x10 21 atoms / cm 3 The p-type impurity of the source / drain region may be any of the impurities discussed previously. The p-type impurity may be implanted while the n-mask layer 94 still protects the n-type region 50N. In some embodiments, the epitaxial source / drain region 92 may be doped in situ during growth.

[0140] As discussed above with respect to the epitaxial source / drain regions 92 in the n-type region 50N, the epitaxial source / drain regions 92 in the p-type region 50P may include similar or different shapes for reasons similar to those stated above with respect to the epitaxial source / drain regions 92 in the n-type region 50N. Due to the epitaxial process used to form the epitaxial source / drain regions 92 in the p-type region 50P, the upper surfaces of the epitaxial source / drain regions 92 have end faces that laterally extend outward beyond the sidewalls of the nanostructures 55. In some embodiments, these end faces cause adjacent epitaxial source / drain regions 92 of the same NSFET to merge, similarly as described above. Fig.15A In other embodiments, after the epitaxy process is completed, adjacent epitaxy source / drain regions 92 remain separated, similarly as described above. Fig. 15C Shown. Fig.15A and Fig. 15C In an embodiment similar to the illustrated embodiment, a first spacer 81 may be formed on the top surface of the STI region 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewall of the nanostructure 55, thereby further blocking epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 may be adjusted to remove the spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 68.

[0141] As above combined Figure 15A-Figure 15C As discussed with respect to the epitaxial source / drain regions 92 in the n-type region 50N, the epitaxial source / drain regions 92 in the p-type region 50P may include one or more semiconductor material layers having one or more different dopant concentrations similarly or differently than discussed above.

[0142] refer to Figures 20A-20D , n-mask layer 94 and nodules 92N may be removed from n-type region 50N. For example, n-mask layer 94 and nodules 92N may be removed using a wet or dry etch with an etchant such as sulfuric acid (H2SO4), hydrogen fluoride (HF), hydrogen chloride (HCl), ammonia (NH3+H2O), the like, any combination thereof, or any suitable etchant. The reduced size and number of nodules 92N (due to the rough surface 94R of n-mask layer 94) improves the efficiency of removing n-mask layer 94 and nodules 92N by the above process.

[0143] refer to Fig.20D , although the outer side wall of the first inner partition 90 is FIG. 10B to FIG. 20B , but the outer sidewalls of the first inner partition 90 may be concave or convex. For example, Fig.20D Embodiments are shown in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer is recessed from the sidewalls of the second nanostructure 54 in the n-type region 50N. As shown with respect to the n-type region 50N, the epitaxial source / drain region 92 can be formed in contact with the first inner spacer 90 and can extend beyond the sidewalls of the second nanostructure 54. Embodiments are also shown in which the sidewalls of the second nanostructure 54 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer is recessed from the sidewalls of the first nanostructure 52 in the p-type region 50P. As shown with respect to the p-type region 50P, the epitaxial source / drain region 92 can be formed in contact with the first inner spacer 90 and can extend beyond the sidewalls of the second nanostructure 54.

[0144] exist Figure 21A-Figure 21C In the embodiment, a first interlayer dielectric (ILD) 96 is deposited on Fig. 6A and Figures 20A-20D The structure shown ( Figures 7A-20D The process does not change Fig. 6A). The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 95 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 78, and the first spacer 81. The CESL 95 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, that has a different etch rate than the material of the overlying first ILD 96 .

[0145] exist Figure 22A-22B In the process, a planarization process, such as CMP, may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within process variations. Accordingly, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0146] exist Fig.23A and Fig. 23BIn the embodiment of the present invention, the dummy gate 76 and the mask 78, if present, are removed in one or more etching steps to form a second recess 98. The portion of the dummy dielectric layer 60 in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and the dummy dielectric layer 60 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etches the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or covers portions of the nanostructures 55 that serve as channel regions of the subsequently completed nano-FET. The portions of the nanostructures 55 that serve as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, when etching the dummy gate 76, the dummy dielectric layer 60 may serve as an etch stop. Then, after removing the dummy gate 76, the dummy dielectric layer 60 may be removed.

[0147] exist Fig.24A and Fig. 24B , the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P are removed, thereby extending the second recess 98. The first nanostructure 52 can be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process such as a wet etching process or the like using an etchant selective to the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched as compared to the first nanostructure 52. In embodiments where the first nanostructure 52 includes, for example, SiGe, and the second nanostructures 54A-54C include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to remove the first nanostructure 52 in the n-type region 50N.

[0148] The second nanostructure 54 in the p-type region 50P may be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process such as a wet etch or the like using an etchant that is selective to the material of the second nanostructure 54, while the first nanostructure 52, the substrate 50, and the STI region 68 remain relatively unetched as compared to the second nanostructure 54. In embodiments where the second nanostructure 54 includes, for example, SiGe, and the first nanostructure 52 includes, for example, Si or SiC, hydrogen fluoride, another fluorine-based etchant, or the like may be used to remove the second nanostructure 54 in the p-type region 50P.

[0149] exist Fig.25A and Fig.25B , a gate dielectric layer 100 and a gate electrode 102 form a replacement gate. The gate dielectric layer 100 is conformally deposited in the second recess 98. In the n-type region 50N, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the second nanostructure 54, and in the p-type region 50P, the gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the first nanostructure 52. The gate dielectric layer 100 may also be deposited on the top surface of the first ILD 96, the CESL 95, the first spacer 81, and the STI region 68.

[0150] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer on the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The formation method of the gate dielectric layer 100 may include molecular-beam deposition (MBD), ALD, PECVD, and the like.

[0151] The gate electrode 102 is deposited over the gate dielectric layer 100 and fills the remaining portion of the second recess 98. The gate electrode 102 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Fig.25A and Fig.25B , a single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of liner layers, any number of work function adjustment layers, and filler materials. Any combination of layers constituting the gate electrode 102 may be deposited in the n-type region 50N between adjacent second nanostructures 54 and between the second nanostructures 54A and the substrate 50, and may be deposited in the p-type region 50P between adjacent first nanostructures 52.

[0152] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may occur simultaneously so that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously so that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by different processes so that the gate dielectric layer 100 may be a different material and / or have a different number of layers, and / or the gate electrode 102 in each region may be formed by different processes so that the gate electrode 102 may be a different material and / or have a different number of layers. When using different processes, various masking steps may be used to shield and expose appropriate regions.

[0153] After filling the second recess 98, a planarization process, such as CMP, may be performed to remove excess portions of the material of the gate dielectric layer 100 and the gate electrode 102 that are above the top surface of the first ILD 96. Thus, the remaining portions of the material of the gate electrode 102 and the gate dielectric layer 100 form a replacement gate structure of the resulting nano-FET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure."

[0154] exist Figure 26A-26C In the embodiment of the present invention, the gate structure (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed so that a groove is formed directly above the gate structure and between the opposite portions of the first spacer 81. A gate mask 104 comprising one or more layers of a dielectric material such as silicon nitride, silicon oxynitride, or the like is filled in the groove, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 96. A gate contact (such as the following relative to Figures 27A-28C The gate contact 114 discussed herein penetrates the gate mask 104 so as to contact the top surface of the recessed gate electrode 102 .

[0155] If further Figure 26A-26C As shown, the second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed by a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable method, such as CVD, PECVD, or the like.

[0156] exist Figure 27A-27CIn the embodiment of the present invention, the second ILD 106, the first ILD 96, the CESL 95, and the gate mask 104 are etched to form a third recess 108, which exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process, such as RIE, NBE, or the like. In some embodiments, the third recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; can be etched through the gate mask 104 using a second etching process; and can then be etched through the CESL 95 using a third etching process. A mask, such as a photoresist, can be formed over the second ILD 106 and patterned so as to shield portions of the second ILD 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the third recess 108 extends into the epitaxial source / drain region 92 and / or the gate structure, and the bottom of the third recess 108 may be flush with the epitaxial source / drain region 92 and / or the gate structure (e.g., at the same level, or having the same distance from the substrate), or lower (e.g., closer to the substrate). Fig.27B The third recess 108 is shown as exposing the epitaxial source / drain region 92 and the gate structure in the same cross-section, but in various embodiments, the epitaxial source / drain region 92 and the gate structure may be exposed in different cross-sections, thereby reducing the risk of shorting subsequently formed contacts. After forming the third recess 108, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a metal (not shown) capable of reacting with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other high temperature resistant metals, rare earth metals, or alloys thereof, over the exposed portion of the epitaxial source / drain region 92, and then performing a thermal annealing process to form the silicide region 110. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, the silicide region 110 may also be a germanide region, or a silicon-germanide region (e.g., a region including silicide and germanide). In one embodiment, the silicide region 110 includes TiSi and has a thickness ranging between about 2 nm and about 10 nm.

[0157] Later, in Figure 28A-28C, contacts 112 and 114 (also referred to as contact plugs) are formed in the third recess 108. The contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the contacts 112 and 114 each include a barrier layer and a conductive material (not shown separately), and are electrically coupled to underlying conductive features (e.g., the gate electrode 102 and / or the silicide region 110 in the illustrated embodiment). The contact 114 is electrically coupled to the gate structure (e.g., the gate electrode 102) and may be referred to as a gate contact, and the contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material 118 may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD 106 .

[0158] Although Figure 28A-28C Contacts 112 are shown extending to each of the epitaxial source / drain regions 92, but contacts 112 may be omitted from certain epitaxial source / drain regions 92. For example, although not specifically shown, a conductive feature (e.g., a power rail) may be subsequently attached via the backside of one or more epitaxial source / drain regions 92. For these particular epitaxial source / drain regions 92, source / drain contacts 112 may be omitted or may be dummy contacts that are not electrically connected to any overlying conductive lines (also not specifically shown).

[0159] Embodiments can achieve advantages. For example, embodiments disclosed herein improve yield and effectiveness in forming epitaxial source / drain regions 92. Specifically, forming mask layers (e.g., p-mask layer 93 and n-mask layer 94) comprising metal oxide allows for thinner mask layers, thereby forming a finish protection layer at critical dimensions that become smaller as technology advances. In addition, performing post-deposition treatment 200 or 300 on the mask layer achieves additional benefits. First, post-deposition treatment 200 or 300 converts the smooth exposed surface of the mask layer (e.g., smooth exposed surfaces 93S and 94S) to a rough exposed surface (e.g., rough exposed surfaces 93R and 94R). The rougher exposed surface 93B / 94B has a lower selectivity for epitaxial growth during the formation of epitaxial source / drain regions 92 than the smoother exposed surface 93A / 94A. Second, the lower selectivity of epitaxial growth improves critical dimension control by minimizing the number and / or duration of epitaxial etching steps that can be performed for epitaxial growth. Third, reducing epitaxial growth over the mask layer produces a mask layer that can be subsequently removed (eg, by isotropic wet etching) without being hindered by large nodules of epitaxial material or a large number of nodules of epitaxial material disposed over the mask layer.

[0160] In one embodiment, the method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first mask layer over the semiconductor layer; performing a first thermal treatment on the first mask layer, the first thermal treatment densifying the first mask layer; etching the first mask layer so as to expose the first recess; forming a first semiconductor material in the first recess; and removing the first mask layer. In another embodiment, the first semiconductor material includes at least one of silicon germanium, silicon carbide, phosphorus-doped silicon carbide, and silicon phosphide. In another embodiment, performing the first thermal treatment includes radiation treatment. In another embodiment, performing the first thermal treatment includes plasma treatment. In another embodiment, the first thermal treatment crystallizes at least a portion of the first mask layer. In another embodiment, after the first thermal treatment, the first mask layer has a rougher upper surface than before the first thermal treatment. In another embodiment, the method includes forming a second mask layer over the semiconductor layer; performing a second thermal treatment on the second mask layer, the second thermal treatment densifying the second mask layer; etching the second mask layer so as to expose the second recess; and forming a second semiconductor material in the second recess. In another embodiment, one of the first thermal treatment and the second thermal treatment further includes plasma treatment.

[0161] In one embodiment, a method includes forming a semiconductor layer over a first substrate; etching the semiconductor layer to form a first recess in a first region and a second recess in a second region; depositing a first mask layer over the first region and the second region; roughening the first mask layer; removing the first mask layer from the second region; forming a first epitaxial source / drain region in the second recess; removing a remaining portion of the first mask layer; depositing a second mask layer over the first region and the second region; roughening the second mask layer; removing the second mask layer from the first region; forming a second epitaxial source / drain region in the first recess; removing a remaining portion of the second mask layer; and forming a gate structure over the semiconductor layer. In another embodiment, roughening the first mask layer includes performing a heat treatment on the first mask layer. In another embodiment, performing the heat treatment on the first mask layer is performed at a temperature greater than 650° C. In another embodiment, the first mask layer includes a metal oxide. In another embodiment, one of roughening the first mask layer and roughening the second mask layer includes a heat treatment, and the other includes a plasma treatment. In another embodiment, one of roughening the first mask layer and roughening the second mask layer further comprises UV radiation treatment. In another embodiment, before roughening the first mask layer, the first mask layer is amorphous, and wherein after roughening the first mask layer, at least an upper portion of the first mask layer is crystalline. In another embodiment, removing the remaining portion of the first mask layer comprises wet etching using hydrofluoric acid.

[0162] In one embodiment, a method includes depositing a mask layer over a substrate, the substrate including a first recess and a second recess; performing a post-deposition treatment on the mask layer; anisotropically etching the mask layer to expose the second recess; epitaxially growing a first portion of semiconductor material over the mask layer and a second portion of semiconductor material in the second recess, the first portion including a discontinuous nodule; and isotropically etching to remove the mask layer. In another embodiment, performing the post-deposition treatment includes performing a thermal treatment. In another embodiment, performing the post-deposition treatment further includes performing a plasma treatment. In another embodiment, the post-deposition treatment further includes a UV treatment.

[0163] The foregoing summarizes the features of multiple embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will recognize that they can easily use the present disclosure as a basis for designing or improving other processes and structures that perform the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a transistor, characterized in that: The following steps are involved: forming a semiconductor layer on a substrate; Etching a portion of the semiconductor layer to form a first groove and a second groove; forming a first mask layer above the semiconductor layer; performing a first thermal treatment on the first mask layer, the first thermal treatment densifying the first mask layer, wherein after the first thermal treatment, the first mask layer has an upper surface that is rougher than before the first thermal treatment; etching the first mask layer to expose the first groove; forming a first semiconductor material in the first groove; and removing the first mask layer.

2. The method according to claim 1, characterized in that The first semiconductor material includes at least one of silicon germanium, silicon carbide, phosphorus-doped silicon carbide, and silicon phosphide.

3. The method according to claim 1, characterized in that The performing of the first thermal treatment includes a radiation treatment.

4. The method according to claim 1, characterized in that The performing of the first thermal treatment includes a plasma treatment.

5. The method according to claim 1, characterized in that The first thermal treatment crystallizes at least a portion of the first mask layer.

6. The method according to claim 1, characterized in that Removing the first mask layer includes a wet etch using hydrofluoric acid.

7. The method according to claim 1, characterized in that Further comprising the steps of: forming a second mask layer above the semiconductor layer; performing a second thermal treatment on the second mask layer, wherein the second thermal treatment densifies the second mask layer; etching the second mask layer to expose the second groove; and forming a second semiconductor material in the second groove.

8. The method according to claim 7, characterized in that One of the first thermal treatment and the second thermal treatment further includes a plasma treatment.

9. A method for manufacturing a transistor, characterized in that: The following steps are involved: forming a semiconductor layer on a first substrate; Etching the semiconductor layer to form a first groove in a first region and a second groove in a second region; Depositing a first mask layer over the first region and the second region; Roughening the first mask layer, wherein the roughening of the first mask layer comprises performing at least one thermal treatment or performing at least one plasma treatment; removing the first mask layer from the second area; forming a first epitaxial source / drain region in the second groove; removing the remaining portion of the first mask layer; depositing a second mask layer over the first region and the second region; roughening the second mask layer; removing the second mask layer from the first area; forming a second epitaxial source / drain region in the first groove; removing the remaining portion of the second mask layer; and forming a gate structure above the semiconductor layer.

10. The method according to claim 9, characterized in that Roughening the first mask layer includes performing the thermal treatment on the first mask layer.

11. The method according to claim 10, characterized in that The heat treatment performed on the first mask layer is performed at a temperature greater than 650°C.

12. The method according to claim 9, characterized in that The first mask layer includes a metal oxide.

13. The method according to claim 9, characterized in that One of roughening the first mask layer and roughening the second mask layer includes performing the thermal treatment, and the other includes performing the plasma treatment.

14. The method according to claim 13, characterized in that One of roughening the first mask layer and roughening the second mask layer further includes performing a UV radiation treatment.

15. The method according to claim 9, characterized in that Prior to roughening the first mask layer, the first mask layer is amorphous, and wherein after roughening the first mask layer, at least an upper portion of the first mask layer is crystalline.

16. The method according to claim 9, characterized in that Removing the remaining portion of the first mask layer includes a wet etch using hydrofluoric acid.

17. A method for manufacturing a transistor, characterized in that: The following steps are involved: Depositing a mask layer on a substrate, the substrate comprising a first groove and a second groove; performing a post-deposition treatment on the mask layer to crystallize at least a portion of the mask layer; After performing the post-deposition treatment on the mask layer, anisotropically etching the mask layer to expose the second recess; epitaxially growing a first portion of a semiconductor material above the mask layer and a second portion of the semiconductor material in the second recess, the first portion comprising a discontinuous nodule; and isotropically etching to remove the mask layer.

18. The method according to claim 17, characterized in that The performing the post-deposition treatment includes performing a thermal treatment.

19. The method according to claim 18, characterized in that The performing the post-deposition treatment further includes performing a plasma treatment.

20. The method according to claim 19, characterized in that The post-deposition treatment further includes a UV treatment.

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